Re: [PATCH v3 00/18] target/arm: sve load/store improvements

Patchew URL: https://patchew.org/QEMU/20200422043309.18430-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v3 00/18] target/arm: sve load/store improvements Message-id:

Re: [PATCH v3 06/10] iotests: add testfinder.py

21.04.2020 19:56, Kevin Wolf wrote: Am 21.04.2020 um 09:35 hat Vladimir Sementsov-Ogievskiy geschrieben: Add python script with new logic of searching for tests: Current ./check behavior: - tests are named [0-9][0-9][0-9] - tests must be registered in group file (even if test doesn't

Re: [PATCH v3 04/10] iotests/check: move QEMU_VXHS_PROG to common.rc

21.04.2020 19:03, Kevin Wolf wrote: Am 21.04.2020 um 09:35 hat Vladimir Sementsov-Ogievskiy geschrieben: QEMU_VXHS_PROG is used only in common.rc. So, move it to common.rc, simplifying a bit further conversion of check into python Signed-off-by: Vladimir Sementsov-Ogievskiy This feels

Re: tst-arm-mte bug: PSTATE.TCO is cleared on exceptions

On 4/20/20 3:29 AM, Szabolcs Nagy wrote: > i'm using the branch at > > https://github.com/rth7680/qemu/tree/tgt-arm-mte > > to test armv8.5-a mte and hope this is ok to report bugs here. > > i'm doing tests in qemu-system-aarch64 with linux userspace > code and it seems TCO bit gets cleared

[PATCH v3 18/18] target/arm: Remove sve_memopidx

None of the sve helpers use TCGMemOpIdx any longer, so we can stop passing it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 - target/arm/sve_helper.c| 14 +++--- target/arm/translate-sve.c | 17 +++-- 3 files

[PATCH v3 17/18] target/arm: Reuse sve_probe_page for gather loads

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 208 +--- 1 file changed, 109 insertions(+), 99 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index f4cdeecdcb..fffde4b6ec 100644 ---

[PATCH v3 15/18] target/arm: Reuse sve_probe_page for gather first-fault loads

This avoids the need for a separate set of helpers to implement no-fault semantics, and will enable MTE in the future. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 323 1 file changed, 127 insertions(+), 196

[PATCH v3 11/18] target/arm: Handle watchpoints in sve_ld1_r

Handle all of the watchpoints for active elements all at once, before we've modified the vector register. This removes the TLB_WATCHPOINT bit from page[].flags, which means that we can use the normal fast path via RAM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---

[PATCH v3 12/18] target/arm: Use SVEContLdSt for multi-register contiguous loads

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 223 ++-- 1 file changed, 79 insertions(+), 144 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 7992a569b0..9365e32646 100644 ---

[PATCH v3 10/18] target/arm: Use SVEContLdSt in sve_ld1_r

First use of the new helper functions, so we can remove the unused markup. No longer need a scratch for user-only, as we completely probe the page set before reading; system mode still requires a scratch for MMIO. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---

Re: [PATCH 03/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits

Hi, Sasha, On Wed, Apr 22, 2020 at 9:42 AM Sasha Levin wrote: > > Hi > > [This is an automated email] > > This commit has been processed because it contains a -stable tag. > The stable tag indicates that it's relevant for the following trees: all > > The bot has tested the following trees:

[PATCH v3 09/18] target/arm: Adjust interface of sve_ld1_host_fn

The current interface includes a loop; change it to load a single element. We will then be able to use the function for ld{2,3,4} where individual vector elements are not adjacent. Replace each call with the simplest possible loop over active elements. Reviewed-by: Peter Maydell Signed-off-by:

[PATCH v3 05/18] accel/tcg: Add endian-specific cpu_{ld, st}* operations

We currently have target-endian versions of these operations, but no easy way to force a specific endianness. This can be helpful if the target has endian-specific operations, or a mode that swaps endianness. Signed-off-by: Richard Henderson --- docs/devel/loads-stores.rst | 39 +++--

[PATCH v3 14/18] target/arm: Use SVEContLdSt for contiguous stores

Follow the model set up for contiguous loads. This handles watchpoints correctly for contiguous stores, recognizing the exception before any changes to memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 285

[PATCH v3 08/18] target/arm: Add sve infrastructure for page lookup

For contiguous predicated memory operations, we want to minimize the number of tlb lookups performed. We have open-coded this for sve_ld1_r, but for correctness with MTE we will need this for all of the memory operations. Create a structure that holds the bounds of active elements, and metadata

[PATCH v3 16/18] target/arm: Reuse sve_probe_page for scatter stores

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 182 1 file changed, 111 insertions(+), 71 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 6229ea65c0..f4cdeecdcb 100644 ---

[PATCH v3 06/18] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn

Use the "normal" memory access functions, rather than the softmmu internal helper functions directly. Since fb901c905dc3, cpu_mem_index is now a simple extract from env->hflags and not a large computation. Which means that it's now more work to pass around this value than it is to recompute it.

[PATCH v3 13/18] target/arm: Update contiguous first-fault and no-fault loads

With sve_cont_ldst_pages, the differences between first-fault and no-fault are minimal, so unify the routines. With cpu_probe_watchpoint, we are able to make progress through pages with TLB_WATCHPOINT set when the watchpoint does not actually fire. Signed-off-by: Richard Henderson ---

[PATCH v3 04/18] accel/tcg: Add probe_access_flags

This new interface will allow targets to probe for a page and then handle watchpoints themselves. This will be most useful for vector predicated memory operations, where one page lookup can be used for many operations, and one test can avoid many watchpoint checks. Signed-off-by: Richard

[PATCH v3 00/18] target/arm: sve load/store improvements

Because there was a separate v2 of one of the patches, avoid confusion and call the whole thing v3. The goal here is to support MTE, but there's some cleanup to do. Technically, we have sufficient interfaces in cputlb.c now, but it requires multiple tlb lookups on different interfaces to do so.

[PATCH v3 03/18] accel/tcg: Add block comment for probe_access

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 350c4b451b..d656a1f05c 100644 --- a/include/exec/exec-all.h +++

[PATCH v3 01/18] exec: Add block comments for watchpoint routines

Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5bf94d28cf..07f7698155 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1100,8 +1100,31 @@

[PATCH v3 02/18] exec: Fix cpu_watchpoint_address_matches address length

The only caller of cpu_watchpoint_address_matches passes TARGET_PAGE_SIZE, so the bug is not currently visible. Signed-off-by: Richard Henderson --- exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/exec.c b/exec.c index 2874bb5088..5162f0d12f 100644 --- a/exec.c +++

[PATCH v3 07/18] target/arm: Drop manual handling of set/clear_helper_retaddr

Since we converted back to cpu_*_data_ra, we do not need to do this ourselves. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 38 -- 1 file changed, 38 deletions(-) diff --git a/target/arm/sve_helper.c

Re: [PATCH 02/15] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(_cpu_data)

Hi, Sasha, On Wed, Apr 22, 2020 at 9:40 AM Sasha Levin wrote: > > Hi > > [This is an automated email] > > This commit has been processed because it contains a -stable tag. > The stable tag indicates that it's relevant for the following trees: all > > The bot has tested the following trees:

Re: [PATCH 6/6] target/arm: Restrict TCG cpus to TCG accel

On 4/21/20 6:19 AM, Philippe Mathieu-Daudé wrote: > A KVM-only build won't be able to run TCG cpus. > > Signed-off-by: Philippe Mathieu-Daudé > --- > This patch review is funnier using: > 'git-diff --color-moved=dimmed-zebra' > --- > target/arm/cpu.c | 634

Re: [PATCH 5/6] target/arm/cpu: Update coding style to make checkpatch.pl happy

On 4/21/20 6:19 AM, Philippe Mathieu-Daudé wrote: > We will move this code in the next commit. Clean it up > first to avoid checkpatch.pl errors. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/cpu.c | 9 ++--- > 1 file changed, 6 insertions(+), 3 deletions(-) Reviewed-by:

Re: [PATCH 4/6] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]

On 4/21/20 6:19 AM, Philippe Mathieu-Daudé wrote: > Suggested-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/cpu.c | 8 +++- > target/arm/cpu64.c | 8 +++- > 2 files changed, 6 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 1/6] target/arm: Restric the Address Translate write operation to TCG accel

On 4/21/20 6:19 AM, Philippe Mathieu-Daudé wrote: > Under KVM these registers are written by the hardware. > Restrict the writefn handlers to TCG to avoid when building > without TCG: > > LINKaarch64-softmmu/qemu-system-aarch64 > target/arm/helper.o: In function `do_ats_write': >

Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition

On 4/21/20 7:34 PM, LIU Zhiwei wrote: > Ping. > > When I port RISU, I find this bug. I can't get the correct registers from the > struct ucontext_t parameter in the signal handler. The RISC-V Linux ABI will need to be extended to handle RVV state. There is room in your sigcontext structure: >

Re: [PATCH] target/arm: Implement SVE2 scatter store insns

On 4/20/20 1:42 PM, Stephen Long wrote: > +static bool trans_ST1_zprz_sve2(DisasContext *s, arg_ST1_zprz_sve2 *a) > +{ > +gen_helper_gvec_mem_scatter *fn; > +bool be = s->be_data == MO_BE; > +bool mte = s->mte_active[0]; > + > +if (!dc_isar_feature(aa64_sve2, s) || a->esz < a->msz

Re: [PATCH] target/arm: Implement SVE2 FMMLA

On 4/20/20 8:10 AM, Stephen Long wrote: > +#define DO_FP_MATRIX_MUL(NAME, TYPE, H) \ > +void HELPER(NAME)(void *vd, void *va, void *vn, void *vm, \ > + void *status, uint32_t desc) \ > +{

Re: [PATCH for-5.1 00/31] target/arm: SVE2, part 1

Hi Richard, I find BF16 is included in the ISA.  Will you extend  the softfpu in this patch set? Zhiwei On 2020/3/27 7:08, Richard Henderson wrote: Posting this for early review. It's based on some other patch sets that I have posted recently that also touch SVE, listed below. But it

Re: [PATCH for-5.1 00/31] target/arm: SVE2, part 1

On 4/21/20 7:51 PM, LIU Zhiwei wrote: > I find BF16 is included in the ISA.  Will you extend  the softfpu in this > patch > set? I will do that eventually, but probably not part of the first full SVE2 patch set. There are several optional extensions to SVE2, of which BF16 is one. But BF16

Re: [PATCH v1 1/2] migration/xbzrle: replace transferred xbzrle bytes with encoded bytes

On 04/22/2020 03:21 AM, Dr. David Alan Gilbert wrote: * Wei Wang (wei.w.w...@intel.com) wrote: Like compressed_size which indicates how many bytes are compressed, we need encoded_size to understand how many bytes are encoded with xbzrle during migration. Replace the old xbzrle_counter.bytes,

Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition

Ping. When I port RISU, I find this bug. I can't get the correct registers from the struct ucontext_t parameter in the signal handler. If you want to reproduce it, just   register a signal handler for SIGILL, and  output an illegal instruction, such as #include #include #include #include

Re: [PATCH 03/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits

Hi [This is an automated email] This commit has been processed because it contains a -stable tag. The stable tag indicates that it's relevant for the following trees: all The bot has tested the following trees: v5.6.5, v5.5.18, v5.4.33, v4.19.116, v4.14.176, v4.9.219, v4.4.219. v5.6.5: Build

Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7

Hi Alistair, On Tue, Apr 21, 2020 at 9:34 AM Bin Meng wrote: > > Hi Alistair, > > On Tue, Apr 21, 2020 at 2:41 AM Alistair Francis wrote: > > > > On Mon, Apr 20, 2020 at 6:25 AM Bin Meng wrote: > > > > > > Upgrade OpenSBI from v0.6 to v0.7 and the pre-built bios images. > > > > > > The v0.7

Re: [PATCH 02/15] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(_cpu_data)

Hi [This is an automated email] This commit has been processed because it contains a -stable tag. The stable tag indicates that it's relevant for the following trees: all The bot has tested the following trees: v5.6.5, v5.5.18, v5.4.33, v4.19.116, v4.14.176, v4.9.219, v4.4.219. v5.6.5: Build

[PATCH v2 35/36] target/ppc: Use tcg_gen_gvec_rotlv

Cc: David Gibson Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 target/ppc/int_helper.c | 17 - target/ppc/translate/vmx-impl.inc.c | 8 3 files changed, 4 insertions(+), 25 deletions(-) diff --git a/target/ppc/helper.h

[PATCH v2 33/36] tcg/aarch64: Implement INDEX_op_rotli_vec

We can implement this in two instructions, using SLI. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.opc.h | 1 + tcg/aarch64/tcg-target.inc.c | 20 +++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.opc.h

[PATCH v2 28/36] tcg: Implement gvec support for rotate by immediate

No host backend support yet, but the interfaces for rotli are in place. Canonicalize immediate rotate to the left, based on a survey of architectures, but provide both left and right shift interfaces to the translators. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++

[PATCH v2 36/36] target/s390x: Use tcg_gen_gvec_rotl{i,s,v}

Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Cc: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/helper.h | 4 -- target/s390x/translate_vx.inc.c | 66 +

[PATCH v2 26/36] tcg: Add load_dest parameter to GVecGen2

We have this same parameter for GVecGen2i, GVecGen3, and GVecGen3i. This will make some SVE2 insns easier to parameterize. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 45 --- 2 files changed, 34

[PATCH v2 30/36] tcg: Remove expansion to shift by vector from do_shifts

We do not reflect this expansion in tcg_can_emit_vecop_list, so it is unused and unusable. However, we actually perform the same expansion in do_gvec_shifts, so it is also unneeded. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 35 +++ 1 file changed,

[PATCH v2 25/36] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec

These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 tcg/tcg-op-vec.c | 20 2 files changed, 24 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index

[PATCH v2 24/36] tcg/i386: Use tcg_constant_vec with tcg vec expanders

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 9cb627d6eb..deace219d2 100644 --- a/tcg/i386/tcg-target.inc.c +++

[PATCH v2 32/36] tcg/i386: Implement INDEX_op_rotl[is]_vec

We must continue the special casing of 8-bit elements and the other element sizes are trivially implemented with shifts. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 85 +++ 1 file changed, 69 insertions(+), 16 deletions(-) diff --git

[PATCH v2 20/36] tcg: Remove movi and dupi opcodes

These are now completely covered by mov from a TYPE_CONST temporary. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 --- tcg/aarch64/tcg-target.inc.c | 3 --- tcg/arm/tcg-target.inc.c | 1 - tcg/i386/tcg-target.inc.c| 3 --- tcg/mips/tcg-target.inc.c| 2

[PATCH v2 29/36] tcg: Implement gvec support for rotate by vector

No host backend support yet, but the interfaces for rotlv and rotrv are in place. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 10 +++ include/tcg/tcg-op-gvec.h| 4 ++ include/tcg/tcg-op.h | 2 + include/tcg/tcg-opc.h| 2 + include/tcg/tcg.h

[PATCH v2 19/36] tcg/tci: Add special tci_movi_{i32,i64} opcodes

The normal movi opcodes are going away. We need something for TCI to use internally. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 8 tcg/tci.c| 4 ++-- tcg/tci/tcg-target.inc.c | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git

[PATCH v2 10/36] tcg: Add temp_readonly

In most, but not all, places that we check for TEMP_FIXED, we are really testing that we do not modify the temporary. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 5 + tcg/tcg.c | 21 ++--- 2 files changed, 15

[PATCH v2 23/36] tcg: Add tcg_reg_alloc_dup2

There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 88 +++ 1 file changed, 88 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index fc1c97d586..d712d19842

[PATCH v2 18/36] tcg/optimize: Use tcg_constant_internal with constant folding

Signed-off-by: Richard Henderson --- tcg/optimize.c | 106 ++--- 1 file changed, 48 insertions(+), 58 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index d36d7e1d7f..dd5187be31 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -178,37

[PATCH v2 16/36] tcg: Rename struct tcg_temp_info to TempOptInfo

Fix this name vs our coding style. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index effb47eefd..b86bf3d707 100644

[PATCH v2 21/36] tcg: Use tcg_out_dupi_vec from temp_load

Having dupi pass though movi is confusing and arguably wrong. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 7 tcg/i386/tcg-target.inc.c| 63 tcg/ppc/tcg-target.inc.c | 6 tcg/tcg.c| 8 - 4

[PATCH v2 17/36] tcg/optimize: Adjust TempOptInfo allocation

Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization.

[PATCH v2 09/36] tcg: Consolidate 3 bits into enum TCGTempKind

The temp_fixed, temp_global, temp_local bits are all related. Combine them into a single enumeration. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 20 +--- tcg/optimize.c| 8 +-- tcg/tcg.c | 122 -- 3 files changed, 90

[PATCH v2 13/36] tcg: Use tcg_constant_{i32, i64} with tcg int expanders

Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 13 +-- tcg/tcg-op.c | 216 --- 2 files changed, 100 insertions(+), 129 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 230db6e022..11ed9192f7 100644 ---

[PATCH v2 15/36] tcg: Use tcg_constant_{i32,i64} with tcg plugins

Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 49 +++--- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 51580d51a0..e5dc9d0ca9 100644 --- a/accel/tcg/plugin-gen.c +++

[PATCH v2 34/36] tcg/ppc: Implement INDEX_op_rot[lr]v_vec

We already had support for rotlv, using a target-specific opcode; convert to use the generic opcode. Handle rotrv via simple negation. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.opc.h | 1 - tcg/ppc/tcg-target.inc.c | 23 +++

[PATCH v2 05/36] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications

Replace the outgoing interface. Reviewed-by: LIU Zhiwei Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 593bb4542e..de16c027b3 100644 ---

[PATCH v2 14/36] tcg: Use tcg_constant_{i32, vec} with tcg vec expanders

Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 63 ++-- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index f3927089a7..655b3ae32d 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@

[PATCH v2 12/36] tcg: Use tcg_constant_i32 with icount expander

We must do this before we adjust how tcg_out_movi_i32, lest the under-the-hood poking that we do be broken. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/gen-icount.h

[PATCH v2 31/36] tcg: Implement gvec support for rotate by scalar

No host backend support yet, but the interfaces for rotls are in place. Only implement left-rotate for now, as the only known use of vector rotate by scalar is s390x, so any right-rotate would be unused and untestable. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++

[PATCH v2 04/36] target/arm: Use tcg_gen_gvec_dup_imm

In a few cases, we're able to remove some manual replication. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 10 +- target/arm/translate-sve.c | 12 +--- target/arm/translate.c | 9 ++--- 3 files changed, 16 insertions(+), 15

[PATCH v2 11/36] tcg: Introduce TYPE_CONST temporaries

These will hold a single constant for the duration of the TB. They are hashed, so that each value has one temp across the TB. Not used yet, this is all infrastructure. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 27 ++- tcg/optimize.c| 40 ++---

[PATCH v2 08/36] tcg: Improve vector tail clearing

Better handling of non-power-of-2 tails as seen with Arm 8-byte vector operations. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 82 --- 1 file changed, 63 insertions(+), 19 deletions(-) diff --git

[PATCH v2 02/36] target/s390x: Use tcg_gen_gvec_dup_imm

The gen_gvec_dupi switch is unnecessary with the new function. Replace it with a local gen_gvec_dup_imm that takes care of the register to offset conversion and length arguments. Drop zero_vec and use use gen_gvec_dup_imm with 0. Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée

[PATCH v2 07/36] tcg: Add tcg_gen_gvec_dup_tl

For use when a target needs to pass a configure-specific target_ulong value to duplicate. Reviewed-by: LIU Zhiwei Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCH v2 03/36] target/ppc: Use tcg_gen_gvec_dup_imm

We can now unify the implementation of the 3 VSPLTI instructions. Acked-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/translate/vmx-impl.inc.c | 32 - target/ppc/translate/vsx-impl.inc.c | 2 +- 2 files changed, 19 insertions(+), 15 deletions(-)

[PATCH v2 27/36] tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32, 64}

For the benefit of compatibility of function pointer types, we have standardized on int32_t and int64_t as the integral argument to tcg expanders. We converted most of them in 474b2e8f0f7, but missed the rotates. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 8

[PATCH v2 01/36] tcg: Add tcg_gen_gvec_dup_imm

Add a version of tcg_gen_dup_* that takes both immediate and a vector element size operand. This will replace the set of tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element size within the function name. Reviewed-by: LIU Zhiwei Reviewed-by: David Hildenbrand Reviewed-by: Alex

[PATCH v2 22/36] tcg: Increase tcg_out_dupi_vec immediate to int64_t

While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 2 +- tcg/i386/tcg-target.inc.c| 20

[PATCH v2 06/36] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i

These interfaces are now unused. Reviewed-by: LIU Zhiwei Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 5 - tcg/tcg-op-gvec.c | 28 2 files changed, 33 deletions(-) diff

[PATCH v2 00/36] tcg 5.1 omnibus patch set

For v1, I had split this into 4 logically distinct parts. But apparently there are minor interdependencies, because the later sets would not apply standalone, says Alex. Rather than tease them apart, and then have to undo that work in order to actually apply them later, I'll just lump them. So:

[PATCH] fixup! qemu-img: Add bitmap sub-command

Signed-off-by: Eric Blake --- Squash this into patch 3/6 to fix docker-test-mingw@fedora qemu-img.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-img.c b/qemu-img.c index 6cfc1f52ef98..cc87eaf12778 100644 --- a/qemu-img.c +++ b/qemu-img.c @@ -4529,7 +4529,7 @@ static

Re: [PATCH v2 0/6] qemu-img: Add convert --bitmaps

Patchew URL: https://patchew.org/QEMU/20200421212019.170707-1-ebl...@redhat.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH v2 2/6] block/nbd-client: drop max_block restriction from discard

On 4/1/20 10:01 AM, Vladimir Sementsov-Ogievskiy wrote: NBD spec is updated, so that max_block doesn't relate to NBD_CMD_TRIM. So, drop the restriction. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/nbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Eric

[PATCH] virtio-vga: fix virtio-vga bar ordering

With virtio-vga, pci bar are reordered. Bar #2 is used for compatibility with stdvga. By default, bar #2 is used by virtio modern io bar. This bar is the last one introduce in the virtio pci bar layout and it's crushed by the virtio-vga reordering. So virtio-vga and modern-pio-notify are

Re: [PATCH 2/2] tools: Fix use of fcntl(F_SETFD) during socket activation

On 4/20/20 12:53 PM, Eric Blake wrote: Blindly setting FD_CLOEXEC without a read-modify-write will inadvertently clear any other intentionally-set bits, such as a proposed new bit for designating a fd that must behave in 32-bit mode. However, we cannot use our wrapper qemu_set_cloexec(), because

Re: [PATCH v2] qcow2: Expose bitmaps' size during measure

On 4/17/20 11:34 AM, Eric Blake wrote: It's useful to know how much space can be occupied by qcow2 persistent bitmaps, even though such metadata is unrelated to the guest-visible data. Report this value as an additional field. Update iotest 190 to cover it. The addition of a new field

[PATCH v2 6/6] iotests: Add test 291 to for qemu-img bitmap coverage

Add a new test covering the 'qemu-img bitmap' subcommand, as well as 'qemu-img convert --bitmaps', both added in recent patches. Signed-off-by: Eric Blake --- tests/qemu-iotests/291 | 103 + tests/qemu-iotests/291.out | 78

[PATCH v2 2/6] blockdev: Split off basic bitmap operations for qemu-img

Upcoming patches want to add some basic bitmap manipulation abilities to qemu-img. But blockdev.o is too heavyweight to link into qemu-img (among other things, it would drag in block jobs and transaction support - qemu-img does offline manipulation, where atomicity is less important because there

[PATCH v2 4/6] qcow2: Expose bitmaps' size during measure

It's useful to know how much space can be occupied by qcow2 persistent bitmaps, even though such metadata is unrelated to the guest-visible data. Report this value as an additional field. Update iotest 190 to cover it and a portion of the just-added qemu-img bitmap command. The addition of a

[PATCH v2 3/6] qemu-img: Add bitmap sub-command

Include actions for --add, --remove, --clear, --enable, --disable, and --merge (note that --clear is a bit of fluff, because the same can be accomplished by removing a bitmap and then adding a new one in its place, but it matches what QMP commands exist). Listing is omitted, because it does not

[PATCH v2 5/6] qemu-img: Add convert --bitmaps option

Make it easier to copy all the persistent bitmaps of a source image along with the contents, by adding a boolean flag for use with qemu-img convert. This is basically shorthand, as the same effect could be accomplished with a series of 'qemu-img bitmap --add' and 'qemu-img bitmap --merge -b

[PATCH v2 1/6] docs: Sort sections on qemu-img subcommand parameters

We already list the subcommand summaries alphabetically, we should do the same for the documentation related to subcommand-specific parameters. Signed-off-by: Eric Blake --- docs/tools/qemu-img.rst | 48 - 1 file changed, 24 insertions(+), 24 deletions(-)

[PATCH v2 0/6] qemu-img: Add convert --bitmaps

Without this series, the process for copying one qcow2 image to another including all of its bitmaps involves running qemu and doing the copying by hand with a series of QMP commands. This makes the process a bit more convenient. Series can also be downloaded at:

Re: [PULL] RISC-V Patches for 5.0-rc4

On Tue, 21 Apr 2020 12:27:50 PDT (-0700), Peter Maydell wrote: On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt wrote: RISC-V Patches for 5.0-rc4 This contains handful of patches that I'd like to target for 5.0. I know it's a bit

Re: [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs

On Tue, Apr 21, 2020 at 12:19 PM Palmer Dabbelt wrote: > > From: Alistair Francis > > The RISC-V spec specifies that when a write happens and the D bit is > clear the implementation will set the bit in the PTE. It does not > describe that the PTE being dirty means that we should provide write >

Re: [PULL] RISC-V Patches for 5.0-rc4

On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt wrote: > > RISC-V Patches for 5.0-rc4 > > This contains handful of patches that I'd like to target for 5.0. I know it's > a bit late, I thought I'd already sent these out but must have

[PULL 4/6] riscv/sifive_u: Fix up file ordering

From: Alistair Francis Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 109 ++-- 1 file changed, 55 insertions(+), 54 deletions(-) diff

[PULL 3/6] riscv: AND stage-1 and stage-2 protection flags

From: Alistair Francis Take the result of stage-1 and stage-2 page table walks and AND the two protection flags together. This way we require both to set permissions instead of just stage-2. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt ---

[PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC

From: Alistair Francis At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created

Re: [PATCH for-5.0?] slirp: update to fix CVE-2020-1983

On Tue, 21 Apr 2020 at 18:03, Marc-André Lureau wrote: > > This is an update on the stable-4.2 branch of libslirp.git: > > git shortlog 55ab21c9a3..2faae0f778f81 > > Marc-André Lureau (1): > Fix use-afte-free in ip_reass() (CVE-2020-1983) > > CVE-2020-1983 is actually a follow up fix for

Re: [PATCH v1 1/2] migration/xbzrle: replace transferred xbzrle bytes with encoded bytes

* Wei Wang (wei.w.w...@intel.com) wrote: > Like compressed_size which indicates how many bytes are compressed, we > need encoded_size to understand how many bytes are encoded with xbzrle > during migration. > > Replace the old xbzrle_counter.bytes, instead of adding a new counter, > because we

[PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags

From: Alistair Francis When doing the fist of a two stage lookup (Hypervisor extensions) don't set the current protection flags from the second stage lookup of the base address PTE. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt ---

[PULL] RISC-V Patches for 5.0-rc4

The following changes since commit 20038cd7a8412feeb49c01f6ede89e36c8995472: Update version for v5.0.0-rc3 release (2020-04-15 20:51:54 +0100) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-rc4 for you to fetch changes up to

[PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs

From: Alistair Francis The RISC-V spec specifies that when a write happens and the D bit is clear the implementation will set the bit in the PTE. It does not describe that the PTE being dirty means that we should provide write access. This patch removes the write access granted to pages when the

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