along side setting host page table to be read-only, the memory regions
are also required to be read-only, so that when guest writes to the
read-only & mmap'd regions, vmexits would happen and region write handlers
are called.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yan Zhao
for vfio regions that are without write permission,
drop guest writes to those regions.
Cc: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yan Zhao
Signed-off-by: Xin Zeng
---
hw/vfio/common.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
Signed-off-by: Markus Armbruster
Message-Id: <20200415083048.14339-6-arm...@redhat.com>
Reviewed-by: Eric Blake
---
util/qemu-option.c | 43 +++
1 file changed, 15 insertions(+), 28 deletions(-)
diff --git a/util/qemu-option.c b/util/qemu-option.c
index
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-14-arm...@redhat.com>
---
qom/object.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index 1812f79224..be700e831f 100644
--- a/qom/object.c
+++
The previous few commits have made this more obvious, and removed the
one exception. Time to clarify the documentation, and drop dead error
checking.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-13-arm...@redhat.com>
---
qdict_iter() has just three uses and no test coverage. Replace by
qdict_first(), qdict_next() for more concise code and less type
punning.
Signed-off-by: Markus Armbruster
Message-Id: <20200415083048.14339-5-arm...@redhat.com>
Reviewed-by: Eric Blake
---
include/qapi/qmp/qdict.h | 3 --
When command FOO has no arguments, its generated qmp_marshal_FOO() is
a bit confusing. Make it simpler:
visit_start_struct(v, NULL, NULL, 0, );
if (err) {
goto out;
}
-
-if (!err) {
-visit_check_struct(v, );
-}
+visit_check_struct(v, );
For QMP commands without arguments, gen_marshal() laboriously
generates a qmp_marshal_FOO() that copes with null @args. Turns
there's just one caller that passes null instead of an empty QDict.
Adjust that caller, and simplify gen_marshal().
Signed-off-by: Markus Armbruster
Message-Id:
30.04.2020 8:30, Vladimir Sementsov-Ogievskiy wrote:
30.04.2020 8:25, Vladimir Sementsov-Ogievskiy wrote:
30.04.2020 1:04, Eric Blake wrote:
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Prepare
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-2-arm...@redhat.com>
---
include/qapi/visitor.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/qapi/visitor.h b/include/qapi/visitor.h
index c5b23851a1..f8a0fc1ea9
Call visit_check_list(). Missed in commit a4a1c70dc7 "qapi: Make
input visitors detect unvisited list tails".
Drop an irrelevant error_propagate() while there.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-3-arm...@redhat.com>
---
An alternate type's visit_type_FOO() fails when it runs into an
invalid ->type.
This is appropriate with an input visitor: visit_start_alternate()
sets ->type according to the input, and bad input can lead to bad
->type.
It should never happen with an output, clone or dealloc visitor: if it
did,
An alternate type's visit_type_FOO() fails when it runs into an
invalid ->type. If it's an input visit, we then need to free the the
object we got from visit_start_alternate(). We do that with
qapi_free_FOO(), which uses the dealloc visitor.
Trouble is that object is in a bad state: its ->type
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-4-arm...@redhat.com>
---
include/qapi/visitor.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qapi/visitor.h b/include/qapi/visitor.h
index 7f63e4c381..c5d0ce9184 100644
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-7-arm...@redhat.com>
---
docs/devel/qapi-code-gen.txt | 2 ++
include/qapi/visitor.h | 5 +
qapi/qapi-visit-core.c | 5 +
scripts/qapi/visit.py| 4
4 files changed, 16
visit_type_intN() and visit_type_uintN() fail when the value is out of
bounds.
This is appropriate with an input visitor: the value comes from input,
and input may be bad.
It should never happen with the other visitors: the value comes from
the caller, and callers must keep it within bounds.
output_type_enum() fails when *obj is not a valid value of the enum
type. Should not happen. Drop the check, along with its unit tests.
This unmasks qapi_enum_lookup()'s assertion.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-9-arm...@redhat.com>
Signed-off-by: Markus Armbruster
Message-Id: <20200415083048.14339-3-arm...@redhat.com>
Reviewed-by: Eric Blake
[Coding style in moved code tidied up]
---
qobject/qjson.c | 40
1 file changed, 16 insertions(+), 24 deletions(-)
diff --git
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-5-arm...@redhat.com>
---
include/qapi/visitor.h | 37 +++--
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/include/qapi/visitor.h b/include/qapi/visitor.h
The contract demands v->start_alternate() for input and dealloc
visitors, but visit_start_alternate() actually requires it for input
and clone visitors. Fix the contract, and delete superfluous
qapi_dealloc_start_alternate().
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id:
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Message-Id: <20200424084338.26803-6-arm...@redhat.com>
---
include/qapi/visitor.h | 104 +
1 file changed, 54 insertions(+), 50 deletions(-)
diff --git a/include/qapi/visitor.h
The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into
staging (2020-04-29 15:07:33 +0100)
are available in the Git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2020-04-30
qlist_iter() has just three uses outside tests/. Replace by
QLIST_FOREACH_ENTRY() for more concise code and less type punning.
Signed-off-by: Markus Armbruster
Message-Id: <20200415083048.14339-4-arm...@redhat.com>
Reviewed-by: Eric Blake
---
include/qapi/qmp/qlist.h | 2 --
qobject/qjson.c
QLIST_FOREACH_ENTRY() traverses a tail queue manually. Use
QTAILQ_FIRST() and QTAILQ_NEXT() instead.
Signed-off-by: Markus Armbruster
Message-Id: <20200415083048.14339-2-arm...@redhat.com>
Reviewed-by: Eric Blake
---
include/qapi/qmp/qlist.h | 8
1 file changed, 4 insertions(+), 4
30.04.2020 8:25, Vladimir Sementsov-Ogievskiy wrote:
30.04.2020 1:04, Eric Blake wrote:
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Prepare bdrv_aligned_pwritev() now (and convert the
for ram device regions, drop guest writes if the regions is read-only.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Yan Zhao
Signed-off-by: Xin Zeng
---
memory.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/memory.c b/memory.c
index 601b749906..90a748912f
guest writes to read-only memory regions need to be dropped.
patch 1 modifies handler of ram device memory regions to drop guest writes
to read-only ram device memory regions
patch 2 modifies handler of non-mmap'd read-only vfio regions to drop guest
writes to those regions
patch 3 set
30.04.2020 1:04, Eric Blake wrote:
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Prepare bdrv_aligned_pwritev() now (and convert the
dependencies: bdrv_co_write_req_prepare() and
Daniel P. Berrangé writes:
> The flake8 program is a standard tool used by Python projects for
> validating many commonly recommended style rules. It would be desirable
> for QEMU to come into alignment with normal Python coding style best
> practices.
>
> QEMU currently violates a huge number
29.04.2020 22:27, Eric Blake wrote:
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Convert bdrv_check_byte_request() now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/io.c | 6 +++---
John Snow writes:
> On 4/21/20 5:42 AM, Philippe Mathieu-Daudé wrote:
>> QEMU Python scripts have been moved in commit 8f8fd9edba4 ("Introduce
>> Python module structure"). Use the same sys.path modification used
>> in the referenced commit to be able to use these scripts again.
>>
>>
29.04.2020 16:29, John Snow wrote:
Hi all,
as you are probably aware I haven't been paying attention to dirty
bitmap work very much for the past month.
Around KVM Forum, we had a giant thread dedicated to discussing the
problems with dirty bitmap migration, which in a nutshell, are that it
On 2020/4/17 21:32, Peter Maydell wrote:
> On Fri, 10 Apr 2020 at 12:46, Dongjiu Geng wrote:
>>
>> In the ARMv8 platform, the CPU error types includes synchronous external
>> abort(SEA)
>> and SError Interrupt (SEI). If exception happens in guest, host does not
>> know the detailed
>>
On 4/28/2020 9:28 AM, Verma, Vishal L wrote:
NVDIMMs can belong to their own proximity domains, as described by the
NFIT. In such cases, the SRAT needs to have Memory Affinity structures
in the SRAT for these NVDIMMs, otherwise Linux doesn't populate node
data structures properly during NUMA
On 4/29/20 5:20 PM, 罗勇刚(Yonggang Luo) wrote:
> Question, in hard-float, if we don't want to read the fp register.
> for example: If we wanna compute c = a + b in fp32
> if c = a + b In hard float
> and if b1 = c - a in hard float
> if b1 != b at bitwise level, the we se the inexat to 1, otherwsie
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
target/arm/sve.decode | 7 ++
target/arm/translate-sve.c | 45 ++
3 files changed, 57 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 6 ++
target/arm/translate-sve.c | 14 ++
2 files changed, 20 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index b73b64c3f2..04985d2bb8 100644
--- a/target/arm/sve.decode
+++
Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 5 -
target/arm/crypto_helper.c | 24
Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared. Which fixes
an existing bug.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 12 +--
target/arm/crypto_helper.c | 24 +++--
Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 5 +-
target/arm/crypto_helper.c | 99
With this conversion, we will be able to use the same helpers
with sve. This also fixes a bug in which we failed to clear
the high bits of the SVE register after an AdvSIMD operation.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 ++
target/arm/translate-a64.h | 2 ++
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
target/arm/sve.decode | 4
target/arm/translate-sve.c | 20
3 files changed, 29 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4f09dd42ba..0a7c68843b 100644
---
Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared. Which fixes
an existing bug.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 15 +
target/arm/crypto_helper.c | 37 +++
With this conversion, we will be able to use the same helpers
with sve. This also fixes a bug in which we failed to clear
the high bits of the SVE register after an AdvSIMD operation.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 6 ++--
target/arm/vec_internal.h | 10
Stephen, what I was looking for when I talked about modifying
the existing helpers is patch 1, which simplifies the final 3
patches for the new SVE2 insns.
In the process I found that the existing implementation of the
AdvSIMD insns is buggy wrt SVE. We need to clear the bits in
the Zreg
Users may need to check the xbzrle encoding rate to know if the guest
memory is xbzrle encoding-friendly, and dynamically turn off the
encoding if the encoding rate is low.
Signed-off-by: Yi Sun
Signed-off-by: Wei Wang
---
migration/migration.c | 1 +
migration/ram.c | 39
Patchew URL:
https://patchew.org/QEMU/20200429200754.18327-1-alex.ben...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200429200754.18327-1-alex.ben...@linaro.org
Subject: [RFC PATCH v2] plugins: new lockstep plugin
On Wed, Apr 29, 2020 at 10:13:01PM +0800, Eric Blake wrote:
> [meta-comment]
>
> On 4/29/20 4:35 AM, Yan Zhao wrote:
> > On Wed, Apr 29, 2020 at 04:22:01PM +0800, Dr. David Alan Gilbert wrote:
> [...]
> > This patchset introduces a migration_version attribute
> >
On Wed, Apr 29, 2020 at 05:48:44PM +0800, Dr. David Alan Gilbert wrote:
> > > > > > > > > > > > > An mdev type is meant to define a software compatible
> > > > > > > > > > > > > interface, so in
> > > > > > > > > > > > > the case of mdev->mdev migration, doesn't migrating
> > > > > > > > > > >
Question, in hard-float, if we don't want to read the fp register.
for example: If we wanna compute c = a + b in fp32
if c = a + b In hard float
and if b1 = c - a in hard float
if b1 != b at bitwise level, the we se the inexat to 1, otherwsie
we set inexat bit to 0? are this valid?
we can also do
Patchew URL: https://patchew.org/QEMU/20200429141126.85159-1-mre...@redhat.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
Patchew URL: https://patchew.org/QEMU/20200429141126.85159-1-mre...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Patchew URL: https://patchew.org/QEMU/20200429173352.29442-1-phi...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On Wed, Apr 29, 2020 at 7:57 PM Alex Bennée wrote:
>
> Dino Papararo writes:
>
> > Hello,
> > about handling of PPC fpu exceptions and Hard Floats support we could
> consider a different approach for different instructions.
> > i.e. not all fpu instructions take care about inexact or exceptions
Patchew URL: https://patchew.org/QEMU/20200429173352.29442-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Prepare bdrv_aligned_pwritev() now (and convert the
dependencies: bdrv_co_write_req_prepare() and
bdrv_co_write_req_finish() to signed type bytes)
Kindly ping to merge this patch.
For more detail. This patch creates a dtb entry to load the optee
driver which is needed for secure boot (atf+optee+uboot+linux). Kernel
part is already there:
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Prepare bdrv_co_do_pwrite_zeroes() now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/io.c | 6 +++---
1 file changed, 3 insertions(+), 3
> Your change just made it true for whenever virtulisation is enabled
> (in which case we don't need it).
This is exactly my point. As I said in the commit message, the spec
clearly tells us that "Interrupts for higher-privilege modes, y>x, are
always globally enabled regardless of the setting of
Hi,
I encountered the following error on the QEMU 5.0.0 release, compiled and run
inside a docker image:
"cannot bind memory to host NUMA nodes: Operation not permitted"
The QEMU command line to reproduce this behavior:
qemu-system-i386 -m 64 -M pc -smp 1 -display none -monitor stdio -drive
Laurent Vivier writes:
> Le 29/04/2020 à 11:26, Alex Bennée a écrit :
>>
>> Laurent Vivier writes:
>>
>>> Le 28/04/2020 à 20:43, Alex Bennée a écrit :
KONRAD Frederic writes:
> The MC68881 say about infinities (3.2.4):
>
> "*For the extended precision format, the
Hi,
I encountered the following error message on the QEMU 5.0.0 release, compiled
and run inside a docker image:
"cannot bind memory to host NUMA nodes: Operation not permitted"
The QEMU command line to reproduce this behavior (it happens also on -x86_64,
-arm, -aarch64 with similar command
> >
> > are available in the Git repository at:
> >
> > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200429-1
> >
> > for you to fetch changes up to 23766b6a35d5b1664ab782c02624bf2435c4ed5d:
> >
From: LIU Zhiwei
As struct target_ucontext will be transfered to signal handler, it
must keep pace with struct ucontext_t defined in Linux kernel.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-id: 20200412020830.607-1-zhiwei_...@c-sky.com
Message-Id:
From: Anup Patel
This patch adds an optional function pointer, "sym_cb", to
riscv_load_firmware() which provides the possibility to access
the symbol table during kernel loading.
The pointer is ignored, if supplied with flat (non-elf) firmware image.
The Spike board requires it locate the HTIF
From: Corey Wharton
Allows the CPU to be changed from the default via the -cpu command
line option.
Signed-off-by: Corey Wharton
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20200313193429.8035-2-core...@fb.com
Message-Id:
From: Bin Meng
32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32".
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 1583585319-26603-1-git-send-email-bmeng...@gmail.com
Message-Id: <1583585319-26603-1-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair
From: Anup Patel
Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.
The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.
Signed-off-by: Anup Patel
Reviewed-by:
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Tested-by: Anup Patel
Message-id:
From: Anup Patel
This patch extends Spike machine support to allow loading OpenSBI
firmware (fw_jump.elf) separately using -bios option.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Message-id: 20200427080644.168461-3-anup.pa...@wdc.com
Message-Id:
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same
From: Anup Patel
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
is required to handle the 34bit intermediate physical address coming
from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2
From: Corey Wharton
The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.
Signed-off-by: Corey Wharton
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id: 20200313193429.8035-3-core...@fb.com
Message-Id:
Split the file into clear machine and SoC sections.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/sifive_u.c | 108 ++--
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index
From: Bin Meng
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and
When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Tested-by: Anup Patel
Message-id:
-20200429-2
for you to fetch changes up to 31e6d70485b1a719ca27e9a2d21f2a61ac497cdf:
hw/riscv/spike: Allow more than one CPUs (2020-04-29 13:16:38 -0700)
RISC-V pull request for 5.1
This is the first pull request for the 5.1
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Convert driver wrappers parameters which are
already 64bit to signed type.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/io.c | 8
When we make changes to the TCG we sometimes cause regressions that
are deep into the execution cycle of the guest. Debugging this often
requires comparing large volumes of trace information to figure out
where behaviour has diverged.
The lockstep plugin utilises a shared socket so two QEMU's
qemu.git tags/pull-riscv-to-apply-20200429-1
>
> for you to fetch changes up to 23766b6a35d5b1664ab782c02624bf2435c4ed5d:
>
> hw/riscv/spike: Allow more than one CPUs (2020-04-29 11:23:44 -0700)
>
>
> RISC-V pu
On Wed, 29 Apr 2020 at 08:23, Markus Armbruster wrote:
>
> The following changes since commit fdd76fecdde1ad444ff4deb7f1c4f7e4a1ef97d6:
>
> Update version for v5.0.0 release (2020-04-28 17:46:57 +0100)
>
> are available in the Git repository at:
>
> git://repo.or.cz/qemu/armbru.git
This patch adds a flag to enable the SafeStack instrumentation provided
by LLVM.
The checks make sure that the compiler supports the flags, and that we
are using the proper coroutine implementation (coroutine-ucontext).
While SafeStack is supported only on Linux, NetBSD, FreeBSD and macOS,
we are
LLVM's SafeStack instrumentation cannot be used inside signal handlers
that make use of sigaltstack().
Since coroutine-sigaltstack relies on sigaltstack(), it is not
compatible with SafeStack. The resulting binary is incorrect, with
different coroutines sharing the same unsafe stack and producing
SafeStack is a stack protection technique implemented in llvm. It is
enabled with a -fsanitize flag.
iotests are currently disabled when any -fsanitize option is used.
Since SafeStack is useful on production environments, and its
implementation may break the binary, filter it out when the check is
LLVM's SafeStack instrumentation does not yet support programs that make
use of the APIs in ucontext.h
With the current implementation of coroutine-ucontext, the resulting
binary is incorrect, with different coroutines sharing the same unsafe
stack and producing undefined behavior at runtime.
This
LLVM supports SafeStack instrumentation to protect against stack buffer
overflows, since version 3.7
>From https://clang.llvm.org/docs/SafeStack.html:
"It works by separating the program stack into two distinct regions: the
safe stack and the unsafe stack. The safe stack stores return addresses,
On 04/29/20 13:52, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> hw/display/ramfb.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/display/ramfb.c b/hw/display/ramfb.c
> index eb8b4bc49a2f..be884c9ea837 100644
> --- a/hw/display/ramfb.c
> +++
On 4/27/20 3:23 AM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Convert bdrv_check_byte_request() now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/io.c | 6 +++---
1 file changed, 3 insertions(+), 3
On 4/29/20 11:36 AM, Daniel P. Berrangé wrote:
> The flake8 program is a standard tool used by Python projects for
> validating many commonly recommended style rules. It would be desirable
> for QEMU to come into alignment with normal Python coding style best
> practices.
>
> QEMU currently
Patchew URL: https://patchew.org/QEMU/20200429141126.85159-1-mre...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Hi Phil,
On Tue, Apr 28, 2020 at 12:06 AM Philippe Mathieu-Daudé
wrote:
> Hi Paul,
>
> On 4/28/20 4:22 AM, Paul Zimmerman wrote:
> > Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
> > emulation. It is very basic, only providing the FIQ interrupt
> > needed to allow the dwc-otg USB
Patchew URL: https://patchew.org/QEMU/20200429141126.85159-1-mre...@redhat.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
Patchew URL: https://patchew.org/QEMU/20200429141126.85159-1-mre...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On Wed, Apr 29, 2020 at 9:07 AM Jose Martins wrote:
>
> > If the Hypervisor sets the V* interrupts why does it then want to
> > receive the interrupt itself?
>
> I don't think this is a question of whether there is a use case for it
> or not (I agree with you, of the top of my head I don't see
Hi Daniel,
here is a patch for keycodemapdb. With this patch I have a working '<' key (the
key right of the left shift key on my german keyboard) in my qemu -display gtk
guests on Windows.
With best regards,
Volker
On 3/30/20 2:03 PM, Peter Maydell wrote:
> The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
> use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
> call it in S1_ptw_translate().
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/helper.c | 5 +++--
> 1
On 3/30/20 2:03 PM, Peter Maydell wrote:
> For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
> whether the stage 1 access is for EL0 or not, because whether
> exec permission is given can depend on whether this is an EL0
> or EL1 access. Add a new argument to get_phys_addr_lpae() so
>
The win32 keycode for VK_OEM_102 is 0xe2. The Microsoft docu-
mentation for virtual-key codes agrees with mingw32/winuser.h.
Signed-off-by: Volker Rümelin
---
data/keymaps.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/data/keymaps.csv b/data/keymaps.csv
index
From: Anup Patel
Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.
The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.
Signed-off-by: Anup Patel
Reviewed-by:
On 3/30/20 2:03 PM, Peter Maydell wrote:
> We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
> TLB. However we never actually use the TLB -- all stage 2 lookups
> are done by direct calls to get_phys_addr_lpae() followed by a
> physical address load via address_space_ld*().
>
>
1 - 100 of 406 matches
Mail list logo
