[PATCH] hw/m68k/mcf5206: Replace remaining hw_error()s by qemu_log_mask()

2020-06-10 Thread Thomas Huth
hw_error() dumps the CPU state and exits QEMU. This is ok during initial code development (to see where the guest code is currently executing), but it is certainly not the desired behavior that we want to present to normal users, and it can also cause trouble when e.g. fuzzing devices. Thus let's

[RFC PATCH 1/3] fuzz: add a general fuzzer for any qemu arguments

2020-06-10 Thread Alexander Bulekov
Signed-off-by: Alexander Bulekov --- tests/qtest/fuzz/Makefile.include | 1 + tests/qtest/fuzz/general_fuzz.c | 454 ++ 2 files changed, 455 insertions(+) create mode 100644 tests/qtest/fuzz/general_fuzz.c diff --git a/tests/qtest/fuzz/Makefile.include

[RFC PATCH 2/3] fuzz: add support for fuzzing DMA regions

2020-06-10 Thread Alexander Bulekov
Signed-off-by: Alexander Bulekov --- tests/qtest/fuzz/general_fuzz.c | 102 1 file changed, 102 insertions(+) diff --git a/tests/qtest/fuzz/general_fuzz.c b/tests/qtest/fuzz/general_fuzz.c index 5c29306bb6..9e981e870f 100644 --- a/tests/qtest/fuzz/general_fuzz.c

Re: [PATCH v4 0/5] modify CPU model info

2020-06-10 Thread Chenyi Qiang
Ping for comments. Ignore the last patch("remove Icelake-Client CPU model"). Robert is working on the CPU model deprecation API in https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg03109.html On 5/20/2020 10:10 AM, Chenyi Qiang wrote: Add the missing VMX features in Skylake-Server,

Re: [PATCH V2] virtio-pci: fix queue_enable write

2020-06-10 Thread Jason Wang
On 2020/6/10 下午5:52, Stefano Garzarella wrote: On Wed, Jun 10, 2020 at 05:42:54AM -0400, Michael S. Tsirkin wrote: On Wed, Jun 10, 2020 at 10:57:26AM +0200, Stefano Garzarella wrote: On Wed, Jun 10, 2020 at 01:43:51PM +0800, Jason Wang wrote: Spec said: The driver uses this to selectively

[PATCH v2 2/2] Mark Icelake-Client CPU models deprecated

2020-06-10 Thread Robert Hoo
Going to obsolete Icelake-Client CPU models in the future. (No changes in v2) Signed-off-by: Robert Hoo --- target/i386/cpu.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0d8638a..47a11b5 100644 ---

[PATCH v2 1/2] Introduce (x86) CPU model deprecation API

2020-06-10 Thread Robert Hoo
Complement versioned CPU model framework with the ability of marking some versions deprecated. When that CPU model is chosen, get some warning. The warning message is customized, e.g. telling in which future QEMU version will it be obsoleted. The deprecation message will also appear by

Re: [PATCH v9 39/61] target/riscv: vector floating-point compare instructions

2020-06-10 Thread LIU Zhiwei
On 2020/6/11 1:33, Richard Henderson wrote: On 6/10/20 4:37 AM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Richard Henderson --- Missed the actual "Reviewed-by:" :-) I tried to make a reasonable explanation, but failed:-). "Reviewed-by: " is really what I

[PATCH v2 4/4] riscv: Keep the CPU init routine names consistent

2020-06-10 Thread Bin Meng
From: Bin Meng Adding a _ to keep some consistency among the CPU init routines. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) target/riscv/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c

[PATCH v2 3/4] riscv: Generalize CPU init routine for the imacu CPU

2020-06-10 Thread Bin Meng
From: Bin Meng There is no need to have two functions that have almost the same codes for 32-bit and 64-bit imacu CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - Change the function names to rvxx_* target/riscv/cpu.c | 31 ++- 1

[PATCH v2 1/4] riscv: Generalize CPU init routine for the base CPU

2020-06-10 Thread Bin Meng
From: Bin Meng There is no need to have two functions that have exactly the same codes for 32-bit and 64-bit base CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) target/riscv/cpu.c | 18 +- 1 file changed, 5 insertions(+), 13

[PATCH v2 2/4] riscv: Generalize CPU init routine for the gcsu CPU

2020-06-10 Thread Bin Meng
From: Bin Meng There is no need to have two functions that have almost the same codes for 32-bit and 64-bit gcsu CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - Change the function names to rvxx_* target/riscv/cpu.c | 20 ++-- 1 file

[PATCH] hw/nios2: Update interrupt request when CR_STATUS_PIE disabled

2020-06-10 Thread wentongw
Update interrupt request when external interupt pends for STATUS_PIE disabled. Otherwise on icount enabled nios2 target there will be cpu abort when guest code changes state register with wrctl instruction. Signed-off-by: Wentong Wu --- hw/nios2/cpu_pic.c | 2 ++ 1 file changed, 2 insertions(+)

Re: [PATCH 1/1] MAINTAINERS: Adjust sh4 maintainership

2020-06-10 Thread Aleksandar Markovic
чет, 11. јун 2020. у 00:51 Philippe Mathieu-Daudé је написао/ла: > > On 6/11/20 12:17 AM, Aleksandar Markovic wrote: > > This patch transfers sh4 sections to Yoshinori Sato, who is best > > positioned in the community to assume their maintainership. > >

Re: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

2020-06-10 Thread Alistair Francis
On Fri, May 29, 2020 at 4:48 AM Anup Patel wrote: > > We add common helper routines which can be shared by RISC-V > multi-socket NUMA machines. > > We have two types of helpers: > 1. riscv_socket_xyz() - These helper assist managing multiple >sockets irrespective whether QEMU NUMA is

Re: [PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

2020-06-10 Thread Alistair Francis
On Fri, May 29, 2020 at 4:49 AM Anup Patel wrote: > > We extend RISC-V virt machine to allow creating a multi-socket > machine. Each RISC-V virt machine socket is a NUMA node having > a set of HARTs, a memory instance, a CLINT instance, and a PLIC > instance. Other devices are shared between all

[Bug 1881645] Re: qemu-system-x86_64 --help (or --version) gives no output

2020-06-10 Thread Adriano Pinaffo
** Description changed: - I have Arch Linux with qemu 5.0.0-6 (seen with pacman). Running VMs work just fine, but when I run qemu-system-x86_64 --version or qemu-system-x86_64 --help, there is no feedback on the screen. This behavior messes up other applications (GNS3 in my case that cannot

[Bug 1882671] Re: qemu-system-x86_64 (ver 4.2) stuck at boot with OVMF bios

2020-06-10 Thread Laszlo Ersek (Red Hat)
Hi Vlad, the ipxe-qemu package in Ubuntu (1.0.0+git-20190109.133f4c4-0ubuntu3) is built with DOWNLOAD_PROTO_HTTPS enabled (in "src/config/general.h"). According to the Ubuntu changelog, this is a new feature added in "1.0.0+git-20190109.133f4c4-0ubuntu1". With DOWNLOAD_PROTO_HTTPS enabled, I can

Re: [PATCH 4/4] riscv: Keep the CPU init routine names consistent

2020-06-10 Thread Alistair Francis
On Fri, Jun 5, 2020 at 12:44 AM Bin Meng wrote: > > From: Bin Meng > > Adding a _ to keep some consistency among the CPU init routines. We now differ from the actual ISA strings, but as these are internal functions I don't think it matters. This seems clearer. > > Signed-off-by: Bin Meng

Re: [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU

2020-06-10 Thread Alistair Francis
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng wrote: > > From: Bin Meng > > There is no need to have two functions that have almost the same > codes for 32-bit and 64-bit imacu CPUs. > > Signed-off-by: Bin Meng > --- > > target/riscv/cpu.c | 31 ++- > 1 file changed, 10

Re: [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU

2020-06-10 Thread Alistair Francis
On Fri, Jun 5, 2020 at 12:42 AM Bin Meng wrote: > > From: Bin Meng > > There is no need to have two functions that have almost the same > codes for 32-bit and 64-bit gcsu CPUs. > > Signed-off-by: Bin Meng > --- > > target/riscv/cpu.c | 20 ++-- > 1 file changed, 6

Re: [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU

2020-06-10 Thread Alistair Francis
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng wrote: > > From: Bin Meng > > There is no need to have two functions that have exactly the same > codes for 32-bit and 64-bit base CPUs. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > target/riscv/cpu.c | 18

Re: [PATCH v8 00/34] Add subcluster allocation to qcow2

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/cover.1591801197.git.be...@igalia.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH 1/1] MAINTAINERS: Adjust sh4 maintainership

2020-06-10 Thread Philippe Mathieu-Daudé
On 6/11/20 12:17 AM, Aleksandar Markovic wrote: > This patch transfers sh4 sections to Yoshinori Sato, who is best > positioned in the community to assume their maintainership. https://www.mail-archive.com/qemu-devel@nongnu.org/msg708235.html "BTW, you also dictate there Yoshimoto that to do and

Re: [PATCH] net: tulip: Set PCI revision to match dec21143

2020-06-10 Thread Marek Vasut
On 6/11/20 12:27 AM, Philippe Mathieu-Daudé wrote: > On 6/10/20 11:13 PM, Sven Schnelle wrote: >> On Mon, Jun 08, 2020 at 12:17:11AM +0200, Philippe Mathieu-Daudé wrote: >>> Hi Sven, could you review thiw one-line patch? >>> >>> On 4/18/20 2:25 AM, Marek Vasut wrote: The tulip driver

Re: [PATCH v3 01/11] MAINTAINERS: Mark SH4 section orphan

2020-06-10 Thread Aleksandar Markovic
чет, 11. јун 2020. у 00:08 Philippe Mathieu-Daudé је написао/ла: > > Aurelien Jarno expressed his desire to orphan the SH4 section [*]: > > I don't mind being [...] removed from there. > I do not really have time to work on that. > > Mark the SH4 section orphan. > > Many thanks to Aurelien

Re: [PATCH] net: tulip: Set PCI revision to match dec21143

2020-06-10 Thread Philippe Mathieu-Daudé
On 6/10/20 11:13 PM, Sven Schnelle wrote: > On Mon, Jun 08, 2020 at 12:17:11AM +0200, Philippe Mathieu-Daudé wrote: >> Hi Sven, could you review thiw one-line patch? >> >> On 4/18/20 2:25 AM, Marek Vasut wrote: >>> The tulip driver claims to emulate dec21143 and it does not emulate >>>

Re: [PATCH v1 2/2] sifive_e: Support the revB machine

2020-06-10 Thread Alistair Francis
On Thu, May 28, 2020 at 11:13 AM Alistair Francis wrote: > > On Thu, May 21, 2020 at 8:57 AM Alistair Francis wrote: > > > > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt wrote: > > > > > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote: > > > > Signed-off-by: Alistair

[PATCH v6 4/6] riscv/opentitan: Connect the PLIC device

2020-06-10 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- include/hw/riscv/opentitan.h | 3 +++ hw/riscv/opentitan.c | 19 +-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/opentitan.h

[PATCH v6 1/6] riscv/opentitan: Fix the ROM size

2020-06-10 Thread Alistair Francis
Signed-off-by: Alistair Francis Reported-by: Damien Hedde --- hw/riscv/opentitan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index b4fb836466..6c7359c190 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -30,7

[PATCH v6 6/6] target/riscv: Use a smaller guess size for no-MMU PMP

2020-06-10 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/pmp.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 0e6b640fbd..9418660f1b 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@

[PATCH v6 5/6] riscv/opentitan: Connect the UART device

2020-06-10 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- include/hw/riscv/opentitan.h | 13 + hw/riscv/opentitan.c | 24 ++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git

[PATCH v6 0/6] RISC-V Add the OpenTitan Machine

2020-06-10 Thread Alistair Francis
OpenTitan is an open source silicon Root of Trust (RoT) project. This series adds initial support for the OpenTitan machine to QEMU. This series add the Ibex CPU to the QEMU RISC-V target. It then adds the OpenTitan machine, the Ibex UART and the Ibex PLIC. The UART has been tested sending and

[PATCH v6 3/6] hw/intc: Initial commit of lowRISC Ibex PLIC

2020-06-10 Thread Alistair Francis
The Ibex core contains a PLIC that although similar to the RISC-V spec is not RISC-V spec compliant. This patch implements a Ibex PLIC in a somewhat generic way. As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex PLIC move towards spec compliance this PLIC implementation

[PATCH v6 2/6] hw/char: Initial commit of Ibex UART

2020-06-10 Thread Alistair Francis
This is the initial commit of the Ibex UART device. Serial TX is working, while RX has been implemeneted but untested. This is based on the documentation from: https://docs.opentitan.org/hw/ip/uart/doc/ Signed-off-by: Alistair Francis Reviewed-by: LIU Zhiwei --- include/hw/char/ibex_uart.h |

[PATCH v3 11/11] .travis.yml: Test SH4 QEMU advent calendar image

2020-06-10 Thread Philippe Mathieu-Daudé
From: Thomas Huth Now that we can select the second serial console in the acceptance tests (see commit 746f244d9720 "Allow to use other serial consoles than default"), we can also test the sh4 image from the QEMU advent calendar 2018. Signed-off-by: Thomas Huth Reviewed-by: Philippe

[PATCH v3 10/11] tests/acceptance: Add boot tests for sh4 QEMU advent calendar image

2020-06-10 Thread Philippe Mathieu-Daudé
From: Thomas Huth Now that we can select the second serial console in the acceptance tests (see commit 746f244d9720 "Allow to use other serial consoles than default"), we can also test the sh4 image from the QEMU advent calendar 2018. Signed-off-by: Thomas Huth Reviewed-by: Philippe

[PATCH 0/1] Resolution of sh4 maintainership

2020-06-10 Thread Aleksandar Markovic
This series consists of a single patch that introduces a new maintainer for sh4 target. He may or may not adjust further the details of sh4 sections, with recent discussions in mind. The idea is that noone imposes his particular vision on the new maintainer person, but that we let him organize

[PATCH 1/1] MAINTAINERS: Adjust sh4 maintainership

2020-06-10 Thread Aleksandar Markovic
This patch transfers sh4 sections to Yoshinori Sato, who is best positioned in the community to assume their maintainership. He is the maintainer of the related target rx. Further adjustments, reorganizations, and improvements of sh4 sections are left to the future maintainer to be devised and

[PATCH v3 08/11] hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'

2020-06-10 Thread Philippe Mathieu-Daudé
Extract timer definitions to 'hw/timer/tmu012.h'. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sh4/sh.h | 9 - include/hw/timer/tmu012.h | 23 +++ hw/sh4/sh7750.c | 1 + hw/timer/sh_timer.c | 2 ++ 4

[PATCH v3 06/11] MAINTAINERS: Add Yoshinori Sato as maintainer of Renesas peripherals

2020-06-10 Thread Philippe Mathieu-Daudé
Renesas peripherals are common to SH4/RX based MCUs. Their datasheets share common sections. It makes sense to maintain them altogether. Yoshinori Sato volonteered to maintain them [*]. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg710928.html Cc: Magnus Damm Cc: Yoshinori Sato

[PATCH v3 04/11] MAINTAINERS: Cover 'hw/sh4/sh_intc.h' with the R2D machine

2020-06-10 Thread Philippe Mathieu-Daudé
Commit 81527b94ad added hw/intc/sh_intc.c, complete by adding its corresponding header. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index e4e27acd26..653fca1da8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@

[PATCH v3 05/11] MAINTAINERS: Add an entry for common Renesas peripherals

2020-06-10 Thread Philippe Mathieu-Daudé
Renesas peripherals are common to SH4/RX based MCUs. Their datasheets share common sections. It makes sense to maintain them altogether. The current names are misleading (see the 'sh' prefix). This will be fixed later when RX peripherals will be added. Cc: Magnus Damm Cc: Yoshinori Sato

[PATCH v3 09/11] hw/timer/sh_timer: Remove unused 'qemu/timer.h' include

2020-06-10 Thread Philippe Mathieu-Daudé
Remove unused "qemu/timer.h" include. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index b9cbacf5d0..bb0e1c8ee5 100644 --- a/hw/timer/sh_timer.c +++

[PATCH v3 00/11] sh4: Update MAINTAINERS & trivial fixes

2020-06-10 Thread Philippe Mathieu-Daudé
Hi, This series clarifies the situation of the SH4 TCG target and peripherals. Since v2: - Keep Magnus as maintainer: https://www.mail-archive.com/qemu-devel@nongnu.org/msg710320.html Addressed Aleksandar review comments: - Split the MAINTAINER patch in various atomic units

[PATCH v3 03/11] MAINTAINERS: Demote SH4 based R2D machine to 'Odd Fixes'

2020-06-10 Thread Philippe Mathieu-Daudé
Magnus Damm doesn't have much time to maintain the R2D machine, but want to keep it [*]. Demote its status to 'Odd Fixes' so contributors won't expect Magnus to take the patches: Odd Fixes: It has a maintainer but they don't have time to do much other than throw the odd

[PATCH v3 02/11] MAINTAINERS: Mark SH4 based Shix machine orphan

2020-06-10 Thread Philippe Mathieu-Daudé
Magnus Damm doesn't have time to keep maintaining the Shix machine [*]. Mark it orphan, so volunteers can step in to maintain it. Orphan: No current maintainer [but maybe you could take the role as you write your new code]. Many thanks to Magnus for introducing this SH4

[PATCH v3 01/11] MAINTAINERS: Mark SH4 section orphan

2020-06-10 Thread Philippe Mathieu-Daudé
Aurelien Jarno expressed his desire to orphan the SH4 section [*]: I don't mind being [...] removed from there. I do not really have time to work on that. Mark the SH4 section orphan. Many thanks to Aurelien for his substantial contributions to QEMU, and for maintaining the SH4 emulation

[PATCH v3 07/11] hw/sh4: Use MemoryRegion typedef

2020-06-10 Thread Philippe Mathieu-Daudé
Use the MemoryRegion type defined in "qemu/typedefs.h", to keep the repository style consistent. Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sh4/sh.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git

Re: [PATCH v8 00/34] Add subcluster allocation to qcow2

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/cover.1591801197.git.be...@igalia.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH v2 1/1] virtio-ccw: auto-manage VIRTIO_F_IOMMU_PLATFORM if PV

2020-06-10 Thread Halil Pasic
On Wed, 10 Jun 2020 14:25:54 +1000 David Gibson wrote: > > > I'm going to definitely have a good look at that. What I think special > > > about s390 is that F_ACCESS_PLATFORM is hurting us because all IO needs > > > to go through ZONE_DMA (this is a problem of the implementation that > > >

Re: [PATCH 0/8] tpm: Split hw/ vs backends/

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200610200247.21378-1-phi...@redhat.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash

Re: [PATCH 0/8] tpm: Split hw/ vs backends/

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200610200247.21378-1-phi...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH] net: tulip: Set PCI revision to match dec21143

2020-06-10 Thread Sven Schnelle
On Mon, Jun 08, 2020 at 12:17:11AM +0200, Philippe Mathieu-Daudé wrote: > Hi Sven, could you review thiw one-line patch? > > On 4/18/20 2:25 AM, Marek Vasut wrote: > > The tulip driver claims to emulate dec21143 and it does not emulate > > dec21142. > > The dec21142 and dec21143 can be discerned

Re: [PATCH v2 1/8] MAINTAINERS: Mark SH4 hardware orphan

2020-06-10 Thread Philippe Mathieu-Daudé
On 6/10/20 1:08 PM, Aleksandar Markovic wrote: > пон, 8. јун 2020. у 11:05 Philippe Mathieu-Daudé је > написао/ла: >> >> Aurelien Jarno expressed his desire to orphan the SH4 hardware [*]: >> >> I don't mind being [...] removed from there. >> I do not really have time to work on that. >> >>

[PATCH v2 5/5] configure: Add -Wno-psabi

2020-06-10 Thread Richard Henderson
On aarch64, gcc 9.3 is generating qemu/exec.c: In function ‘address_space_translate_iommu’: qemu/exec.c:431:28: note: parameter passing for argument of type \ ‘MemTxAttrs’ {aka ‘struct MemTxAttrs’} changed in GCC 9.1 and many other reptitions. This structure, and the functions amongst which

[PATCH v2 1/5] fpu/softfloat: Silence 'bitwise negation of boolean expression' warning

2020-06-10 Thread Richard Henderson
From: Philippe Mathieu-Daudé When building with clang version 10.0.0-4ubuntu1, we get: CC lm32-softmmu/fpu/softfloat.o fpu/softfloat.c:3365:13: error: bitwise negation of a boolean expression; did you mean logical negation? [-Werror,-Wbool-operation] absZ &= ~ ( ( ( roundBits

[PATCH v2 4/5] configure: Disable -Wtautological-type-limit-compare

2020-06-10 Thread Richard Henderson
Clang 10 enables this by default with -Wtype-limit. All of the instances flagged by this Werror so far have been cases in which we really do want the compiler to optimize away the test completely. Disabling the warning will avoid having to add ifdefs to work around this. Cc: Eric Blake Fixes:

[PATCH v2 3/5] configure: Clean up warning flag lists

2020-06-10 Thread Richard Henderson
Use a helper function to tidy the assembly of gcc_flags. Separate flags that disable warnings from those that enable, and sort the disable warnings to the end. Suggested-by: Eric Blake Signed-off-by: Richard Henderson --- configure | 40 ++-- 1 file changed,

[PATCH v2 0/5] Vs clang-10 and gcc-9 warnings

2020-06-10 Thread Richard Henderson
Three of these patches are for cleaning up warnings vs clang-10. The -Wtautological-type-limit-compare patch has been improved as suggested by Eric Blake. The final patch is for a "new" warning from gcc-9 on aarch64 hosts. Our build box has been upgraded from bionic, so the warning is new to me,

[PATCH v2 2/5] migration: fix xbzrle encoding rate calculation

2020-06-10 Thread Richard Henderson
From: Wei Wang It's reported an error of implicit conversion from "unsigned long" to "double" when compiling with Clang 10. Simply make the encoding rate 0 when the encoded_size is 0. Fixes: e460a4b1a4 Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Richard Henderson Reported-by: Richard

Re: [PATCH v3 0/4] nbd: reduce max_block restrictions

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200610182305.3462-1-vsement...@virtuozzo.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT

Re: [PATCH v8 34/34] iotests: Add tests for qcow2 images with extended L2 entries

2020-06-10 Thread Eric Blake
On 6/10/20 10:03 AM, Alberto Garcia wrote: Signed-off-by: Alberto Garcia --- tests/qemu-iotests/271 | 801 + tests/qemu-iotests/271.out | 676 +++ tests/qemu-iotests/group | 1 + 3 files changed, 1478 insertions(+)

Re: [PATCH 0/8] tpm: Split hw/ vs backends/

2020-06-10 Thread Philippe Mathieu-Daudé
On 6/10/20 10:09 PM, Marc-André Lureau wrote: > Hi > > On Thu, Jun 11, 2020 at 12:03 AM Philippe Mathieu-Daudé > mailto:phi...@redhat.com>> wrote: > > Hi, > > Today I started to review some vTPM patches and got very > confused by the files under hw/tpm/. In particular after >

Re: [PATCH 0/8] tpm: Split hw/ vs backends/

2020-06-10 Thread Philippe Mathieu-Daudé
On 6/10/20 10:02 PM, Philippe Mathieu-Daudé wrote: > Hi, > > Today I started to review some vTPM patches and got very > confused by the files under hw/tpm/. In particular after > running: > > $ git grep TYPE_TPM_BACKEND > backends/tpm.c:188:.name = TYPE_TPM_BACKEND, >

Re: [PATCH 0/8] tpm: Split hw/ vs backends/

2020-06-10 Thread Marc-André Lureau
Hi On Thu, Jun 11, 2020 at 12:03 AM Philippe Mathieu-Daudé wrote: > Hi, > > Today I started to review some vTPM patches and got very > confused by the files under hw/tpm/. In particular after > running: > > $ git grep TYPE_TPM_BACKEND > backends/tpm.c:188:.name = TYPE_TPM_BACKEND, >

[PATCH 6/8] hw/tpm: Move DEFINE_PROP_TPMBE() macro to 'tmp_prop.h' local header

2020-06-10 Thread Philippe Mathieu-Daudé
We are going to make "tpm_util.h" publicly accessible by moving it to the include/ directory in the next commit. The DEFINE_PROP_TPMBE() macro is only meaningful for the TPM hardware files (in hw/tpm/), so keep this macro in a local header. Signed-off-by: Philippe Mathieu-Daudé ---

Re: [PATCH v7 0/9] acpi: i386 tweaks

2020-06-10 Thread Michael S. Tsirkin
On Wed, Jun 10, 2020 at 05:53:46PM +0200, Gerd Hoffmann wrote: > On Wed, Jun 10, 2020 at 10:54:26AM -0400, Michael S. Tsirkin wrote: > > On Wed, Jun 10, 2020 at 01:40:02PM +0200, Igor Mammedov wrote: > > > On Wed, 10 Jun 2020 11:41:22 +0200 > > > Gerd Hoffmann wrote: > > > > > > > First batch of

[RFC PATCH 8/8] tpm: Move backend code under the 'backends/' directory

2020-06-10 Thread Philippe Mathieu-Daudé
TPM subsytem is split into backends (see commit f4ede81eed2) and frontends (see i.e. 3676bc69b35). Keep the emulated hardware 'frontends' under hw/tpm/, but move the backends in the backends/ directory. Signed-off-by: Philippe Mathieu-Daudé --- RFC due to a FIXME in tpm_tis_common.c, it uses

[PATCH 3/8] hw/tpm: Move 'hw/acpi/tpm.h' inclusion from header to sources

2020-06-10 Thread Philippe Mathieu-Daudé
Nothing in "tpm_ppi.h" require declarations from "hw/acpi/tpm.h". Reduce dependencies and include it only in the files requiring it. Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_ppi.h| 1 - hw/tpm/tpm_tis_isa.c| 1 + hw/tpm/tpm_tis_sysbus.c | 1 + 3 files changed, 2

Re: [PATCH v8 00/34] Add subcluster allocation to qcow2

2020-06-10 Thread Eric Blake
On 6/10/20 10:02 AM, Alberto Garcia wrote: Hi, here's the new version of the patches to add subcluster allocation support to qcow2. Please refer to the cover letter of the first version for a full description of the patches:

[PATCH 2/8] hw/tpm: Include missing 'qemu/option.h' header

2020-06-10 Thread Philippe Mathieu-Daudé
Files using the TPM_STANDARD_CMDLINE_OPTS macro declared in "tpm_int.h" will use QEMU_OPT_STRING definition declared in "qemu/option.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_int.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/tpm/tpm_int.h b/hw/tpm/tpm_int.h index

[PATCH 7/8] hw/tpm: Make 'tpm_util.h' publicly accessible as "sysemu/tpm_util.h"

2020-06-10 Thread Philippe Mathieu-Daudé
We are going to split the TPM backends from the TPM emulated hardware in the next commit. Make the TPM util helpers accessible by moving local "tpm_util.h" to global "sysemu/tpm_util.h". Signed-off-by: Philippe Mathieu-Daudé --- {hw/tpm => include/sysemu}/tpm_util.h | 6 +++--- hw/tpm/tpm_crb.c

[PATCH 5/8] hw/tpm: Move few declarations from 'tpm_util.h' to 'tpm_int.h'

2020-06-10 Thread Philippe Mathieu-Daudé
We are going to make "tpm_util.h" publicly accessible by moving it to the include/ directory in a pair of commits. Keep declarations internals to hw/tpm/ in "tpm_int.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_int.h | 11 +++ hw/tpm/tpm_util.h | 10 -- 2 files

[PATCH 1/8] hw/tpm: Do not include 'qemu/osdep.h' in header

2020-06-10 Thread Philippe Mathieu-Daudé
>From CODING_STYLE.rst: Do not include "qemu/osdep.h" from header files since the .c file will have already included it. Remove "qemu/osdep.h" from "tpm_tis.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_tis.h | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/tpm/tpm_tis.h

Re: [PATCH] qcow2: Fix preallocation on images with unaligned sizes

2020-06-10 Thread Eric Blake
On 6/10/20 4:46 AM, Alberto Garcia wrote: When resizing an image with qcow2_co_truncate() using the falloc or full preallocation modes the code assumes that both the old and new sizes are cluster-aligned. There are two problems with this: 1) The calculation of how many clusters are involved

[PATCH 4/8] hw/tpm: Remove unnecessary 'tpm_int.h' header inclusion

2020-06-10 Thread Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_crb.c| 1 - hw/tpm/tpm_spapr.c | 1 - hw/tpm/tpm_tis_common.c | 1 - 3 files changed, 3 deletions(-) diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index cd004e7f8e..664ff70ef9 100644 --- a/hw/tpm/tpm_crb.c +++

[PATCH 0/8] tpm: Split hw/ vs backends/

2020-06-10 Thread Philippe Mathieu-Daudé
Hi, Today I started to review some vTPM patches and got very confused by the files under hw/tpm/. In particular after running: $ git grep TYPE_TPM_BACKEND backends/tpm.c:188:.name = TYPE_TPM_BACKEND, hw/tpm/tpm_emulator.c:985:.parent = TYPE_TPM_BACKEND,

Re: [PATCH] travis.yml: Test also the other targets on s390x

2020-06-10 Thread Alex Bennée
Thomas Huth writes: > s390x is our only big endian host in our CI, so building and testing QEMU > there is quite valuable. Thus let's also test the other targets with > additional jobs (also using different sets of pre-installed libraries to > get a better coverage of the things that we test).

Re: [PATCH v8 33/34] qcow2: Assert that expand_zero_clusters_in_l1() does not support subclusters

2020-06-10 Thread Eric Blake
On 6/10/20 10:03 AM, Alberto Garcia wrote: This function is only used by qcow2_expand_zero_clusters() to downgrade a qcow2 image to a previous version. It is however not possible to downgrade an image with extended L2 entries because older versions of qcow2 do not have this feature. Well, it

Re: [PATCH v8 32/34] qcow2: Allow preallocation and backing files if extended_l2 is set

2020-06-10 Thread Eric Blake
On 6/10/20 10:03 AM, Alberto Garcia wrote: Traditional qcow2 images don't allow preallocation if a backing file is set. This is because once a cluster is allocated there is no way to tell that its data should be read from the backing file. Extended L2 entries have individual allocation bits for

Re: [PATCH] migration: fix xbzrle encoding rate calculation

2020-06-10 Thread Dr. David Alan Gilbert
* Richard Henderson (richard.hender...@linaro.org) wrote: > On 6/7/20 5:53 PM, Wei Wang wrote: > > It's reported an error of implicit conversion from "unsigned long" to > > "double" when compiling with Clang 10. Simply make the encoding rate 0 > > when the encoded_size is 0. > > > > Fixes:

Re: [PATCH v2 3/6] linux-user: Add strace support for printing argument of syscalls used for extended attributes

2020-06-10 Thread Laurent Vivier
Le 08/06/2020 à 18:43, Filip Bozuta a écrit : > From: Filip Bozuta > > This patch implements strace argument printing functionality for following > syscalls: > > *getxattr, lgetxattr, fgetxattr - retrieve an extended attribute value > > ssize_t getxattr(const char *path, const

Re: [PATCH 2/2] qcow2: improve savevm performance - please ignore

2020-06-10 Thread Denis V. Lunev
On 6/10/20 9:58 PM, Denis V. Lunev wrote: > This patch does 2 standard basic things: > - it creates intermediate buffer for all writes from QEMU migration code > to QCOW2 image, > - this buffer is sent to disk asynchronously, allowing several writes to > run in parallel. > > In general,

[PATCH v2 0/2] qcow2: seriously improve savevm performance

2020-06-10 Thread Denis V. Lunev
This series do standard basic things: - it creates intermediate buffer for all writes from QEMU migration code to QCOW2 image, - this buffer is sent to disk asynchronously, allowing several writes to run in parallel. In general, migration code is fantastically inefficent (by observation),

[PATCH 1/2] aio: allow to wait for coroutine pool from different coroutine

2020-06-10 Thread Denis V. Lunev
The patch preserves the constraint that the only waiter is allowed. The patch renames AioTaskPool->main_co to wake_co and removes AioTaskPool->waiting flag. wake_co keeps coroutine, which is waiting for wakeup on worker completion. Thus 'waiting' flag in this semantics is equivalent to 'wake_co

Re: [PATCH 1/2] aio: allow to wait for coroutine pool from different coroutine - please ignore

2020-06-10 Thread Denis V. Lunev
On 6/10/20 9:58 PM, Denis V. Lunev wrote: > The patch preserves the constraint that the only waiter is allowed. > > The patch renames AioTaskPool->main_co to wake_co and removes > AioTaskPool->waiting flag. wake_co keeps coroutine, which is > waiting for wakeup on worker completion. Thus 'waiting'

[PATCH 2/2] qcow2: improve savevm performance

2020-06-10 Thread Denis V. Lunev
This patch does 2 standard basic things: - it creates intermediate buffer for all writes from QEMU migration code to QCOW2 image, - this buffer is sent to disk asynchronously, allowing several writes to run in parallel. In general, migration code is fantastically inefficent (by observation),

[PATCH 1/2] aio: allow to wait for coroutine pool from different coroutine

2020-06-10 Thread Denis V. Lunev
The patch preserves the constraint that the only waiter is allowed. The patch renames AioTaskPool->main_co to wake_co and removes AioTaskPool->waiting flag. wake_co keeps coroutine, which is waiting for wakeup on worker completion. Thus 'waiting' flag in this semantics is equivalent to 'wake_co

[PATCH 2/2] qcow2: improve savevm performance

2020-06-10 Thread Denis V. Lunev
This patch does 2 standard basic things: - it creates intermediate buffer for all writes from QEMU migration code to QCOW2 image, - this buffer is sent to disk asynchronously, allowing several writes to run in parallel. In general, migration code is fantastically inefficent (by observation),

[Bug 1882671] Re: qemu-system-x86_64 (ver 4.2) stuck at boot with OVMF bios

2020-06-10 Thread Vladislav K. Valtchev
Hi Laszlo, thanks for investigating the problem so rapidly. So, I downgraded the ipxe-qemu package from 1.0.0+git-20190109.133f4c4-0ubuntu3 (focal) to 1.0.0+git-20180124 .fbe8c52d-0ubuntu2 (bionic) and the problem completely disappeared. Your theory looks absolutely correct to me. For what it's

Re: [PATCH 0/2] qcow2: seriously improve savevm performance

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200610144129.27659-1-...@openvz.org/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!

Re: [PATCH 0/2] qcow2: seriously improve savevm performance

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200610144129.27659-1-...@openvz.org/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash export

[PATCH v3 4/4] block/io: auto-no-fallback for write-zeroes

2020-06-10 Thread Vladimir Sementsov-Ogievskiy
When BDRV_REQ_NO_FALLBACK is supported, the NBD driver supports a larger request size. Add code to try large zero requests with a NO_FALLBACK request prior to having to split a request into chunks according to max_pwrite_zeroes. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/io.c | 18

[PATCH v3 2/4] block/nbd: define new max_write_zero_fast limit

2020-06-10 Thread Vladimir Sementsov-Ogievskiy
The NBD spec was recently updated to clarify that max_block doesn't relate to NBD_CMD_WRITE_ZEROES with NBD_CMD_FLAG_FAST_ZERO (which mirrors Qemu flag BDRV_REQ_NO_FALLBACK). bs->bl.max_write_zero_fast is zero by default which means using max_pwrite_zeroes. Update nbd driver to allow larger

[PATCH v3 3/4] block/io: refactor bdrv_co_do_pwrite_zeroes head calculation

2020-06-10 Thread Vladimir Sementsov-Ogievskiy
It's wrong to update head using num in this place, as num may be reduced during the iteration (seems it doesn't, but it's not obvious), and we'll have wrong head value on next iteration. Instead update head at iteration end. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Eric Blake

[PATCH v3 1/4] block: add max_pwrite_zeroes_fast to BlockLimits

2020-06-10 Thread Vladimir Sementsov-Ogievskiy
The NBD spec was recently updated to clarify that max_block doesn't relate to NBD_CMD_WRITE_ZEROES with NBD_CMD_FLAG_FAST_ZERO (which mirrors Qemu flag BDRV_REQ_NO_FALLBACK). To drop the restriction we need new max_pwrite_zeroes_fast. Default value of new max_pwrite_zeroes_fast is zero and it

[PATCH v3 0/4] nbd: reduce max_block restrictions

2020-06-10 Thread Vladimir Sementsov-Ogievskiy
Recent changes in NBD protocol allowed to use some commands without max_block restriction. Let's drop the restrictions. NBD change is here: https://github.com/NetworkBlockDevice/nbd/commit/9f30fedb8699f151e7ef4ccc07e624330be3316b#diff-762fb7c670348da69cc9050ef58fe3ae v3: first two patches from

Re: [PATCH 0/2] qcow2: seriously improve savevm performance

2020-06-10 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200610144129.27659-1-...@openvz.org/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH 3/3] spapr: Forbid nested KVM-HV in pre-power9 compat mode

2020-06-10 Thread Vladimir Sementsov-Ogievskiy
10.06.2020 20:17, Greg Kurz wrote: Nested KVM-HV only works on POWER9. Worth mention that existing usage of error_append_hint in the function is fixed too by this patch? Signed-off-by: Greg Kurz --- hw/ppc/spapr_caps.c | 11 +++ 1 file changed, 11 insertions(+) diff --git

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