>From 'Application Note AN521', chapter 4.7:
The SMM implements four SBCon serial modules:
One SBCon module for use by the Color LCD touch interface.
One SBCon module to configure the audio controller.
Two general purpose SBCon modules, that connect to the
Expansion headers J7 and J8,
Signed-off-by: Philippe Mathieu-Daudé
---
v2: 25MHz prescale-clk property
---
hw/arm/mps2.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index c66c595d4a..e106123225 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -38,8 +38,10 @@
#include
We already model the CMSDK APB watchdog device, let's use it!
Suggested-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Use existing TYPE_CMSDK_APB_WATCHDOG (pm215)
---
hw/arm/mps2.c | 7 +++
hw/arm/Kconfig | 1 +
2 files changed, 8 insertions(+)
diff --git
>From 'Application Note AN385', chapter 3.14:
The SMM implements a simple SBCon interface based on I2C.
There are 4 SBCon interfaces on the FPGA APB subsystem.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/mps2.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/mps2.c
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/mps2.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index daa55f730b..ee555f919d 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -65,7 +65,9 @@ typedef struct {
MemoryRegion
Register the GPIO peripherals as unimplemented to better
follow their accesses, for example booting Zephyr:
IN: arm_mps2_pinmux_init
0x1160: f64f 0231 movw r2, #0xf831
0x1164: 4b06 ldr r3, [pc, #0x18]
0x1166: 2000 movs r0, #0
'ARM SBCon two-wire serial bus interface' is the official
name describing the pair of registers used to bitbanging
I2C in the Versatile boards.
Make the private VersatileI2CState structure as public
ArmSbconI2CState.
Add the TYPE_ARM_SBCON_I2C, alias to our current
TYPE_VERSATILE_I2C model.
To differenciate with the CMSDK APB peripheral region,
rename this region 'CMSDK AHB peripheral region'.
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/mps2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index
Use self-explicit definitions instead of magic values.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i2c/versatile_i2c.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index 1ac2a6f59a..040139d701 100644
---
Use self-explicit definitions instead of magic values.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i2c/versatile_i2c.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index 040139d701..0ce10a1bcc 100644
---
Add a trace event to see when a guest disable/enable the watchdog.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/watchdog/cmsdk-apb-watchdog.c | 1 +
hw/watchdog/trace-events | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c
Few patches while playing with Zephyr on the MPS2:
- clean 'versatile_i2c' a bit,
- describe it as 'ARM SBCon two-wire serial bus interface'
which is common on the ARM documentation,
- add watchdog
- added fpgaio with correct prescale clk
- added i2c and spi
- added gpio/i2s as unimp
- dropped
By using the TYPE_* definitions for devices, we can:
- quickly find where devices are used with 'git-grep'
- easily rename a device (one-line change).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c| 3 ++-
hw/arm/versatilepb.c | 3 ++-
hw/arm/vexpress.c| 3 ++-
3 files
среда, 17. јун 2020., Ahmed Karaman је
написао/ла:
> This new section includes the 'Performance Tools and Tests' subsection
> which will contain the the performance scripts and benchmarks written
> as a part of the 'TCG Continuous Benchmarking' project.
>
> Signed-off-by: Ahmed Karaman
> ---
** Summary changed:
- qemu system emulator crashed with the attachment of usb-bt-dongle device
+ qemu system emulator crashed when using xhci usb controller
** Tags added: usb xhci
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
From: Prasad J Pandit
Add nrf51_soc mmio read method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun
Signed-off-by: Prasad J Pandit
---
hw/nvram/nrf51_nvm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c
index
From: Prasad J Pandit
Add vfio quirk device mmio write method to avoid NULL pointer
dereference issue.
Reported-by: Lei Sun
Signed-off-by: Prasad J Pandit
---
hw/vfio/pci-quirks.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index
среда, 17. јун 2020., Ahmed Karaman је
написао/ла:
> Python script that prints the top 25 most executed functions in QEMU
> using callgrind.
>
> Signed-off-by: Ahmed Karaman
> ---
I think you should add an example of script usage in the commit message
(even though you mention such example in
From: Prasad J Pandit
Add spapr msi mmio read method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun
Signed-off-by: Prasad J Pandit
---
hw/ppc/spapr_pci.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index
From: Prasad J Pandit
Add pci-intack mmio write method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun
Signed-off-by: Prasad J Pandit
---
hw/pci-host/prep.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index
From: Prasad J Pandit
Add ppc-parity mmio write method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun
Signed-off-by: Prasad J Pandit
---
hw/ppc/prep_systemio.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
index
From: Prasad J Pandit
Add pcie-msi mmio read method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun
Signed-off-by: Prasad J Pandit
---
hw/pci-host/designware.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index
From: Prasad J Pandit
Hello,
This series adds various undefined MMIO read/write functions
to avoid potential guest crash via a NULL pointer dereference.
ex. ->
https://git.qemu.org/?p=qemu.git;a=commit;h=bb15013ef34617eb1344f5276292cadd326c21b2
Thank you.
--
Prasad J Pandit (6):
среда, 17. јун 2020., Ahmed Karaman је
написао/ла:
> This new section includes the 'Performance Tools and Tests' subsection
> which will contain the the performance scripts and benchmarks written
> as a part of the 'TCG Continuous Benchmarking' project.
>
> Signed-off-by: Ahmed Karaman
> ---
>
We had the 14 (instead f 7) days in -proposed for some extended maturing.
Nothing came up in regard to this and all validations were good.
Dropping block-proposed to be released once the SRU Team gets to it.
** Tags removed: block-proposed-bionic block-proposed-eoan block-
proposed-focal
--
This patch sets CMBS bit in controller capabilities register when user
configures NVMe driver with CMB support, so capabilites are correctly
reported to guest OS.
Signed-off-by: Andrzej Jakowski
Reviewed-by: Klaus Jensen
---
hw/block/nvme.c | 2 +-
include/block/nvme.h | 6 +-
2 files
So far it was not possible to have CMB and PMR emulated on the same
device, because BAR2 was used exclusively either of PMR or CMB. This
patch places CMB at BAR4 offset so it not conflicts with MSI-X vectors.
Signed-off-by: Andrzej Jakowski
---
hw/block/nvme.c | 122
Hi All,
Resending series recently posted on mailing list related to nvme device
extension.
This patch series does following:
- Fixes problem where CMBS bit was not set in controller capabilities
register, so support for CMB was not correctly advertised to guest.
This is resend of patch
Patchew URL:
https://patchew.org/QEMU/20200617043757.1623337-1-richard.hender...@linaro.org/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On 6/16/20 11:45 AM, Philippe Mathieu-Daudé wrote:
> The PCA9552 has 3 GPIOs, add them.
This is an example of an HW configuration. All pins can be used
as GPIOs.
> See 'PCA9552 Product Datasheet Rev. 05 - 9 March 2006',
> chapter 6.4 'Pins used as GPIOs':
>
> LED pins not used to control
On aarch64, gcc 9.3 is generating
qemu/exec.c: In function ‘address_space_translate_iommu’:
qemu/exec.c:431:28: note: parameter passing for argument of type \
‘MemTxAttrs’ {aka ‘struct MemTxAttrs’} changed in GCC 9.1
and many other reptitions. This structure, and the functions
amongst which
From: Wei Wang
It's reported an error of implicit conversion from "unsigned long" to
"double" when compiling with Clang 10. Simply make the encoding rate 0
when the encoded_size is 0.
Fixes: e460a4b1a4
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Richard Henderson
Reported-by: Richard
Clang 10 enables this by default with -Wtype-limit.
All of the instances flagged by this Werror so far have been
cases in which we really do want the compiler to optimize away
the test completely. Disabling the warning will avoid having
to add ifdefs to work around this.
Cc: Eric Blake
Fixes:
Use a helper function to tidy the assembly of gcc_flags.
Separate flags that disable warnings from those that enable,
and sort the disable warnings to the end.
Suggested-by: Eric Blake
Signed-off-by: Richard Henderson
---
configure | 42 --
1 file
Three of these patches are for cleaning up warnings vs clang-10.
The -Wtautological-type-limit-compare patch has been improved
as suggested by Eric Blake.
The final patch is for a "new" warning from gcc-9 on aarch64 hosts.
Our build box has been upgraded from bionic, so the warning is new
to me,
From: Philippe Mathieu-Daudé
When building with clang version 10.0.0-4ubuntu1, we get:
CC lm32-softmmu/fpu/softfloat.o
fpu/softfloat.c:3365:13: error: bitwise negation of a boolean expression; did
you mean logical negation? [-Werror,-Wbool-operation]
absZ &= ~ ( ( ( roundBits
Hi Andrew,
On 6/17/20 3:18 AM, Andrew Jeffery wrote:
> On Tue, 16 Jun 2020, at 17:21, Philippe Mathieu-Daudé wrote:
>> The current implementation uses nano-second precision, while
>> the watchdog can not be more precise than a micro-second.
>
> What's the basis for this assertion? It's true for
On 6/16/20 7:58 PM, John Snow wrote:
>
>
> On 6/9/20 4:58 AM, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> On 6/8/20 5:33 PM, Kevin Wolf wrote:
Am 08.06.2020 um 17:19 hat John Snow geschrieben:
>
>
> On 6/5/20 5:26 AM, Kevin Wolf wrote:
>> Am 04.06.2020
On 6/16/20 5:26 PM, Thomas Huth wrote:
> On 16/06/2020 14.26, Peter Maydell wrote:
>> On Mon, 15 Jun 2020 at 21:43, Markus Armbruster wrote:
>>>
>>> The following changes since commit 7d3660e79830a069f1848bb4fa1cdf8f666424fb:
>>>
>>> Merge remote-tracking branch
On 6/16/20 12:21 PM, Peter Maydell wrote:
> On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote:
>>
>> There are 4 different I2C peripherals on the FPGA APB.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/arm/mps2.c | 7 +++
>> 1 file changed, 7 insertions(+)
>>
>> diff
On Tue, Jun 16, 2020 at 4:17 PM Laurent Vivier wrote:
>
> On 29/05/2020 16:06, Cindy Lu wrote:
> > export the helper then we can reuse some of them in vhost-vdpa
> >
> > Signed-off-by: Cindy Lu
> > ---
> > hw/virtio/vhost-backend.c | 34 ++-
> >
On 6/16/20 5:41 PM, Eric Blake wrote:
> On 5/14/20 2:31 PM, John Snow wrote:
>
Nah, it's fine. I'll clean it up. This is pretty close to an RFC series
anyway, so I didn't really polish it.
(Or, I will try to clean it up. I probably won't work on it again in
the
On 6/11/20 7:25 AM, Eric Blake wrote:
>> +add_to warn_flags -Wold-style-declaration
>
> Hmm - should we add:
> warn_flags= nowarn_flags=
> prior to this line, to ensure that something inherited from the environment
> doesn't mess us up.
>
>> +add_to warn_flags -Wold-style-definition
>> +add_to
On Tue, 16 Jun 2020, at 17:21, Philippe Mathieu-Daudé wrote:
> The current implementation uses nano-second precision, while
> the watchdog can not be more precise than a micro-second.
What's the basis for this assertion? It's true for the AST2500 and AST2600, but
the AST2400 can run the
On Tue, Jun 16, 2020 at 9:32 AM Peter Maydell
wrote:
>
> On Tue, 16 Jun 2020 at 17:08, Alex Bennée wrote:
> > Apart from "a more perfect emulation" is there a particular use case
> > served by the extra functionality? AIUI up until this point we've
> > basically supported glibc's use of clone()
Patchew URL:
https://patchew.org/QEMU/20200616231204.8850-1-ahmedkhaledkara...@gmail.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Python script that prints the top 25 most executed functions in QEMU
using perf.
Signed-off-by: Ahmed Karaman
---
scripts/performance/perf_top_25.py | 82 ++
1 file changed, 82 insertions(+)
create mode 100644 scripts/performance/perf_top_25.py
diff --git
Python script that prints the top 25 most executed functions in QEMU
using callgrind.
Signed-off-by: Ahmed Karaman
---
scripts/performance/callgrind_top_25.py | 95 +
1 file changed, 95 insertions(+)
create mode 100644 scripts/performance/callgrind_top_25.py
diff --git
This new section includes the 'Performance Tools and Tests' subsection
which will contain the the performance scripts and benchmarks written
as a part of the 'TCG Continuous Benchmarking' project.
Signed-off-by: Ahmed Karaman
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff
Greetings,
As a part of the TCG Continous Benchmarking project for GSoC this
year, detailed reports discussing different performance measurement
methodologies and analysis results will be sent here on the mailing
list.
The project's first report is currently being revised and will be
posted on
Patchew URL:
https://patchew.org/QEMU/20200616205721.1191408-1-stef...@linux.vnet.ibm.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Quoting Greg Kurz (2020-06-16 11:41:36)
> On Tue, 16 Jun 2020 18:09:04 +0200
> Christian Schoenebeck wrote:
>
> > On Dienstag, 16. Juni 2020 17:14:40 CEST Greg Kurz wrote:
> > > Cc'ing co-maintainer Christian Schoenebeck.
> > >
> > > Christian,
> > >
> > > If there are some more commits you
Hi Andrew,
Thanks for the feedback.
On Tue, 16 Jun 2020 at 09:33, Andrew Jones wrote:
>
> Hi Beata,
>
> I see Peter just picked this up, so I'm a bit late getting to it. I do
> have a couple comments below though.
>
> Thanks,
> drew
>
> On Fri, May 29, 2020 at 12:27:56PM +0100, Beata Michalska
Patchew URL:
https://patchew.org/QEMU/20200616192700.1900260-1-atish.pa...@wdc.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
Patchew URL: https://patchew.org/QEMU/20200616190942.24624-1-js...@redhat.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export
Patchew URL: https://patchew.org/QEMU/20200616190942.24624-1-js...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
Patchew URL:
https://patchew.org/QEMU/ca+xhmqxwc10xhvs4z-jfe0-wlau3ztduu9qkvi31mjr59hw...@mail.gmail.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
Patchew URL:
https://patchew.org/QEMU/20200616170844.13318-1-peter.mayd...@linaro.org/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On Mon, Jun 15, 2020 at 05:21:18PM +0200, Philippe Mathieu-Daudé wrote:
> On 6/9/20 11:55 PM, John Snow wrote:
> >
> >
> > On 6/9/20 9:08 AM, Philippe Mathieu-Daudé wrote:
> >> Hi John,
> >>
> >> On 6/4/20 9:52 PM, John Snow wrote:
> >>> v3:
> >>> - Split _post_shutdown refactor into own patch
On 5/14/20 2:31 PM, John Snow wrote:
Nah, it's fine. I'll clean it up. This is pretty close to an RFC series
anyway, so I didn't really polish it.
(Or, I will try to clean it up. I probably won't work on it again in the
near term. I think I just wanted to see if this seemed useful in general
Patchew URL:
https://patchew.org/QEMU/20200616170844.13318-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 00/21] target/arm: Finish neon decodetree conversion
Type: series
Message-id:
Patchew URL: https://patchew.org/QEMU/20200616165805.ga324...@fuller.cnet/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export
** Tags added: tcg testcase
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1883784
Title:
[ppc64le] qemu behavior differs from ppc64le hardware
Status in QEMU:
New
Bug description:
I have
On 6/17/20 12:11 AM, Eric Blake wrote:
> On 6/16/20 11:20 AM, Denis V. Lunev wrote:
>> Right now bdrv_fclose() is just calling bdrv_flush().
>>
>> The problem is that migration code is working inefficently from black
>
> inefficiently, block
>
>> layer terms and are frequently called for very
уторак, 16. јун 2020., Huacai Chen је написао/ла:
> Hi, Thomas and Aleksandar,
>
> On Tue, Jun 16, 2020 at 3:45 AM Aleksandar Markovic
> wrote:
> >
> > On Mon, Jun 15, 2020 at 10:55 AM Thomas Huth wrote:
> > >
> > > On 15/06/2020 02.52, Huacai Chen wrote:
> > > > Hi, Aleksandar,
> > > >
> > >
On 6/16/20 11:20 AM, Denis V. Lunev wrote:
Right now bdrv_fclose() is just calling bdrv_flush().
The problem is that migration code is working inefficently from black
inefficiently, block
layer terms and are frequently called for very small pieces of not
properly aligned data. Block layer
On Tue, 16 Jun 2020 at 21:26, Trystan Larey-Williams
wrote:
> I'm trying to get a sense of where QEMU headed in terms of supporting
> Apple's Metal API. Apple will likely be removing OpenGL support entirely
> from OSX, perhaps as early as the next major release of OSX in Sep/Oct.
QEMU on OSX
The x87 fyl2xp1 emulation is currently based around conversion to
double. This is inherently unsuitable for a good emulation of any
floatx80 operation, even before considering that it is a particularly
naive implementation using double (adding 1 then using log rather than
attempting a better
Disable interrupt support for the TIS on sysbus.
Signed-off-by: Stefan Berger
---
include/hw/acpi/tpm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h
index d356f2e06e..21f81690a5 100644
--- a/include/hw/acpi/tpm.h
+++
Ignore DSDT table differences before enabling IRQ support for TPM.
Signed-off-by: Stefan Berger
CC: Michael S. Tsirkin
Reviewed-by: Eric Auger
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
This series of patches enables the usage of the TPM TIS with interrupts.
We use the unused IRQ 13, which is also accepted by Windows.
Stefan
v2->v3:
- Extended series to disable IRQ for TIS on sysbus
v1->v2:
- Added updated DSDT
Stefan Berger (8):
tpm_tis: Allow lowering of IRQ also
Before the enablement of interrupts on PCs, split the TPM_TIS_IRQ
into TPM_TIS_ISA_IRQ for PCs and TPM_TIS_SYSBUS_IRQ for ARM.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_tis_isa.c| 2 +-
hw/tpm/tpm_tis_sysbus.c | 3 ++-
include/hw/acpi/tpm.h | 3 ++-
3 files changed, 5 insertions(+), 3
From: Stefan Berger
Move the TPM TIS IRQ to unused IRQ 13, which is the only one accepted by
Windows. Query for the TPM's irq number and enable the TPM IRQ unless
TPM_IRQ_DISABLED is returned.
Signed-off-by: Stefan Berger
CC: Michael S. Tsirkin
---
hw/i386/acpi-build.c | 11 +--
Add the updated DSDT following the interrupt enablement.
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.tis, Mon Jun 15 09:57:05 2020
+ * Disassembly of /tmp/aml-Y77YL0, Mon Jun 15 09:57:05 2020
*
* Original Table Header:
*
From: Stefan Berger
Implement get_irqnum() as part of the TPMIfClass to get the assigned IRQ
number or TPM_IRQ_DISABLED (-1) in case IRQs cannot be used.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_tis_isa.c| 9 +
hw/tpm/tpm_tis_sysbus.c | 9 +
include/sysemu/tpm.h|
Check for irq_num having the value of TPM_IRQ_DISABLED before calling any
IRQ related functions or allowing the user to try to enable interrupts.
Explicitly allow the value of TPM_IRQ_DISABLED in irq_num.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_tis_common.c | 12 +++-
From: Stefan Berger
This patch fixes a bug that occurs when using interrupts. It
allows to lower the IRQ also when a locality is not active.
Signed-off-by: Stefan Berger
Reviewed-by: Eric Auger
---
hw/tpm/tpm_tis_common.c | 4
1 file changed, 4 deletions(-)
diff --git
Public bug reported:
I have some code which passes my test suite on PPC64LE hardware when
compiled with GCC 10, but the saem binary fails with both qemu-ppc64le
4.2 (on Fedora 32) and qemu-ppc64le-static 5.0.0 (Debian testing).
I'm not getting any errors about illegal instructions or anything,
On Mon, Jun 15, 2020 at 5:51 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This series updates the 'sifive_u' machine support:
>
> - Change SiFive E/U series CPU reset vector to 0x1004
> - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
> "msel" machine property
> - Add a dummy DDR
On Mon, Jun 15, 2020 at 8:23 PM Anup Patel wrote:
>
> This series adds multi-socket support for RISC-V virt machine and
> RISC-V spike machine. The multi-socket support will help us improve
> various RISC-V operating systems, firmwares, and bootloader to
> support RISC-V NUMA systems.
>
> These
Patchew URL: https://patchew.org/QEMU/20200616162035.29857-1-...@openvz.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v4 0/4] block: seriously improve savevm performance
Type: series
Message-id:
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: 5c24bce3 (
https://gitlab.com/qemu-project/qemu/-/commit/5c24bce3056ff209a1ecc50ff4b7e65b85ad8e74
)
Commit Message: Merge
Hi all,
I'm trying to get a sense of where QEMU headed in terms of supporting
Apple's Metal API. Apple will likely be removing OpenGL support entirely
from OSX, perhaps as early as the next major release of OSX in Sep/Oct.
Information on support for graphics acceleration on an OSX client
On 6/16/20 10:32 AM, Kevin Wolf wrote:
Am 15.06.2020 um 21:32 hat Nir Soffer geschrieben:
We can zero 2.3 g/s:
# time blkdiscard -z test-lv
real 0m43.902s
user 0m0.002s
sys 0m0.130s
We can write 445m/s:
# dd if=/dev/zero bs=2M count=51200 of=test-lv oflag=direct conv=fsync
107374182400
On 6/16/20 2:46 PM, Eric Blake wrote:
+BlockJob *bitpop_job_create(
+ if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_BACKUP_SOURCE, errp)) {
+ return NULL;
+ }
What does this protect? And why does BACKUP_SOURCE describe acccurately
what this job does?
I'm less certain what the
On Tue, Jun 16, 2020 at 8:39 PM Nir Soffer wrote:
>
> On Tue, Jun 16, 2020 at 6:32 PM Kevin Wolf wrote:
> >
> > Am 15.06.2020 um 21:32 hat Nir Soffer geschrieben:
> > > We can zero 2.3 g/s:
> > >
> > > # time blkdiscard -z test-lv
> > >
> > > real 0m43.902s
> > > user 0m0.002s
> > > sys 0m0.130s
On 6/16/20 3:46 PM, Eric Blake wrote:
> I'm less certain what the BLOCK_OP_TYPE_* constants are supposed to
> block, or if this is just copy/paste from backup.c. Does BlockOpType in
> block.h need a new entry?
Copy paste. I wasn't sure myself.
On 6/4/20 4:01 AM, Kevin Wolf wrote:
Am 14.05.2020 um 05:49 hat John Snow geschrieben:
This job copies the allocation map into a bitmap. It's a job because
there's no guarantee that allocation interrogation will be quick (or
won't hang), so it cannot be retrofit into block-dirty-bitmap-merge.
On 4/30/20 12:14 PM, Stephen Long wrote:
> Signed-off-by: Stephen Long
> ---
>
> I made the changes Richard requested. I took out the status field for
> the helper function.
>
> include/fpu/softfloat.h| 5 +++
> target/arm/helper-sve.h| 4 +++
> target/arm/sve.decode | 4 +++
>
Currently, all riscv machines have identical reset vector code
implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.
Move it to common function and let all the machines use the common function.
Signed-off-by:
This series adds support OpenSBI dynamic firmware support to Qemu.
Qemu loader passes the information about the DT and next stage (i.e. kernel
or U-boot) via "a2" register. It allows the user to build bigger OS images
without worrying about overwriting DT. It also unifies the reset vector code
in
Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the
OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and
> > increment the revision to '2' so that these larger addresses are
> > addressable. This matters because the DSDT revision represents the
> > maximum capability of all other SSDTs. This is also what arm does.
> it was keept at 1 for compat reasons with WindowsXP.
> by now it is long time EOL, so
On 4/30/20 6:28 AM, Stephen Long wrote:
> Implements FCVTLT, FCVTX, FCVTNT, FCVTXNT
>
> Signed-off-by: Stephen Long
> ---
>
> Fixed a compilation error and collapsed the translation functions with a
> macro.
>
>> Ignore my previous patchset. I missed the insn FCVTX and I ended up
>> squashing
Hi, this is a followup to my patch which attempted to prefer
'sphinx-build' to 'sphinx-build-3' which intended to prefer a VENV
installation of sphinx over Fedora's system installation.
That got confusing, though, so here's something that's simpler and
better: use python to invoke sphinx so we
Using an explicit entry path script for sphinx can lead to confusing
results: If the python binary belongs to a virtual environment, our
configure script may still select a sphinx script that belongs to the
system distribution packages.
It is likely best to use python itself (whichever one the
On 4/28/20 10:43 AM, Stephen Long wrote:
> The only insn left in this category is BFCVTNT. I couldn't find any
> helper functions for bfloats so I'm not sure how to approach this insn.
>
> Also, for insn FCVTXNT, I'm not sure if it is ok to set the status rounding
> mode to odd like that.
>
>
On 4/28/20 10:43 AM, Stephen Long wrote:
> +void HELPER(sve2_fcvtxnt)(void *vd, void *vn, void *vg,
> + void *status, uint32_t desc)
> +{
> +set_float_rounding_mode(float_round_to_odd, status);
> +HELPER(sve2_fcvtnt_ds)(vd, vn, vg, status, desc);
> +}
This is
On Tue, Jun 16, 2020 at 2:16 AM Igor Mammedov wrote:
> On Mon, 15 Jun 2020 18:36:54 -0600
> "Jason A. Donenfeld" wrote:
> > SSDTs cannot address 64-bit physical addresses in 32-bit tables, so we
> please clarify what accesses waht within tables (i.e. be more concrete).
If you add an ssdt or a
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