On Tue, Jun 30, 2020 at 3:37 PM LIU Zhiwei wrote:
>
>
> On 2020/6/30 15:31, Chih-Min Chao wrote:
>
> On Sat, Jun 27, 2020 at 5:09 AM LIU Zhiwei wrote:
>
>> Signed-off-by: LIU Zhiwei
>> ---
>> target/riscv/insn_trans/trans_rvd.inc.c | 7 +-
>> target/riscv/insn_trans/trans_rvf.inc.c | 272 +++
Hi Alex, Markus, Paolo,
maybe this could be queued in one of your queues?
Thanks a lot,
Claudio
On 6/29/20 11:35 AM, Claudio Fontana wrote:
> Motivation and higher level steps:
>
> https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html
>
> Previous series: [RFC RESEND v7 0/4] QE
We’ve made the review changes to the doc, and moved to RST format,
so the doc can go into the QEMU sources.
Thanos & JJ
https://github.com/tmakatos/qemu/blob/master/docs/devel/vfio-over-socket.rst
Is it true, that semihosting can be used to access (read and write) host
files from the guest?
In such a case it can't be used with RR for the following reasons:
1. We don't preserve modified files, therefore the execution result may
change in the future runs.
2. Even in the case, when all the file
On 01.07.2020 19:54, Philippe Mathieu-Daudé wrote:
+Pavel/Paul/Alexander
On 7/1/20 5:12 PM, Paolo Bonzini wrote:
On 01/07/20 17:07, Philippe Mathieu-Daudé wrote:
$ cat .ignoredmailmap
#
# From man git-shortlog the forms are:
#
# Proper Name
#
#
Jean-Christophe PLAGNIOL-VILLARD
Caio Carrar
This patch adds a flag to enable/disable control flow integrity checks
on indirect function calls. This feature is only provided by LLVM/Clang
v3.9 or higher, and only allows indirect function calls to functions
with compatible signatures.
We also add an option to enable a debugging version of cfi
cfi-icall is a form of Control-Flow Integrity for indirect function
calls implemented by llvm. It is enabled with a -fsanitize flag.
iotests are currently disabled when -fsanitize options is used, with the
exception of SafeStack.
This patch implements a generic filtering mechanism to allow iotest
LLVM/Clang, starting from v3.9, supports runtime checks for forward-edge
Control-Flow Integrity (CFI).
CFI on indirect function calls can have a huge impact in enhancing QEMU
security, by significantly limiting one of the most used attack vectors
for VM Escape. Attacks demonstrated in [1],[2] and
Daniel P. Berrangé writes:
> Create a "qemu_open_err" method which does the same as "qemu_open",
> but with a "Error **errp" for error reporting. There should be no
> behavioural difference for existing callers at this stage.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> include/qemu/osdep.h |
Signed-off-by: Aurelien Jarno
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index dec252f38b..0535e043f0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -130,7 +130,6 @@ F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
FPU emulation
-M: Aurelien Ja
On 2020-07-01 20:55, Aurelien Jarno wrote:
> NACK
This NACK was because I find inacceptable to claim that you got not
answer from Paul or from myself after very few time.
Now about the content of the patch, QEMU used to be a fun ride, but it
happens that interactions are now hurtful, especially o
Igor, Paolo, you showed me the error in v2. Could you have a look at
this revision?
Markus Armbruster writes:
> The Error ** argument must be NULL, &error_abort, &error_fatal, or a
> pointer to a variable containing NULL. Passing an argument of the
> latter kind twice without clearing it in be
Paolo Bonzini writes:
> On 01/07/20 09:06, Markus Armbruster wrote:
>> lichun writes:
>>
>>> Signed-off-by: lichun
>>> ---
>>> chardev/char-socket.c | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/chardev/char-socket.c b/chardev/char-socket.c
>>> index afebeec
On 7/1/20 10:54 AM, Philippe Mathieu-Daudé wrote:
> This code was introduced with SMP support in commit 6a00d60127,
> later commit 296af7c952 moved CPU parts to cpus.c but forgot this
> code. Move now and simplify ifdef'ry.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> cpus.c | 18 ++
Jason Andryuk writes:
> On Wed, Jul 1, 2020 at 3:03 AM Paul Durrant wrote:
>>
>> > -Original Message-
>> > From: Philippe Mathieu-Daudé
>> > Sent: 30 June 2020 18:27
>> > To: p...@xen.org; xen-de...@lists.xenproject.org; qemu-devel@nongnu.org
>> > Cc: 'Eduardo Habkost' ; 'Michael S. Tsi
On Tue, Jun 30, 2020 at 5:19 PM LIU Zhiwei wrote:
>
>
>
> On 2020/7/1 4:12, Alistair Francis wrote:
> > Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
> > "memory: Revert "memory: accept mismatching sizes in
> > memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
> > accesses
On Wed, Jul 1, 2020 at 8:26 AM LIU Zhiwei wrote:
>
> This patchset implements the vector extension for RISC-V on QEMU.
>
> You can also find the patchset and all *test cases* in
> my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v12).
> All the test cases are in the directory
在 2020/7/2 1:01, Philippe Mathieu-Daudé 写道:
On 7/1/20 6:43 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
On 7/1/20 3:56 PM, Alex Bennée wrote:
For some reason these tests fail all the time on GitLab. I can
re-create the hang around 3% of the time locally but it doesn't seem
to be M
On 2020/7/1 下午4:09, Jason Wang wrote:
On 2020/6/30 下午11:39, Peter Xu wrote:
On Tue, Jun 30, 2020 at 10:41:10AM +0800, Jason Wang wrote:
/* According to ATS spec table 2.4:
* S = 0, bits 15:12 = range size: 4K
* S = 1, bits 15:12 = xxx0 range size: 8K
*
On 2020/7/1 下午8:41, Peter Xu wrote:
On Wed, Jul 01, 2020 at 08:30:07PM +0800, Jason Wang wrote:
I overlooked myself that the IR region will be there even if ir=off.
Yes, but the point stands still but the issue is still if ir=off.
So I
think the assert should stand.
Do you mean vhos
On 2020/7/1 下午8:44, Peter Xu wrote:
Add this entry as suggested by Jason and Michael.
CC: Jason Wang
CC: Michael S. Tsirkin
CC: Paolo Bonzini
Signed-off-by: Peter Xu
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dec252f38b..
Hi Michael, Eric,
This was fix in the latest version, v4
https://patchew.org/QEMU/20200701145538.22333-1-l...@redhat.com/20200701145538.22333-15-l...@redhat.com/
On Wed, Jul 1, 2020 at 11:21 PM Michael S. Tsirkin wrote:
>
> On Wed, Jul 01, 2020 at 09:28:27AM -0500, Eric Blake wrote:
> > On 7/1/20
> From: Peter Xu
> Sent: Wednesday, July 1, 2020 8:44 PM>
> Add this entry as suggested by Jason and Michael.
>
> CC: Jason Wang
> CC: Michael S. Tsirkin
> CC: Paolo Bonzini
> Signed-off-by: Peter Xu
> ---
> MAINTAINERS | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAIN
On Wed, Jul 1, 2020 at 4:03 PM Alex Bennée wrote:
>
> For some reason these tests fail all the time on GitLab. I can
> re-create the hang around 3% of the time locally but it doesn't seem
> to be MTTCG related. For now skipIf on GITLAB_CI.
>
> Signed-off-by: Alex Bennée
> Cc: Aleksandar Markovic
On 2020/7/2 0:56, Richard Henderson wrote:
The smin/smax/umin/umax operations require the operands to be
properly sign extended. Do not drop the MO_SIGN bit from the
load, and additionally extend the val input.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 1
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
v3: simplify helper_vmulh{su}d
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc/
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Double
On 2020/7/2 0:25, Richard Henderson wrote:
On 7/1/20 8:21 AM, LIU Zhiwei wrote:
-tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
+tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
+tcg_gen_ext_i32(val, val, memop);
gen(t2, t1, val);
I was just about to post a simiar patch.
T
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4
2 files
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
v4: make it compile on all targets
v3: fix the store issue in br[dwh]
simplify brw implementation
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
no change since v1
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.
Convert the original implementation of vmuluwm to the more generic
tcg_gen_gvec_mul.
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
v3: newly introduced
target/ppc/helper.h | 1 -
target/ppc/int_helper.c | 13 -
target/ppc/translate/vmx-imp
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.
Signed-off-by: Lijun Pan
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
tcg/ppc/tcg-target.h | 2 ++
tcg/ppc/tcg-ta
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
this version. In v4 version, coding style issues are fixed, community
reviews/suggestions are taken into consideration.
Lijun Pan (11):
target/ppc: Introduce Power I
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
v3: inline the helper_vmulh{su}w multiply directly instead of using macro
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h
This patch enables the Power ISA 3.1 in QEMU.
Signed-off-by: Lijun Pan
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag
target/ppc/cpu.h| 2 +-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/ta
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Lijun Pan
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
include/elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/incl
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag
target/ppc/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1988b436cb..a5e9c08dcc 100644
--- a/target/ppc/c
On 6/30/20 9:45 AM, Klaus Jensen wrote:
> On Jun 30 17:16, Philippe Mathieu-Daudé wrote:
>> On 6/30/20 5:10 PM, Andrzej Jakowski wrote:
>>> On 6/30/20 4:04 AM, Philippe Mathieu-Daudé wrote:
The Persistent Memory Region Controller Memory Space Control
register is 64-bit wide. See 'Figure 6
Hi Kevin & Max,
Just pinging this patch for your consideration.
Thank you,
Connor
On 6/17/20 11:27 AM, Connor Kuehl wrote:
Providing an empty string for the backing file parameter like so:
qemu-img create -f qcow2 -b '' /tmp/foo
allows the flow of control to reach and subsequently f
On 01.07.20 22:47, Peter Maydell wrote:
> On Wed, 1 Jul 2020 at 21:08, Alexander Graf wrote:
>> We currently treat unknown SMC calls as UNDEF. This behavior is different
>> from KVM, which treats them as NOP.
>>
>> Unfortunately, the UNDEF exception breaks running Windows for ARM in QEMU,
>> as
This patch sets CMBS bit in controller capabilities register when user
configures NVMe driver with CMB support, so capabilites are correctly
reported to guest OS.
Signed-off-by: Andrzej Jakowski
Reviewed-by: Klaus Jensen
---
hw/block/nvme.c | 2 +-
include/block/nvme.h | 6 +-
2 files
So far it was not possible to have CMB and PMR emulated on the same
device, because BAR2 was used exclusively either of PMR or CMB. This
patch places CMB at BAR4 offset so it not conflicts with MSI-X vectors.
Signed-off-by: Andrzej Jakowski
---
hw/block/nvme.c | 101
Hi All,
Resending series recently posted on mailing list related to nvme device
extension with couple of fixes after review.
This patch series does following:
- Fixes problem where CMBS bit was not set in controller capabilities
register, so support for CMB was not correctly advertised to gu
On Wednesday, July 1, 2020, Aurelien Jarno wrote:
> Hi Aleksandar,
>
> I know you have sent a v3 of this patch in the meantime, but I would
> still like to comment on it.
>
> First of all I confirm, that I do not have time to contribute to QEMU
> anymore and that I said I would like to resign fro
Aleksandar,
On 2020-07-01 20:51, Aleksandar Markovic wrote:
> On Wed, Jul 1, 2020 at 7:39 PM Aurelien Jarno wrote:
> >
> > Aleksandar,
> >
> > On 2020-06-30 23:54, Aleksandar Markovic wrote:
> > > As, in a very clear way, evidenced from the previous versions of this
> > > series, this series real
On Wed, 1 Jul 2020 at 21:08, Alexander Graf wrote:
>
> We currently treat unknown SMC calls as UNDEF. This behavior is different
> from KVM, which treats them as NOP.
>
> Unfortunately, the UNDEF exception breaks running Windows for ARM in QEMU,
> as that probes an OEM SMCCC call on boot, but does
On Wed, 1 Jul 2020 at 19:21, Philippe Mathieu-Daudé wrote:
>
> We can run I/O access with the 'i' or 'o' HMP commands in the
> monitor. These commands are expected to run on a vCPU. The
> monitor is not a vCPU thread. To avoid crashing, initialize
> the 'current_cpu' variable with the first vCPU c
Since all callers to get_physical_address() now apply the same page offset to
the translation result, move the logic into get_physical_address() itself to
avoid duplication.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Mark Cave-Ayland
---
target/m68k/helper.c | 17 ++---
1 f
The result of the get_physical_address() function should be combined with the
offset of the original page access before being returned. Otherwise the
m68k_cpu_get_phys_page_debug() function can round to the wrong page causing
incorrect lookups in gdbstub and various "Disassembler disagrees with
tra
The first patch in the series fixes the original bug, whilst the second patch
implements the suggestion by Philippe to consolidate the translation offset
logic into get_physical_address() itself now that all callers are identical.
Signed-off-by: Mark Cave-Ayland
v4:
- Remove extra TARGET_PAGE_M
Hi Aleksandar,
On Wed, Jul 1, 2020 at 11:26 AM Aleksandar Markovic
wrote:
> Paul Burton and Aurelien Jarno removed for not being present.
> A polite email was sent to them with question whether they
> intend to actively participate, but there was no response.
It was 2 days ago, not 2 months :)
Background
I have a test environment which runs QEMU 4.2 with a plugin that runs two
copies of a PCIE device simulator on a CentOS 7.5 host with an Ubuntu 18.04
guest. When running with a single QEMU CPU using:
-cpu kvm64,+lahf_lm -M q35,kernel-irqchip=off -device
intel-iommu,intremap=on
Hi Aleksandar,
I know you have sent a v3 of this patch in the meantime, but I would
still like to comment on it.
First of all I confirm, that I do not have time to contribute to QEMU
anymore and that I said I would like to resign from QEMU maintainership.
We discussed that in person in Lyon back
We currently treat unknown SMC calls as UNDEF. This behavior is different
from KVM, which treats them as NOP.
Unfortunately, the UNDEF exception breaks running Windows for ARM in QEMU,
as that probes an OEM SMCCC call on boot, but does not expect to receive
an UNDEF exception as response.
So inst
On 30/06/2020 22:20, Laurent Vivier wrote:
> Le 30/06/2020 à 13:27, Mark Cave-Ayland a écrit :
>> Since all callers to get_physical_address() now apply the same page offset to
>> the translation result, move the logic into get_physical_address() itself to
>> avoid duplication.
>>
>> Suggested-by:
On 6/26/20 3:44 AM, Paolo Bonzini wrote:
> In 32-bit mode, the higher 16 bits of the destination
> register are undefined. In practice CR0[31:0] is stored,
> just like in 64-bit mode, so just remove the "if" that
> currently differentiates the behavior.
>
> Signed-off-by: Paolo Bonzini
> ---
>
On 01.07.20 18:54, Philippe Mathieu-Daudé wrote:
+Pavel/Paul/Alexander
On 7/1/20 5:12 PM, Paolo Bonzini wrote:
On 01/07/20 17:07, Philippe Mathieu-Daudé wrote:
$ cat .ignoredmailmap
#
# From man git-shortlog the forms are:
#
# Proper Name
#
#
Jean-Christophe PLAGNIOL-VILLARD
Caio Carr
On 7/1/20 9:11 AM, Alex Bennée wrote:
> -This document outlines the design for multi-threaded TCG system-mode
> -emulation. The current user-mode emulation mirrors the thread
> -structure of the translated executable. Some of the work will be
> -applicable to both system and linux-user emulation.
>
On 7/1/20 9:11 AM, Alex Bennée wrote:
> While working on some test cases I realised there was quite a lot of
> assumed knowledge about how things boot up. I thought it would be
> worth gathering this together in a user facing document where we could
> pour in the details and background to the boot
qemu_set_nonblock() checks that the file descriptor can be used and, if
not, crashes QEMU. An assert() is used for that. The use of assert() is
used to detect programming error and the coredump will allow to debug
the problem.
But in the case of the tap device, this assert() can be triggered by
a
v3: move qemu_fd_is_valid() checking into a new function
qemu_try_set_nonblock(), and use qemu_try_set_nonblock() in
qemu_set_nonblock().
v2: Add patch from Daniel to check the fd can be used
I have updated Daniel's patch not to check for EINVAL on TUNGETIFF
as I think we can avoi
From: "Daniel P. Berrange"
When QEMU sets up a tap based network device backend, it mostly ignores errors
reported from various ioctl() calls it makes, assuming the TAP file descriptor
is valid. This assumption can easily be violated when the user is passing in a
pre-opened file descriptor. At be
Patchew URL:
https://patchew.org/QEMU/20200701152549.1218-1-zhiwei_...@c-sky.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1
Type: series
Message-id: 20200701152549.1
On Wed, Jul 1, 2020 at 11:30 AM Gerd Hoffmann wrote:
> Hi,
>
> > This patch series adds emulation for the dwc-hsotg USB controller,
> > which is used on the Raspberry Pi 3 and earlier, as well as a number
> > of other development boards. The main benefit for Raspberry Pi is that
> > this enable
On Wed, Jul 1, 2020 at 8:55 PM Aurelien Jarno wrote:
>
> NACK
>
> On 2020-07-01 20:25, Aleksandar Markovic wrote:
> > Paul Burton and Aurelien Jarno removed for not being present.
> > A polite email was sent to them with question whether they
> > intend to actively participate, but there was no re
On Wed, Jul 1, 2020 at 8:43 PM Paul Burton wrote:
>
> Hi Aleksandar,
>
> On Wed, Jul 1, 2020 at 11:26 AM Aleksandar Markovic
> wrote:
> > Paul Burton and Aurelien Jarno removed for not being present.
> > A polite email was sent to them with question whether they
> > intend to actively participate
NACK
On 2020-07-01 20:25, Aleksandar Markovic wrote:
> Paul Burton and Aurelien Jarno removed for not being present.
> A polite email was sent to them with question whether they
> intend to actively participate, but there was no response.
I indeed received a polite email, but it was sent less tha
On 200701 2021, Philippe Mathieu-Daudé wrote:
> We can run I/O access with the 'i' or 'o' HMP commands in the
> monitor. These commands are expected to run on a vCPU. The
> monitor is not a vCPU thread. To avoid crashing, initialize
> the 'current_cpu' variable with the first vCPU created. The
> co
On Wed, Jul 1, 2020 at 7:39 PM Aurelien Jarno wrote:
>
> Aleksandar,
>
> On 2020-06-30 23:54, Aleksandar Markovic wrote:
> > As, in a very clear way, evidenced from the previous versions of this
> > series, this series real goal was not not to create some new
> > "malta-strict" machine, but to pre
Thanks, sounds good! Of course the best solution would be in HVF itself,
similar to KVM and WHPX, but at least it's possible to work around it.
Paolo
Il mer 1 lug 2020, 20:37 Roman Bolshakov ha scritto:
> On Tue, Jun 30, 2020 at 06:04:23PM +0200, Paolo Bonzini wrote:
> > On 30/06/20 17:50, Roma
Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the e
OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and availab
This series adds support OpenSBI dynamic firmware support to Qemu.
Qemu loader passes the information about the DT and next stage (i.e. kernel
or U-boot) via "a2" register. It allows the user to build bigger OS images
without worrying about overwriting DT. It also unifies the reset vector code
in r
Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.
Move it to common function and let all the machines use the common function.
Si
Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.
Update the ROM code correctly to reflect the 64bit value.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 6 +-
hw/riscv/sifive_u.c | 6 +-
On Tue, Jun 30, 2020 at 06:04:23PM +0200, Paolo Bonzini wrote:
> On 30/06/20 17:50, Roman Bolshakov wrote:
> > On Tue, Jun 30, 2020 at 02:33:42PM +0200, Paolo Bonzini wrote:
> >> Can a signal interrupt hv_vcpu_run? If so you actually don't need
> >> hv_vcpu_interrupt at all.
> >
> > Existing sign
Hi,
> This patch series adds emulation for the dwc-hsotg USB controller,
> which is used on the Raspberry Pi 3 and earlier, as well as a number
> of other development boards. The main benefit for Raspberry Pi is that
> this enables networking on these boards, since the network adapter is
> attac
On 6/26/20 3:44 AM, Paolo Bonzini wrote:
> Force the end of a translation block after an I/O instruction in
> icount mode. For consistency, all CF_USE_ICOUNT code is kept in
> disas_insn instead of having it in gen_ins and gen_outs.
>
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/translate
A collection of pending fixes and improvements.
v2->v3:
- minor content and commit message changes
v1->v2:
- minor content and commit message changes
Aleksandar Markovic (2):
target/mips: Remove identical if/else branches
MAINTAINERS: Adjust MIPS maintainership
MAINTAINERS
Remove the segment:
if (other_tc == other->current_tc) {
tccause = other->CP0_Cause;
} else {
tccause = other->CP0_Cause;
}
Original contributor can't remember what was his intention.
Fixes: 5a25ce9487 ("mips: Hook in more reg accesses via mttr/mftr")
Buglin
Paul Burton and Aurelien Jarno removed for not being present.
A polite email was sent to them with question whether they
intend to actively participate, but there was no response.
In cases where needed, other persons step in instead.
Huacai Chen and Jiaxun Yang step in as new energy.
CC: Paul Bur
On 7/1/20 8:03 PM, Gerd Hoffmann wrote:
> Given this isn't perforance critical at all lets avoid the non-portable
> d_type and use fstat instead to check whenever the file is a chardev.
>
> Signed-off-by: Gerd Hoffmann
Reported-by: David Carlier
Reviewed-by: Philippe Mathieu-Daudé
> ---
> ut
We can run I/O access with the 'i' or 'o' HMP commands in the
monitor. These commands are expected to run on a vCPU. The
monitor is not a vCPU thread. To avoid crashing, initialize
the 'current_cpu' variable with the first vCPU created. The
command executed on the monitor will end using it.
This f
In case the string doesn't fit into the buffer snprintf returns the size
it would need, so len can be larger than the buffer. Fix this by simply
using g_strdup_printf() instead of a static buffer.
Reported-by: Wenxiang Qian
Signed-off-by: Gerd Hoffmann
---
ui/console.c | 8
1 file cha
On 7/1/20 7:48 PM, Philippe Mathieu-Daudé wrote:
> +MST/Igor for ICH9
>
> On 7/1/20 7:37 PM, Philippe Mathieu-Daudé wrote:
>> On 7/1/20 7:34 PM, Philippe Mathieu-Daudé wrote:
>>> +Paolo
>>>
>>> On 7/1/20 7:09 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
> On 7/1/20 6:40 PM, Alex
Given this isn't perforance critical at all lets avoid the non-portable
d_type and use fstat instead to check whenever the file is a chardev.
Signed-off-by: Gerd Hoffmann
---
util/drm.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/util/drm.c b/util/drm.c
This code was introduced with SMP support in commit 6a00d60127,
later commit 296af7c952 moved CPU parts to cpus.c but forgot this
code. Move now and simplify ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
---
cpus.c | 18 ++
exec.c | 22 --
2 files changed, 1
+MST/Igor for ICH9
On 7/1/20 7:37 PM, Philippe Mathieu-Daudé wrote:
> On 7/1/20 7:34 PM, Philippe Mathieu-Daudé wrote:
>> +Paolo
>>
>> On 7/1/20 7:09 PM, Alex Bennée wrote:
>>> Philippe Mathieu-Daudé writes:
On 7/1/20 6:40 PM, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>
>>
On Wed, Jul 1, 2020 at 5:42 PM Alex Bennée wrote:
>
>
> Ahmed Karaman writes:
>
> > On Mon, Jun 29, 2020 at 6:03 PM Alex Bennée wrote:
> >>
> >> Assuming your test case is constant execution (i.e. runs the same each
> >> time) you could run in through a plugins build to extract the number of
> >
This series fixes couple of issues with recent topology related code.
1. Maintain consistency while building the topology. Use the numa
information passed from user to build the apic_id.
2. Fix uninitialized memory with -device and CPU hotplug
Here are the discussion thread.
https://lore.kernel
Aleksandar,
On 2020-06-30 23:54, Aleksandar Markovic wrote:
> As, in a very clear way, evidenced from the previous versions of this
> series, this series real goal was not not to create some new
> "malta-strict" machine, but to prepare path to creation of some
> imagined "malta-unleashed" machine
On 7/1/20 7:34 PM, Philippe Mathieu-Daudé wrote:
> +Paolo
>
> On 7/1/20 7:09 PM, Alex Bennée wrote:
>> Philippe Mathieu-Daudé writes:
>>> On 7/1/20 6:40 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
> On 7/1/20 3:56 PM, Alex Bennée wrote:
>> It's possible to trigger thi
+Paolo
On 7/1/20 7:09 PM, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>> On 7/1/20 6:40 PM, Alex Bennée wrote:
>>> Philippe Mathieu-Daudé writes:
>>>
On 7/1/20 3:56 PM, Alex Bennée wrote:
> It's possible to trigger this function from qtest/monitor at which
> point current_cp
Noticed the following command failure while testing CPU hotplug.
$ qemu-system-x86_64 -machine q35,accel=kvm -smp 1,maxcpus=2,
cores=1, threads=1,sockets=2 -cpu EPYC -device EPYC-x86_64-
cpu,core-id=0,socket-id=1,thread-id=0
qemu-system-x86_64: -device EPYC-x86_64-cpu,core-id=0,socket-id=1,
Build apic_id from CpuInstanceProperties if numa configured.
Use the node_id from user provided numa information. This
will avoid conflicts between numa information and apic_id
generated.
Re-arranged the code little bit to make sure CpuInstanceProperties
is initialized before calling.
Signed-off-
This is in preparation to build the apic_id from user
provided topology information.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 07239f95f4..7cb21
Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector register length, default value is 128 bit.
elen is the max operator size in bits, default val
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 26 +++
On Jun 18 06:34, Dmitry Fomichev wrote:
> A ZNS drive that is emulated by this driver is currently initialized
> with all zones Empty upon startup. However, actual ZNS SSDs save the
> state and condition of all zones in their internal NVRAM in the event
> of power loss. When such a drive is powered
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