Re: [PATCH v5 09/14] cpus: cleanup now unneeded includes

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana 
> ---
>  softmmu/cpus.c | 7 ---
>  1 file changed, 7 deletions(-)

Reviewed-by: Richard Henderson 


r~

Re: [PATCH v5 08/14] cpus: extract out hvf-specific code to target/i386/hvf/

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel hvf_cpus = {
> +.create_vcpu_thread = hvf_start_vcpu_thread,
> +
> +.synchronize_post_reset = hvf_cpu_synchronize_post_reset,
> +.synchronize_post_init = hvf_cpu_synchronize_post_init,
> +.synchronize_state = hvf_cpu_synchronize_state,
> +.synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm,
> +};

const.

Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH v5 07/14] cpus: extract out whpx-specific code to target/i386/

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel whpx_cpus = {
> +.create_vcpu_thread = whpx_start_vcpu_thread,
> +.kick_vcpu_thread = whpx_kick_vcpu_thread,
> +
> +.synchronize_post_reset = whpx_cpu_synchronize_post_reset,
> +.synchronize_post_init = whpx_cpu_synchronize_post_init,
> +.synchronize_state = whpx_cpu_synchronize_state,
> +.synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm,
> +};

const.

Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH v5 06/14] cpus: extract out hax-specific code to target/i386/

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel hax_cpus = {
> +.create_vcpu_thread = hax_start_vcpu_thread,
> +.kick_vcpu_thread = hax_kick_vcpu_thread,
> +
> +.synchronize_post_reset = hax_cpu_synchronize_post_reset,
> +.synchronize_post_init = hax_cpu_synchronize_post_init,
> +.synchronize_state = hax_cpu_synchronize_state,
> +.synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm,
> +};

const.

Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH v5 05/14] cpus: extract out kvm-specific code to accel/kvm

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +
> +CpusAccel kvm_cpus = {
> +.create_vcpu_thread = kvm_start_vcpu_thread,
> +
> +.synchronize_post_reset = kvm_cpu_synchronize_post_reset,
> +.synchronize_post_init = kvm_cpu_synchronize_post_init,
> +.synchronize_state = kvm_cpu_synchronize_state,
> +.synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm,
> +};

const.

Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH v5 04/14] cpus: extract out qtest-specific code to accel/qtest

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel qtest_cpus = {
> +.create_vcpu_thread = qtest_start_vcpu_thread,
> +.get_virtual_clock = qtest_get_virtual_clock,
> +};

const.

Do you need to fill in the other methods, even if they do nothing but
g_assert_not_reached()?


> -qemu_dummy_start_vcpu(cpu);
> +assert(0);

g_assert_not_reached();


r~

Re: [PATCH v5 03/14] cpus: extract out TCG-specific code to accel/tcg

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +static int64_t tcg_get_virtual_clock(void)
> +{
> +if (icount_enabled()) {
> +return icount_get();
> +}
> +return cpu_get_clock();
> +}
> +
> +static int64_t tcg_get_elapsed_ticks(void)
> +{
> +if (icount_enabled()) {
> +return icount_get();
> +}
> +return cpu_get_ticks();
> +}
> +
> +CpusAccel tcg_cpus = {
> +.create_vcpu_thread = tcg_start_vcpu_thread,
> +.kick_vcpu_thread = tcg_kick_vcpu_thread,
> +.get_virtual_clock = tcg_get_virtual_clock,
> +.get_elapsed_ticks = tcg_get_elapsed_ticks,
> +};

I think this variable should be const.  Which of course means that the previous
patch needs to add const annotations.

I think you should actually have multiple dispatch variables: with icount and
without, with mttcg and without.  That way these methods don't have to check
icount_enabled() or qemu_tcg_mttcg_enabled() at runtime, only at startup.


r~

Re: [PATCH v5 02/14] cpus: prepare new CpusAccel cpu accelerator interface

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
>  uint64_t cpu_get_tsc(CPUX86State *env)
>  {
> -return cpu_get_ticks();
> +return cpus_get_elapsed_ticks();

What has this change got to do with creating the interface?
You said the interface wasn't used yet...


> diff --git a/stubs/cpu-synchronize-state.c b/stubs/cpu-synchronize-state.c
> new file mode 100644
> index 00..3112fe439d
> --- /dev/null
> +++ b/stubs/cpu-synchronize-state.c
> @@ -0,0 +1,15 @@
> +#include "qemu/osdep.h"
> +#include "sysemu/hw_accel.h"
> +
> +void cpu_synchronize_state(CPUState *cpu)
> +{
> +}
> +void cpu_synchronize_post_reset(CPUState *cpu)
> +{
> +}
> +void cpu_synchronize_post_init(CPUState *cpu)
> +{
> +}
> +void cpu_synchronize_pre_loadvm(CPUState *cpu)
> +{
> +}
> diff --git a/stubs/cpus-get-virtual-clock.c b/stubs/cpus-get-virtual-clock.c
> new file mode 100644
> index 00..fd447d53f3
> --- /dev/null
> +++ b/stubs/cpus-get-virtual-clock.c
> @@ -0,0 +1,8 @@
> +#include "qemu/osdep.h"
> +#include "sysemu/cpu-timers.h"
> +#include "qemu/main-loop.h"
> +
> +int64_t cpus_get_virtual_clock(void)
> +{
> +return cpu_get_clock();
> +}

How do these stubs get used?


r~

Re: [PATCH v5 01/14] cpu-timers, icount: new modules

[Richard Henderson]

On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +/*
> + * Return the icount enablement state:
> + *
> + * 0 = Disabled - Do not count executed instructions.
> + * 1 = Enabled - Fixed conversion of insn to ns via "shift" option
> + * 2 = Enabled - Runtime adaptive algorithm to compute shift
> + */
> +int icount_enabled(void);

Why does use_icount need to change to a function?

If it does, or even if this just comes under the heading of cleanup, it should
certainly be done in a separate patch.

Either way, I think we should expose the fact that this is always disabled when
#ifndef CONFIG_TCG, just like we do for tcg_enabled().

> -if (use_icount) {
> -return cpu_get_icount();
> +if (icount_enabled()) {
> +return icount_get();

Renaming of other functions like this should also be done in a separate patch.


r~

Re: [PATCH v3 1/1] cputlb: Make store_helper less fragile to compiler optimizations

[Shu-Chun Weng]

Can confirm this fixed the build in our configuration. Thank you.

Shu-Chun

On Thu, Aug 13, 2020 at 1:40 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> This has no functional change.
>
> The current function structure is:
>
> inline QEMU_ALWAYSINLINE
> store_memop() {
> switch () {
> ...
> default:
> qemu_build_not_reached();
> }
> }
> inline QEMU_ALWAYSINLINE
> store_helper() {
> ...
> if (span_two_pages_or_io) {
> ...
> helper_ret_stb_mmu();
> }
> store_memop();
> }
> helper_ret_stb_mmu() {
> store_helper();
> }
>
> Whereas GCC will generate an error at compile-time when an always_inline
> function is not inlined, Clang does not.  Nor does Clang prioritize the
> inlining of always_inline functions.  Both of these are arguably bugs.
>
> Both `store_memop` and `store_helper` need to be inlined and allow
> constant propogations to eliminate the `qemu_build_not_reached` call.
>
> However, if the compiler instead chooses to inline helper_ret_stb_mmu
> into store_helper, then store_helper is now self-recursive and the
> compiler is no longer able to propagate the constant in the same way.
>
> This does not produce at current QEMU head, but was reproducible
> at v4.2.0 with `clang-10 -O2 -fexperimental-new-pass-manager`.
>
> The inline recursion problem can be fixed solely by marking
> helper_ret_stb_mmu as noinline, so the compiler does not make an
> incorrect decision about which functions to inline.
>
> In addition, extract store_helper_unaligned as a noinline subroutine
> that can be shared by all of the helpers.  This saves about 6k code
> size in an optimized x86_64 build.
>
> Reported-by: Shu-Chun Weng 
> Reviewed-by: Alex Bennée 
> Signed-off-by: Richard Henderson 
> ---
>  accel/tcg/cputlb.c | 138 ++---
>  1 file changed, 79 insertions(+), 59 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 5698292749..7e603d 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -2009,6 +2009,80 @@ store_memop(void *haddr, uint64_t val, MemOp op)
>  }
>  }
>
> +static void __attribute__((noinline))
> +store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
> +   uintptr_t retaddr, size_t size, uintptr_t mmu_idx,
> +   bool big_endian)
> +{
> +const size_t tlb_off = offsetof(CPUTLBEntry, addr_write);
> +uintptr_t index, index2;
> +CPUTLBEntry *entry, *entry2;
> +target_ulong page2, tlb_addr, tlb_addr2;
> +TCGMemOpIdx oi;
> +size_t size2;
> +int i;
> +
> +/*
> + * Ensure the second page is in the TLB.  Note that the first page
> + * is already guaranteed to be filled, and that the second page
> + * cannot evict the first.
> + */
> +page2 = (addr + size) & TARGET_PAGE_MASK;
> +size2 = (addr + size) & ~TARGET_PAGE_MASK;
> +index2 = tlb_index(env, mmu_idx, page2);
> +entry2 = tlb_entry(env, mmu_idx, page2);
> +
> +tlb_addr2 = tlb_addr_write(entry2);
> +if (!tlb_hit_page(tlb_addr2, page2)) {
> +if (!victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) {
> +tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> +index2 = tlb_index(env, mmu_idx, page2);
> +entry2 = tlb_entry(env, mmu_idx, page2);
> +}
> +tlb_addr2 = tlb_addr_write(entry2);
> +}
> +
> +index = tlb_index(env, mmu_idx, addr);
> +entry = tlb_entry(env, mmu_idx, addr);
> +tlb_addr = tlb_addr_write(entry);
> +
> +/*
> + * Handle watchpoints.  Since this may trap, all checks
> + * must happen before any store.
> + */
> +if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
> +cpu_check_watchpoint(env_cpu(env), addr, size - size2,
> + env_tlb(env)->d[mmu_idx].iotlb[index].attrs,
> + BP_MEM_WRITE, retaddr);
> +}
> +if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) {
> +cpu_check_watchpoint(env_cpu(env), page2, size2,
> + env_tlb(env)->d[mmu_idx].iotlb[index2].attrs,
> + BP_MEM_WRITE, retaddr);
> +}
> +
> +/*
> + * XXX: not efficient, but simple.
> + * This loop must go in the forward direction to avoid issues
> + * with self-modifying code in Windows 64-bit.
> + */
> +oi = make_memop_idx(MO_UB, mmu_idx);
> +if (big_endian) {
> +for (i = 0; i < size; ++i) {
> +/* Big-endian extract.  */
> +uint8_t val8 = val >> (((size - 1) * 8) - (i * 8));
> +helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr);
> +}
> +} else {
> +for (i = 0; i < size; ++i) {
> +/* Little-endian extract.  */
> +uint8_t val8 = val >> (i * 8);
> +

[Bug 1805256] Re: qemu-img hangs on rcu_call_ready_event logic in Aarch64 when converting images

[dann frazier]

** Changed in: kunpeng920/ubuntu-18.04-hwe
   Status: Triaged => Fix Committed

** Changed in: kunpeng920/ubuntu-18.04
   Status: Triaged => Fix Committed

** Changed in: kunpeng920
   Status: Triaged => Fix Committed

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1805256

Title:
  qemu-img hangs on rcu_call_ready_event logic in Aarch64 when
  converting images

Status in kunpeng920:
  Fix Committed
Status in kunpeng920 ubuntu-18.04 series:
  Fix Committed
Status in kunpeng920 ubuntu-18.04-hwe series:
  Fix Committed
Status in kunpeng920 ubuntu-19.10 series:
  Fix Released
Status in kunpeng920 ubuntu-20.04 series:
  Fix Released
Status in kunpeng920 upstream-kernel series:
  Invalid
Status in QEMU:
  Fix Released
Status in qemu package in Ubuntu:
  Fix Released
Status in qemu source package in Bionic:
  Fix Committed
Status in qemu source package in Eoan:
  Fix Released
Status in qemu source package in Focal:
  Fix Released

Bug description:
  
  SRU TEAM REVIEWER: This has already been SRUed for Focal, Eoan and Bionic. 
Unfortunately the Bionic SRU did not work and we had to reverse the change. 
Since then we had another update and now I'm retrying the SRU.

  After discussing with @paelzer (and @dannf as a reviewer) extensively,
  Christian and I agreed that we should scope this SRU as Aarch64 only
  AND I was much, much more conservative in question of what is being
  changed in the AIO qemu code.

  New code has been tested against the initial Test Case and the new
  one, regressed for Bionic. More information (about tests and
  discussion) can be found in the MR at
  ~rafaeldtinoco/ubuntu/+source/qemu:lp1805256-bionic-refix

  BIONIC REGRESSION BUG:

  https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1885419

  [Impact]

  * QEMU locking primitives might face a race condition in QEMU Async
  I/O bottom halves scheduling. This leads to a dead lock making either
  QEMU or one of its tools to hang indefinitely.

  [Test Case]

  INITIAL

  * qemu-img convert -f qcow2 -O qcow2 ./disk01.qcow2 ./output.qcow2

  Hangs indefinitely approximately 30% of the runs in Aarch64.

  [Regression Potential]

  * This is a change to a core part of QEMU: The AIO scheduling. It
  works like a "kernel" scheduler, whereas kernel schedules OS tasks,
  the QEMU AIO code is responsible to schedule QEMU coroutines or event
  listeners callbacks.

  * There was a long discussion upstream about primitives and Aarch64.
  After quite sometime Paolo released this patch and it solves the
  issue. Tested platforms were: amd64 and aarch64 based on his commit
  log.

  * Christian suggests that this fix stay little longer in -proposed to
  make sure it won't cause any regressions.

  * dannf suggests we also check for performance regressions; e.g. how
  long it takes to convert a cloud image on high-core systems.

  BIONIC REGRESSED ISSUE

  https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1885419

  [Other Info]

   * Original Description bellow:

  Command:

  qemu-img convert -f qcow2 -O qcow2 ./disk01.qcow2 ./output.qcow2

  Hangs indefinitely approximately 30% of the runs.

  

  Workaround:

  qemu-img convert -m 1 -f qcow2 -O qcow2 ./disk01.qcow2 ./output.qcow2

  Run "qemu-img convert" with "a single coroutine" to avoid this issue.

  

  (gdb) thread 1
  ...
  (gdb) bt
  #0 0xbf1ad81c in __GI_ppoll
  #1 0xaabcf73c in ppoll
  #2 qemu_poll_ns
  #3 0xaabd0764 in os_host_main_loop_wait
  #4 main_loop_wait
  ...

  (gdb) thread 2
  ...
  (gdb) bt
  #0 syscall ()
  #1 0xaabd41cc in qemu_futex_wait
  #2 qemu_event_wait (ev=ev@entry=0xaac86ce8 )
  #3 0xaabed05c in call_rcu_thread
  #4 0xaabd34c8 in qemu_thread_start
  #5 0xbf25c880 in start_thread
  #6 0xbf1b6b9c in thread_start ()

  (gdb) thread 3
  ...
  (gdb) bt
  #0 0xbf11aa20 in __GI___sigtimedwait
  #1 0xbf2671b4 in __sigwait
  #2 0xaabd1ddc in sigwait_compat
  #3 0xaabd34c8 in qemu_thread_start
  #4 0xbf25c880 in start_thread
  #5 0xbf1b6b9c in thread_start

  

  (gdb) run
  Starting program: /usr/bin/qemu-img convert -f qcow2 -O qcow2
  ./disk01.ext4.qcow2 ./output.qcow2

  [New Thread 0xbec5ad90 (LWP 72839)]
  [New Thread 0xbe459d90 (LWP 72840)]
  [New Thread 0xbdb57d90 (LWP 72841)]
  [New Thread 0xacac9d90 (LWP 72859)]
  [New Thread 0xa7ffed90 (LWP 72860)]
  [New Thread 0xa77fdd90 (LWP 72861)]
  [New Thread 0xa6ffcd90 (LWP 72862)]
  [New Thread 0xa67fbd90 (LWP 72863)]
  [New Thread 0xa5ffad90 (LWP 72864)]

  [Thread 0xa5ffad90 (LWP 72864) exited]
  [Thread 0xa6ffcd90 (LWP 72862) exited]
  [Thread 0xa77fdd90 (LWP 72861) exited]
  [Thread 0xbdb57d90 (LWP 72841) exited]
  [Thread 0xa67fbd90 (LWP 72863) exited]
  [Thread 0xacac9d90 (LWP 72859) exited]
  [Thread 0xa7ffed90 

Re: [PATCH 7/7] target/arm/cpu: spe: Enable spe to work with host cpu

[Richard Henderson]

On 8/11/20 9:49 AM, Andrew Jones wrote:
> Yes, except you need to drop the ARM_FEATURE_SPE define and use the ID
> register bit instead like "sve_supported" does.

On a related note, I think we have a latent bug, or at least a mis-feature:

sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
...
/* Add feature bits that can't appear until after VCPU init. */
if (sve_supported) {
t = ahcf->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
ahcf->isar.id_aa64pfr0 = t;
}


Should it in fact be

if (!sve_supported) {
t = ahcf->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 0);
ahcf->isar.id_aa64pfr0 = t;
}

?

Forcing the value to 1 here is going to be wrong the moment we have an SVE2
enabled cpu.

Similarly, SPE has more than one "enabled" value for PMSVer.


r~

Re: [PATCH 2/7] target/arm/kvm: spe: Add helper to detect SPE when using KVM

[Richard Henderson]

On 8/7/20 1:10 AM, Haibo Xu wrote:
> Signed-off-by: Haibo Xu 
> ---
>  target/arm/kvm.c |  5 +
>  target/arm/kvm_arm.h | 13 +
>  2 files changed, 18 insertions(+)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 3/7] target/arm/cpu: spe: Add an option to turn on/off vSPE support

[Richard Henderson]

On 8/7/20 1:10 AM, Haibo Xu wrote:
> +static void arm_set_spe(Object *obj, bool value, Error **errp)
> +{
> +ARMCPU *cpu = ARM_CPU(obj);
> +
> +if (value) {
> +if (kvm_enabled() && !kvm_arm_spe_supported()) {
> +error_setg(errp, "'spe' feature not supported by KVM on this 
> host");
> +return;
> +}
> +set_feature(>env, ARM_FEATURE_SPE);
> +} else {
> +unset_feature(>env, ARM_FEATURE_SPE);
> +}
> +cpu->has_spe = value;
> +}

I think you want to simply set cpu->has_spe here, and leave the adjustment of
ID_AA64DFR0 to a finalize routine.  Because there are multiple values that
PMSVer can take.

Once the get/set routines are only setting a flag on ARMCPU, you can use a
simpler property interface:

static Property arm_cpu_spe_property =
DEFINE_PROP_BOOL("spe", ARMCPU, has_spe, true);

qdev_property_add_static(DEVICE(obj), _cpu_spe_property);

The finalize routine would be called from arm_cpu_finalize_features(), much
like the existing arm_cpu_sve_finalize().

Since you're only registering the spe property when the selected cpu supports
spe, the finalize routine only needs to set PMSVer to 0 to turn it off,
preserving the initial enabled value of 1 or 2.


r~

Re: [PATCH 3/7] target/arm/cpu: spe: Add an option to turn on/off vSPE support

[Richard Henderson]

On 8/10/20 3:50 AM, Andrew Jones wrote:
>> @@ -1959,6 +1961,7 @@ enum arm_features {
>>  ARM_FEATURE_VBAR, /* has cp15 VBAR */
>>  ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
>>  ARM_FEATURE_M_MAIN, /* M profile Main Extension */
>> +ARM_FEATURE_SPE, /* has SPE support */
> 
> We shouldn't need to add this feature bit. SPE should have an ID register
> bit to use instead.

Yes indeed: ID_AA64DFR0_EL1.PMSVer.


r~

Re: [PATCH v5 09/20] docs/sphinx: Add new qapi-doc Sphinx extension

[Richard Henderson]

On 8/10/20 12:50 PM, Peter Maydell wrote:
> Some of our documentation is auto-generated from documentation
> comments in the JSON schema.
> 
> For Sphinx, rather than creating a file to include, the most natural
> way to handle this is to have a small custom Sphinx extension which
> processes the JSON file and inserts documentation into the rST
> file being processed.
> 
> This is the same approach that kerneldoc and hxtool use.
> 
> Signed-off-by: Peter Maydell 
> ---
> Changes v4->v5: match the changes in parameters to the
> various visit_* methods from commit 7b3bc9e28f366
> ---
>  docs/conf.py   |   6 +-
>  docs/sphinx/qapidoc.py | 504 +
>  MAINTAINERS|   1 +
>  3 files changed, 510 insertions(+), 1 deletion(-)
>  create mode 100644 docs/sphinx/qapidoc.py

Reviewed-by: Richard Henderson 

r~

Re: [PATCH v5 02/20] qapi: Fix indentation, again

[Richard Henderson]

On 8/10/20 12:50 PM, Peter Maydell wrote:
> In commit 26ec4e53f2 and similar commits we fixed the indentation
> for doc comments in our qapi json files to follow a new stricter
> standard for indentation, which permits only:
> @arg: description line 1
>   description line 2
> 
> or:
> @arg:
> line 1
> line 2
> 
> Unfortunately since we didn't manage to get the script changes that
> enforced the new style in, a variety of commits (eg df4097aeaf71,
> 2e4457032105) introduced new doc text which doesn't follow the new
> stricter rules for indentation on multi-line doc comments.  Bring
> those into line with the new rules.
> 
> Signed-off-by: Peter Maydell 
> ---

Reviewed-by: Richard Henderson 

r~

Re: [PATCH v5 03/20] qapi/block-core.json: Fix nbd-server-start docs

[Richard Henderson]

On 8/10/20 12:50 PM, Peter Maydell wrote:
> Commit eed8b6917832 added some new text to the nbd-server-start
> documentation in the wrong place.  Since this is after the 'Returns:'
> line it's parsed as if it were part of the documentation of the
> "Returns:' information.  Move it up to join the rest of the
> "documentation of the type as a whole" doc text.
> 
> This doesn't look odd in the current HTML rendering, but the
> new QAPI-to-rST handling will complain about the indent level
> of the lines not matching up with the 'Returns:' line.
> 
> Signed-off-by: Peter Maydell 
> ---
>  qapi/block-core.json | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson 

r~

Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

[Richard Henderson]

On 8/13/20 7:48 PM, Frank Chang wrote:
> esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
> 
>> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)        \
>> void HELPER(NAME)(void *vd, void * v0, target_ulong base,  \
>>                   target_ulong stride, CPURISCVState *env, \
>>                   uint32_t desc)                           \
>> {                                                          \
>>     uint32_t vm = vext_vm(desc);                           \
>>     vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
>>                      sizeof(ETYPE), GETPC(), MMU_DATA_LOAD);       \
>> }
>>
>> GEN_VEXT_LD_STRIDE(vlse8_v,  int8_t,  lde_b)
> 
> which is calculated by sizeof(ETYPE), so the results would be: 1, 2, 4, 8.
> and vext_max_elems() is called by e.g. vext_ldst_stride():

Ah, yes.

>> uint32_t max_elems = vext_max_elems(desc, esz);
> 
> I can add another parameter to the macro and pass the hard-coded log2(esz) 
> number
> if it's the better way instead of using ctzl().
> Or if there's another approach to get the log2(esz) number more elegantly?

Using ctzl(sizeof(type)) in the GEN_VEXT_LD_STRIDE macro will work well.  This
will be constant folded by the compiler.


r~

DROP Re: [PATCH v2 0/9] preallocate filter

[Vladimir Sementsov-Ogievskiy]

v3 will come soon, don't look at this.

14.08.2020 16:03, Vladimir Sementsov-Ogievskiy wrote:

Hi all!

Here is a filter, which does preallocation on write.

In Virtuozzo we have to deal with some custom distributed storage
solution, where allocation is relatively expensive operation. We have to
workaround it in Qemu, so here is a new filter.

For the details refer to original cover-letter
"[PATCH 0/5] preallocate filter"
https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg06443.html

v2:
1-6 are new and substitutes bdrv_co_range_try_lock mechanism used in v1
07: add note to docs/system/qemu-block-drivers.rst.inc
 add open options
 rebase on new BDRV_REQ_NO_WAIT flag
 drop bs->file check in _co_flush()
08: new
09: use new iotests.verify_o_direct()

Vladimir Sementsov-Ogievskiy (9):
   block: simplify comment to BDRV_REQ_SERIALISING
   block/io.c: drop assertion on double waiting for request serialisation
   block/io: split out bdrv_find_conflicting_request
   block/io: bdrv_wait_serialising_requests_locked: drop extra bs arg
   block: bdrv_mark_request_serialising: split non-waiting function
   block: introduce BDRV_REQ_NO_WAIT flag
   block: introduce preallocate filter
   iotests.py: add verify_o_direct helper
   iotests: add 298 to test new preallocate filter driver

  docs/system/qemu-block-drivers.rst.inc |  26 +++
  qapi/block-core.json   |  20 +-
  include/block/block.h  |  20 +-
  include/block/block_int.h  |   3 +-
  block/file-posix.c |   2 +-
  block/io.c | 131 +++-
  block/preallocate.c| 264 +
  block/Makefile.objs|   1 +
  tests/qemu-iotests/298 |  46 +
  tests/qemu-iotests/298.out |   5 +
  tests/qemu-iotests/group   |   1 +
  tests/qemu-iotests/iotests.py  |   6 +
  12 files changed, 457 insertions(+), 68 deletions(-)
  create mode 100644 block/preallocate.c
  create mode 100644 tests/qemu-iotests/298
  create mode 100644 tests/qemu-iotests/298.out




--
Best regards,
Vladimir

Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1597423256-14847-1-git-send-email-bmeng...@gmail.com/



Hi,

This series failed the docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

  TESTcheck-unit: tests/test-char
Unexpected error in object_property_try_add() at 
/tmp/qemu-test/src/qom/object.c:1181:
attempt to add duplicate property 'serial-id' to object (type 'container')
ERROR test-char - too few tests run (expected 38, got 9)
make: *** [check-unit] Error 1
make: *** Waiting for unfinished jobs
  TESTcheck-qtest-x86_64: tests/qtest/hd-geo-test
qemu-system-aarch64: -accel kvm: invalid accelerator kvm
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', 
'--label', 'com.qemu.instance.uuid=5d87ed4b32104d3fa300f89248e59809', '-u', 
'1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', 
'-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-okrr9kbl/src/docker-src.2020-08-14-13.56.55.12251:/var/tmp/qemu:z,ro',
 'qemu/centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=5d87ed4b32104d3fa300f89248e59809
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-okrr9kbl/src'
make: *** [docker-run-test-quick@centos7] Error 2

real13m35.300s
user0m8.266s


The full log is available at
http://patchew.org/logs/1597423256-14847-1-git-send-email-bmeng...@gmail.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PATCH 1/1] qcow2: Skip copy-on-write when allocating a zero cluster

[Vladimir Sementsov-Ogievskiy]

14.08.2020 17:57, Alberto Garcia wrote:

Since commit c8bb23cbdbe32f5c326365e0a82e1b0e68cdcd8a when a write
request results in a new allocation QEMU first tries to see if the
rest of the cluster outside the written area contains only zeroes.

In that case, instead of doing a normal copy-on-write operation and
writing explicit zero buffers to disk, the code zeroes the whole
cluster efficiently using pwrite_zeroes() with BDRV_REQ_NO_FALLBACK.

This improves performance very significantly but it only happens when
we are writing to an area that was completely unallocated before. Zero
clusters (QCOW2_CLUSTER_ZERO_*) are treated like normal clusters and
are therefore slower to allocate.

This happens because the code uses bdrv_is_allocated_above() rather
bdrv_block_status_above(). The former is not as accurate for this
purpose but it is faster. However in the case of qcow2 the underlying
call does already report zero clusters just fine so there is no reason
why we cannot use that information.

After testing 4KB writes on an image that only contains zero clusters
this patch results in almost five times more IOPS.


Would be great to add this case to simplebench as well.

The idea is good, but I'm a bit confused with new interface.

As I understand the "The former is not as accurate for this
purpose but it is faster" is related to (and only to) want_zero
parameter of block_status. bdrv_is_allocated_above is about
allocation (in terms of backing chains), and is_unallocated() is
just wrong user (with wrong name:)): it actually want another kind
of information.
So, for me it looks like we need an interface to
bdrv_block_status_above with want_zero=false (add another
function, or add this parameter to public interface).

And even with your approach, I'd keep original
bdrv_is_allocated_above as is, and just add new function with *is_zero
argument, to not modify all users of bdrv_is_allocated_above to pass
additional NULL value, in this way patch will touch less files.

Also, note, I have a series about block_status & is_allocated:
"[PATCH v5 0/5] fix & merge block_status_above and is_allocated_above"
(me go and ping it), which a bit reduces all the mess around
block_status & is_allocated.



--
Best regards,
Vladimir

Re: [PATCH 0/1] qcow2: Skip copy-on-write when allocating a zero cluster

[Vladimir Sementsov-Ogievskiy]

Hi!

14.08.2020 17:57, Alberto Garcia wrote:

Hi,

the patch is self-explanatory, but I'm using the cover letter to raise
a couple of related questions.

Since commit c8bb23cbdbe / QEMU 4.1.0 (and if the storage backend
allows it) writing to an image created with preallocation=metadata can
be slower (20% in my tests) than writing to an image with no
preallocation at all.

So:

a) shall we include a warning in the documentation ("note that this
preallocation mode can result in worse performance")?


I think, the best thing to do is to make it work fast in all cases if possible 
(I assume, that would be, with your patch + positive answer to [b]? Or not?) :)

Andrey recently added a benchmark, with some cases, where c8bb23cbdbe bring 
benefits:
[PATCH v6] scripts/simplebench: compare write request performance
<1594741846-475697-1-git-send-email-andrey.shinkev...@virtuozzo.com>
queued in Eduardo's python-next: 
https://github.com/ehabkost/qemu/commit/9519f87d900b0ef30075c749fa097bd93471553f

So, as a first step, could you post your tests, so we can add it into this 
benchmark? Or post a patch to simplebench on top of Eduardo's python-next.



b) why don't we also initialize preallocated clusters with
QCOW_OFLAG_ZERO? (at least when there's no subclusters involved,
i.e. no backing file). This would make reading from them (and
writing to them, after this patch) faster.


Probably, they are not guaranteed to be zero on all filesystems? But I think at 
least in some cases (99% :) we can mark them as ZERO.. Honestly, I may be not 
aware of actual reasons.



Berto

Alberto Garcia (1):
   qcow2: Skip copy-on-write when allocating a zero cluster

  include/block/block.h |  2 +-
  block/commit.c|  2 +-
  block/io.c| 20 +---
  block/mirror.c|  3 ++-
  block/qcow2.c | 26 --
  block/replication.c   |  2 +-
  block/stream.c|  2 +-
  qemu-img.c|  2 +-
  8 files changed, 40 insertions(+), 19 deletions(-)




--
Best regards,
Vladimir

Re: [PATCH 30/41] qom: Make type checker functions accept const pointers

[Philippe Mathieu-Daudé]

On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> The existing type check macros all unconditionally drop const
> qualifiers from their arguments.  Keep this behavior in the
> macros generated by DECLARE_*CHECKER* by now.
> 
> In the future, we might use _Generic to preserve const-ness of
> the cast function arguments.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  include/qom/object.h | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/include/qom/object.h b/include/qom/object.h
> index 4cd84998c2..1d6a520d35 100644
> --- a/include/qom/object.h
> +++ b/include/qom/object.h
> @@ -567,7 +567,7 @@ struct Object
>   */
>  #define DECLARE_INSTANCE_CHECKER(InstanceType, OBJ_NAME, TYPENAME) \
>  static inline G_GNUC_UNUSED InstanceType * \
> -OBJ_NAME(void *obj) \
> +OBJ_NAME(const void *obj) \
>  { return OBJECT_CHECK(InstanceType, obj, TYPENAME); }
>  
>  /**
> @@ -581,14 +581,16 @@ struct Object
>   *
>   * This macro will provide the three standard type cast functions for a
>   * QOM type.
> + *
> + *FIXME: Use _Generic to make this const-safe
>   */
>  #define DECLARE_CLASS_CHECKERS(ClassType, OBJ_NAME, TYPENAME) \
>  static inline G_GNUC_UNUSED ClassType * \
> -OBJ_NAME##_GET_CLASS(void *obj) \
> +OBJ_NAME##_GET_CLASS(const void *obj) \
>  { return OBJECT_GET_CLASS(ClassType, obj, TYPENAME); } \
>  \
>  static inline G_GNUC_UNUSED ClassType * \
> -OBJ_NAME##_CLASS(void *klass) \
> +OBJ_NAME##_CLASS(const void *klass) \
>  { return OBJECT_CLASS_CHECK(ClassType, klass, TYPENAME); }
>  
>  /**
> 

Re: [PATCH 18/41] i8254: Move PITCommonState/PITCommonClass typedefs to i8254.h

[Philippe Mathieu-Daudé]

On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  include/hw/timer/i8254.h  | 2 ++
>  include/hw/timer/i8254_internal.h | 8 
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/include/hw/timer/i8254.h b/include/hw/timer/i8254.h
> index e75b4a5a08..206b8f8464 100644
> --- a/include/hw/timer/i8254.h
> +++ b/include/hw/timer/i8254.h
> @@ -39,6 +39,8 @@ typedef struct PITChannelInfo {
>  } PITChannelInfo;
>  
>  #define TYPE_PIT_COMMON "pit-common"
> +typedef struct PITCommonState PITCommonState;
> +typedef struct PITCommonClass PITCommonClass;
>  #define PIT_COMMON(obj) \
>   OBJECT_CHECK(PITCommonState, (obj), TYPE_PIT_COMMON)
>  #define PIT_COMMON_CLASS(klass) \
> diff --git a/include/hw/timer/i8254_internal.h 
> b/include/hw/timer/i8254_internal.h
> index 3db462aecd..a9a600d941 100644
> --- a/include/hw/timer/i8254_internal.h
> +++ b/include/hw/timer/i8254_internal.h
> @@ -50,14 +50,14 @@ typedef struct PITChannelState {
>  uint32_t irq_disabled;
>  } PITChannelState;
>  
> -typedef struct PITCommonState {
> +struct PITCommonState {
>  ISADevice dev;
>  MemoryRegion ioports;
>  uint32_t iobase;
>  PITChannelState channels[3];
> -} PITCommonState;
> +};
>  
> -typedef struct PITCommonClass {
> +struct PITCommonClass {
>  ISADeviceClass parent_class;
>  
>  void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int 
> val);
> @@ -65,7 +65,7 @@ typedef struct PITCommonClass {
>   PITChannelInfo *info);
>  void (*pre_save)(PITCommonState *s);
>  void (*post_load)(PITCommonState *s);
> -} PITCommonClass;
> +};
>  
>  int pit_get_out(PITChannelState *s, int64_t current_time);
>  int64_t pit_get_next_transition_time(PITChannelState *s, int64_t 
> current_time);
> 

Re: [PATCH 22/41] can_emu: Delete macros for non-existing typedef

[Philippe Mathieu-Daudé]

On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> CanBusClass doesn't exist.  This will break when we automatically
> convert the code to use OBJECT_DEFINE_TYPE().  Delete the macros
> that reference the non-existing typedef.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  include/net/can_emu.h | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/include/net/can_emu.h b/include/net/can_emu.h
> index fce9770928..7e90fd8a45 100644
> --- a/include/net/can_emu.h
> +++ b/include/net/can_emu.h
> @@ -100,10 +100,6 @@ struct CanBusClientState {
>  };
>  
>  #define TYPE_CAN_BUS "can-bus"
> -#define CAN_BUS_CLASS(klass) \
> - OBJECT_CLASS_CHECK(CanBusClass, (klass), TYPE_CAN_BUS)
> -#define CAN_BUS_GET_CLASS(obj) \
> - OBJECT_GET_CLASS(CanBusClass, (obj), TYPE_CAN_BUS)
>  #define CAN_BUS(obj) \
>   OBJECT_CHECK(CanBusState, (obj), TYPE_CAN_BUS)
>  
> 

Re: [PATCH 23/41] nubus: Delete unused NUBUS_BRIDGE macro

[Philippe Mathieu-Daudé]

On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> The macro never worked because the NubusBridge typedef doesn't
> exist.  Delete it.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  include/hw/nubus/nubus.h | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h
> index a8634e54c5..c350948262 100644
> --- a/include/hw/nubus/nubus.h
> +++ b/include/hw/nubus/nubus.h
> @@ -29,7 +29,6 @@
>  #define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS)
>  
>  #define TYPE_NUBUS_BRIDGE "nubus-bridge"
> -#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRIDGE)
>  
>  typedef struct NubusBus {
>  BusState qbus;
> 

Re: [PATCH v5 0/5] fix & merge block_status_above and is_allocated_above

[Vladimir Sementsov-Ogievskiy]

ping :)

10.06.2020 15:04, Vladimir Sementsov-Ogievskiy wrote:

v5: rebase on coroutine-wrappers series, 02 changed correspondingly

Based on series "[PATCH v7 0/7] coroutines: generate wrapper code", or
in other words:
Based-on: <20200610100336.23451-1-vsement...@virtuozzo.com>

Hi all!

These series are here to address the following problem:
block-status-above functions may consider space after EOF of
intermediate backing files as unallocated, which is wrong, as these
backing files are the reason of producing zeroes, we never go further by
backing chain after a short backing file. So, if such short-backing file
is _inside_ requested sub-chain of the backing chain, we should never
report space after its EOF as unallocated.

See patches 01,04,05 for details.

Note, that this series leaves for another day the general problem
around block-status: misuse of BDRV_BLOCK_ALLOCATED as is-fs-allocated
vs go-to-backing.
Audit for this problem is done here:
"backing chain & block status & filters"
https://lists.gnu.org/archive/html/qemu-devel/2020-04/msg04706.html
And I'm going to prepare series to address this problem.

Also, get_block_status func have same disease, but remains unfixed here:
I want to make separate series for it, as it need some more refactoring,
which should be based on series
"[PATCH v5 0/7] coroutines: generate wrapper code"

Vladimir Sementsov-Ogievskiy (5):
   block/io: fix bdrv_co_block_status_above
   block/io: bdrv_common_block_status_above: support include_base
   block/io: bdrv_common_block_status_above: support bs == base
   block/io: fix bdrv_is_allocated_above
   iotests: add commit top->base cases to 274

  block/coroutines.h |   2 +
  block/io.c | 100 ++---
  block/qcow2.c  |  16 +-
  tests/qemu-iotests/274 |  20 
  tests/qemu-iotests/274.out |  65 
  5 files changed, 150 insertions(+), 53 deletions(-)




--
Best regards,
Vladimir

Re: [PATCH 15/41] tulip: Move TulipState typedef to header

[Philippe Mathieu-Daudé]

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  hw/net/tulip.h | 1 +
>  hw/net/tulip.c | 4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/net/tulip.h b/hw/net/tulip.h
> index 5271aad8d5..c3fcd4d4e1 100644
> --- a/hw/net/tulip.h
> +++ b/hw/net/tulip.h
> @@ -5,6 +5,7 @@
>  #include "net/net.h"
>  
>  #define TYPE_TULIP "tulip"
> +typedef struct TULIPState TULIPState;
>  #define TULIP(obj) OBJECT_CHECK(TULIPState, (obj), TYPE_TULIP)
>  
>  #define CSR(_x) ((_x) << 3)
> diff --git a/hw/net/tulip.c b/hw/net/tulip.c
> index 4487fd61cf..ca69f7ea5e 100644
> --- a/hw/net/tulip.c
> +++ b/hw/net/tulip.c
> @@ -18,7 +18,7 @@
>  #include "trace.h"
>  #include "net/eth.h"
>  
> -typedef struct TULIPState {
> +struct TULIPState {
>  PCIDevice dev;
>  MemoryRegion io;
>  MemoryRegion memory;
> @@ -44,7 +44,7 @@ typedef struct TULIPState {
>  
>  uint32_t rx_status;
>  uint8_t filter[16][6];
> -} TULIPState;
> +};
>  
>  static const VMStateDescription vmstate_pci_tulip = {
>  .name = "tulip",
> 

Re: [PATCH 16/41] throttle-groups: Move ThrottleGroup typedef to header

[Philippe Mathieu-Daudé]

On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  include/block/throttle-groups.h | 1 +
>  block/throttle-groups.c | 4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/block/throttle-groups.h b/include/block/throttle-groups.h
> index 712a8e64b4..5e77db700f 100644
> --- a/include/block/throttle-groups.h
> +++ b/include/block/throttle-groups.h
> @@ -59,6 +59,7 @@ typedef struct ThrottleGroupMember {
>  } ThrottleGroupMember;
>  
>  #define TYPE_THROTTLE_GROUP "throttle-group"
> +typedef struct ThrottleGroup ThrottleGroup;
>  #define THROTTLE_GROUP(obj) OBJECT_CHECK(ThrottleGroup, (obj), 
> TYPE_THROTTLE_GROUP)
>  
>  const char *throttle_group_get_name(ThrottleGroupMember *tgm);
> diff --git a/block/throttle-groups.c b/block/throttle-groups.c
> index 98fea7fd47..4e28365d8d 100644
> --- a/block/throttle-groups.c
> +++ b/block/throttle-groups.c
> @@ -63,7 +63,7 @@ static void timer_cb(ThrottleGroupMember *tgm, bool 
> is_write);
>   * access some other ThrottleGroupMember's timers only after verifying that
>   * that ThrottleGroupMember has throttled requests in the queue.
>   */
> -typedef struct ThrottleGroup {
> +struct ThrottleGroup {
>  Object parent_obj;
>  
>  /* refuse individual property change if initialization is complete */
> @@ -79,7 +79,7 @@ typedef struct ThrottleGroup {
>  
>  /* This field is protected by the global QEMU mutex */
>  QTAILQ_ENTRY(ThrottleGroup) list;
> -} ThrottleGroup;
> +};
>  
>  /* This is protected by the global QEMU mutex */
>  static QTAILQ_HEAD(, ThrottleGroup) throttle_groups =
> 

Re: [PATCH 14/41] hcd-dwc2: Rename USB_*CLASS macros for consistency

[Philippe Mathieu-Daudé]

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Rename the DWC2_CLASS to DWC2_USB_CLASS and DWC2_GET_CLASS to
> DWC2_USB_GET_CLASS, for consistency with the DWC2_USB macro.
> 
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  hw/usb/hcd-dwc2.h | 4 ++--
>  hw/usb/hcd-dwc2.c | 8 
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h
> index 4ba809a07b..54111d835e 100644
> --- a/hw/usb/hcd-dwc2.h
> +++ b/hw/usb/hcd-dwc2.h
> @@ -182,9 +182,9 @@ struct DWC2Class {
>  #define TYPE_DWC2_USB   "dwc2-usb"
>  #define DWC2_USB(obj) \
>  OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
> -#define DWC2_CLASS(klass) \
> +#define DWC2_USB_CLASS(klass) \
>  OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
> -#define DWC2_GET_CLASS(obj) \
> +#define DWC2_USB_GET_CLASS(obj) \
>  OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
>  
>  #endif
> diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
> index 56f91f6bee..97688d21bf 100644
> --- a/hw/usb/hcd-dwc2.c
> +++ b/hw/usb/hcd-dwc2.c
> @@ -1155,7 +1155,7 @@ static void dwc2_work_timer(void *opaque)
>  
>  static void dwc2_reset_enter(Object *obj, ResetType type)
>  {
> -DWC2Class *c = DWC2_GET_CLASS(obj);
> +DWC2Class *c = DWC2_USB_GET_CLASS(obj);
>  DWC2State *s = DWC2_USB(obj);
>  int i;
>  
> @@ -1239,7 +1239,7 @@ static void dwc2_reset_enter(Object *obj, ResetType 
> type)
>  
>  static void dwc2_reset_hold(Object *obj)
>  {
> -DWC2Class *c = DWC2_GET_CLASS(obj);
> +DWC2Class *c = DWC2_USB_GET_CLASS(obj);
>  DWC2State *s = DWC2_USB(obj);
>  
>  trace_usb_dwc2_reset_hold();
> @@ -1253,7 +1253,7 @@ static void dwc2_reset_hold(Object *obj)
>  
>  static void dwc2_reset_exit(Object *obj)
>  {
> -DWC2Class *c = DWC2_GET_CLASS(obj);
> +DWC2Class *c = DWC2_USB_GET_CLASS(obj);
>  DWC2State *s = DWC2_USB(obj);
>  
>  trace_usb_dwc2_reset_exit();
> @@ -1382,7 +1382,7 @@ static Property dwc2_usb_properties[] = {
>  static void dwc2_class_init(ObjectClass *klass, void *data)
>  {
>  DeviceClass *dc = DEVICE_CLASS(klass);
> -DWC2Class *c = DWC2_CLASS(klass);
> +DWC2Class *c = DWC2_USB_CLASS(klass);
>  ResettableClass *rc = RESETTABLE_CLASS(klass);
>  
>  dc->realize = dwc2_realize;
> 

Re: [PATCH 11/41] versatile: Fix typo in PCI_VPB_HOST definition

[Philippe Mathieu-Daudé]

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Signed-off-by: Eduardo Habkost 
> ---
>  hw/pci-host/versatile.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
> index 616882a80d..7e4aa467a2 100644
> --- a/hw/pci-host/versatile.c
> +++ b/hw/pci-host/versatile.c
> @@ -161,7 +161,7 @@ static const VMStateDescription pci_vpb_vmstate = {
>  
>  #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host"
>  #define PCI_VPB_HOST(obj) \
> -OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST)
> +OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCI_HOST)

Uh, since cd93dbf375 ("versatile_pci: Update to realize and instance
init functions") 7 years ago...

Reviewed-by: Philippe Mathieu-Daudé 

>  
>  typedef enum {
>  PCI_IMAP0 = 0x0,
> 

Re: [PATCH 08/41] opentitan: Rename memmap enum constants

[Philippe Mathieu-Daudé]

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Some of the enum constant names conflict with the QOM type check
> macros.  This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
> 
> Rename all the constants to IBEX_DEV_*, to avoid conflicts.
> 
> Signed-off-by: Eduardo Habkost 
> ---
>  include/hw/riscv/opentitan.h | 38 
>  hw/riscv/opentitan.c | 84 ++--
>  2 files changed, 61 insertions(+), 61 deletions(-)
> 
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 8f29b9cbbf..835a80f896 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -49,25 +49,25 @@ typedef struct OpenTitanState {
>  } OpenTitanState;
>  
>  enum {
> -IBEX_ROM,
> -IBEX_RAM,
> -IBEX_FLASH,
> -IBEX_UART,
> -IBEX_GPIO,
> -IBEX_SPI,
> -IBEX_FLASH_CTRL,
> -IBEX_RV_TIMER,
> -IBEX_AES,
> -IBEX_HMAC,
> -IBEX_PLIC,
> -IBEX_PWRMGR,
> -IBEX_RSTMGR,
> -IBEX_CLKMGR,
> -IBEX_PINMUX,
> -IBEX_ALERT_HANDLER,
> -IBEX_NMI_GEN,
> -IBEX_USBDEV,
> -IBEX_PADCTRL,
> +IBEX_DEV_ROM,
> +IBEX_DEV_RAM,
> +IBEX_DEV_FLASH,
> +IBEX_DEV_UART,
> +IBEX_DEV_GPIO,
> +IBEX_DEV_SPI,
> +IBEX_DEV_FLASH_CTRL,
> +IBEX_DEV_RV_TIMER,
> +IBEX_DEV_AES,
> +IBEX_DEV_HMAC,
> +IBEX_DEV_PLIC,
> +IBEX_DEV_PWRMGR,
> +IBEX_DEV_RSTMGR,
> +IBEX_DEV_CLKMGR,
> +IBEX_DEV_PINMUX,
> +IBEX_DEV_ALERT_HANDLER,
> +IBEX_DEV_NMI_GEN,
> +IBEX_DEV_USBDEV,
> +IBEX_DEV_PADCTRL,

Similarly, why is this enum in a public header and not local
to opentitan.c, only place where it is used?

>  };
>  
>  enum {
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index a8f0039e51..23ba3b4bfc 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -32,25 +32,25 @@ static const struct MemmapEntry {
>  hwaddr base;
>  hwaddr size;
>  } ibex_memmap[] = {
> -[IBEX_ROM] ={  0x8000, 16 * KiB },
> -[IBEX_RAM] ={  0x1000,  0x1 },
> -[IBEX_FLASH] =  {  0x2000,  0x8 },
> -[IBEX_UART] =   {  0x4000,  0x1 },
> -[IBEX_GPIO] =   {  0x4001,  0x1 },
> -[IBEX_SPI] ={  0x4002,  0x1 },
> -[IBEX_FLASH_CTRL] = {  0x4003,  0x1 },
> -[IBEX_PINMUX] = {  0x4007,  0x1 },
> -[IBEX_RV_TIMER] =   {  0x4008,  0x1 },
> -[IBEX_PLIC] =   {  0x4009,  0x1 },
> -[IBEX_PWRMGR] = {  0x400A,  0x1 },
> -[IBEX_RSTMGR] = {  0x400B,  0x1 },
> -[IBEX_CLKMGR] = {  0x400C,  0x1 },
> -[IBEX_AES] ={  0x4011,  0x1 },
> -[IBEX_HMAC] =   {  0x4012,  0x1 },
> -[IBEX_ALERT_HANDLER] =  {  0x4013,  0x1 },
> -[IBEX_NMI_GEN] ={  0x4014,  0x1 },
> -[IBEX_USBDEV] = {  0x4015,  0x1 },
> -[IBEX_PADCTRL] ={  0x4016,  0x1 }
> +[IBEX_DEV_ROM] ={  0x8000, 16 * KiB },
> +[IBEX_DEV_RAM] ={  0x1000,  0x1 },
> +[IBEX_DEV_FLASH] =  {  0x2000,  0x8 },
> +[IBEX_DEV_UART] =   {  0x4000,  0x1 },
> +[IBEX_DEV_GPIO] =   {  0x4001,  0x1 },
> +[IBEX_DEV_SPI] ={  0x4002,  0x1 },
> +[IBEX_DEV_FLASH_CTRL] = {  0x4003,  0x1 },
> +[IBEX_DEV_PINMUX] = {  0x4007,  0x1 },
> +[IBEX_DEV_RV_TIMER] =   {  0x4008,  0x1 },
> +[IBEX_DEV_PLIC] =   {  0x4009,  0x1 },
> +[IBEX_DEV_PWRMGR] = {  0x400A,  0x1 },
> +[IBEX_DEV_RSTMGR] = {  0x400B,  0x1 },
> +[IBEX_DEV_CLKMGR] = {  0x400C,  0x1 },
> +[IBEX_DEV_AES] ={  0x4011,  0x1 },
> +[IBEX_DEV_HMAC] =   {  0x4012,  0x1 },
> +[IBEX_DEV_ALERT_HANDLER] =  {  0x4013,  0x1 },
> +[IBEX_DEV_NMI_GEN] ={  0x4014,  0x1 },
> +[IBEX_DEV_USBDEV] = {  0x4015,  0x1 },
> +[IBEX_DEV_PADCTRL] ={  0x4016,  0x1 }
>  };
>  
>  static void opentitan_board_init(MachineState *machine)
> @@ -66,12 +66,12 @@ static void opentitan_board_init(MachineState *machine)
>  qdev_realize(DEVICE(>soc), NULL, _abort);
>  
>  memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
> -memmap[IBEX_RAM].size, _fatal);
> +memmap[IBEX_DEV_RAM].size, _fatal);
>  memory_region_add_subregion(sys_mem,
> -memmap[IBEX_RAM].base, main_mem);
> +memmap[IBEX_DEV_RAM].base, main_mem);
>  
>  if (machine->firmware) {
> -riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
> +riscv_load_firmware(machine->firmware, 

Re: [PATCH 06/41] allwinner-h3: Rename memmap enum constants

[Philippe Mathieu-Daudé]

+Niek as maintainer.

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Some of the enum constant names conflict with the QOM type check
> macros.  This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
> 
> Rename all the constants to AW_H3_DEV_*, to avoid conflicts.
> 
> Signed-off-by: Eduardo Habkost 
> ---
>  include/hw/arm/allwinner-h3.h |  62 -
>  hw/arm/allwinner-h3.c | 124 +-
>  hw/arm/orangepi.c |   6 +-
>  3 files changed, 96 insertions(+), 96 deletions(-)
> 
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
> index 82e4e59216..626139dcb3 100644
> --- a/include/hw/arm/allwinner-h3.h
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -61,37 +61,37 @@
>   * @see AwH3State
>   */
>  enum {
> -AW_H3_SRAM_A1,
> -AW_H3_SRAM_A2,
> -AW_H3_SRAM_C,
> -AW_H3_SYSCTRL,
> -AW_H3_MMC0,
> -AW_H3_SID,
> -AW_H3_EHCI0,
> -AW_H3_OHCI0,
> -AW_H3_EHCI1,
> -AW_H3_OHCI1,
> -AW_H3_EHCI2,
> -AW_H3_OHCI2,
> -AW_H3_EHCI3,
> -AW_H3_OHCI3,
> -AW_H3_CCU,
> -AW_H3_PIT,
> -AW_H3_UART0,
> -AW_H3_UART1,
> -AW_H3_UART2,
> -AW_H3_UART3,
> -AW_H3_EMAC,
> -AW_H3_DRAMCOM,
> -AW_H3_DRAMCTL,
> -AW_H3_DRAMPHY,
> -AW_H3_GIC_DIST,
> -AW_H3_GIC_CPU,
> -AW_H3_GIC_HYP,
> -AW_H3_GIC_VCPU,
> -AW_H3_RTC,
> -AW_H3_CPUCFG,
> -AW_H3_SDRAM
> +AW_H3_DEV_SRAM_A1,
> +AW_H3_DEV_SRAM_A2,
> +AW_H3_DEV_SRAM_C,
> +AW_H3_DEV_SYSCTRL,

My 2 cents:
These are not devices, but peripheral blocks or IP cores.
Anyway, short change could be to name them E_AW_H3_xxx,
but I don't understand why these are exposed. This enum
should be locally declared in hw/arm/allwinner-h3.c,
and the SoC might provide a get_sdram_base_address()
method so the machine can access it.

> +AW_H3_DEV_MMC0,
> +AW_H3_DEV_SID,
> +AW_H3_DEV_EHCI0,
> +AW_H3_DEV_OHCI0,
> +AW_H3_DEV_EHCI1,
> +AW_H3_DEV_OHCI1,
> +AW_H3_DEV_EHCI2,
> +AW_H3_DEV_OHCI2,
> +AW_H3_DEV_EHCI3,
> +AW_H3_DEV_OHCI3,
> +AW_H3_DEV_CCU,
> +AW_H3_DEV_PIT,
> +AW_H3_DEV_UART0,
> +AW_H3_DEV_UART1,
> +AW_H3_DEV_UART2,
> +AW_H3_DEV_UART3,
> +AW_H3_DEV_EMAC,
> +AW_H3_DEV_DRAMCOM,
> +AW_H3_DEV_DRAMCTL,
> +AW_H3_DEV_DRAMPHY,
> +AW_H3_DEV_GIC_DIST,
> +AW_H3_DEV_GIC_CPU,
> +AW_H3_DEV_GIC_HYP,
> +AW_H3_DEV_GIC_VCPU,
> +AW_H3_DEV_RTC,
> +AW_H3_DEV_CPUCFG,
> +AW_H3_DEV_SDRAM
>  };
>  
>  /** Total number of CPU cores in the H3 SoC */
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> index ff92ded82c..341abe6718 100644
> --- a/hw/arm/allwinner-h3.c
> +++ b/hw/arm/allwinner-h3.c
> @@ -35,37 +35,37 @@
>  
>  /* Memory map */
>  const hwaddr allwinner_h3_memmap[] = {
> -[AW_H3_SRAM_A1]= 0x,
> -[AW_H3_SRAM_A2]= 0x00044000,
> -[AW_H3_SRAM_C] = 0x0001,
> -[AW_H3_SYSCTRL]= 0x01c0,
> -[AW_H3_MMC0]   = 0x01c0f000,
> -[AW_H3_SID]= 0x01c14000,
> -[AW_H3_EHCI0]  = 0x01c1a000,
> -[AW_H3_OHCI0]  = 0x01c1a400,
> -[AW_H3_EHCI1]  = 0x01c1b000,
> -[AW_H3_OHCI1]  = 0x01c1b400,
> -[AW_H3_EHCI2]  = 0x01c1c000,
> -[AW_H3_OHCI2]  = 0x01c1c400,
> -[AW_H3_EHCI3]  = 0x01c1d000,
> -[AW_H3_OHCI3]  = 0x01c1d400,
> -[AW_H3_CCU]= 0x01c2,
> -[AW_H3_PIT]= 0x01c20c00,
> -[AW_H3_UART0]  = 0x01c28000,
> -[AW_H3_UART1]  = 0x01c28400,
> -[AW_H3_UART2]  = 0x01c28800,
> -[AW_H3_UART3]  = 0x01c28c00,
> -[AW_H3_EMAC]   = 0x01c3,
> -[AW_H3_DRAMCOM]= 0x01c62000,
> -[AW_H3_DRAMCTL]= 0x01c63000,
> -[AW_H3_DRAMPHY]= 0x01c65000,
> -[AW_H3_GIC_DIST]   = 0x01c81000,
> -[AW_H3_GIC_CPU]= 0x01c82000,
> -[AW_H3_GIC_HYP]= 0x01c84000,
> -[AW_H3_GIC_VCPU]   = 0x01c86000,
> -[AW_H3_RTC]= 0x01f0,
> -[AW_H3_CPUCFG] = 0x01f01c00,
> -[AW_H3_SDRAM]  = 0x4000
> +[AW_H3_DEV_SRAM_A1]= 0x,
> +[AW_H3_DEV_SRAM_A2]= 0x00044000,
> +[AW_H3_DEV_SRAM_C] = 0x0001,
> +[AW_H3_DEV_SYSCTRL]= 0x01c0,
> +[AW_H3_DEV_MMC0]   = 0x01c0f000,
> +[AW_H3_DEV_SID]= 0x01c14000,
> +[AW_H3_DEV_EHCI0]  = 0x01c1a000,
> +[AW_H3_DEV_OHCI0]  = 0x01c1a400,
> +[AW_H3_DEV_EHCI1]  = 0x01c1b000,
> +[AW_H3_DEV_OHCI1]  = 0x01c1b400,
> +[AW_H3_DEV_EHCI2]  = 0x01c1c000,
> +[AW_H3_DEV_OHCI2]  = 0x01c1c400,
> +[AW_H3_DEV_EHCI3]  = 0x01c1d000,
> +[AW_H3_DEV_OHCI3]  = 0x01c1d400,
> +[AW_H3_DEV_CCU]= 0x01c2,
> +[AW_H3_DEV_PIT]= 0x01c20c00,
> +[AW_H3_DEV_UART0]  = 0x01c28000,
> +[AW_H3_DEV_UART1]  = 0x01c28400,
> +[AW_H3_DEV_UART2]  = 0x01c28800,
> +[AW_H3_DEV_UART3]  = 

Re: [PATCH 05/41] aspeed_timer: Fix ASPEED_TIMER macro definition

[Philippe Mathieu-Daudé]

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> The macro definition had an extra semicolon.  This was never
> noticed because the macro was only being used where it didn't
> make a difference.
> 
> Signed-off-by: Eduardo Habkost 
> ---
>  include/hw/timer/aspeed_timer.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
> index 948329893c..d7c7d8ad28 100644
> --- a/include/hw/timer/aspeed_timer.h
> +++ b/include/hw/timer/aspeed_timer.h
> @@ -26,7 +26,7 @@
>  #include "hw/misc/aspeed_scu.h"
>  
>  #define ASPEED_TIMER(obj) \
> -OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
> +OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER)
>  #define TYPE_ASPEED_TIMER "aspeed.timer"
>  #define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
>  #define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
> 

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 01/41] pl1110: Rename PL1110 enum

[Philippe Mathieu-Daudé]

On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> The PL1110 enum value name will conflict with the PL1110 type
> cast checker, when we replace the existing macro with an inline
> function.  Rename it to PL1110_STOCK.

typo s/PL1110/PL110/ in subject and description.

> 
> Signed-off-by: Eduardo Habkost 
> ---
>  hw/display/pl110.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/display/pl110.c b/hw/display/pl110.c
> index c2991a28d2..4664fde3f2 100644
> --- a/hw/display/pl110.c
> +++ b/hw/display/pl110.c
> @@ -42,7 +42,7 @@ enum pl110_bppmode
>  /* The Versatile/PB uses a slightly modified PL110 controller.  */
>  enum pl110_version
>  {
> -PL110,
> +PL110_STOCK,
>  PL110_VERSATILE,
>  PL111

For completeness I'd also rename PL111.

What about:

 enum pl110_version
 {
PL110_VERSION,
PL110_VERSATILE_VERSION,
PL111_VERSION
 }

?

>  };
> @@ -372,12 +372,12 @@ static uint64_t pl110_read(void *opaque, hwaddr offset,
>  case 5: /* LCDLPBASE */
>  return s->lpbase;
>  case 6: /* LCDIMSC */
> -if (s->version != PL110) {
> +if (s->version != PL110_STOCK) {
>  return s->cr;
>  }
>  return s->int_mask;
>  case 7: /* LCDControl */
> -if (s->version != PL110) {
> +if (s->version != PL110_STOCK) {
>  return s->int_mask;
>  }
>  return s->cr;
> @@ -437,7 +437,7 @@ static void pl110_write(void *opaque, hwaddr offset,
>  s->lpbase = val;
>  break;
>  case 6: /* LCDIMSC */
> -if (s->version != PL110) {
> +if (s->version != PL110_STOCK) {
>  goto control;
>  }
>  imsc:
> @@ -445,7 +445,7 @@ static void pl110_write(void *opaque, hwaddr offset,
>  pl110_update(s);
>  break;
>  case 7: /* LCDControl */
> -if (s->version != PL110) {
> +if (s->version != PL110_STOCK) {
>  goto imsc;
>  }
>  control:
> @@ -513,7 +513,7 @@ static void pl110_init(Object *obj)
>  {
>  PL110State *s = PL110(obj);
>  
> -s->version = PL110;
> +s->version = PL110_STOCK;
>  }
>  
>  static void pl110_versatile_init(Object *obj)
> 

Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

[Anup Patel]

On Fri, Aug 14, 2020 at 10:12 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This adds support for Microchip PolarFire SoC Icicle Kit board.
> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> E51 plus four U54 cores and many on-chip peripherals and an FPGA.

Nice Work !!! This is very helpful.

>
> For more details about Microchip PolarFire Soc, please see:
> https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
>
> The Icicle Kit board information can be found here:
> https://www.microsemi.com/existing-parts/parts/152514
>
> Unlike SiFive FU540, the RISC-V core resect vector is at 0x2022.
> The RISC-V CPU and HART codes has been updated to set the core's
> reset vector based on a configurable property from machine codes.
>
> The following perepherals are created as an unimplemented device:
>
> - Bus Error Uint 0/1/2/3/4
> - L2 cache controller
> - SYSREG
> - MPUCFG
> - IOSCBCFG
> - GPIO
>
> The following perepherals are emulated:
> - SiFive CLINT
> - SiFive PLIC
> - PolarFire SoC Multi-Mode UART
> - PolarFire SoC DMA
> - Cadence eMMC/SDHCI controller
> - Cadence Gigabit Ethernet MAC
>
> Some bugs in the SD card codes are fixed during the development.
>
> The BIOS image used by this machine is hss.bin, aka Hart Software
> Services, which can be built from:
> https://github.com/polarfire-soc/hart-software-services
>
> To launch this machine:
> $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
> -bios path/to/hss.bin -sd path/to/sdcard.img \
> -nic tap,ifname=tap,script=no,model=cadence_gem \
> -display none -serial stdio \
> -chardev socket,id=serial1,path=serial1.sock,server,wait \
> -serial chardev:serial1

Currently, it is fine to use HSS (with OpenSBI v0.6 as a library) but
this is not aligned with the existing booting flow of many RISC-V
systems.

It will be nice to have standard U-Boot RISC-V boot-flow working
on Microchip PolarFire SoC:
U-Boot SPL (BIOS) => FW_DYNAMIC (Generic) => U-Boot S-mode

The Microchip HSS is quite convoluted. It has:
1. DDR Init
2. Boot device support
3. SBI support using OpenSBI as library
4. Simple TEE support

I think point 1) and 2) above should be part of U-Boot SPL.
The point 3) can be OpenSBI FW_DYNAMIC.

Lastly,for point 4), we are working on a new OpenSBI feature using
which we can run independent Secure OS and Non-Secure OS using
U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip
PolarFire).

Do you have plans for adding U-Boot SPL support for this board ??

Regards,
Anup

>
> The memory is set to 1 GiB by default to match the hardware.
> A sanity check on ram size is performed in the machine init routine
> to prompt user to increase the RAM size to > 1 GiB when less than
> 1 GiB ram is detected.
>
> HSS output is on the first serial port (stdio) and U-Boot/Linux
> outputs on the 2nd serial port. OpenSBI outputs on a random serial
> port due to the lottery mechanism used during the multi-core boot.
>
>
> Bin Meng (18):
>   target/riscv: cpu: Add a new 'resetvec' property
>   hw/riscv: hart: Add a new 'resetvec' property
>   target/riscv: cpu: Set reset vector based on the configured property
> value
>   hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
>   hw/char: Add Microchip PolarFire SoC MMUART emulation
>   hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
>   hw/sd: sd: Fix incorrect populated function switch status data
> structure
>   hw/sd: sd: Correctly set the high capacity bit
>   hw/sd: sdhci: Make sdhci_poweron_reset() internal visible
>   hw/sd: Add Cadence SDHCI emulation
>   hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an
> SD card
>   hw/dma: Add Microchip PolarFire Soc DMA controller emulation
>   hw/riscv: microchip_pfsoc: Connect a DMA controller
>   hw/net: cadence_gem: Add a new 'phy-addr' property
>   hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
>   hw/riscv: microchip_pfsoc: Hook GPIO controllers
>   hw/riscv: clint: Avoid using hard-coded timebase frequency
>   hw/riscv: microchip_pfsoc: Document the software used for testing
>
>  MAINTAINERS |  11 +
>  default-configs/riscv64-softmmu.mak |   1 +
>  hw/char/Kconfig |   3 +
>  hw/char/Makefile.objs   |   1 +
>  hw/char/mchp_pfsoc_mmuart.c |  82 +++
>  hw/dma/Kconfig  |   3 +
>  hw/dma/Makefile.objs|   1 +
>  hw/dma/mchp_pfsoc_dma.c | 322 +
>  hw/net/cadence_gem.c|   7 +-
>  hw/riscv/Kconfig|   9 +
>  hw/riscv/Makefile.objs  |   1 +
>  hw/riscv/microchip_pfsoc.c  | 456 
> 
>  hw/riscv/opentitan.c|   1 +
>  hw/riscv/riscv_hart.c   |   3 +
>  hw/riscv/sifive_clint.c |  25 +-
>  hw/riscv/sifive_e.c |   4 +-
>  hw/riscv/sifive_u.c |   5 +-
>  hw/riscv/spike.c

Re: [PATCH 5/5] hw/char/avr_usart: Trace baudrate changes

[Richard Henderson]

On 8/14/20 9:39 AM, Philippe Mathieu-Daudé wrote:
> +static void avr_usart_update_baudrate(AVRUsartState *s)
> +{
> +unsigned baudrate = (clock_get_hz(s->clkin) / USART_CLOCK_DIVISOR)
> +/ (((s->brrh << 8) | s->brrl) + 1);
> +
> +trace_avr_usart_update_baudrate((s->brrh << 8) | s->brrl, baudrate);

Would you pull that brrh|brrl expression out and give it a name?

I do wonder if one division would be better, e.g.

baudrate = clock_get_hz / (DIVISOR * (regval + 1))


r~

Re: [PATCH 1/1] include/elf.h: Add EM_RX.

[Richard Henderson]

On 8/14/20 6:14 AM, Yoshinori Sato wrote:
> RX's ELF machine not defined elf.h.
> Added it.
> 
> Signed-off-by: Yoshinori Sato 
> ---
>  include/elf.h | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH] hw/arm/musicpal: Use AddressSpace for DMA transfers

[Richard Henderson]

On 8/14/20 5:55 AM, Philippe Mathieu-Daudé wrote:
> Allow the device to execute the DMA transfers in a different
> AddressSpace.
> 
> We keep using the system_memory address space, but via the
> proper dma_memory_access() API.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/arm/musicpal.c | 45 +++--
>  1 file changed, 31 insertions(+), 14 deletions(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH] hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers

[Richard Henderson]

On 8/14/20 5:29 AM, Philippe Mathieu-Daudé wrote:
> Allow the device to execute the DMA transfers in a different
> AddressSpace.
> 
> The H3 SoC keeps using the system_memory address space,
> but via the proper dma_memory_access() API.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
> Tested with:
>   AVOCADO_ALLOW_LARGE_STORAGE=1 avocado run -t machine:orangepi-pc 
> tests/acceptance/
> ---
>  include/hw/net/allwinner-sun8i-emac.h |  6 
>  hw/arm/allwinner-h3.c |  2 ++
>  hw/net/allwinner-sun8i-emac.c | 46 +--
>  3 files changed, 38 insertions(+), 16 deletions(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 0/7] hw/sd: Use sdbus_read_data/sdbus_write_data for multiple bytes access

[Richard Henderson]

On 8/14/20 2:23 AM, Philippe Mathieu-Daudé wrote:
> Introduce sdbus_read_data() and sdbus_write_data() methods to
> access multiple bytes on the data line of a SD bus.
> 
> I haven't named then sdbus_access_block() because I expect a
> block to be a power of 2, while there is no such restriction
> on the SD bus (think of SPI).
> 
> We can also simplify the bcm2835_sdhost and pl181 models, but
> it is simpler to first let them use the Fifo32 API.
> 
> Based-on: <20200705204630.4133-1-f4...@amsat.org>
> "hw/sd: convert legacy SDHCI devices to the SDBus API"
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg720136.html
> 
> Philippe Mathieu-Daudé (7):
>   hw/sd: Rename read/write_data() as read/write_byte()
>   hw/sd: Rename sdbus_write_data() as sdbus_write_byte()
>   hw/sd: Rename sdbus_read_data() as sdbus_read_byte()
>   hw/sd: Add sdbus_write_data() to write multiples bytes on the data
> line
>   hw/sd: Use sdbus_write_data() instead of sdbus_write_byte when
> possible
>   hw/sd: Add sdbus_read_data() to read multiples bytes on the data line
>   hw/sd: Use sdbus_read_data() instead of sdbus_read_byte() when
> possible

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 7/7] hw/scsi/scsi-disk: Replace magic '512' value by BDRV_SECTOR_SIZE

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/scsi/scsi-disk.c | 44 +++-
>  1 file changed, 23 insertions(+), 21 deletions(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH] spapr/xive: Use xive_source_esb_len()

[Cédric Le Goater]

> I found out recently that XIVE support was
> merged into FreeBSD and with that it also came some good comments
> about xive...

cool ! Does it run in a QEMU PowerNV machine ? 

C.

Re: [PATCH 6/7] hw/ide/pci: Replace magic '512' value by BDRV_SECTOR_SIZE

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/ide/pci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 4/7] hw/ide/ahci: Replace magic '512' value by BDRV_SECTOR_SIZE

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/ide/ahci.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 5/7] hw/ide/atapi: Replace magic '512' value by BDRV_SECTOR_SIZE

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/ide/atapi.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)


Reviewed-by: Richard Henderson 


> diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
> index 17a9d635d8..14a2b0bb2f 100644
> --- a/hw/ide/atapi.c
> +++ b/hw/ide/atapi.c
> @@ -824,9 +824,9 @@ static void cmd_get_configuration(IDEState *s, uint8_t 
> *buf)
>   *
>   *  Only a problem if the feature/profiles grow.
>   */
> -if (max_len > 512) {
> +if (max_len > BDRV_SECTOR_SIZE) {
>  /* XXX: assume 1 sector */
> -max_len = 512;
> +max_len = BDRV_SECTOR_SIZE;
>  }
>  
>  memset(buf, 0, max_len);
> @@ -1186,8 +1186,8 @@ static void cmd_read_dvd_structure(IDEState *s, 
> uint8_t* buf)
>  }
>  }
>  
> -memset(buf, 0, max_len > IDE_DMA_BUF_SECTORS * 512 + 4 ?
> -   IDE_DMA_BUF_SECTORS * 512 + 4 : max_len);
> +memset(buf, 0, max_len > IDE_DMA_BUF_SECTORS * BDRV_SECTOR_SIZE + 4 ?
> +   IDE_DMA_BUF_SECTORS * BDRV_SECTOR_SIZE + 4 : max_len);

If you're queuing other cleanups, both of these places could usefully use MIN().


r~

Re: [PATCH 3/7] hw/ide/core: Replace magic '512' value by BDRV_SECTOR_SIZE

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/ide/core.c | 23 ---
>  1 file changed, 12 insertions(+), 11 deletions(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 2/7] hw/ide/core: Trivial typo fix

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/ide/core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 1/7] block/null: Make more explicit the driver default size is 1GiB

[Richard Henderson]

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> As it is not obvious the default size for the null block driver
> is 1 GiB, replace the obfuscated '1 << 30' magic value by a
> definition using IEC binary prefixes.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  block/null.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson 

r~

[PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency

[Bin Meng]

From: Bin Meng 

At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.

Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.

Signed-off-by: Bin Meng 
---

 hw/riscv/microchip_pfsoc.c  |  6 +-
 hw/riscv/sifive_clint.c | 25 ++---
 hw/riscv/sifive_e.c |  3 ++-
 hw/riscv/sifive_u.c |  3 ++-
 hw/riscv/spike.c|  2 +-
 hw/riscv/virt.c |  3 ++-
 include/hw/riscv/sifive_clint.h |  3 ++-
 target/riscv/cpu.h  |  6 --
 target/riscv/cpu_helper.c   |  4 +++-
 target/riscv/csr.c  |  4 ++--
 10 files changed, 37 insertions(+), 22 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 139284a..e8b7f86 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -60,6 +60,9 @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR0x2022
 
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 100
+
 /* GEM version */
 #define GEM_REVISION0x0107010c
 
@@ -189,7 +192,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 /* CLINT */
 sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
 memmap[MICROCHIP_PFSOC_CLINT].size, ms->smp.cpus,
-SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+CLINT_TIMEBASE_FREQ, false);
 
 /* L2 cache controller */
 create_unimplemented_device("microchip.pfsoc.l2cc",
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index 669c21a..a568568 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -29,22 +29,23 @@
 #include "hw/riscv/sifive_clint.h"
 #include "qemu/timer.h"
 
-static uint64_t cpu_riscv_read_rtc(void)
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
 {
 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
-SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
+timebase_freq, NANOSECONDS_PER_SECOND);
 }
 
 /*
  * Called when timecmp is written to update the QEMU timer or immediately
  * trigger timer interrupt if mtimecmp <= current timer value.
  */
-static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
+   uint32_t timebase_freq)
 {
 uint64_t next;
 uint64_t diff;
 
-uint64_t rtc_r = cpu_riscv_read_rtc();
+uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
 
 cpu->env.timecmp = value;
 if (cpu->env.timecmp <= rtc_r) {
@@ -59,7 +60,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, 
uint64_t value)
 diff = cpu->env.timecmp - rtc_r;
 /* back to ns (note args switched in muldiv64) */
 next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
-muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
+muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
 timer_mod(cpu->env.timer, next);
 }
 
@@ -111,10 +112,10 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr 
addr, unsigned size)
 }
 } else if (addr == clint->time_base) {
 /* time_lo */
-return cpu_riscv_read_rtc() & 0x;
+return cpu_riscv_read_rtc(clint->timebase_freq) & 0x;
 } else if (addr == clint->time_base + 4) {
 /* time_hi */
-return (cpu_riscv_read_rtc() >> 32) & 0x;
+return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0x;
 }
 
 error_report("clint: invalid read: %08x", (uint32_t)addr);
@@ -151,13 +152,13 @@ static void sifive_clint_write(void *opaque, hwaddr addr, 
uint64_t value,
 /* timecmp_lo */
 uint64_t timecmp_hi = env->timecmp >> 32;
 sifive_clint_write_timecmp(RISCV_CPU(cpu),
-timecmp_hi << 32 | (value & 0x));
+timecmp_hi << 32 | (value & 0x), clint->timebase_freq);
 return;
 } else if ((addr & 0x7) == 4) {
 /* timecmp_hi */
 uint64_t timecmp_lo = env->timecmp;
 sifive_clint_write_timecmp(RISCV_CPU(cpu),
-value << 32 | (timecmp_lo & 0x));
+value << 32 | (timecmp_lo & 0x), clint->timebase_freq);
 } else {
 error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
 }
@@ -191,6 +192,7 @@ static Property sifive_clint_properties[] = {
 DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
 DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
 DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
+DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
 

[PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers

[Bin Meng]

From: Bin Meng 

Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.

With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(1st stage bootloader).

Signed-off-by: Bin Meng 
---

 hw/riscv/microchip_pfsoc.c | 14 ++
 include/hw/riscv/microchip_pfsoc.h |  3 +++
 2 files changed, 17 insertions(+)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 625b511..139284a 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -89,6 +89,9 @@ static const struct MemmapEntry {
 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
 [MICROCHIP_PFSOC_GEM0] ={ 0x2011, 0x2000 },
 [MICROCHIP_PFSOC_GEM1] ={ 0x20112000, 0x2000 },
+[MICROCHIP_PFSOC_GPIO0] =   { 0x2012, 0x1000 },
+[MICROCHIP_PFSOC_GPIO1] =   { 0x20121000, 0x1000 },
+[MICROCHIP_PFSOC_GPIO2] =   { 0x20122000, 0x1000 },
 [MICROCHIP_PFSOC_ENVM_CFG] ={ 0x2020, 0x1000 },
 [MICROCHIP_PFSOC_ENVM_DATA] =   { 0x2022,0x2 },
 [MICROCHIP_PFSOC_IOSCB_CFG] =   { 0x3708, 0x1000 },
@@ -308,6 +311,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 sysbus_connect_irq(SYS_BUS_DEVICE(>gem1), 0,
 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
 
+/* GPIOs */
+create_unimplemented_device("microchip.pfsoc.gpio0",
+memmap[MICROCHIP_PFSOC_GPIO0].base,
+memmap[MICROCHIP_PFSOC_GPIO0].size);
+create_unimplemented_device("microchip.pfsoc.gpio1",
+memmap[MICROCHIP_PFSOC_GPIO1].base,
+memmap[MICROCHIP_PFSOC_GPIO1].size);
+create_unimplemented_device("microchip.pfsoc.gpio2",
+memmap[MICROCHIP_PFSOC_GPIO2].base,
+memmap[MICROCHIP_PFSOC_GPIO2].size);
+
 /* eNVM */
 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/include/hw/riscv/microchip_pfsoc.h 
b/include/hw/riscv/microchip_pfsoc.h
index 60f994c..993b17c 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -89,6 +89,9 @@ enum {
 MICROCHIP_PFSOC_MMUART4,
 MICROCHIP_PFSOC_GEM0,
 MICROCHIP_PFSOC_GEM1,
+MICROCHIP_PFSOC_GPIO0,
+MICROCHIP_PFSOC_GPIO1,
+MICROCHIP_PFSOC_GPIO2,
 MICROCHIP_PFSOC_ENVM_CFG,
 MICROCHIP_PFSOC_ENVM_DATA,
 MICROCHIP_PFSOC_IOSCB_CFG,
-- 
2.7.4

[PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation

[Bin Meng]

From: Bin Meng 

Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution

This creates a simple model to support polling mode which is
enough for firmware usage. While there are codes for interrupts
handling, please note the interrupt path has not been validated
due to missing kernel driver for testing as of now.

Signed-off-by: Bin Meng 
---

 MAINTAINERS |   2 +
 hw/dma/Kconfig  |   3 +
 hw/dma/Makefile.objs|   1 +
 hw/dma/mchp_pfsoc_dma.c | 322 
 include/hw/dma/mchp_pfsoc_dma.h |  57 +++
 5 files changed, 385 insertions(+)
 create mode 100644 hw/dma/mchp_pfsoc_dma.c
 create mode 100644 include/hw/dma/mchp_pfsoc_dma.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e51edac..0aacc90 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1320,8 +1320,10 @@ L: qemu-ri...@nongnu.org
 S: Supported
 F: hw/riscv/microchip_pfsoc.c
 F: hw/char/mchp_pfsoc_mmuart.c
+F: hw/dma/mchp_pfsoc_dma.c
 F: include/hw/riscv/microchip_pfsoc.h
 F: include/hw/char/mchp_pfsoc_mmuart.h
+F: include/hw/dma/mchp_pfsoc_dma.h
 
 RX Machines
 ---
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
index 5c61b67..778e20b 100644
--- a/hw/dma/Kconfig
+++ b/hw/dma/Kconfig
@@ -20,3 +20,6 @@ config ZYNQ_DEVCFG
 
 config STP2000
 bool
+
+config MCHP_PFSOC_DMA
+bool
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index f4b1cfe..fd7e836 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -14,3 +14,4 @@ common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zdma.o
 common-obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
 common-obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
 common-obj-$(CONFIG_RASPI) += bcm2835_dma.o
+common-obj-$(CONFIG_MCHP_PFSOC_DMA) += mchp_pfsoc_dma.o
diff --git a/hw/dma/mchp_pfsoc_dma.c b/hw/dma/mchp_pfsoc_dma.c
new file mode 100644
index 000..8531a6f
--- /dev/null
+++ b/hw/dma/mchp_pfsoc_dma.c
@@ -0,0 +1,322 @@
+/*
+ * Microchip PolarFire SoC DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "sysemu/dma.h"
+#include "hw/dma/mchp_pfsoc_dma.h"
+
+#define DMA_CONTROL 0x000
+#define   CONTROL_CLAIM BIT(0)
+#define   CONTROL_RUN   BIT(1)
+#define   CONTROL_DONE_IE   BIT(14)
+#define   CONTROL_ERR_IEBIT(15)
+#define   CONTROL_DONE  BIT(30)
+#define   CONTROL_ERR   BIT(31)
+
+#define DMA_NEXT_CONFIG 0x004
+#define   CONFIG_REPEAT BIT(2)
+#define   CONFIG_ORDER  BIT(3)
+#define   CONFIG_WRSZ_SHIFT 24
+#define   CONFIG_RDSZ_SHIFT 28
+#define   CONFIG_SZ_MASK0xf
+
+#define DMA_NEXT_BYTES  0x008
+#define DMA_NEXT_DST0x010
+#define DMA_NEXT_SRC0x018
+#define DMA_EXEC_CONFIG 0x104
+#define DMA_EXEC_BYTES  0x108
+#define DMA_EXEC_DST0x110
+#define DMA_EXEC_SRC0x118
+
+enum dma_chan_state {
+DMA_CHAN_STATE_IDLE,
+DMA_CHAN_STATE_STARTED,
+DMA_CHAN_STATE_ERROR,
+DMA_CHAN_STATE_DONE
+};
+
+static void mchp_pfsoc_dma_run(MchpPfSoCDMAState *s, int ch)
+{
+uint64_t bytes = s->chan[ch].next_bytes;
+uint64_t dst = s->chan[ch].next_dst;
+uint64_t src = s->chan[ch].next_src;
+uint32_t config = s->chan[ch].next_config;
+int wsize, rsize, size;
+uint8_t buf[64];
+int n;
+
+/* do nothing if bytes to transfer is zero */
+if (!bytes) {
+goto error;
+}
+
+/*
+ * The manual does not describe how the hardware behaviors when
+ * config.wsize and config.rsize are given different values.
+ * A common case is memory to memory DMA, and in this case they
+ * are normally the same. Abort if this expectation fails.
+ */
+wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
+rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
+if (wsize != rsize) {
+goto error;
+}
+
+/*
+ * Calculate the transaction size
+ *
+ * size field is base 2 logarithm of DMA transaction size,
+ * but there is 

[PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs

[Bin Meng]

From: Bin Meng 

Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.

On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.

The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
must specify 2 '-nic' options from the command line in order to get
a working ethernet.

Signed-off-by: Bin Meng 
---

 hw/riscv/microchip_pfsoc.c | 39 ++
 include/hw/riscv/microchip_pfsoc.h |  7 +++
 2 files changed, 46 insertions(+)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 1c67cbc..625b511 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -14,6 +14,7 @@
  * 3) MMUARTs (Multi-Mode UART)
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  * 5) DMA (Direct Memory Access Controller)
+ * 6) GEM (Gigabit Ethernet MAC Controller)
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -59,6 +60,9 @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR0x2022
 
+/* GEM version */
+#define GEM_REVISION0x0107010c
+
 static const struct MemmapEntry {
 hwaddr base;
 hwaddr size;
@@ -83,6 +87,8 @@ static const struct MemmapEntry {
 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
+[MICROCHIP_PFSOC_GEM0] ={ 0x2011, 0x2000 },
+[MICROCHIP_PFSOC_GEM1] ={ 0x20112000, 0x2000 },
 [MICROCHIP_PFSOC_ENVM_CFG] ={ 0x2020, 0x1000 },
 [MICROCHIP_PFSOC_ENVM_DATA] =   { 0x2022,0x2 },
 [MICROCHIP_PFSOC_IOSCB_CFG] =   { 0x3708, 0x1000 },
@@ -119,6 +125,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
 object_initialize_child(obj, "dma-controller", >dma,
 TYPE_MCHP_PFSOC_DMA);
 
+object_initialize_child(obj, "gem0", >gem0, TYPE_CADENCE_GEM);
+object_initialize_child(obj, "gem1", >gem1, TYPE_CADENCE_GEM);
+
 object_initialize_child(obj, "sd-controller", >sdhci,
 TYPE_CADENCE_SDHCI);
 object_initialize_child(OBJECT(>sdhci), "sd-controller.sdhci",
@@ -136,6 +145,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 MemoryRegion *envm_data = g_new(MemoryRegion, 1);
 char *plic_hart_config;
 size_t plic_hart_config_len;
+NICInfo *nd;
 int i;
 
 sysbus_realize(SYS_BUS_DEVICE(>e_cpus), _abort);
@@ -269,6 +279,35 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
 serial_hd(4));
 
+/* GEMs */
+
+nd = _table[0];
+if (nd->used) {
+qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+qdev_set_nic_properties(DEVICE(>gem0), nd);
+}
+nd = _table[1];
+if (nd->used) {
+qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+qdev_set_nic_properties(DEVICE(>gem1), nd);
+}
+
+object_property_set_int(OBJECT(>gem0), "revision", GEM_REVISION, errp);
+object_property_set_int(OBJECT(>gem0), "phy-addr", 8, errp);
+sysbus_realize(SYS_BUS_DEVICE(>gem0), errp);
+sysbus_mmio_map(SYS_BUS_DEVICE(>gem0), 0,
+memmap[MICROCHIP_PFSOC_GEM0].base);
+sysbus_connect_irq(SYS_BUS_DEVICE(>gem0), 0,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
+
+object_property_set_int(OBJECT(>gem1), "revision", GEM_REVISION, errp);
+object_property_set_int(OBJECT(>gem1), "phy-addr", 9, errp);
+sysbus_realize(SYS_BUS_DEVICE(>gem1), errp);
+sysbus_mmio_map(SYS_BUS_DEVICE(>gem1), 0,
+memmap[MICROCHIP_PFSOC_GEM1].base);
+sysbus_connect_irq(SYS_BUS_DEVICE(>gem1), 0,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
+
 /* eNVM */
 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/include/hw/riscv/microchip_pfsoc.h 
b/include/hw/riscv/microchip_pfsoc.h
index 7825935..60f994c 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -24,6 +24,7 @@
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
 #include "hw/dma/mchp_pfsoc_dma.h"
+#include "hw/net/cadence_gem.h"
 #include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
@@ -42,6 +43,8 @@ typedef struct MicrochipPFSoCState {
 MchpPfSoCMMUartState *serial3;
 MchpPfSoCMMUartState *serial4;
 MchpPfSoCDMAState dma;
+CadenceGEMState gem0;
+CadenceGEMState gem1;
 CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
@@ -84,6 +87,8 @@ enum {
 MICROCHIP_PFSOC_MMUART2,
 

[PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure

[Bin Meng]

From: Bin Meng 

At present the function switch status data structure bit [399:376]
are wrongly pupulated. These 3 bytes encode function switch status
for the 6 function groups, with 4 bits per group, starting from
function group 6 at bit 399, then followed by function group 5 at
bit 395, and so on.

However the codes mistakenly fills in the function group 1 status
at bit 399. This fixes the code logic.

Signed-off-by: Bin Meng 
---

 hw/sd/sd.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index fad9cf1..51f5900 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -806,11 +806,15 @@ static void sd_function_switch(SDState *sd, uint32_t arg)
 sd->data[11] = 0x43;
 sd->data[12] = 0x80;   /* Supported group 1 functions */
 sd->data[13] = 0x03;
+
+sd->data[14] = 0;
+sd->data[15] = 0;
+sd->data[16] = 0;
 for (i = 0; i < 6; i ++) {
 new_func = (arg >> (i * 4)) & 0x0f;
 if (mode && new_func != 0x0f)
 sd->function_group[i] = new_func;
-sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
+sd->data[16 - (i >> 1)] |= new_func << ((i % 2) * 4);
 }
 memset(>data[17], 0, 47);
 stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
-- 
2.7.4

[PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property

[Bin Meng]

From: Bin Meng 

At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.

Signed-off-by: Bin Meng 
---

 hw/net/cadence_gem.c | 7 +--
 include/hw/net/cadence_gem.h | 2 ++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index a93b5c0..9fa03de 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1446,7 +1446,8 @@ static uint64_t gem_read(void *opaque, hwaddr offset, 
unsigned size)
 uint32_t phy_addr, reg_num;
 
 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0 ||
+phy_addr == s->phy_addr) {
 reg_num = (retval & GEM_PHYMNTNC_REG) >> 
GEM_PHYMNTNC_REG_SHIFT;
 retval &= 0x;
 retval |= gem_phy_read(s, reg_num);
@@ -1569,7 +1570,8 @@ static void gem_write(void *opaque, hwaddr offset, 
uint64_t val,
 uint32_t phy_addr, reg_num;
 
 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0 ||
+phy_addr == s->phy_addr) {
 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
 gem_phy_write(s, reg_num, val);
 }
@@ -1682,6 +1684,7 @@ static Property gem_properties[] = {
 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
GEM_MODID_VALUE),
+DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, 0),
 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
   num_priority_queues, 1),
 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 54e646f..01c6189 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
 /* Mask of register bits which are write 1 to clear */
 uint32_t regs_w1c[CADENCE_GEM_MAXREG];
 
+/* PHY address */
+uint8_t phy_addr;
 /* PHY registers backing store */
 uint16_t phy_regs[32];
 
-- 
2.7.4

[PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing

[Bin Meng]

From: Bin Meng 

Add some useful comments to document the software used for testing.
including how to patch HSS to bypass the DDR memory initialization,
HSS and Yocto BSP build instructions, etc.

To launch this machine for testing:
$ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
-bios path/to/hss.bin -sd path/to/sdcard.img \
-nic user,model=cadence_gem \
-nic tap,ifname=tap,model=cadence_gem \
-display none -serial stdio \
-chardev socket,id=serial1,path=serial1.sock,server,wait \
-serial chardev:serial1

Signed-off-by: Bin Meng 

---

 hw/riscv/microchip_pfsoc.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e8b7f86..1575fef 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -56,6 +56,27 @@
 /*
  * The BIOS image used by this machine is called Hart Software Services (HSS).
  * See https://github.com/polarfire-soc/hart-software-services
+ *
+ * As of now the DDR memory controller in the Microchip PolarFire SoC has not
+ * been modeled. Simply creating unimplemented devices does not make HSS happy.
+ * Emulating the DDR memory controller is tedious, so a patched HSS should be
+ * used as the BIOS for this machine.
+ *
+ * To patch HSS, open boards/icicle-kit-es/hss_board_init.c in the HSS source
+ * tree, find the boardInitFunctions[] array that contains the initialization
+ * routines for this board, and remove the line that contains 'HSS_DDRInit'.
+ *
+ * QEMU does not support eMMC hence the SD configuration shall be used in the
+ * HSS and Yocto BSP build. The eMMC configuration is not supported.
+ *
+ * Instructions to build HSS:
+ *   $ cp boards/icicle-kit-es/def_config.sdcard .config
+ *   $ make BOARD=icicle-kit-es
+ *
+ * For Yocto build, "MACHINE=icicle-kit-es-sd" should be specified, otherwise
+ * when booting Linux kernel the rootfs cannot be mounted. The generated image
+ * is something like: mpfs-dev-cli-icicle-kit-es-sd.rootfs.wic. Resize the file
+ * with 'qemu-image' to a power of 2 before passing to QEMU '-sd' command line.
  */
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR0x2022
-- 
2.7.4

[PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs

[Bin Meng]

From: Bin Meng 

Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.

Signed-off-by: Bin Meng 
---

 hw/riscv/Kconfig   |  1 +
 hw/riscv/microchip_pfsoc.c | 30 ++
 include/hw/riscv/microchip_pfsoc.h | 20 
 3 files changed, 51 insertions(+)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 3292fae..ceb7c16 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -54,3 +54,4 @@ config MICROCHIP_PFSOC
 select HART
 select SIFIVE
 select UNIMP
+select MCHP_PFSOC_MMUART
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 20a642c..f6b375c 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -11,6 +11,7 @@
  * 0) CLINT (Core Level Interruptor)
  * 1) PLIC (Platform Level Interrupt Controller)
  * 2) eNVM (Embedded Non-Volatile Memory)
+ * 3) MMUARTs (Multi-Mode UART)
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -38,6 +39,7 @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "hw/sysbus.h"
+#include "chardev/char.h"
 #include "hw/cpu/cluster.h"
 #include "target/riscv/cpu.h"
 #include "hw/misc/unimp.h"
@@ -46,6 +48,7 @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
+#include "sysemu/sysemu.h"
 
 /*
  * The BIOS image used by this machine is called Hart Software Services (HSS).
@@ -69,8 +72,13 @@ static const struct MemmapEntry {
 [MICROCHIP_PFSOC_L2CC] ={  0x201, 0x1000 },
 [MICROCHIP_PFSOC_L2LIM] =   {  0x800,  0x200 },
 [MICROCHIP_PFSOC_PLIC] ={  0xc00,  0x400 },
+[MICROCHIP_PFSOC_MMUART0] = { 0x2000, 0x1000 },
 [MICROCHIP_PFSOC_SYSREG] =  { 0x20002000, 0x2000 },
 [MICROCHIP_PFSOC_MPUCFG] =  { 0x20005000, 0x1000 },
+[MICROCHIP_PFSOC_MMUART1] = { 0x2010, 0x1000 },
+[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
+[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
+[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
 [MICROCHIP_PFSOC_ENVM_CFG] ={ 0x2020, 0x1000 },
 [MICROCHIP_PFSOC_ENVM_DATA] =   { 0x2022,0x2 },
 [MICROCHIP_PFSOC_IOSCB_CFG] =   { 0x3708, 0x1000 },
@@ -215,6 +223,28 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 memmap[MICROCHIP_PFSOC_MPUCFG].base,
 memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+/* MMUARTs */
+s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
+memmap[MICROCHIP_PFSOC_MMUART0].base,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
+serial_hd(0));
+s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
+memmap[MICROCHIP_PFSOC_MMUART1].base,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
+serial_hd(1));
+s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
+memmap[MICROCHIP_PFSOC_MMUART2].base,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
+serial_hd(2));
+s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
+memmap[MICROCHIP_PFSOC_MMUART3].base,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
+serial_hd(3));
+s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
+memmap[MICROCHIP_PFSOC_MMUART4].base,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
+serial_hd(4));
+
 /* eNVM */
 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/include/hw/riscv/microchip_pfsoc.h 
b/include/hw/riscv/microchip_pfsoc.h
index 1953ef1..a5efa1d 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -22,6 +22,8 @@
 #ifndef HW_MICROCHIP_PFSOC_H
 #define HW_MICROCHIP_PFSOC_H
 
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
 typedef struct MicrochipPFSoCState {
 /*< private >*/
 DeviceState parent_obj;
@@ -32,6 +34,11 @@ typedef struct MicrochipPFSoCState {
 RISCVHartArrayState e_cpus;
 RISCVHartArrayState u_cpus;
 DeviceState *plic;
+MchpPfSoCMMUartState *serial0;
+MchpPfSoCMMUartState *serial1;
+MchpPfSoCMMUartState *serial2;
+MchpPfSoCMMUartState *serial3;
+MchpPfSoCMMUartState *serial4;
 } MicrochipPFSoCState;
 
 #define TYPE_MICROCHIP_PFSOC"microchip.pfsoc"
@@ -64,14 +71,27 @@ enum {
 MICROCHIP_PFSOC_L2CC,
 MICROCHIP_PFSOC_L2LIM,
 MICROCHIP_PFSOC_PLIC,
+MICROCHIP_PFSOC_MMUART0,
 MICROCHIP_PFSOC_SYSREG,
 MICROCHIP_PFSOC_MPUCFG,
+MICROCHIP_PFSOC_MMUART1,
+MICROCHIP_PFSOC_MMUART2,
+MICROCHIP_PFSOC_MMUART3,
+

[PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller

[Bin Meng]

From: Bin Meng 

Connect a DMA controller to Microchip PolarFire SoC. Note interrupt
has not been connected due to missing information in the manual how
interrupts are routed to PLIC.

On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.

Signed-off-by: Bin Meng 
---

 hw/riscv/Kconfig   |  1 +
 hw/riscv/microchip_pfsoc.c | 10 ++
 include/hw/riscv/microchip_pfsoc.h |  3 +++
 3 files changed, 14 insertions(+)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 7412db9..9323701 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -55,4 +55,5 @@ config MICROCHIP_PFSOC
 select SIFIVE
 select UNIMP
 select MCHP_PFSOC_MMUART
+select MCHP_PFSOC_DMA
 select CADENCE_SDHCI
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 7c09078..1c67cbc 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -13,6 +13,7 @@
  * 2) eNVM (Embedded Non-Volatile Memory)
  * 3) MMUARTs (Multi-Mode UART)
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
+ * 5) DMA (Direct Memory Access Controller)
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -71,6 +72,7 @@ static const struct MemmapEntry {
 [MICROCHIP_PFSOC_BUSERR_UNIT4] ={  0x1704000, 0x1000 },
 [MICROCHIP_PFSOC_CLINT] =   {  0x200,0x1 },
 [MICROCHIP_PFSOC_L2CC] ={  0x201, 0x1000 },
+[MICROCHIP_PFSOC_DMA] = {  0x300,   0x10 },
 [MICROCHIP_PFSOC_L2LIM] =   {  0x800,  0x200 },
 [MICROCHIP_PFSOC_PLIC] ={  0xc00,  0x400 },
 [MICROCHIP_PFSOC_MMUART0] = { 0x2000, 0x1000 },
@@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
  TYPE_RISCV_CPU_SIFIVE_U54);
 qdev_prop_set_uint64(DEVICE(>u_cpus), "resetvec", RESET_VECTOR);
 
+object_initialize_child(obj, "dma-controller", >dma,
+TYPE_MCHP_PFSOC_DMA);
+
 object_initialize_child(obj, "sd-controller", >sdhci,
 TYPE_CADENCE_SDHCI);
 object_initialize_child(OBJECT(>sdhci), "sd-controller.sdhci",
@@ -220,6 +225,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 memmap[MICROCHIP_PFSOC_PLIC].size);
 g_free(plic_hart_config);
 
+/* DMA */
+sysbus_realize(SYS_BUS_DEVICE(>dma), errp);
+sysbus_mmio_map(SYS_BUS_DEVICE(>dma), 0,
+memmap[MICROCHIP_PFSOC_DMA].base);
+
 /* SYSREG */
 create_unimplemented_device("microchip.pfsoc.sysreg",
 memmap[MICROCHIP_PFSOC_SYSREG].base,
diff --git a/include/hw/riscv/microchip_pfsoc.h 
b/include/hw/riscv/microchip_pfsoc.h
index d810ee8..7825935 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -23,6 +23,7 @@
 #define HW_MICROCHIP_PFSOC_H
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/dma/mchp_pfsoc_dma.h"
 #include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
@@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
 MchpPfSoCMMUartState *serial2;
 MchpPfSoCMMUartState *serial3;
 MchpPfSoCMMUartState *serial4;
+MchpPfSoCDMAState dma;
 CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
@@ -71,6 +73,7 @@ enum {
 MICROCHIP_PFSOC_BUSERR_UNIT4,
 MICROCHIP_PFSOC_CLINT,
 MICROCHIP_PFSOC_L2CC,
+MICROCHIP_PFSOC_DMA,
 MICROCHIP_PFSOC_L2LIM,
 MICROCHIP_PFSOC_PLIC,
 MICROCHIP_PFSOC_MMUART0,
-- 
2.7.4

[PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible

[Bin Meng]

From: Bin Meng 

sdhci_poweron_reset() might be needed for any SDHCI compatible
device that is built on top of the generic SDHCI device.

Signed-off-by: Bin Meng 
---

 hw/sd/sdhci-internal.h | 1 +
 hw/sd/sdhci.c  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e8c753d..b587e8e 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -342,5 +342,6 @@ void sdhci_uninitfn(SDHCIState *s);
 void sdhci_common_realize(SDHCIState *s, Error **errp);
 void sdhci_common_unrealize(SDHCIState *s);
 void sdhci_common_class_init(ObjectClass *klass, void *data);
+void sdhci_poweron_reset(DeviceState *dev);
 
 #endif
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index deac181..20f2fe0 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -294,7 +294,7 @@ static void sdhci_reset(SDHCIState *s)
 s->pending_insert_state = false;
 }
 
-static void sdhci_poweron_reset(DeviceState *dev)
+void sdhci_poweron_reset(DeviceState *dev)
 {
 /* QOM (ie power-on) reset. This is identical to reset
  * commanded via device register apart from handling of the
-- 
2.7.4

Re: [PATCH] hw/block/nand: Decommission the NAND museum

[Philippe Mathieu-Daudé]

On 8/14/20 4:22 PM, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20200814132118.12450-1-f4...@amsat.org/
> Hi,
> 
> This series failed the docker-quick@centos7 build test. Please find the 
> testing commands and
> their output below. If you have Docker installed, you can probably reproduce 
> it
> locally.
> 
> === TEST SCRIPT BEGIN ===
> #!/bin/bash
> make docker-image-centos7 V=1 NETWORK=1
> time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
> === TEST SCRIPT END ===
> 
>   TESTcheck-unit: tests/test-char
> Unexpected error in object_property_try_add() at 
> /tmp/qemu-test/src/qom/object.c:1181:
> attempt to add duplicate property 'serial-id' to object (type 'container')

Unrelated, this is a bug Marc-André is tracking.

> ERROR test-char - too few tests run (expected 38, got 9)
> make: *** [check-unit] Error 1
> make: *** Waiting for unfinished jobs
>   TESTiotest-qcow2: 024
>   TESTiotest-qcow2: 025

[PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card

[Bin Meng]

From: Bin Meng 

Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.

As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:

$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es

The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp

Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G

Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img

Signed-off-by: Bin Meng 
---

 hw/riscv/Kconfig   |  1 +
 hw/riscv/microchip_pfsoc.c | 26 ++
 include/hw/riscv/microchip_pfsoc.h |  4 
 3 files changed, 31 insertions(+)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index ceb7c16..7412db9 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -55,3 +55,4 @@ config MICROCHIP_PFSOC
 select SIFIVE
 select UNIMP
 select MCHP_PFSOC_MMUART
+select CADENCE_SDHCI
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index f6b375c..7c09078 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -12,6 +12,7 @@
  * 1) PLIC (Platform Level Interrupt Controller)
  * 2) eNVM (Embedded Non-Volatile Memory)
  * 3) MMUARTs (Multi-Mode UART)
+ * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -75,6 +76,7 @@ static const struct MemmapEntry {
 [MICROCHIP_PFSOC_MMUART0] = { 0x2000, 0x1000 },
 [MICROCHIP_PFSOC_SYSREG] =  { 0x20002000, 0x2000 },
 [MICROCHIP_PFSOC_MPUCFG] =  { 0x20005000, 0x1000 },
+[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
 [MICROCHIP_PFSOC_MMUART1] = { 0x2010, 0x1000 },
 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
@@ -111,6 +113,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
 qdev_prop_set_string(DEVICE(>u_cpus), "cpu-type",
  TYPE_RISCV_CPU_SIFIVE_U54);
 qdev_prop_set_uint64(DEVICE(>u_cpus), "resetvec", RESET_VECTOR);
+
+object_initialize_child(obj, "sd-controller", >sdhci,
+TYPE_CADENCE_SDHCI);
+object_initialize_child(OBJECT(>sdhci), "sd-controller.sdhci",
+>sdhci.slot, TYPE_SYSBUS_SDHCI);
 }
 
 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -223,6 +230,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, 
Error **errp)
 memmap[MICROCHIP_PFSOC_MPUCFG].base,
 memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+/* SDHCI */
+sysbus_realize(SYS_BUS_DEVICE(>sdhci), errp);
+sysbus_mmio_map(SYS_BUS_DEVICE(>sdhci), 0,
+memmap[MICROCHIP_PFSOC_EMMC_SD].base);
+sysbus_connect_irq(SYS_BUS_DEVICE(>sdhci.slot), 0,
+qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
+
 /* MMUARTs */
 s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
 memmap[MICROCHIP_PFSOC_MMUART0].base,
@@ -290,6 +304,7 @@ static void microchip_icicle_kit_machine_init(MachineState 
*machine)
 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
 MemoryRegion *system_memory = get_system_memory();
 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+DriveInfo *dinfo = drive_get_next(IF_SD);
 
 /* Sanity check on RAM size */
 if (machine->ram_size < mc->default_ram_size) {
@@ -312,6 +327,17 @@ static void microchip_icicle_kit_machine_init(MachineState 
*machine)
 
 /* Load the firmware */
 riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+
+/* Attach an SD card */
+if (dinfo) {
+SDHCIState *sdhci = &(s->soc.sdhci.slot);
+DeviceState *card = qdev_new(TYPE_SD_CARD);
+BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus");
+
+qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
+_fatal);
+qdev_realize_and_unref(card, bus, _fatal);
+}
 }
 
 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void 
*data)
diff --git a/include/hw/riscv/microchip_pfsoc.h 
b/include/hw/riscv/microchip_pfsoc.h
index a5efa1d..d810ee8 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -23,6 +23,7 @@
 #define HW_MICROCHIP_PFSOC_H
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
 /*< private >*/
@@ 

[PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation

[Bin Meng]

From: Bin Meng 

Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.

Signed-off-by: Bin Meng 
---

 MAINTAINERS |  2 +
 hw/char/Kconfig |  3 ++
 hw/char/Makefile.objs   |  1 +
 hw/char/mchp_pfsoc_mmuart.c | 82 +
 include/hw/char/mchp_pfsoc_mmuart.h | 61 +++
 5 files changed, 149 insertions(+)
 create mode 100644 hw/char/mchp_pfsoc_mmuart.c
 create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 8716cb6..e51edac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1319,7 +1319,9 @@ M: Bin Meng 
 L: qemu-ri...@nongnu.org
 S: Supported
 F: hw/riscv/microchip_pfsoc.c
+F: hw/char/mchp_pfsoc_mmuart.c
 F: include/hw/riscv/microchip_pfsoc.h
+F: include/hw/char/mchp_pfsoc_mmuart.h
 
 RX Machines
 ---
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index b7e0e4d..1d64555 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -52,3 +52,6 @@ config RENESAS_SCI
 
 config AVR_USART
 bool
+
+config MCHP_PFSOC_MMUART
+bool
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index bf177ac..f705845 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -33,6 +33,7 @@ common-obj-$(CONFIG_LM32) += lm32_juart.o
 common-obj-$(CONFIG_LM32) += lm32_uart.o
 common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o
 common-obj-$(CONFIG_SCLPCONSOLE) += sclpconsole.o sclpconsole-lm.o
+common-obj-$(CONFIG_MCHP_PFSOC_MMUART) += mchp_pfsoc_mmuart.o
 
 obj-$(CONFIG_VIRTIO) += virtio-serial-bus.o
 obj-$(CONFIG_PSERIES) += spapr_vty.o
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
new file mode 100644
index 000..9984acc
--- /dev/null
+++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -0,0 +1,82 @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "chardev/char.h"
+#include "exec/address-spaces.h"
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned 
size)
+{
+MchpPfSoCMMUartState *s = opaque;
+
+if ((addr % sizeof(uint32_t)) || (addr >= 0x34)) {
+qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+  __func__, addr);
+return 0;
+}
+
+return s->reg[addr / sizeof(uint32_t)];
+}
+
+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+uint64_t value, unsigned size)
+{
+MchpPfSoCMMUartState *s = opaque;
+uint32_t val32 = (uint32_t)value;
+
+if ((addr % sizeof(uint32_t)) || (addr >= 0x34)) {
+qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
+  " v=0x%x\n", __func__, addr, val32);
+return;
+}
+
+s->reg[addr / sizeof(uint32_t)] = val32;
+}
+
+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+.read = mchp_pfsoc_mmuart_read,
+.write = mchp_pfsoc_mmuart_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+hwaddr base, qemu_irq irq, Chardev *chr)
+{
+MchpPfSoCMMUartState *s;
+
+s = g_new0(MchpPfSoCMMUartState, 1);
+
+memory_region_init_io(>iomem, NULL, _pfsoc_mmuart_ops, s,
+  "mchp.pfsoc.mmuart", 0x1000);
+
+s->base = base;
+s->irq = irq;
+
+s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
+   DEVICE_LITTLE_ENDIAN);
+
+memory_region_add_subregion(sysmem, base + 0x20, >iomem);
+
+return s;
+}
diff --git a/include/hw/char/mchp_pfsoc_mmuart.h 
b/include/hw/char/mchp_pfsoc_mmuart.h
new file mode 100644
index 000..f619902
--- /dev/null
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
@@ -0,0 +1,61 @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without 

[PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value

[Bin Meng]

From: Bin Meng 

Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.

Signed-off-by: Bin Meng 
---

 hw/riscv/opentitan.c | 1 +
 hw/riscv/sifive_e.c  | 1 +
 hw/riscv/sifive_u.c  | 2 ++
 target/riscv/cpu.c   | 7 ++-
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index a8f0039..b0a4eae 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, 
Error **errp)
 _abort);
 object_property_set_int(OBJECT(>cpus), "num-harts", ms->smp.cpus,
 _abort);
+object_property_set_int(OBJECT(>cpus), "resetvec", 0x8090, 
_abort);
 sysbus_realize(SYS_BUS_DEVICE(>cpus), _abort);
 
 /* Boot ROM */
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index c8b0604..c84d407 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj)
 object_initialize_child(obj, "cpus", >cpus, TYPE_RISCV_HART_ARRAY);
 object_property_set_int(OBJECT(>cpus), "num-harts", ms->smp.cpus,
 _abort);
+object_property_set_int(OBJECT(>cpus), "resetvec", 0x1004, 
_abort);
 object_initialize_child(obj, "riscv.sifive.e.gpio0", >gpio,
 TYPE_SIFIVE_GPIO);
 }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 18301e6..e256da2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -611,6 +611,7 @@ static void sifive_u_soc_instance_init(Object *obj)
 qdev_prop_set_uint32(DEVICE(>e_cpus), "num-harts", 1);
 qdev_prop_set_uint32(DEVICE(>e_cpus), "hartid-base", 0);
 qdev_prop_set_string(DEVICE(>e_cpus), "cpu-type", SIFIVE_E_CPU);
+qdev_prop_set_uint64(DEVICE(>e_cpus), "resetvec", 0x1004);
 
 object_initialize_child(obj, "u-cluster", >u_cluster, TYPE_CPU_CLUSTER);
 qdev_prop_set_uint32(DEVICE(>u_cluster), "cluster-id", 1);
@@ -620,6 +621,7 @@ static void sifive_u_soc_instance_init(Object *obj)
 qdev_prop_set_uint32(DEVICE(>u_cpus), "num-harts", ms->smp.cpus - 1);
 qdev_prop_set_uint32(DEVICE(>u_cpus), "hartid-base", 1);
 qdev_prop_set_string(DEVICE(>u_cpus), "cpu-type", SIFIVE_U_CPU);
+qdev_prop_set_uint64(DEVICE(>u_cpus), "resetvec", 0x1004);
 
 object_initialize_child(obj, "prci", >prci, TYPE_SIFIVE_U_PRCI);
 object_initialize_child(obj, "otp", >otp, TYPE_SIFIVE_U_OTP);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8067a26..bd41286 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -128,7 +128,6 @@ static void riscv_any_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 set_priv_version(env, PRIV_VERSION_1_11_0);
-set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 static void riscv_base_cpu_init(Object *obj)
@@ -136,7 +135,6 @@ static void riscv_base_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 /* We set this in the realise function */
 set_misa(env, 0);
-set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 static void rvxx_sifive_u_cpu_init(Object *obj)
@@ -144,7 +142,6 @@ static void rvxx_sifive_u_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 set_priv_version(env, PRIV_VERSION_1_10_0);
-set_resetvec(env, 0x1004);
 }
 
 static void rvxx_sifive_e_cpu_init(Object *obj)
@@ -152,7 +149,6 @@ static void rvxx_sifive_e_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
 set_priv_version(env, PRIV_VERSION_1_10_0);
-set_resetvec(env, 0x1004);
 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
 
@@ -163,7 +159,6 @@ static void rv32_ibex_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 set_priv_version(env, PRIV_VERSION_1_10_0);
-set_resetvec(env, 0x8090);
 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
 
@@ -373,6 +368,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 set_feature(env, RISCV_FEATURE_PMP);
 }
 
+set_resetvec(env, cpu->cfg.resetvec);
+
 /* If misa isn't set (rv32 and rv64 machines) set it here */
 if (!env->misa) {
 /* Do some ISA extension error checking */
-- 
2.7.4

[PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit

[Bin Meng]

From: Bin Meng 

Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports
capacity up to and including 2 GiB.

Signed-off-by: Bin Meng 
---

 hw/sd/sd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 51f5900..5e7fc3f 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -313,7 +313,7 @@ static void sd_ocr_powerup(void *opaque)
 /* card power-up OK */
 sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
 
-if (sd->size > 1 * GiB) {
+if (sd->size > 2 * GiB) {
 sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
 }
 }
-- 
2.7.4

[PATCH 10/18] hw/sd: Add Cadence SDHCI emulation

[Bin Meng]

From: Bin Meng 

Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.

This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.

Signed-off-by: Bin Meng 
---

 hw/sd/Kconfig |   4 ++
 hw/sd/Makefile.objs   |   1 +
 hw/sd/cadence_sdhci.c | 162 ++
 include/hw/sd/cadence_sdhci.h |  65 +
 4 files changed, 232 insertions(+)
 create mode 100644 hw/sd/cadence_sdhci.c
 create mode 100644 include/hw/sd/cadence_sdhci.h

diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
index c5e1e55..633b9af 100644
--- a/hw/sd/Kconfig
+++ b/hw/sd/Kconfig
@@ -19,3 +19,7 @@ config SDHCI_PCI
 default y if PCI_DEVICES
 depends on PCI
 select SDHCI
+
+config CADENCE_SDHCI
+bool
+select SDHCI
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
index 0d1df17..4d500a6 100644
--- a/hw/sd/Makefile.objs
+++ b/hw/sd/Makefile.objs
@@ -10,3 +10,4 @@ common-obj-$(CONFIG_OMAP) += omap_mmc.o
 common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
 common-obj-$(CONFIG_RASPI) += bcm2835_sdhost.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o
+common-obj-$(CONFIG_CADENCE_SDHCI) += cadence_sdhci.o
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
new file mode 100644
index 000..67ffd14
--- /dev/null
+++ b/hw/sd/cadence_sdhci.c
@@ -0,0 +1,162 @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/sd/cadence_sdhci.h"
+#include "sdhci-internal.h"
+
+#define TO_REG(addr)((addr) / sizeof(uint32_t))
+
+static void cadence_sdhci_reset(DeviceState *dev)
+{
+CadenceSDHCIState *sdhci = CADENCE_SDHCI(dev);
+
+memset(sdhci->regs, 0, CADENCE_SDHCI_REG_SIZE);
+sdhci->regs[TO_REG(SDHCI_CDNS_HRS00)] = SDHCI_CDNS_HRS00_POR_VAL;
+}
+
+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int 
size)
+{
+uint32_t val = 0;
+CadenceSDHCIState *sdhci = opaque;
+
+if (addr < CADENCE_SDHCI_REG_SIZE) {
+val = sdhci->regs[TO_REG(addr)];
+} else {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
+  __func__, addr);
+}
+
+return (uint64_t)val;
+}
+
+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
+unsigned int size)
+{
+CadenceSDHCIState *sdhci = opaque;
+uint32_t val32 = (uint32_t)val;
+
+switch (addr) {
+case SDHCI_CDNS_HRS00:
+/*
+ * The only writable bit is SWR (software reset) and it automatically
+ * clears to zero, so essentially this register remains unchanged.
+ */
+if (val32 & SDHCI_CDNS_HRS00_SWR) {
+cadence_sdhci_reset(DEVICE(sdhci));
+sdhci_poweron_reset(DEVICE(>slot));
+}
+
+break;
+case SDHCI_CDNS_HRS04:
+/*
+ * Only emulate the ACK bit behavior when read or write transaction
+ * are requested.
+ */
+if (val32 & (SDHCI_CDNS_HRS04_WR | SDHCI_CDNS_HRS04_RD)) {
+val32 |= SDHCI_CDNS_HRS04_ACK;
+} else {
+val32 &= ~SDHCI_CDNS_HRS04_ACK;
+}
+
+sdhci->regs[TO_REG(addr)] = val32;
+break;
+case SDHCI_CDNS_HRS06:
+if (val32 & SDHCI_CDNS_HRS06_TUNE_UP) {
+val32 &= ~SDHCI_CDNS_HRS06_TUNE_UP;
+}
+
+sdhci->regs[TO_REG(addr)] = val32;
+break;
+default:
+if (addr < CADENCE_SDHCI_REG_SIZE) {
+sdhci->regs[TO_REG(addr)] = val32;
+} else {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
+  __func__, addr);
+}
+}
+}
+
+static const MemoryRegionOps cadence_sdhci_ops = {
+.read = cadence_sdhci_read,
+.write = cadence_sdhci_write,
+.endianness = 

[PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property

[Bin Meng]

From: Bin Meng 

Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.

Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.

Signed-off-by: Bin Meng 
---

 target/riscv/cpu.c | 1 +
 target/riscv/cpu.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bd..8067a26 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -518,6 +518,7 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d..d34bcfa 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -291,6 +291,7 @@ typedef struct RISCVCPU {
 uint16_t elen;
 bool mmu;
 bool pmp;
+uint64_t resetvec;
 } cfg;
 } RISCVCPU;
 
-- 
2.7.4

[PATCH 4/5] hw/char/avr_usart: Use the Clock API

[Philippe Mathieu-Daudé]

Expose the 'xck' clock source. Connect the MCU I/O clock to it.

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/hw/char/avr_usart.h | 2 ++
 hw/avr/atmega.c | 1 +
 hw/char/avr_usart.c | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/include/hw/char/avr_usart.h b/include/hw/char/avr_usart.h
index 46d6c76e50..13cfd5ea07 100644
--- a/include/hw/char/avr_usart.h
+++ b/include/hw/char/avr_usart.h
@@ -25,6 +25,7 @@
 #include "hw/sysbus.h"
 #include "chardev/char-fe.h"
 #include "hw/hw.h"
+#include "hw/clock.h"
 
 #define TYPE_AVR_USART "avr-usart"
 #define AVR_USART(obj) \
@@ -51,6 +52,7 @@ typedef struct {
 /* Baud Rate Registers (low/high byte) */
 uint8_t brrh;
 uint8_t brrl;
+Clock *clkin;
 
 /* Receive Complete */
 qemu_irq rxc_irq;
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index f14b558140..b6e86a4531 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -302,6 +302,7 @@ static void atmega_realize(DeviceState *dev, Error **errp)
 object_initialize_child(OBJECT(dev), devname, >usart[i],
 TYPE_AVR_USART);
 qdev_prop_set_chr(DEVICE(>usart[i]), "chardev", serial_hd(i));
+qdev_connect_clock_in(DEVICE(>usart[i]), "xck", s->ioclk);
 sbd = SYS_BUS_DEVICE(>usart[i]);
 sysbus_realize(sbd, _abort);
 sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[USART(i)].addr);
diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c
index fd0b488ef9..4a43492082 100644
--- a/hw/char/avr_usart.c
+++ b/hw/char/avr_usart.c
@@ -23,6 +23,7 @@
 #include "hw/char/avr_usart.h"
 #include "qemu/log.h"
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 
 /* Offsets of registers. */
@@ -307,12 +308,14 @@ static void avr_usart_pr(void *opaque, int irq, int level)
 static void avr_usart_init(Object *obj)
 {
 AVRUsartState *s = AVR_USART(obj);
+
 sysbus_init_irq(SYS_BUS_DEVICE(obj), >rxc_irq);
 sysbus_init_irq(SYS_BUS_DEVICE(obj), >dre_irq);
 sysbus_init_irq(SYS_BUS_DEVICE(obj), >txc_irq);
 memory_region_init_io(>mmio, obj, _usart_ops, s, TYPE_AVR_USART, 7);
 sysbus_init_mmio(SYS_BUS_DEVICE(obj), >mmio);
 qdev_init_gpio_in(DEVICE(s), avr_usart_pr, 1);
+s->clkin = qdev_init_clock_in(DEVICE(obj), "xck", NULL, s);
 s->enabled = true;
 }
 
-- 
2.21.3

[PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board

[Bin Meng]

From: Bin Meng 

This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.

For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

Unlike SiFive FU540, the RISC-V core resect vector is at 0x2022.
The following perepherals are created as an unimplemented device:

- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG

More devices will be added later.

The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services

To launch this machine:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit

The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.

Signed-off-by: Bin Meng 
---

 MAINTAINERS |   7 +
 default-configs/riscv64-softmmu.mak |   1 +
 hw/riscv/Kconfig|   6 +
 hw/riscv/Makefile.objs  |   1 +
 hw/riscv/microchip_pfsoc.c  | 312 
 include/hw/riscv/microchip_pfsoc.h  |  88 ++
 6 files changed, 415 insertions(+)
 create mode 100644 hw/riscv/microchip_pfsoc.c
 create mode 100644 include/hw/riscv/microchip_pfsoc.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 0886eb3..8716cb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1314,6 +1314,13 @@ F: include/hw/riscv/opentitan.h
 F: include/hw/char/ibex_uart.h
 F: include/hw/intc/ibex_plic.h
 
+Microchip PolarFire SoC Icicle Kit
+M: Bin Meng 
+L: qemu-ri...@nongnu.org
+S: Supported
+F: hw/riscv/microchip_pfsoc.c
+F: include/hw/riscv/microchip_pfsoc.h
+
 RX Machines
 ---
 rx-gdbsim
diff --git a/default-configs/riscv64-softmmu.mak 
b/default-configs/riscv64-softmmu.mak
index aaf6d73..76b6195 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -10,3 +10,4 @@ CONFIG_SPIKE=y
 CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=y
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 28947ef..3292fae 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -48,3 +48,9 @@ config RISCV_VIRT
 select PCI_EXPRESS_GENERIC_BRIDGE
 select PFLASH_CFI01
 select SIFIVE
+
+config MICROCHIP_PFSOC
+bool
+select HART
+select SIFIVE
+select UNIMP
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index 57cc708..419a5a0 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -14,3 +14,4 @@ obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_uart.o
 obj-$(CONFIG_SPIKE) += spike.o
 obj-$(CONFIG_RISCV_VIRT) += virt.o
+obj-$(CONFIG_MICROCHIP_PFSOC) += microchip_pfsoc.o
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
new file mode 100644
index 000..20a642c
--- /dev/null
+++ b/hw/riscv/microchip_pfsoc.c
@@ -0,0 +1,312 @@
+/*
+ * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng 
+ *
+ * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
+ *
+ * 0) CLINT (Core Level Interruptor)
+ * 1) PLIC (Platform Level Interrupt Controller)
+ * 2) eNVM (Embedded Non-Volatile Memory)
+ *
+ * This board currently generates devicetree dynamically that indicates at 
least
+ * two harts and up to five harts.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/cpu/cluster.h"
+#include "target/riscv/cpu.h"
+#include "hw/misc/unimp.h"
+#include "hw/riscv/boot.h"
+#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_clint.h"
+#include "hw/riscv/sifive_plic.h"
+#include "hw/riscv/microchip_pfsoc.h"
+
+/*
+ * The BIOS image used by this machine is called Hart Software Services (HSS).
+ * See https://github.com/polarfire-soc/hart-software-services
+ */
+#define BIOS_FILENAME   "hss.bin"

[PATCH 02/18] hw/riscv: hart: Add a new 'resetvec' property

[Bin Meng]

From: Bin Meng 

RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.

Signed-off-by: Bin Meng 
---

 hw/riscv/riscv_hart.c | 3 +++
 include/hw/riscv/riscv_hart.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index f59fe52..613ea2a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -31,6 +31,8 @@ static Property riscv_harts_props[] = {
 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
+DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
+   DEFAULT_RSTVEC),
 DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int 
idx,
char *cpu_type, Error **errp)
 {
 object_initialize_child(OBJECT(s), "harts[*]", >harts[idx], cpu_type);
+qdev_prop_set_uint64(DEVICE(>harts[idx]), "resetvec", s->resetvec);
 s->harts[idx].env.mhartid = s->hartid_base + idx;
 qemu_register_reset(riscv_harts_cpu_reset, >harts[idx]);
 return qdev_realize(DEVICE(>harts[idx]), NULL, errp);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index c75856f..77aa4bc 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState {
 uint32_t num_harts;
 uint32_t hartid_base;
 char *cpu_type;
+uint64_t resetvec;
 RISCVCPU *harts;
 } RISCVHartArrayState;
 
-- 
2.7.4

[PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

[Bin Meng]

From: Bin Meng 

This adds support for Microchip PolarFire SoC Icicle Kit board.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.

For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

The Icicle Kit board information can be found here:
https://www.microsemi.com/existing-parts/parts/152514

Unlike SiFive FU540, the RISC-V core resect vector is at 0x2022.
The RISC-V CPU and HART codes has been updated to set the core's
reset vector based on a configurable property from machine codes.

The following perepherals are created as an unimplemented device:

- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG
- GPIO

The following perepherals are emulated:
- SiFive CLINT
- SiFive PLIC
- PolarFire SoC Multi-Mode UART
- PolarFire SoC DMA
- Cadence eMMC/SDHCI controller
- Cadence Gigabit Ethernet MAC

Some bugs in the SD card codes are fixed during the development.

The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services

To launch this machine:
$ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
-bios path/to/hss.bin -sd path/to/sdcard.img \
-nic tap,ifname=tap,script=no,model=cadence_gem \
-display none -serial stdio \
-chardev socket,id=serial1,path=serial1.sock,server,wait \
-serial chardev:serial1

The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.

HSS output is on the first serial port (stdio) and U-Boot/Linux
outputs on the 2nd serial port. OpenSBI outputs on a random serial
port due to the lottery mechanism used during the multi-core boot.


Bin Meng (18):
  target/riscv: cpu: Add a new 'resetvec' property
  hw/riscv: hart: Add a new 'resetvec' property
  target/riscv: cpu: Set reset vector based on the configured property
value
  hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
  hw/char: Add Microchip PolarFire SoC MMUART emulation
  hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
  hw/sd: sd: Fix incorrect populated function switch status data
structure
  hw/sd: sd: Correctly set the high capacity bit
  hw/sd: sdhci: Make sdhci_poweron_reset() internal visible
  hw/sd: Add Cadence SDHCI emulation
  hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an
SD card
  hw/dma: Add Microchip PolarFire Soc DMA controller emulation
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Document the software used for testing

 MAINTAINERS |  11 +
 default-configs/riscv64-softmmu.mak |   1 +
 hw/char/Kconfig |   3 +
 hw/char/Makefile.objs   |   1 +
 hw/char/mchp_pfsoc_mmuart.c |  82 +++
 hw/dma/Kconfig  |   3 +
 hw/dma/Makefile.objs|   1 +
 hw/dma/mchp_pfsoc_dma.c | 322 +
 hw/net/cadence_gem.c|   7 +-
 hw/riscv/Kconfig|   9 +
 hw/riscv/Makefile.objs  |   1 +
 hw/riscv/microchip_pfsoc.c  | 456 
 hw/riscv/opentitan.c|   1 +
 hw/riscv/riscv_hart.c   |   3 +
 hw/riscv/sifive_clint.c |  25 +-
 hw/riscv/sifive_e.c |   4 +-
 hw/riscv/sifive_u.c |   5 +-
 hw/riscv/spike.c|   2 +-
 hw/riscv/virt.c |   3 +-
 hw/sd/Kconfig   |   4 +
 hw/sd/Makefile.objs |   1 +
 hw/sd/cadence_sdhci.c   | 162 +
 hw/sd/sd.c  |   8 +-
 hw/sd/sdhci-internal.h  |   1 +
 hw/sd/sdhci.c   |   2 +-
 include/hw/char/mchp_pfsoc_mmuart.h |  61 +
 include/hw/dma/mchp_pfsoc_dma.h |  57 +
 include/hw/net/cadence_gem.h|   2 +
 include/hw/riscv/microchip_pfsoc.h  | 125 ++
 include/hw/riscv/riscv_hart.h   |   1 +
 include/hw/riscv/sifive_clint.h |   3 +-
 include/hw/sd/cadence_sdhci.h   |  65 +
 target/riscv/cpu.c  |   8 +-
 target/riscv/cpu.h  |   7 +-
 target/riscv/cpu_helper.c   |   4 +-
 target/riscv/csr.c  |   4 +-
 36 files changed, 1424 insertions(+), 31 deletions(-)
 create mode 100644 hw/char/mchp_pfsoc_mmuart.c
 create mode 100644 hw/dma/mchp_pfsoc_dma.c
 create mode 100644 hw/riscv/microchip_pfsoc.c
 create mode 100644 

[PATCH 3/5] hw/char/avr_usart: Restrict register definitions to source

[Philippe Mathieu-Daudé]

Nothing out of our model implementation is supposed to access its
registers. Keep the definitions local.

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/hw/char/avr_usart.h | 30 --
 hw/char/avr_usart.c | 30 ++
 2 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/include/hw/char/avr_usart.h b/include/hw/char/avr_usart.h
index 5739aaf26f..46d6c76e50 100644
--- a/include/hw/char/avr_usart.h
+++ b/include/hw/char/avr_usart.h
@@ -26,36 +26,6 @@
 #include "chardev/char-fe.h"
 #include "hw/hw.h"
 
-/* Offsets of registers. */
-#define USART_DR   0x06
-#define USART_CSRA  0x00
-#define USART_CSRB  0x01
-#define USART_CSRC  0x02
-#define USART_BRRH 0x05
-#define USART_BRRL 0x04
-
-/* Relevant bits in regiters. */
-#define USART_CSRA_RXC(1 << 7)
-#define USART_CSRA_TXC(1 << 6)
-#define USART_CSRA_DRE(1 << 5)
-#define USART_CSRA_MPCM   (1 << 0)
-
-#define USART_CSRB_RXCIE  (1 << 7)
-#define USART_CSRB_TXCIE  (1 << 6)
-#define USART_CSRB_DREIE  (1 << 5)
-#define USART_CSRB_RXEN   (1 << 4)
-#define USART_CSRB_TXEN   (1 << 3)
-#define USART_CSRB_CSZ2   (1 << 2)
-#define USART_CSRB_RXB8   (1 << 1)
-#define USART_CSRB_TXB8   (1 << 0)
-
-#define USART_CSRC_MSEL1  (1 << 7)
-#define USART_CSRC_MSEL0  (1 << 6)
-#define USART_CSRC_PM1(1 << 5)
-#define USART_CSRC_PM0(1 << 4)
-#define USART_CSRC_CSZ1   (1 << 2)
-#define USART_CSRC_CSZ0   (1 << 1)
-
 #define TYPE_AVR_USART "avr-usart"
 #define AVR_USART(obj) \
 OBJECT_CHECK(AVRUsartState, (obj), TYPE_AVR_USART)
diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c
index fbe2a112b7..fd0b488ef9 100644
--- a/hw/char/avr_usart.c
+++ b/hw/char/avr_usart.c
@@ -25,6 +25,36 @@
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
 
+/* Offsets of registers. */
+#define USART_DR   0x06
+#define USART_CSRA  0x00
+#define USART_CSRB  0x01
+#define USART_CSRC  0x02
+#define USART_BRRH 0x05
+#define USART_BRRL 0x04
+
+/* Relevant bits in regiters. */
+#define USART_CSRA_RXC(1 << 7)
+#define USART_CSRA_TXC(1 << 6)
+#define USART_CSRA_DRE(1 << 5)
+#define USART_CSRA_MPCM   (1 << 0)
+
+#define USART_CSRB_RXCIE  (1 << 7)
+#define USART_CSRB_TXCIE  (1 << 6)
+#define USART_CSRB_DREIE  (1 << 5)
+#define USART_CSRB_RXEN   (1 << 4)
+#define USART_CSRB_TXEN   (1 << 3)
+#define USART_CSRB_CSZ2   (1 << 2)
+#define USART_CSRB_RXB8   (1 << 1)
+#define USART_CSRB_TXB8   (1 << 0)
+
+#define USART_CSRC_MSEL1  (1 << 7)
+#define USART_CSRC_MSEL0  (1 << 6)
+#define USART_CSRC_PM1(1 << 5)
+#define USART_CSRC_PM0(1 << 4)
+#define USART_CSRC_CSZ1   (1 << 2)
+#define USART_CSRC_CSZ0   (1 << 1)
+
 static int avr_usart_can_receive(void *opaque)
 {
 AVRUsartState *usart = opaque;
-- 
2.21.3

[PATCH 2/5] hw/timer/avr_timer16: Use the Clock API

[Philippe Mathieu-Daudé]

Expose the 'clkt' clock source. Connect the MCU I/O clock to it.
Drop the now unused 'cpu-frequency-hz' static property.

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/hw/timer/avr_timer16.h |  3 ++-
 hw/avr/atmega.c|  3 +--
 hw/timer/avr_timer16.c | 12 
 3 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/include/hw/timer/avr_timer16.h b/include/hw/timer/avr_timer16.h
index 982019d242..fb1ef5d3be 100644
--- a/include/hw/timer/avr_timer16.h
+++ b/include/hw/timer/avr_timer16.h
@@ -31,6 +31,7 @@
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "hw/hw.h"
+#include "hw/clock.h"
 
 enum NextInterrupt {
 OVERFLOW,
@@ -52,6 +53,7 @@ typedef struct AVRTimer16State {
 MemoryRegion iomem;
 MemoryRegion imsk_iomem;
 MemoryRegion ifr_iomem;
+Clock *clkin;
 QEMUTimer *timer;
 qemu_irq capt_irq;
 qemu_irq compa_irq;
@@ -84,7 +86,6 @@ typedef struct AVRTimer16State {
 uint8_t ifr;
 
 uint8_t id;
-uint64_t cpu_freq_hz;
 uint64_t freq_hz;
 uint64_t period_ns;
 uint64_t reset_time_ns;
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index 9d814de499..f14b558140 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -332,8 +332,7 @@ static void atmega_realize(DeviceState *dev, Error **errp)
 devname = g_strdup_printf("timer%zu", i);
 object_initialize_child(OBJECT(dev), devname, >timer[i],
 TYPE_AVR_TIMER16);
-object_property_set_uint(OBJECT(>timer[i]), "cpu-frequency-hz",
- s->xtal_freq_hz, _abort);
+qdev_connect_clock_in(DEVICE(>timer[i]), "clkt", s->ioclk);
 sbd = SYS_BUS_DEVICE(>timer[i]);
 sysbus_realize(sbd, _abort);
 sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr);
diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c
index c48555da52..7634fe6587 100644
--- a/hw/timer/avr_timer16.c
+++ b/hw/timer/avr_timer16.c
@@ -35,6 +35,7 @@
 #include "qapi/error.h"
 #include "qemu/log.h"
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "hw/timer/avr_timer16.h"
 #include "trace.h"
@@ -167,7 +168,7 @@ static void avr_timer16_clksrc_update(AVRTimer16State *t16)
 break;
 }
 if (divider) {
-t16->freq_hz = t16->cpu_freq_hz / divider;
+t16->freq_hz = clock_get_hz(t16->clkin) / divider;
 t16->period_ns = NANOSECONDS_PER_SECOND / t16->freq_hz;
 trace_avr_timer16_clksrc_update(t16->freq_hz, t16->period_ns,
 (uint64_t)(1e6 / t16->freq_hz));
@@ -544,8 +545,6 @@ static const MemoryRegionOps avr_timer16_ifr_ops = {
 
 static Property avr_timer16_properties[] = {
 DEFINE_PROP_UINT8("id", struct AVRTimer16State, id, 0),
-DEFINE_PROP_UINT64("cpu-frequency-hz", struct AVRTimer16State,
-   cpu_freq_hz, 0),
 DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -564,6 +563,8 @@ static void avr_timer16_init(Object *obj)
 {
 AVRTimer16State *s = AVR_TIMER16(obj);
 
+s->clkin = qdev_init_clock_in(DEVICE(obj), "clkt", NULL, s);
+
 sysbus_init_irq(SYS_BUS_DEVICE(obj), >capt_irq);
 sysbus_init_irq(SYS_BUS_DEVICE(obj), >compa_irq);
 sysbus_init_irq(SYS_BUS_DEVICE(obj), >compb_irq);
@@ -587,11 +588,6 @@ static void avr_timer16_realize(DeviceState *dev, Error 
**errp)
 {
 AVRTimer16State *s = AVR_TIMER16(dev);
 
-if (s->cpu_freq_hz == 0) {
-error_setg(errp, "AVR timer16: cpu-frequency-hz property must be set");
-return;
-}
-
 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_timer16_interrupt, s);
 s->enabled = true;
 }
-- 
2.21.3

[PATCH 1/5] hw/avr/atmega: Introduce the I/O clock

[Philippe Mathieu-Daudé]

Use the Clock API to model the I/O clock. As we don't model
the Clock Control Unit, the XTAL is its unique clock source.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/avr/atmega.h | 2 ++
 hw/avr/atmega.c | 4 
 2 files changed, 6 insertions(+)

diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index 0928cb0ce6..c91317107f 100644
--- a/hw/avr/atmega.h
+++ b/hw/avr/atmega.h
@@ -14,6 +14,7 @@
 #include "hw/char/avr_usart.h"
 #include "hw/timer/avr_timer16.h"
 #include "hw/misc/avr_power.h"
+#include "hw/clock.h"
 #include "target/avr/cpu.h"
 
 #define TYPE_ATMEGA_MCU "ATmega"
@@ -35,6 +36,7 @@ typedef struct AtmegaMcuState {
 /*< public >*/
 
 AVRCPU cpu;
+Clock *ioclk;
 MemoryRegion flash;
 MemoryRegion eeprom;
 MemoryRegion sram;
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index 7131224431..9d814de499 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -15,6 +15,7 @@
 #include "exec/memory.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h" /* FIXME memory_region_allocate_system_memory for sram 
*/
@@ -231,6 +232,9 @@ static void atmega_realize(DeviceState *dev, Error **errp)
 error_setg(errp, "\"xtal-frequency-hz\" property must be provided.");
 return;
 }
+s->ioclk = qdev_init_clock_out(dev, "ioclk");
+/* Clock Control Unit not implemented: directly distribute from xtal */
+clock_set_hz(s->ioclk, s->xtal_freq_hz);
 
 /* CPU */
 object_initialize_child(OBJECT(dev), "cpu", >cpu, mc->cpu_type);
-- 
2.21.3

[PATCH 0/5] hw/avr: Start using the Clock API

[Philippe Mathieu-Daudé]

In this series we slowly start to use the recently added
Clock API in the AVR ATmega MCU.

As the Clock Control Unit is not yet modelled, we simply
connect the XTAL sink to the UART and Timer sources.

Philippe Mathieu-Daudé (5):
  hw/avr/atmega: Introduce the I/O clock
  hw/timer/avr_timer16: Use the Clock API
  hw/char/avr_usart: Restrict register definitions to source
  hw/char/avr_usart: Use the Clock API
  hw/char/avr_usart: Trace baudrate changes

 hw/avr/atmega.h|  2 ++
 include/hw/char/avr_usart.h| 32 ++-
 include/hw/timer/avr_timer16.h |  3 ++-
 hw/avr/atmega.c|  8 --
 hw/char/avr_usart.c| 46 ++
 hw/timer/avr_timer16.c | 12 +++--
 hw/char/trace-events   |  3 +++
 7 files changed, 65 insertions(+), 41 deletions(-)

-- 
2.21.3

[PATCH 5/5] hw/char/avr_usart: Trace baudrate changes

[Philippe Mathieu-Daudé]

Add a trace event to track baudrate changes.

Example when running the FreeRTOS acceptance test [1]:

  $ qemu-system-avr -machine arduino-mega-2560-v3 -bios demo.elf -trace avr\*
  2546@1597415281.399619:avr_usart_update_baudrate baudrate 0x0019 (38461 bauds)
  2546@1597415281.400029:avr_usart_update_baudrate baudrate 0x0019 (38461 bauds)

Which confirm the definition from the test [2]:

  #define mainCOM_TEST_BAUD_RATE( ( unsigned long ) 38400 )

[1] tests/acceptance/machine_avr6.py
[2] 
https://github.com/seharris/qemu-avr-tests/blob/9c0c24da1b1/free-rtos/Demo/AVR_ATMega2560_GCC/main.c#L80

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/char/avr_usart.c  | 13 +
 hw/char/trace-events |  3 +++
 2 files changed, 16 insertions(+)

diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c
index 4a43492082..176158a96b 100644
--- a/hw/char/avr_usart.c
+++ b/hw/char/avr_usart.c
@@ -25,6 +25,7 @@
 #include "hw/irq.h"
 #include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
+#include "trace.h"
 
 /* Offsets of registers. */
 #define USART_DR   0x06
@@ -56,6 +57,8 @@
 #define USART_CSRC_CSZ1   (1 << 2)
 #define USART_CSRC_CSZ0   (1 << 1)
 
+#define USART_CLOCK_DIVISOR  16  /* baudrate is input clock / 16 */
+
 static int avr_usart_can_receive(void *opaque)
 {
 AVRUsartState *usart = opaque;
@@ -120,6 +123,14 @@ static void update_char_mask(AVRUsartState *usart)
 }
 }
 
+static void avr_usart_update_baudrate(AVRUsartState *s)
+{
+unsigned baudrate = (clock_get_hz(s->clkin) / USART_CLOCK_DIVISOR)
+/ (((s->brrh << 8) | s->brrl) + 1);
+
+trace_avr_usart_update_baudrate((s->brrh << 8) | s->brrl, baudrate);
+}
+
 static void avr_usart_reset(DeviceState *dev)
 {
 AVRUsartState *usart = AVR_USART(dev);
@@ -269,9 +280,11 @@ static void avr_usart_write(void *opaque, hwaddr addr, 
uint64_t value,
 break;
 case USART_BRRL:
 usart->brrl = value;
+avr_usart_update_baudrate(usart);
 break;
 case USART_BRRH:
 usart->brrh = value & 0b;
+avr_usart_update_baudrate(usart);
 break;
 default:
 qemu_log_mask(
diff --git a/hw/char/trace-events b/hw/char/trace-events
index d20eafd56f..b92cecbfaa 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -100,3 +100,6 @@ exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, 
uint32_t intsp) "UART%d:
 
 # hw/char/cadence_uart.c
 cadence_uart_baudrate(unsigned baudrate) "baudrate %u"
+
+# avr_usart.c
+avr_usart_update_baudrate(uint16_t regval, unsigned baudrate) "baudrate 0x%04x 
(%u bauds)"
-- 
2.21.3

Re: [PATCH v2 0/9] preallocate filter

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20200814130348.20625-1-vsement...@virtuozzo.com/



Hi,

This series failed the docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

  TESTcheck-unit: tests/test-char
Unexpected error in object_property_try_add() at 
/tmp/qemu-test/src/qom/object.c:1181:
attempt to add duplicate property 'serial-id' to object (type 'container')
ERROR test-char - too few tests run (expected 38, got 9)
make: *** [check-unit] Error 1
make: *** Waiting for unfinished jobs
  TESTiotest-qcow2: 029
  TESTcheck-qtest-x86_64: tests/qtest/hd-geo-test
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', 
'--label', 'com.qemu.instance.uuid=933e39134d33428cb91c95a7f1ece9e6', '-u', 
'1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', 
'-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-u8odh47c/src/docker-src.2020-08-14-12.16.21.29250:/var/tmp/qemu:z,ro',
 'qemu/centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=933e39134d33428cb91c95a7f1ece9e6
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-u8odh47c/src'
make: *** [docker-run-test-quick@centos7] Error 2

real13m58.743s
user0m8.567s


The full log is available at
http://patchew.org/logs/20200814130348.20625-1-vsement...@virtuozzo.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PATCH v2 0/9] preallocate filter

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20200814130348.20625-1-vsement...@virtuozzo.com/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===

  CC  nbd/trace.o
  CC  scsi/trace.o

Warning, treated as error:
../src/docs/system/qemu-block-drivers.rst.inc:980:Duplicate explicit target 
name: "cmdoption-preallocate-arg-prealloc-align".
  CC  audio/trace.o
  CC  chardev/trace.o
---
  CC  hw/ide/trace.o
  CC  hw/input/trace.o
  CC  hw/intc/trace.o
make: *** [Makefile:: 
.docs_system_qemu.1_docs_system_qemu-block-drivers.7_docs_system_qemu-cpu-models.7.sentinel.]
 Error 2
make: *** Deleting file 
'.docs_system_qemu.1_docs_system_qemu-block-drivers.7_docs_system_qemu-cpu-models.7.sentinel.'
make: *** Waiting for unfinished jobs

Warning, treated as error:
../src/docs/system/qemu-block-drivers.rst.inc:980:Duplicate explicit target 
name: "cmdoption-preallocate-arg-prealloc-align".
make: *** [Makefile:1100: docs/system/index.html] Error 2
Traceback (most recent call last):
  File "./tests/docker/docker.py", line 709, in 
sys.exit(main())
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', 
'--label', 'com.qemu.instance.uuid=2b8332eeb0c84671bf5f795b37073245', '-u', 
'1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', 
'-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-msztbvd9/src/docker-src.2020-08-14-12.13.08.24140:/var/tmp/qemu:z,ro',
 'qemu/fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=2b8332eeb0c84671bf5f795b37073245
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-msztbvd9/src'
make: *** [docker-run-test-mingw@fedora] Error 2

real2m29.643s
user0m7.966s


The full log is available at
http://patchew.org/logs/20200814130348.20625-1-vsement...@virtuozzo.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation

[Richard Henderson]

On 8/14/20 1:59 AM, Chih-Min Chao wrote:
> By the way,  the other patches have been queued in softfloat-next. 
> Do I need to resend the other two patches in the next version or just this 
> one ?

Just this one.  Thanks.


r~

Re: [PATCH v2 2/3] target/arm: Implement an IMPDEF pauth algorithm

[Richard Henderson]

On 8/14/20 2:26 AM, Andrew Jones wrote:
>> +static uint64_t __attribute__((noinline))
>> +pauth_computepac_impdef(uint64_t data, uint64_t modifier, ARMPACKey key)
> 
> Out of curiosity, why do we need to make these computepac functions
> noinline?

Oh, heh.  Left over from profiling.  Will remove.

> I think this patch should come before the last one. As it stands, when
> bisecting between the last one and this one a user could attempt to
> enable pauth-imdef, but it wouldn't do anything, or it would potentially
> break things. However, this patch shouldn't change anything if it comes
> first.

The current patch ordering would enable impdef but implement that with the
architected algorithm.  Which is ok.

But you're right that the other ordering makes more sense.


r~

Re: [PATCH] ide:do nothing for identify cmd if no any device attached

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20200814043657.5815-1-rockcui...@zhaoxin.com/



Hi,

This series failed the docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

  TESTcheck-unit: tests/test-char
Unexpected error in object_property_try_add() at 
/tmp/qemu-test/src/qom/object.c:1181:
attempt to add duplicate property 'serial-id' to object (type 'container')
ERROR test-char - too few tests run (expected 38, got 9)
make: *** [check-unit] Error 1
make: *** Waiting for unfinished jobs
  TESTiotest-qcow2: 024
  TESTiotest-qcow2: 025
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', 
'--label', 'com.qemu.instance.uuid=3d9b744ea9784590902f0fd1b1c1cc94', '-u', 
'1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', 
'-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-uf3g3t43/src/docker-src.2020-08-14-11.29.38.3773:/var/tmp/qemu:z,ro',
 'qemu/centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=3d9b744ea9784590902f0fd1b1c1cc94
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-uf3g3t43/src'
make: *** [docker-run-test-quick@centos7] Error 2

real13m29.699s
user0m8.487s


The full log is available at
http://patchew.org/logs/20200814043657.5815-1-rockcui...@zhaoxin.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PATCH v7 14/47] stream: Deal with filters

[Andrey Shinkevich]

On 10.08.2020 14:04, Vladimir Sementsov-Ogievskiy wrote:

10.08.2020 11:12, Max Reitz wrote:

On 07.08.20 12:29, Vladimir Sementsov-Ogievskiy wrote:

16.07.2020 17:59, Max Reitz wrote:

On 10.07.20 19:41, Andrey Shinkevich wrote:

On 10.07.2020 18:24, Max Reitz wrote:

On 09.07.20 16:52, Andrey Shinkevich wrote:

On 25.06.2020 18:21, Max Reitz wrote:

Because of the (not so recent anymore) changes that make the
stream job
independent of the base node and instead track the node above 
it, we
have to split that "bottom" node into two cases: The bottom COW 
node,
and the node directly above the base node (which may be an R/W 
filter

or the bottom COW node).

Signed-off-by: Max Reitz 
---
 qapi/block-core.json |  4 +++
 block/stream.c   | 63

 blockdev.c   |  4 ++-
 3 files changed, 53 insertions(+), 18 deletions(-)

diff --git a/qapi/block-core.json b/qapi/block-core.json
index b20332e592..df87855429 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -2486,6 +2486,10 @@
 # On successful completion the image file is updated to 
drop the

backing file
 # and the BLOCK_JOB_COMPLETED event is emitted.
 #
+# In case @device is a filter node, block-stream modifies the 
first

non-filter
+# overlay node below it to point to base's backing node (or 
NULL if

@base was
+# not specified) instead of modifying @device itself.
+#
 # @job-id: identifier for the newly-created block job. If
 #  omitted, the device name will be used. (Since 2.7)
 #
diff --git a/block/stream.c b/block/stream.c
index aa2e7af98e..b9c1141656 100644
--- a/block/stream.c
+++ b/block/stream.c
@@ -31,7 +31,8 @@ enum {
   typedef struct StreamBlockJob {
 BlockJob common;
-    BlockDriverState *bottom;
+    BlockDriverState *base_overlay; /* COW overlay (stream from
this) */
+    BlockDriverState *above_base;   /* Node directly above the
base */

Keeping the base_overlay is enough to complete the stream job.
Depends on the definition.  If we decide it isn’t enough, then it 
isn’t

enough.

The above_base may disappear during the job and we can't rely on 
it.

In this version of this series, it may not, because the chain is
frozen.
    So the above_base cannot disappear.


Once we insert a filter above the top bs of the stream job, the 
parallel

jobs in

the iotests #030 will fail with 'frozen link error'. It is because of
the

independent parallel stream or commit jobs that insert/remove their
filters

asynchroniously.


I’m not sure whether that’s a problem with this series specifically.


We can discuss whether we should allow it to disappear, but I think
not.

The problem is, we need something to set as the backing file after
streaming.  How do we figure out what that should be? My proposal
is we
keep above_base and use its immediate child.


We can do the same with the base_overlay.

If the backing node turns out to be a filter, the proper backing
child will

be set after the filter is removed. So, we shouldn't care.


And what if the user manually added some filter above the base (i.e.
below base_overlay) that they want to keep after the job?



It's automatically kept, if we use base_overlay->backing->bs as final
backing node.

You mean, that they want it to be dropped?


Er, yes.  Point is, the graph structure below with @base at the root may
be different than the one right below @base_overlay.


so, assuming the following:

top -(backing)-> manually-inserted-filter -(file)-> base

and user do stream with base=base, and expects filter to be removed by
stream job?

Hmm, yes, such use-case is broken with our proposed way...



Let me now clarify the problem we'll have with your way.

When stream don't have any filter, we can easily imagine two parallel
stream jobs:

top -(backing)-> mid1 -(backing)-> mid2 -(backing)-> base

stream1: top=top, base=mid2
stream2: top=mid2, base=NULL

final picture is obvious:

top (merged with mid1) -(backing)-> mid2 (merged with base)


Yes, and I don’t think this currently working case is broken by this 
series.



But we want stream job has own filter, like mirror.


Which it does not have yet, right?  Which is why I was saying that I
don’t think this is a problem with this series.  We could try to address
it later.

Or do you think we can’t address it later because right now all filter
cases are broken anyway so now would be the time to make a breaking
change (which the suggestion to not use @base as the final backing 
node is)?


I think, we can address it later, but it would be good to fit into one 
release cycle with these series, to not make incompatible behavior 
changes later.





So the picture becomes more complex.

Assume stream2 starts first.

top -(backing)-> mid1 -(backing)-> stream2-filter -(backing)-> mid2
-(backing)-> base


stream2-filter would be on top of mid2, right?


Right. In my picture, "-(backing)->" means backing link. Hmm, most 
probably stream-filter 

Re: [PATCH 09/41] sifive_e: Rename memmap enum constants

[Alistair Francis]

On Thu, Aug 13, 2020 at 3:28 PM Eduardo Habkost  wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros.  This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  include/hw/riscv/sifive_e.h | 38 -
>  hw/riscv/sifive_e.c | 82 ++---
>  2 files changed, 60 insertions(+), 60 deletions(-)
>
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 637414130b..7c2eb70189 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -53,25 +53,25 @@ typedef struct SiFiveEState {
>  OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
>
>  enum {
> -SIFIVE_E_DEBUG,
> -SIFIVE_E_MROM,
> -SIFIVE_E_OTP,
> -SIFIVE_E_CLINT,
> -SIFIVE_E_PLIC,
> -SIFIVE_E_AON,
> -SIFIVE_E_PRCI,
> -SIFIVE_E_OTP_CTRL,
> -SIFIVE_E_GPIO0,
> -SIFIVE_E_UART0,
> -SIFIVE_E_QSPI0,
> -SIFIVE_E_PWM0,
> -SIFIVE_E_UART1,
> -SIFIVE_E_QSPI1,
> -SIFIVE_E_PWM1,
> -SIFIVE_E_QSPI2,
> -SIFIVE_E_PWM2,
> -SIFIVE_E_XIP,
> -SIFIVE_E_DTIM
> +SIFIVE_E_DEV_DEBUG,
> +SIFIVE_E_DEV_MROM,
> +SIFIVE_E_DEV_OTP,
> +SIFIVE_E_DEV_CLINT,
> +SIFIVE_E_DEV_PLIC,
> +SIFIVE_E_DEV_AON,
> +SIFIVE_E_DEV_PRCI,
> +SIFIVE_E_DEV_OTP_CTRL,
> +SIFIVE_E_DEV_GPIO0,
> +SIFIVE_E_DEV_UART0,
> +SIFIVE_E_DEV_QSPI0,
> +SIFIVE_E_DEV_PWM0,
> +SIFIVE_E_DEV_UART1,
> +SIFIVE_E_DEV_QSPI1,
> +SIFIVE_E_DEV_PWM1,
> +SIFIVE_E_DEV_QSPI2,
> +SIFIVE_E_DEV_PWM2,
> +SIFIVE_E_DEV_XIP,
> +SIFIVE_E_DEV_DTIM
>  };
>
>  enum {
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index c8b060486a..88b4524117 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -54,25 +54,25 @@ static const struct MemmapEntry {
>  hwaddr base;
>  hwaddr size;
>  } sifive_e_memmap[] = {
> -[SIFIVE_E_DEBUG] ={0x0, 0x1000 },
> -[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> -[SIFIVE_E_OTP] =  {0x2, 0x2000 },
> -[SIFIVE_E_CLINT] ={  0x200,0x1 },
> -[SIFIVE_E_PLIC] = {  0xc00,  0x400 },
> -[SIFIVE_E_AON] =  { 0x1000, 0x8000 },
> -[SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
> -[SIFIVE_E_OTP_CTRL] = { 0x1001, 0x1000 },
> -[SIFIVE_E_GPIO0] ={ 0x10012000, 0x1000 },
> -[SIFIVE_E_UART0] ={ 0x10013000, 0x1000 },
> -[SIFIVE_E_QSPI0] ={ 0x10014000, 0x1000 },
> -[SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
> -[SIFIVE_E_UART1] ={ 0x10023000, 0x1000 },
> -[SIFIVE_E_QSPI1] ={ 0x10024000, 0x1000 },
> -[SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
> -[SIFIVE_E_QSPI2] ={ 0x10034000, 0x1000 },
> -[SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
> -[SIFIVE_E_XIP] =  { 0x2000, 0x2000 },
> -[SIFIVE_E_DTIM] = { 0x8000, 0x4000 }
> +[SIFIVE_E_DEV_DEBUG] ={0x0, 0x1000 },
> +[SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
> +[SIFIVE_E_DEV_OTP] =  {0x2, 0x2000 },
> +[SIFIVE_E_DEV_CLINT] ={  0x200,0x1 },
> +[SIFIVE_E_DEV_PLIC] = {  0xc00,  0x400 },
> +[SIFIVE_E_DEV_AON] =  { 0x1000, 0x8000 },
> +[SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
> +[SIFIVE_E_DEV_OTP_CTRL] = { 0x1001, 0x1000 },
> +[SIFIVE_E_DEV_GPIO0] ={ 0x10012000, 0x1000 },
> +[SIFIVE_E_DEV_UART0] ={ 0x10013000, 0x1000 },
> +[SIFIVE_E_DEV_QSPI0] ={ 0x10014000, 0x1000 },
> +[SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
> +[SIFIVE_E_DEV_UART1] ={ 0x10023000, 0x1000 },
> +[SIFIVE_E_DEV_QSPI1] ={ 0x10024000, 0x1000 },
> +[SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
> +[SIFIVE_E_DEV_QSPI2] ={ 0x10034000, 0x1000 },
> +[SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
> +[SIFIVE_E_DEV_XIP] =  { 0x2000, 0x2000 },
> +[SIFIVE_E_DEV_DTIM] = { 0x8000, 0x4000 }
>  };
>
>  static void sifive_e_machine_init(MachineState *machine)
> @@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine)
>
>  /* Data Tightly Integrated Memory */
>  memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> -memmap[SIFIVE_E_DTIM].size, _fatal);
> +memmap[SIFIVE_E_DEV_DTIM].size, _fatal);
>  memory_region_add_subregion(sys_mem,
> -memmap[SIFIVE_E_DTIM].base, main_mem);
> +memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
>
>  /* Mask ROM reset vector */
>  uint32_t reset_vec[4];
> @@ -111,7 +111,7 @@ static void 

Re: [PATCH 10/41] sifive_u: Rename memmap enum constants

[Alistair Francis]

On Thu, Aug 13, 2020 at 3:37 PM Eduardo Habkost  wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros.  This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  include/hw/riscv/sifive_u.h |  30 
>  hw/riscv/sifive_u.c | 136 ++--
>  2 files changed, 83 insertions(+), 83 deletions(-)
>
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index aba4d0181f..0dab922f3a 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -68,21 +68,21 @@ typedef struct SiFiveUState {
>  } SiFiveUState;
>
>  enum {
> -SIFIVE_U_DEBUG,
> -SIFIVE_U_MROM,
> -SIFIVE_U_CLINT,
> -SIFIVE_U_L2LIM,
> -SIFIVE_U_PLIC,
> -SIFIVE_U_PRCI,
> -SIFIVE_U_UART0,
> -SIFIVE_U_UART1,
> -SIFIVE_U_GPIO,
> -SIFIVE_U_OTP,
> -SIFIVE_U_DMC,
> -SIFIVE_U_FLASH0,
> -SIFIVE_U_DRAM,
> -SIFIVE_U_GEM,
> -SIFIVE_U_GEM_MGMT
> +SIFIVE_U_DEV_DEBUG,
> +SIFIVE_U_DEV_MROM,
> +SIFIVE_U_DEV_CLINT,
> +SIFIVE_U_DEV_L2LIM,
> +SIFIVE_U_DEV_PLIC,
> +SIFIVE_U_DEV_PRCI,
> +SIFIVE_U_DEV_UART0,
> +SIFIVE_U_DEV_UART1,
> +SIFIVE_U_DEV_GPIO,
> +SIFIVE_U_DEV_OTP,
> +SIFIVE_U_DEV_DMC,
> +SIFIVE_U_DEV_FLASH0,
> +SIFIVE_U_DEV_DRAM,
> +SIFIVE_U_DEV_GEM,
> +SIFIVE_U_DEV_GEM_MGMT
>  };
>
>  enum {
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index e5682c38a9..0dfbcb5160 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -69,21 +69,21 @@ static const struct MemmapEntry {
>  hwaddr base;
>  hwaddr size;
>  } sifive_u_memmap[] = {
> -[SIFIVE_U_DEBUG] ={0x0,  0x100 },
> -[SIFIVE_U_MROM] = { 0x1000, 0xf000 },
> -[SIFIVE_U_CLINT] ={  0x200,0x1 },
> -[SIFIVE_U_L2LIM] ={  0x800,  0x200 },
> -[SIFIVE_U_PLIC] = {  0xc00,  0x400 },
> -[SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
> -[SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
> -[SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
> -[SIFIVE_U_GPIO] = { 0x1006, 0x1000 },
> -[SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
> -[SIFIVE_U_GEM] =  { 0x1009, 0x2000 },
> -[SIFIVE_U_GEM_MGMT] = { 0x100a, 0x1000 },
> -[SIFIVE_U_DMC] =  { 0x100b,0x1 },
> -[SIFIVE_U_FLASH0] =   { 0x2000, 0x1000 },
> -[SIFIVE_U_DRAM] = { 0x8000,0x0 },
> +[SIFIVE_U_DEV_DEBUG] ={0x0,  0x100 },
> +[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
> +[SIFIVE_U_DEV_CLINT] ={  0x200,0x1 },
> +[SIFIVE_U_DEV_L2LIM] ={  0x800,  0x200 },
> +[SIFIVE_U_DEV_PLIC] = {  0xc00,  0x400 },
> +[SIFIVE_U_DEV_PRCI] = { 0x1000, 0x1000 },
> +[SIFIVE_U_DEV_UART0] ={ 0x1001, 0x1000 },
> +[SIFIVE_U_DEV_UART1] ={ 0x10011000, 0x1000 },
> +[SIFIVE_U_DEV_GPIO] = { 0x1006, 0x1000 },
> +[SIFIVE_U_DEV_OTP] =  { 0x1007, 0x1000 },
> +[SIFIVE_U_DEV_GEM] =  { 0x1009, 0x2000 },
> +[SIFIVE_U_DEV_GEM_MGMT] = { 0x100a, 0x1000 },
> +[SIFIVE_U_DEV_DMC] =  { 0x100b,0x1 },
> +[SIFIVE_U_DEV_FLASH0] =   { 0x2000, 0x1000 },
> +[SIFIVE_U_DEV_DRAM] = { 0x8000,0x0 },
>  };
>
>  #define OTP_SERIAL  1
> @@ -142,10 +142,10 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  g_free(nodename);
>
>  nodename = g_strdup_printf("/memory@%lx",
> -(long)memmap[SIFIVE_U_DRAM].base);
> +(long)memmap[SIFIVE_U_DEV_DRAM].base);
>  qemu_fdt_add_subnode(fdt, nodename);
>  qemu_fdt_setprop_cells(fdt, nodename, "reg",
> -memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
> +memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
>  mem_size >> 32, mem_size);
>  qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
>  g_free(nodename);
> @@ -200,39 +200,39 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  g_free(nodename);
>  }
>  nodename = g_strdup_printf("/soc/clint@%lx",
> -(long)memmap[SIFIVE_U_CLINT].base);
> +(long)memmap[SIFIVE_U_DEV_CLINT].base);
>  qemu_fdt_add_subnode(fdt, nodename);
>  qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
>  qemu_fdt_setprop_cells(fdt, nodename, "reg",
> -0x0, memmap[SIFIVE_U_CLINT].base,
> -0x0, memmap[SIFIVE_U_CLINT].size);
> +0x0, memmap[SIFIVE_U_DEV_CLINT].base,
> +0x0, 

Re: [PATCH v9 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

[Francisco Iglesias]

On Wed, Aug 12, 2020 at 05:31:05PM -0700, Vikram Garhwal wrote:
> The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
> implementation. Bus connection and socketCAN connection for each CAN module
> can be set through command lines.
> 
> Example for using single CAN:
> -object can-bus,id=canbus0 \
> -machine xlnx-zcu102.canbus0=canbus0 \
> -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0
> 
> Example for connecting both CAN to same virtual CAN on host machine:
> -object can-bus,id=canbus0 -object can-bus,id=canbus1 \
> -machine xlnx-zcu102.canbus0=canbus0 \
> -machine xlnx-zcu102.canbus1=canbus1 \
> -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \
> -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1
> 
> To create virtual CAN on the host machine, please check the QEMU CAN docs:
> https://github.com/qemu/qemu/blob/master/docs/can.txt
> 
> Signed-off-by: Vikram Garhwal 

Reviewed-by: Francisco Iglesias 

> ---
>  hw/net/can/Makefile.objs |1 +
>  hw/net/can/xlnx-zynqmp-can.c | 1165 
> ++
>  include/hw/net/xlnx-zynqmp-can.h |   78 +++
>  3 files changed, 1244 insertions(+)
>  create mode 100644 hw/net/can/xlnx-zynqmp-can.c
>  create mode 100644 include/hw/net/xlnx-zynqmp-can.h
> 
> diff --git a/hw/net/can/Makefile.objs b/hw/net/can/Makefile.objs
> index 9f0c4ee..0fe87dd 100644
> --- a/hw/net/can/Makefile.objs
> +++ b/hw/net/can/Makefile.objs
> @@ -2,3 +2,4 @@ common-obj-$(CONFIG_CAN_SJA1000) += can_sja1000.o
>  common-obj-$(CONFIG_CAN_PCI) += can_kvaser_pci.o
>  common-obj-$(CONFIG_CAN_PCI) += can_pcm3680_pci.o
>  common-obj-$(CONFIG_CAN_PCI) += can_mioe3680_pci.o
> +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-can.o
> diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
> new file mode 100644
> index 000..367230c
> --- /dev/null
> +++ b/hw/net/can/xlnx-zynqmp-can.c
> @@ -0,0 +1,1165 @@
> +/*
> + * QEMU model of the Xilinx ZynqMP CAN controller.
> + * This implementation is based on the following datasheet:
> + * 
> https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
> + *
> + * Copyright (c) 2020 Xilinx Inc.
> + *
> + * Written-by: Vikram Garhwal
> + *
> + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
> + * Pavel Pisa
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +#include "hw/irq.h"
> +#include "qapi/error.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "qemu/cutils.h"
> +#include "sysemu/sysemu.h"
> +#include "migration/vmstate.h"
> +#include "hw/qdev-properties.h"
> +#include "net/can_emu.h"
> +#include "net/can_host.h"
> +#include "qemu/event_notifier.h"
> +#include "qom/object_interfaces.h"
> +#include "hw/net/xlnx-zynqmp-can.h"
> +
> +#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG
> +#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT(dev, ...) do { \
> +if (XLNX_ZYNQMP_CAN_ERR_DEBUG) { \
> +g_autofree char *path = object_get_canonical_path(OBJECT(dev)); \
> +qemu_log("%s: %s", path, ## __VA_ARGS__); \
> +} \
> +} while (0)
> +
> +#define MAX_DLC8
> +#undef ERROR
> +
> +REG32(SOFTWARE_RESET_REGISTER, 0x0)
> +FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
> +FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
> +REG32(MODE_SELECT_REGISTER, 0x4)
> +FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
> +FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
> +FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
> +REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
> +FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
> +REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
> +FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2)
> +   

[PULL v2 11/20] roms/opensbi: Upgrade from v0.7 to v0.8

[Alistair Francis]

From: Bin Meng 

Upgrade OpenSBI from v0.7 to v0.8.

The v0.8 release includes the following commits:

1bb00ab lib: No need to provide default PMP region using platform callbacks
a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback
6585fab lib: utils: Add SiFive test device
4781545 platform: Add Nuclei UX600 platform
3a326af scripts: adapt binary archive script for Nuclei UX600
5bdf022 firmware: fw_base: Remove CSR_MTVEC update check
e6c1345 lib: utils/serial: Skip baudrate config if input frequency is zero
01a8c8e lib: utils: Improve fdt_parse_uart8250() API
0a0093b lib: utils: Add fdt_parse_uart8250_node() function
243b0d0 lib: utils: Remove redundant clint_ipi_sync() declaration
e3ad7c1 lib: utils: Rename fdt_parse_clint() to fdt_parse_compat_addr()
a39cd6f lib: utils: Add FDT match table based node lookup
dd33b9e lib: utils: Make fdt_get_node_addr_size() public function
66185b3 lib: utils: Add fdt_parse_sifive_uart_node() function
19e966b lib: utils: Add fdt_parse_hart_id() function
44dd7be lib: utils: Add fdt_parse_max_hart_id() API
f0eb503 lib: utils: Add fdt_parse_plic_node() function
1ac794c include: Add array_size() macro
8ff2b94 lib: utils: Add simple FDT timer framework
76f0f81 lib: utils: Add simple FDT ipi framework
75322a6 lib: utils: Add simple FDT irqchip framework
76a8940 lib: utils: Add simple FDT serial framework
7cc6fa4 lib: utils: Add simple FDT reset framework
4d06353 firmware: fw_base: Introduce optional fw_platform_init()
f1aa9e5 platform: Add generic FDT based platform support
1f21b99 lib: sbi: Print platform hart count at boot time
2ba7087 scripts: Add generic platform to create-binary-archive.sh
4f18c6e platform: generic: Add Sifive FU540 TLB flush range limit override
13717a8 platform: Remove qemu/virt directory
65c06b0 platform: Remove spike directory
d626037 docs: Add missing links in platform.md
7993ca2 include: sbi: Remove redundant page table related defines
5338679 lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation
dc38929 lib: sbi: Improve misa_string() implementation
433bac7 docs: platform/generic: Add details about stdout-path DT property
b4efa70 docs: platform/generic: Add details about IPI and timer expectations
dfd9dd6 docs: Add platform requirements document
c2286b6 docs: Fix ordering of pages in table of contents
7be75f5 docs: Don't use italic text in page title
63a513e lib: Rename unprivileged trap handler
aef9a60 lib: Add csr detect support
13ca20d lib: Create a separate math helper function file
79d0fad lib: utils: Update reserved memory fdt node even if PMP is not present
6a053f6 lib: Add support for hart specific features
b2df751 platform: Move platform features to hart
4938024 platform: fpga: Remove redundant platform specific features
ec0d2a7 lib: timer: Provide a hart based timer feature
1f235ec lib: Add platform features in boot time print
22c4334 lib: Add hart features in boot time print
36833ab lib: Optimize inline assembly for unprivilege access functions
38a4b54 firmware: Correct spelling mistakes
28b4052 lib: sbi: detect features before everything else in sbi_hart_init()
4984183 lib: sbi: Improve get_feature_str() implementation and usage
3aa1036 lib: sbi: Remove extra spaces from boot time prints
3a8fc81 lib: sbi: Print platform HART count just before boot HART id
63b0f5f include: sbi: Use scratch pointer as parmeter in HART feature APIs
2966510 lib: sbi: Few cosmetic improvements to HART feature detection
a38bea9 lib: sbi_hart: Detect number of supported PMP regions
89ba634 include: sbi: Add firmware extension constants
73d6ef3 lib: utils: Remove redundant parameters from PLIC init functions
446a9c6 lib: utils: Allow PLIC functions to be used for multiple PLICs
2c685c2 lib: utils: Extend fdt_find_match() Implementation
d30bb68 lib: utils/irqchip: Initialize all matching irqchip DT nodes
a9a9751 lib: utils: Allow CLINT functions to be used for multiple CLINTs
569dd64 lib: utils: Add fdt_parse_clint_node() function
6956e83 lib: utils/ipi: Initialize all matching ipi DT nodes
a63f05f lib: utils/timer: Initialize all matching timer DT nodes
30b6040 Makefile: Fix builtin DTB compilation for out-of-tree platforms
64f1408 firmware: fw_base: Make builtin DTB available to fw_platform_init()
4ce6b7a firmware: fw_base: Don't OR forced FW_OPTIONS
86ec534 firmware: Allow fw_platform_init() to return updated FDT location
c6c65ee Makefile: Preprocess builtin DTS
4e3876d Makefile: Add mechanism for platforms to have multiple builtin DTBs
72019ee platform: kendryte/k210: Use new mechanism of builtin DTB
51f0e4a firmware: Remove FW_PAYLOAD_FDT and related documentation
1b8c012 lib: Add RISC-V hypervisor v0.6.1 support
79bfd67 docs: Use doxygen config to mark the main page
106b888 docs: Remove redundant documentation about combined payload use case
9802906 platform: Add AE350 platform specific SBI handler
32f87e5 platform: Add AE350 cache control SBIs
e2c3f01 lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()
6966ad0 

[PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines

[Alistair Francis]

Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.

Signed-off-by: Alistair Francis 
Message-Id: 
<394c3f070615ff2b4fab61a1cf9cb48c122913b7.1595655188.git.alistair.fran...@wdc.com>
---
 include/hw/intc/ibex_plic.h |  1 +
 hw/intc/ibex_plic.c | 17 +
 2 files changed, 18 insertions(+)

diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
index ddc7909903..d8eb09b258 100644
--- a/include/hw/intc/ibex_plic.h
+++ b/include/hw/intc/ibex_plic.h
@@ -33,6 +33,7 @@ typedef struct IbexPlicState {
 MemoryRegion mmio;
 
 uint32_t *pending;
+uint32_t *claimed;
 uint32_t *source;
 uint32_t *priority;
 uint32_t *enable;
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 578edd2ce0..669247ef08 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -43,6 +43,14 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int 
irq, bool level)
 {
 int pending_num = irq / 32;
 
+if (s->claimed[pending_num] & 1 << (irq % 32)) {
+/*
+ * The interrupt has been claimed, but not compelted.
+ * The pending bit can't be set.
+ */
+return;
+}
+
 s->pending[pending_num] |= level << (irq % 32);
 }
 
@@ -120,6 +128,10 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
 int pending_num = s->claim / 32;
 s->pending[pending_num] &= ~(1 << (s->claim % 32));
 
+/* Set the interrupt as claimed, but not compelted */
+s->claimed[pending_num] |= 1 << (s->claim % 32);
+
+/* Return the current claimed interrupt */
 ret = s->claim;
 
 /* Update the interrupt status after the claim */
@@ -155,6 +167,10 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
 /* Interrupt was completed */
 s->claim = 0;
 }
+if (s->claimed[value / 32] & 1 << (value % 32)) {
+/* This value was already claimed, clear it. */
+s->claimed[value / 32] &= ~(1 << (value % 32));
+}
 }
 
 ibex_plic_update(s);
@@ -215,6 +231,7 @@ static void ibex_plic_realize(DeviceState *dev, Error 
**errp)
 int i;
 
 s->pending = g_new0(uint32_t, s->pending_num);
+s->claimed = g_new0(uint32_t, s->pending_num);
 s->source = g_new0(uint32_t, s->source_num);
 s->priority = g_new0(uint32_t, s->priority_num);
 s->enable = g_new0(uint32_t, s->enable_num);
-- 
2.27.0

[PULL v2 10/20] configure: Create symbolic links for pc-bios/*.elf files

[Alistair Francis]

From: Bin Meng 

Now we need to ship the OpenSBI fw_dynamic.elf image for the
RISC-V Spike machine, it requires us to create symbolic links
for pc-bios/*.elf files.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Message-Id: <1596439832-29238-2-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair Francis 
---
 configure | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configure b/configure
index 2acc4d1465..790b21d4a5 100755
--- a/configure
+++ b/configure
@@ -8545,6 +8545,7 @@ LINKS="$LINKS tests/qemu-iotests/check"
 LINKS="$LINKS python"
 for bios_file in \
 $source_path/pc-bios/*.bin \
+$source_path/pc-bios/*.elf \
 $source_path/pc-bios/*.lid \
 $source_path/pc-bios/*.rom \
 $source_path/pc-bios/*.dtb \
-- 
2.27.0

Re: [PATCH] ide:do nothing for identify cmd if no any device attached

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20200814043657.5815-1-rockcui...@zhaoxin.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20200814043657.5815-1-rockcui...@zhaoxin.com
Subject: [PATCH] ide:do nothing for identify cmd if no any device attached

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
c0ee2f5 ide:do nothing for identify cmd if no any device attached

=== OUTPUT BEGIN ===
ERROR: trailing whitespace
#27: FILE: hw/ide/core.c:2077:
+if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || $

ERROR: code indent should never use tabs
#28: FILE: hw/ide/core.c:2078:
+^I(s != bus->ifs && !s->blk)) {$

total: 2 errors, 0 warnings, 11 lines checked

Commit c0ee2f5abbf3 (ide:do nothing for identify cmd if no any device attached) 
has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200814043657.5815-1-rockcui...@zhaoxin.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

[PULL v2 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware

[Alistair Francis]

From: Bin Meng 

The RISC-V generic platform is a flattened device tree (FDT) based
platform where all platform specific functionality is provided based
on FDT passed by previous booting stage. The support was added in
the upstream OpenSBI v0.8 release recently.

Update our Makefile to build the generic platform instead of building
virt and sifive_u separately for RISC-V OpenSBI firmware, and change
to use fw_dynamic type images as well.

Signed-off-by: Bin Meng 
Reviewed-by: Anup Patel 
Reviewed-by: Alistair Francis 
Message-Id: <1596439832-29238-4-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair Francis 
---
 roms/Makefile | 32 ++--
 1 file changed, 10 insertions(+), 22 deletions(-)

diff --git a/roms/Makefile b/roms/Makefile
index f9acf39954..5d9f15b677 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -64,10 +64,8 @@ default help:
@echo "  u-boot.e500-- update u-boot.e500"
@echo "  u-boot.sam460  -- update u-boot.sam460"
@echo "  efi-- update UEFI (edk2) platform firmware"
-   @echo "  opensbi32-virt -- update OpenSBI for 32-bit virt machine"
-   @echo "  opensbi64-virt -- update OpenSBI for 64-bit virt machine"
-   @echo "  opensbi32-sifive_u -- update OpenSBI for 32-bit sifive_u 
machine"
-   @echo "  opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u 
machine"
+   @echo "  opensbi32-generic  -- update OpenSBI for 32-bit generic 
machine"
+   @echo "  opensbi64-generic  -- update OpenSBI for 64-bit generic 
machine"
@echo "  bios-microvm   -- update bios-microvm.bin (qboot)"
@echo "  clean  -- delete the files generated by the 
previous" \
  "build targets"
@@ -170,29 +168,19 @@ skiboot:
 efi: edk2-basetools
$(MAKE) -f Makefile.edk2
 
-opensbi32-virt:
+opensbi32-generic:
$(MAKE) -C opensbi \
CROSS_COMPILE=$(riscv32_cross_prefix) \
-   PLATFORM="qemu/virt"
-   cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin 
../pc-bios/opensbi-riscv32-virt-fw_jump.bin
+   PLATFORM="generic"
+   cp opensbi/build/platform/generic/firmware/fw_dynamic.bin 
../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
+   cp opensbi/build/platform/generic/firmware/fw_dynamic.elf 
../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 
-opensbi64-virt:
+opensbi64-generic:
$(MAKE) -C opensbi \
CROSS_COMPILE=$(riscv64_cross_prefix) \
-   PLATFORM="qemu/virt"
-   cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin 
../pc-bios/opensbi-riscv64-virt-fw_jump.bin
-
-opensbi32-sifive_u:
-   $(MAKE) -C opensbi \
-   CROSS_COMPILE=$(riscv32_cross_prefix) \
-   PLATFORM="sifive/fu540"
-   cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin 
../pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
-
-opensbi64-sifive_u:
-   $(MAKE) -C opensbi \
-   CROSS_COMPILE=$(riscv64_cross_prefix) \
-   PLATFORM="sifive/fu540"
-   cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin 
../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
+   PLATFORM="generic"
+   cp opensbi/build/platform/generic/firmware/fw_dynamic.bin 
../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
+   cp opensbi/build/platform/generic/firmware/fw_dynamic.elf 
../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
 
 bios-microvm:
$(MAKE) -C qboot
-- 
2.27.0

[PULL v2 18/20] hw/intc: ibex_plic: Update the pending irqs

[Alistair Francis]

After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"

Signed-off-by: Alistair Francis 
Cc: Jessica Clarke 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: 
<0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.fran...@wdc.com>
---
 hw/intc/ibex_plic.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 41079518c6..578edd2ce0 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
 s->pending[pending_num] &= ~(1 << (s->claim % 32));
 
 ret = s->claim;
+
+/* Update the interrupt status after the claim */
+ibex_plic_update(s);
 }
 
 return ret;
@@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
 } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
 s->priority[irq] = value & 7;
+ibex_plic_update(s);
 } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 uint32_t enable_reg = (addr - s->enable_base) / 4;
 
-- 
2.27.0

Re: [PATCH 08/41] opentitan: Rename memmap enum constants

[Alistair Francis]

On Thu, Aug 13, 2020 at 3:29 PM Eduardo Habkost  wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros.  This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants to IBEX_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  include/hw/riscv/opentitan.h | 38 
>  hw/riscv/opentitan.c | 84 ++--
>  2 files changed, 61 insertions(+), 61 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 8f29b9cbbf..835a80f896 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -49,25 +49,25 @@ typedef struct OpenTitanState {
>  } OpenTitanState;
>
>  enum {
> -IBEX_ROM,
> -IBEX_RAM,
> -IBEX_FLASH,
> -IBEX_UART,
> -IBEX_GPIO,
> -IBEX_SPI,
> -IBEX_FLASH_CTRL,
> -IBEX_RV_TIMER,
> -IBEX_AES,
> -IBEX_HMAC,
> -IBEX_PLIC,
> -IBEX_PWRMGR,
> -IBEX_RSTMGR,
> -IBEX_CLKMGR,
> -IBEX_PINMUX,
> -IBEX_ALERT_HANDLER,
> -IBEX_NMI_GEN,
> -IBEX_USBDEV,
> -IBEX_PADCTRL,
> +IBEX_DEV_ROM,
> +IBEX_DEV_RAM,
> +IBEX_DEV_FLASH,
> +IBEX_DEV_UART,
> +IBEX_DEV_GPIO,
> +IBEX_DEV_SPI,
> +IBEX_DEV_FLASH_CTRL,
> +IBEX_DEV_RV_TIMER,
> +IBEX_DEV_AES,
> +IBEX_DEV_HMAC,
> +IBEX_DEV_PLIC,
> +IBEX_DEV_PWRMGR,
> +IBEX_DEV_RSTMGR,
> +IBEX_DEV_CLKMGR,
> +IBEX_DEV_PINMUX,
> +IBEX_DEV_ALERT_HANDLER,
> +IBEX_DEV_NMI_GEN,
> +IBEX_DEV_USBDEV,
> +IBEX_DEV_PADCTRL,
>  };
>
>  enum {
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index a8f0039e51..23ba3b4bfc 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -32,25 +32,25 @@ static const struct MemmapEntry {
>  hwaddr base;
>  hwaddr size;
>  } ibex_memmap[] = {
> -[IBEX_ROM] ={  0x8000, 16 * KiB },
> -[IBEX_RAM] ={  0x1000,  0x1 },
> -[IBEX_FLASH] =  {  0x2000,  0x8 },
> -[IBEX_UART] =   {  0x4000,  0x1 },
> -[IBEX_GPIO] =   {  0x4001,  0x1 },
> -[IBEX_SPI] ={  0x4002,  0x1 },
> -[IBEX_FLASH_CTRL] = {  0x4003,  0x1 },
> -[IBEX_PINMUX] = {  0x4007,  0x1 },
> -[IBEX_RV_TIMER] =   {  0x4008,  0x1 },
> -[IBEX_PLIC] =   {  0x4009,  0x1 },
> -[IBEX_PWRMGR] = {  0x400A,  0x1 },
> -[IBEX_RSTMGR] = {  0x400B,  0x1 },
> -[IBEX_CLKMGR] = {  0x400C,  0x1 },
> -[IBEX_AES] ={  0x4011,  0x1 },
> -[IBEX_HMAC] =   {  0x4012,  0x1 },
> -[IBEX_ALERT_HANDLER] =  {  0x4013,  0x1 },
> -[IBEX_NMI_GEN] ={  0x4014,  0x1 },
> -[IBEX_USBDEV] = {  0x4015,  0x1 },
> -[IBEX_PADCTRL] ={  0x4016,  0x1 }
> +[IBEX_DEV_ROM] ={  0x8000, 16 * KiB },
> +[IBEX_DEV_RAM] ={  0x1000,  0x1 },
> +[IBEX_DEV_FLASH] =  {  0x2000,  0x8 },
> +[IBEX_DEV_UART] =   {  0x4000,  0x1 },
> +[IBEX_DEV_GPIO] =   {  0x4001,  0x1 },
> +[IBEX_DEV_SPI] ={  0x4002,  0x1 },
> +[IBEX_DEV_FLASH_CTRL] = {  0x4003,  0x1 },
> +[IBEX_DEV_PINMUX] = {  0x4007,  0x1 },
> +[IBEX_DEV_RV_TIMER] =   {  0x4008,  0x1 },
> +[IBEX_DEV_PLIC] =   {  0x4009,  0x1 },
> +[IBEX_DEV_PWRMGR] = {  0x400A,  0x1 },
> +[IBEX_DEV_RSTMGR] = {  0x400B,  0x1 },
> +[IBEX_DEV_CLKMGR] = {  0x400C,  0x1 },
> +[IBEX_DEV_AES] ={  0x4011,  0x1 },
> +[IBEX_DEV_HMAC] =   {  0x4012,  0x1 },
> +[IBEX_DEV_ALERT_HANDLER] =  {  0x4013,  0x1 },
> +[IBEX_DEV_NMI_GEN] ={  0x4014,  0x1 },
> +[IBEX_DEV_USBDEV] = {  0x4015,  0x1 },
> +[IBEX_DEV_PADCTRL] ={  0x4016,  0x1 }
>  };
>
>  static void opentitan_board_init(MachineState *machine)
> @@ -66,12 +66,12 @@ static void opentitan_board_init(MachineState *machine)
>  qdev_realize(DEVICE(>soc), NULL, _abort);
>
>  memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
> -memmap[IBEX_RAM].size, _fatal);
> +memmap[IBEX_DEV_RAM].size, _fatal);
>  memory_region_add_subregion(sys_mem,
> -memmap[IBEX_RAM].base, main_mem);
> +memmap[IBEX_DEV_RAM].base, main_mem);
>
>  if (machine->firmware) {
> -riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
> +riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, 
> NULL);
>  }
>
>  if 

[PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64

[Alistair Francis]

From: Hou Weiying 

First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.

If the parameter reg_index equals to 2 (means that we will change the
value of pmpcfg2, or the second pmpcfg on riscv64), then
pmpcfg_csr_write(env, 2, val) will map write tasks to
pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed
by value 16 or 23 on riscv64, so we consider it as a bug.

We are looking for constant (e.g., define a new constant named
RISCV_WORD_SIZE) in QEMU to help others understand code better,
but none was found. A possible good explanation of this literal is it is
the minimum word length on riscv is 4 bytes (32 bit).

Signed-off-by: Hongzheng-Li 
Signed-off-by: Hou Weiying 
Signed-off-by: Myriad-Dreamin 
Reviewed-by: Alistair Francis 
Message-Id: 

Signed-off-by: Alistair Francis 
---
 target/riscv/pmp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2a2b9f5363..b14feeb7da 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -320,8 +320,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t 
reg_index,
 
 for (i = 0; i < sizeof(target_ulong); i++) {
 cfg_val = (val >> 8 * i)  & 0xff;
-pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
-cfg_val);
+pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
 }
 }
 
@@ -336,7 +335,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t 
reg_index)
 target_ulong val = 0;
 
 for (i = 0; i < sizeof(target_ulong); i++) {
-val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
+val = pmp_read_cfg(env, (reg_index * 4) + i);
 cfg_val |= (val << (i * 8));
 }
 trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
-- 
2.27.0

[PULL v2 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device

[Alistair Francis]

From: Bin Meng 

It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Message-Id: <1595227748-24720-1-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair Francis 
---
 include/hw/riscv/sifive_u.h |  4 
 hw/riscv/sifive_u.c | 22 ++
 2 files changed, 26 insertions(+)

diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index aba4d0181f..d3c0c00d10 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -71,6 +71,7 @@ enum {
 SIFIVE_U_DEBUG,
 SIFIVE_U_MROM,
 SIFIVE_U_CLINT,
+SIFIVE_U_L2CC,
 SIFIVE_U_L2LIM,
 SIFIVE_U_PLIC,
 SIFIVE_U_PRCI,
@@ -86,6 +87,9 @@ enum {
 };
 
 enum {
+SIFIVE_U_L2CC_IRQ0 = 1,
+SIFIVE_U_L2CC_IRQ1 = 2,
+SIFIVE_U_L2CC_IRQ2 = 3,
 SIFIVE_U_UART0_IRQ = 4,
 SIFIVE_U_UART1_IRQ = 5,
 SIFIVE_U_GPIO_IRQ0 = 7,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e5682c38a9..55b3383c31 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -72,6 +72,7 @@ static const struct MemmapEntry {
 [SIFIVE_U_DEBUG] ={0x0,  0x100 },
 [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
 [SIFIVE_U_CLINT] ={  0x200,0x1 },
+[SIFIVE_U_L2CC] = {  0x201, 0x1000 },
 [SIFIVE_U_L2LIM] ={  0x800,  0x200 },
 [SIFIVE_U_PLIC] = {  0xc00,  0x400 },
 [SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
@@ -302,6 +303,24 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
 g_free(nodename);
 
+nodename = g_strdup_printf("/soc/cache-controller@%lx",
+(long)memmap[SIFIVE_U_L2CC].base);
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cells(fdt, nodename, "reg",
+0x0, memmap[SIFIVE_U_L2CC].base,
+0x0, memmap[SIFIVE_U_L2CC].size);
+qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
+qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
+qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
+qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
+qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
+qemu_fdt_setprop_string(fdt, nodename, "compatible",
+"sifive,fu540-c000-ccache");
+g_free(nodename);
+
 phy_phandle = phandle++;
 nodename = g_strdup_printf("/soc/ethernet@%lx",
 (long)memmap[SIFIVE_U_GEM].base);
@@ -733,6 +752,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error 
**errp)
 
 create_unimplemented_device("riscv.sifive.u.dmc",
 memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+
+create_unimplemented_device("riscv.sifive.u.l2cc",
+memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
 }
 
 static Property sifive_u_soc_props[] = {
-- 
2.27.0

[PULL v2 06/20] target/riscv: Clean up fmv.w.x

[Alistair Francis]

From: LIU Zhiwei 

Use tcg_gen_extu_tl_i64 to avoid the ifdef.

Signed-off-by: LIU Zhiwei 
Signed-off-by: Richard Henderson 
Message-Id: <20200626205917.4545-7-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson 
Message-Id: <20200724002807.441147-7-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvf.inc.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvf.inc.c 
b/target/riscv/insn_trans/trans_rvf.inc.c
index 832f01db6f..138e317723 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x 
*a)
 TCGv t0 = tcg_temp_new();
 gen_get_gpr(t0, a->rs1);
 
-#if defined(TARGET_RISCV64)
-tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
-#else
-tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
-#endif
+tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
 gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
 
 mark_fs_dirty(ctx);
-- 
2.27.0

Re: [PATCH] hw/net/xilinx_axienet: Remove unused code

[Alistair Francis]

On Fri, Aug 14, 2020 at 6:30 AM Philippe Mathieu-Daudé  wrote:
>
> Most of the MDIOBus fields are unused.  The ADVERTISE_10HALF
> definition is unused.  Remove unused code.
>
> Signed-off-by: Philippe Mathieu-Daudé 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  hw/net/xilinx_axienet.c | 23 ---
>  1 file changed, 23 deletions(-)
>
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 1e48eb70c9..2e89f236b4 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -54,7 +54,6 @@
>   TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
>
>  /* Advertisement control register. */
> -#define ADVERTISE_10HALF0x0020  /* Try for 10mbps half-duplex  */
>  #define ADVERTISE_10FULL0x0040  /* Try for 10mbps full-duplex  */
>  #define ADVERTISE_100HALF   0x0080  /* Try for 100mbps half-duplex */
>  #define ADVERTISE_100FULL   0x0100  /* Try for 100mbps full-duplex */
> @@ -169,28 +168,6 @@ tdk_init(struct PHY *phy)
>  }
>
>  struct MDIOBus {
> -/* bus.  */
> -int mdc;
> -int mdio;
> -
> -/* decoder.  */
> -enum {
> -PREAMBLE,
> -SOF,
> -OPC,
> -ADDR,
> -REQ,
> -TURNAROUND,
> -DATA
> -} state;
> -unsigned int drive;
> -
> -unsigned int cnt;
> -unsigned int addr;
> -unsigned int opc;
> -unsigned int req;
> -unsigned int data;
> -
>  struct PHY *devs[32];
>  };
>
> --
> 2.21.3
>
>

[PULL v2 20/20] hw/intc: ibex_plic: Honour source priorities

[Alistair Francis]

This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.

Signed-off-by: Alistair Francis 
Cc: Jessica Clarke 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: 

---
 hw/intc/ibex_plic.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 669247ef08..f49fa67c91 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -57,6 +57,8 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int 
irq, bool level)
 static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
 {
 int i;
+uint32_t max_irq = 0;
+uint32_t max_prio = s->threshold;
 
 for (i = 0; i < s->pending_num; i++) {
 uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
@@ -66,14 +68,17 @@ static bool ibex_plic_irqs_pending(IbexPlicState *s, 
uint32_t context)
 continue;
 }
 
-if (s->priority[irq_num] > s->threshold) {
-if (!s->claim) {
-s->claim = irq_num;
-}
-return true;
+if (s->priority[irq_num] > max_prio) {
+max_irq = irq_num;
+max_prio = s->priority[irq_num];
 }
 }
 
+if (max_irq) {
+s->claim = max_irq;
+return true;
+}
+
 return false;
 }
 
-- 
2.27.0

[PULL v2 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

[Alistair Francis]

From: Richard Henderson 

If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan.  The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.

Signed-off-by: Richard Henderson 
Reviewed-by: LIU Zhiwei 
Message-Id: <20200724002807.441147-6-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvf.inc.c | 71 +++--
 target/riscv/translate.c| 18 +++
 2 files changed, 73 insertions(+), 16 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvf.inc.c 
b/target/riscv/insn_trans/trans_rvf.inc.c
index 264d3139f1..832f01db6f 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -161,47 +161,86 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s 
*a)
 {
 REQUIRE_FPU;
 REQUIRE_EXT(ctx, RVF);
+
 if (a->rs1 == a->rs2) { /* FMOV */
-tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+gen_check_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
 } else { /* FSGNJ */
-tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
-0, 31);
+TCGv_i64 rs1 = tcg_temp_new_i64();
+TCGv_i64 rs2 = tcg_temp_new_i64();
+
+gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
+gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
+
+/* This formulation retains the nanboxing of rs2. */
+tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 31);
+tcg_temp_free_i64(rs1);
+tcg_temp_free_i64(rs2);
 }
-gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
 mark_fs_dirty(ctx);
 return true;
 }
 
 static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
 {
+TCGv_i64 rs1, rs2, mask;
+
 REQUIRE_FPU;
 REQUIRE_EXT(ctx, RVF);
+
+rs1 = tcg_temp_new_i64();
+gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
+
 if (a->rs1 == a->rs2) { /* FNEG */
-tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(31, 1));
 } else {
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
-tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
-tcg_temp_free_i64(t0);
+rs2 = tcg_temp_new_i64();
+gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
+
+/*
+ * Replace bit 31 in rs1 with inverse in rs2.
+ * This formulation retains the nanboxing of rs1.
+ */
+mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1));
+tcg_gen_nor_i64(rs2, rs2, mask);
+tcg_gen_and_i64(rs1, mask, rs1);
+tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2);
+
+tcg_temp_free_i64(mask);
+tcg_temp_free_i64(rs2);
 }
-gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
+tcg_temp_free_i64(rs1);
+
 mark_fs_dirty(ctx);
 return true;
 }
 
 static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
 {
+TCGv_i64 rs1, rs2;
+
 REQUIRE_FPU;
 REQUIRE_EXT(ctx, RVF);
+
+rs1 = tcg_temp_new_i64();
+gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
+
 if (a->rs1 == a->rs2) { /* FABS */
-tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
+tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(31, 1));
 } else {
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
-tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
-tcg_temp_free_i64(t0);
+rs2 = tcg_temp_new_i64();
+gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
+
+/*
+ * Xor bit 31 in rs1 with that in rs2.
+ * This formulation retains the nanboxing of rs1.
+ */
+tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(31, 1));
+tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2);
+
+tcg_temp_free_i64(rs2);
 }
-gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
+tcg_temp_free_i64(rs1);
+
 mark_fs_dirty(ctx);
 return true;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 12a746da97..bf35182776 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -101,6 +101,24 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
 }
 
+/*
+ * A narrow n-bit operation, where n < FLEN, checks that input operands
+ * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
+ * If so, the least-significant bits of the input are used, otherwise the
+ * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
+ *
+ * Here, the result is always nan-boxed, even the canonical nan.
+ */
+static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
+{
+TCGv_i64 t_max = tcg_const_i64(0xull);
+TCGv_i64 t_nan = tcg_const_i64(0x7fc0ull);
+
+tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+  

[PULL v2 17/20] target/riscv: Change the TLB page size depends on PMP entries.

[Alistair Francis]

From: Zong Li 

The minimum granularity of PMP is 4 bytes, it is small than 4KB page
size, therefore, the pmp checking would be ignored if its range doesn't
start from the alignment of one page. This patch detects the pmp entries
and sets the small page size to TLB if there is a PMP entry which cover
the page size.

Signed-off-by: Zong Li 
Reviewed-by: Alistair Francis 
Message-Id: 
<6b0bf48662ef26ab4c15381a08e78a74ebd7ca79.1595924470.git.zong...@sifive.com>
Signed-off-by: Alistair Francis 
---
 target/riscv/pmp.h|  2 ++
 target/riscv/cpu_helper.c | 10 ++--
 target/riscv/pmp.c| 52 +++
 3 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 8e19793132..6a8f072871 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -60,5 +60,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t 
addr_index,
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 target_ulong size, pmp_priv_t priv, target_ulong mode);
+bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+ target_ulong *tlb_size);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2f337e418c..fd1d373b6f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -693,6 +693,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 bool first_stage_error = true;
 int ret = TRANSLATE_FAIL;
 int mode = mmu_idx;
+target_ulong tlb_size = 0;
 
 env->guest_phys_fault_addr = 0;
 
@@ -784,8 +785,13 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 }
 
 if (ret == TRANSLATE_SUCCESS) {
-tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
- prot, mmu_idx, TARGET_PAGE_SIZE);
+if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, _size)) {
+tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+ prot, mmu_idx, tlb_size);
+} else {
+tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
+ prot, mmu_idx, TARGET_PAGE_SIZE);
+}
 return true;
 } else if (probe) {
 return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b14feeb7da..c394e867f8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -383,3 +383,55 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t 
addr_index)
 
 return val;
 }
+
+/*
+ * Calculate the TLB size if the start address or the end address of
+ * PMP entry is presented in thie TLB page.
+ */
+static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
+ target_ulong tlb_sa, target_ulong tlb_ea)
+{
+target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
+target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
+
+if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) {
+return pmp_ea - pmp_sa + 1;
+}
+
+if (pmp_sa >= tlb_sa && pmp_sa <= tlb_ea && pmp_ea >= tlb_ea) {
+return tlb_ea - pmp_sa + 1;
+}
+
+if (pmp_ea <= tlb_ea && pmp_ea >= tlb_sa && pmp_sa <= tlb_sa) {
+return pmp_ea - tlb_sa + 1;
+}
+
+return 0;
+}
+
+/*
+ * Check is there a PMP entry which range covers this page. If so,
+ * try to find the minimum granularity for the TLB size.
+ */
+bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+ target_ulong *tlb_size)
+{
+int i;
+target_ulong val;
+target_ulong tlb_ea = (tlb_sa + TARGET_PAGE_SIZE - 1);
+
+for (i = 0; i < MAX_RISCV_PMPS; i++) {
+val = pmp_get_tlb_size(env, i, tlb_sa, tlb_ea);
+if (val) {
+if (*tlb_size == 0 || *tlb_size > val) {
+*tlb_size = val;
+}
+}
+}
+
+if (*tlb_size != 0) {
+return true;
+}
+
+return false;
+}
-- 
2.27.0

[PULL v2 01/20] target/riscv: Generate nanboxed results from fp helpers

[Alistair Francis]

From: Richard Henderson 

Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson 
Reviewed-by: LIU Zhiwei 
Message-Id: <20200724002807.441147-2-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis 
---
 target/riscv/internals.h  |  5 +
 target/riscv/fpu_helper.c | 42 +--
 2 files changed, 28 insertions(+), 19 deletions(-)

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 37d33820ad..9f4ba7d617 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1);
 #define SEW32 2
 #define SEW64 3
 
+static inline uint64_t nanbox_s(float32 f)
+{
+return f | MAKE_64BIT_MASK(32, 32);
+}
+
 #endif
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 4379756dc4..72541958a7 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,10 +81,16 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t 
rm)
 set_float_rounding_mode(softrm, >fp_status);
 }
 
+static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
+   uint64_t frs3, int flags)
+{
+return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, >fp_status));
+}
+
 uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 uint64_t frs3)
 {
-return float32_muladd(frs1, frs2, frs3, 0, >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3, 0);
 }
 
 uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -96,8 +102,7 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, 
uint64_t frs2,
 uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 uint64_t frs3)
 {
-return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c,
-  >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c);
 }
 
 uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -110,8 +115,7 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, 
uint64_t frs2,
 uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
  uint64_t frs3)
 {
-return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product,
-  >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product);
 }
 
 uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -124,8 +128,8 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, 
uint64_t frs2,
 uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
  uint64_t frs3)
 {
-return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c |
-  float_muladd_negate_product, >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3,
+  float_muladd_negate_c | float_muladd_negate_product);
 }
 
 uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -137,37 +141,37 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t 
frs1, uint64_t frs2,
 
 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-return float32_add(frs1, frs2, >fp_status);
+return nanbox_s(float32_add(frs1, frs2, >fp_status));
 }
 
 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-return float32_sub(frs1, frs2, >fp_status);
+return nanbox_s(float32_sub(frs1, frs2, >fp_status));
 }
 
 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-return float32_mul(frs1, frs2, >fp_status);
+return nanbox_s(float32_mul(frs1, frs2, >fp_status));
 }
 
 uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-return float32_div(frs1, frs2, >fp_status);
+return nanbox_s(float32_div(frs1, frs2, >fp_status));
 }
 
 uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-return float32_minnum(frs1, frs2, >fp_status);
+return nanbox_s(float32_minnum(frs1, frs2, >fp_status));
 }
 
 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-return float32_maxnum(frs1, frs2, >fp_status);
+return nanbox_s(float32_maxnum(frs1, frs2, >fp_status));
 }
 
 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
 {
-return float32_sqrt(frs1, >fp_status);
+return nanbox_s(float32_sqrt(frs1, >fp_status));
 }
 
 target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
@@ -209,23 +213,23 @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t 
frs1)
 
 uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
 {
-return int32_to_float32((int32_t)rs1, >fp_status);
+return nanbox_s(int32_to_float32((int32_t)rs1, >fp_status));
 }
 
 uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
 {
-