On Mon, Sep 21, 2020 at 03:10:51PM +0200, Stefan Reiter wrote:
> Hi list,
>
> since SeaBIOS 1.14.0 (QEMU 5.1) VMs with LVM root disks spanning more than
> one PV fail to boot, if only the first is set as bootable. I believe this is
> due to the changes in SeaBIOS only initializing drives marked
Hi, Chen and Lei
Using Lei's patch is OK to me.
Please help to add "Signed-off-by: Derek Su " for merging
it.
Thank you. :)
Regards
Derek
Zhang, Chen 於 2020年9月22日 週二 下午1:37寫道：
> So, Derek, you will send new version patch?
>
>
>
> Thanks
>
> Zhang Chen
>
>
>
> *From:* Derek Su
> *Sent:*
So, Derek, you will send new version patch?
Thanks
Zhang Chen
From: Derek Su
Sent: Tuesday, September 22, 2020 1:18 PM
To: Rao, Lei
Cc: Zhang, Chen ; qemu-devel ;
zhang.zhanghaili...@huawei.com; quint...@redhat.com; dgilb...@redhat.com
Subject: Re: [PATCH v1 1/1] COLO: only flush dirty ram
Hi, Lei
Got it. Thanks.
Regards,
Derek
Rao, Lei 於 2020年9月22日 週二 下午1:04寫道：
> Hi, Derek and Chen
>
> ram_bulk_stage is false by default before Hailiang's patch.
> For COLO, it does not seem to be used, so I think there is no need to
> reset it to true.
>
> Thanks,
> Lei.
>
> From: Derek Su
>
On Mon, 2020-09-21 at 11:37 -0400, Eduardo Habkost wrote:
> >
...
> > Yes. Trying as less refactor as possible. I think my changes even
> > cannot be called refactor at all. :)
> > My idea is to make unversioned CPU model virtual. I did some patch,
> > doable:
> > 1) in
Hi, Derek and Chen
ram_bulk_stage is false by default before Hailiang's patch.
For COLO, it does not seem to be used, so I think there is no need to reset it
to true.
Thanks,
Lei.
From: Derek Su
Sent: Tuesday, September 22, 2020 11:48 AM
To: Zhang, Chen
Cc: qemu-devel ; Rao, Lei ;
On Tue, Sep 22, 2020 at 09:47:57AM +0800, Li Qiang wrote:
> Eduardo Habkost 于2020年9月22日周二 上午6:11写道：
> >
> > Class properties make QOM introspection simpler and easier, as it
> > doesn't require an object to be instantiated. This series
> > converts a few existing object_property_add*() calls to
Hi, Chen
Sure.
BTW, I just went through Lei's patch.
ram_bulk_stage() might need to reset to true after stopping COLO service as
my patch.
How about your opinion?
Thanks.
Best regards,
Derek
Zhang, Chen 於 2020年9月22日 週二 上午11:41寫道：
> Hi Derek and Lei,
>
>
>
> It looks same with Lei’ patch:
>
Hi Derek and Lei,
It looks same with Lei’ patch:
[PATCH 2/3] Reduce the time of checkpoint for COLO
Can you discuss to merge it into one patch?
Thanks
Zhang Chen
From: Derek Su
Sent: Tuesday, September 22, 2020 11:31 AM
To: qemu-devel
Cc: zhang.zhanghaili...@huawei.com; quint...@redhat.com;
Hello, all
Ping...
Regards,
Derek Su
Derek Su 於 2020年9月10日 週四 下午6:47寫道：
> In secondary side, the colo_flush_ram_cache() calls
> migration_bitmap_find_dirty() to finding the dirty pages and
> flush them to host. But ram_state's ram_bulk_stage flag is always
> enabled in secondary side, it
Fore-commit(c6beefd674) only saves features of queue0,
this makes wrong features of other queues in multiqueues
situation.
For examples:
qemu-system-aarch64 ... \
-chardev socket,id=charnet0,path=/var/run/vhost_sock \
-netdev vhost-user,chardev=charnet0,queues=2,id=hostnet0 \
...
There are
Patchew URL:
https://patchew.org/QEMU/20200921221045.699690-1-ehabk...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
On Tue, Sep 22, 2020 at 9:55 AM Jason Wang wrote:
>
>
> On 2020/9/17 下午11:58, Cindy Lu wrote:
> > If the peer's type is vdpa,set the mac address to NIC in
> > virtio_net_device_realize,
> > Also sometime vdpa get an all 0 macaddress from the hardware, this will
> > cause the traffic down
> > So
Public bug reported:
When using the EFI firmware from
https://www.kraxel.org/repos/jenkins/edk2/
(https://www.kraxel.org/repos/jenkins/edk2/edk2.git-
ovmf-x64-0-20200919.1453.g7faece6985.noarch.rpm) (OVMF-pure-efi.fd and
OVMF_VARS-pure-efi.fd) then using the GOP, setting the mode to 1366x768,
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19 +++
hw/mips/meson.build | 2 +-
3 files changed,
Add Loongson-3A CPU models and Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/cpu-models-mips.rst.inc | 10 --
docs/system/target-mips.rst | 10 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git
From: Jiaxun Yang
LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.
This patch add implementation of these instructions:
gslbx: load 1 bytes to GPR
gslhx: load 2 bytes to GPR
gslwx: load 4 bytes to GPR
gsldx: load 8 bytes to GPR
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
From: Jiaxun Yang
Our current code assumed the target page size is always 4k
when handling PageMask and VPN2, however, variable page size
was just added to mips target and that's nolonger true.
Signed-off-by: Huacai Chen
Signed-off-by: Jiaxun Yang
---
target/mips/cp0_helper.c | 36
Add Loongson-3 based machine support, it use liointc as the interrupt
controler and use GPEX as the pci controller. Currently it can work with
both TCG and KVM.
As the machine model is not based on any exiting physical hardware, the
name of the machine is "loongson3-virt". It may be superseded in
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, in QEMU we just define two CPU types:
1,
Update MIPS KVM type defintition from Linux 5.9-rc6.
Signed-off-by: Huacai Chen
---
linux-headers/linux/kvm.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index a28c366737..36a480fd77 100644
---
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslwlc1: similar to lwl but RT is FPR instead of GPR
gslwrc1: similar to lwr but RT is FPR
On 2020/9/21 下午9:04, Laurent Vivier wrote:
Add trace functionis in vhost-vdpa.c.
All traces from this file can be enabled with '-trace vhost_vdpa*'.
Acked-by: Stefan Hajnoczi
Signed-off-by: Laurent Vivier
---
hw/virtio/trace-events | 29 ++
hw/virtio/vhost-vdpa.c | 86
On 2020/9/17 下午11:58, Cindy Lu wrote:
Fix the bug that while Check qemu supported netdev,
there is no vhost-vdpa
Signed-off-by: Cindy Lu
Acked-by: Jason Wang
---
net/net.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/net/net.c b/net/net.c
index 7a2a0fb5ac..794c652282
On 2020/9/17 下午11:58, Cindy Lu wrote:
fix the bug that fd will still open after the cleanup
Signed-off-by: Cindy Lu
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 4
1 file changed, 4 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index bc0e0d2d35..0480b92102
On 2020/9/17 下午11:58, Cindy Lu wrote:
If the peer's type is vdpa,set the mac address to NIC in
virtio_net_device_realize,
Also sometime vdpa get an all 0 macaddress from the hardware, this will cause
the traffic down
So we add the check for this part.
if we get an 0 mac address we will use
Eduardo Habkost 于2020年9月22日周二 上午6:11写道：
>
> Class properties make QOM introspection simpler and easier, as it
> doesn't require an object to be instantiated. This series
> converts a few existing object_property_add*() calls to register
> class properties instead.
>
Hello Eduardo,
IIUC, most
On 200815 0020, Li Qiang wrote:
> In 'map_page' we need to check the return value of
> 'dma_memory_map' to ensure the we actully maped something.
> Otherwise, we will hit an assert in 'address_space_unmap'.
> This is because we can't find the MR with the NULL buffer.
> This is the LP#1884693:
>
>
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Tuesday, September 22, 2020 6:10 AM
> To: qemu-devel@nongnu.org
> Cc: Paolo Bonzini ; Daniel P. Berrange
> ; John Snow ; Gonglei (Arei)
>
> Subject: [PATCH 01/24] cryptodev-vhost-user: Register "chardev"
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Tuesday, September 22, 2020 6:10 AM
> To: qemu-devel@nongnu.org
> Cc: Paolo Bonzini ; Daniel P. Berrange
> ; John Snow ; Gonglei (Arei)
>
> Subject: [PATCH 02/24] cryptodev-backend: Register "chardev" as
On Mon, Sep 21, 2020 at 04:49:57PM +0200, Laurent Vivier wrote:
> max-bandwidth is set by default to 32 MiB/s (256 Mib/s)
> since 2008 (5bb7910af031c).
>
> Most of the CPUs can dirty memory faster than that now,
> and this is clearly a problem with POWER where the page
> size is 64 kiB and not 4
Ping!!
Li Qiang 于2020年9月15日周二 下午9:38写道：
>
> ping!!
>
> Li Qiang 于2020年9月7日周一 上午9:39写道：
> >
> > Ping!
> >
> > Li Qiang 于2020年9月1日周二 下午6:34写道：
> > >
> > > Ping.
> > >
> > > Li Qiang 于2020年8月15日周六 下午3:21写道：
> > > >
> > > > In 'map_page' we need to check the return value of
> > > >
The following changes since commit 5df6c87e8080e0021e975c8387baa20cfe43c932:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request'
into staging (2020-09-21 17:41:32 +0100)
are available in the Git repository at:
https://repo.or.cz/qemu/ericb.git
If you have the chain 'base.qcow2 <- top.qcow2' and want to merge a
bitmap from top into base, qemu-img was failing with:
qemu-img: Could not open 'top.qcow2': Could not open backing file: Failed to
get shared "write" lock
Is another process using the image [base.qcow2]?
The easiest fix is to
On Mon, Sep 21, 2020 at 07:04:20PM -0400, Raphael Norwitz wrote:
> MST already sent a PR with all the patches :)
Thank you! )
>
> On Wed, Sep 16, 2020 at 6:13 PM Dima Stepanov wrote:
> >
> > On Mon, Sep 14, 2020 at 09:23:42PM -0400, Raphael Norwitz wrote:
> > > On Fri, Sep 11, 2020 at 4:43 AM
Patchew URL:
https://patchew.org/QEMU/20200921174118.39352-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200921174118.39352-1-richard.hender...@linaro.org
Subject: [PATCH v4 00/11]
Adding Paul
On Sat, 19 Sep 2020, Philippe Mathieu-Daudé wrote:
> Cc'ing qemu-trivial@
>
> On 7/27/20 5:09 PM, Anthony PERARD wrote:
> > On Mon, Jul 27, 2020 at 05:00:48PM +0300, Michael Tokarev wrote:
> >> There's no references in only file which includes xenguest.h
> >> to any xen definitions.
On Mon, Sep 21, 2020 at 05:47:28PM -0500, Babu Moger wrote:
> With x2apic enabled, configurations can have more that 255 cores.
> Noticed the device add test is hitting an assert when during cpu
> hotplug with core_id > 255. This is due to assert check in the
> CPUID 0x801E.
>
> Remove the
On Mon, Sep 21, 2020 at 12:31:21PM +0200, Philippe Mathieu-Daudé wrote:
> Back to the SDcard, it might be less critical, so a migration
> breaking change might be acceptable. I'm only aware of Paolo
> and Kevin using this device for testing. Not sure of its
> importance in production.
FWIW, I
Adding Paul
On Mon, 21 Sep 2020, Dr. David Alan Gilbert wrote:
> * Dov Murik (dovmu...@linux.vnet.ibm.com) wrote:
> >
> >
> > On 21/09/2020 14:17, Dr. David Alan Gilbert wrote:
> > > * Dov Murik (dovmu...@linux.vnet.ibm.com) wrote:
> > > > When running the xen-save-devices-state QMP command,
On Fri, Sep 18, 2020 at 12:34:30PM +0200, Thomas Huth wrote:
> Python 3.6 is already the default Python in the jobs that are based
> on Ubuntu Bionic, so it does not make much sense to test this again
> separately.
>
> Signed-off-by: Thomas Huth
> ---
> .travis.yml | 8
> 1 file
On Fri, Sep 18, 2020 at 12:34:29PM +0200, Thomas Huth wrote:
> According to our support policy, we do not support Xenial anymore.
> Time to switch the bigger parts of the builds to Focal instead.
> Some few jobs have to be updated to Bionic instead, since they are
> currently still failing on
MST already sent a PR with all the patches :)
On Wed, Sep 16, 2020 at 6:13 PM Dima Stepanov wrote:
>
> On Mon, Sep 14, 2020 at 09:23:42PM -0400, Raphael Norwitz wrote:
> > On Fri, Sep 11, 2020 at 4:43 AM Dima Stepanov
> > wrote:
> > >
> > > Add support for the vhost-user-blk-pci device. This
I see your point - all the open source backends I could find which
support VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD rely on knowing the vq
type to allocate the fd.
That said, it looks like dpdk supports both
VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD and packed vqs without needing
such an API
With x2apic enabled, configurations can have more that 255 cores.
Noticed the device add test is hitting an assert when during cpu
hotplug with core_id > 255. This is due to assert check in the
CPUID 0x801E.
Remove the assert check and fix the problem.
Fixes the bug:
Link:
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: "Michael S. Tsirkin"
Cc: Marcel Apfelbaum
Cc: qemu-devel@nongnu.org
---
hw/pci-host/i440fx.c | 32
1 file
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: qemu-ri...@nongnu.org
Cc: qemu-devel@nongnu.org
---
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Alistair Francis
Cc: "Edgar E. Iglesias"
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/xlnx-zcu102.c | 25
Hi David,
Thank you for your comments.
First, I want to underline that this driver targets Windows guests,
where ability to modify and adapt the guest memory management
code is extremely limited.
While it does work with Linux guests, too, this is definitely not its
native environment.
It also
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Gerd Hoffmann
Cc: qemu-devel@nongnu.org
---
hw/display/vga-pci.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: qemu-devel@nongnu.org
---
target/i386/cpu.c | 33
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Eduardo Habkost
Cc: Marcel Apfelbaum
Cc: qemu-devel@nongnu.org
---
hw/core/machine.c | 12 ++--
1 file changed, 6 insertions(+), 6
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: qemu-devel@nongnu.org
---
hw/cpu/core.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/cpu/core.c
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Cornelia Huck
Cc: Thomas Huth
Cc: Richard Henderson
Cc: David Hildenbrand
Cc: Halil Pasic
Cc: Christian Borntraeger
Cc:
On 9/21/20 3:33 PM, Tobin Feldman-Fitzthum wrote:
> On 2020-09-21 15:16, Dr. David Alan Gilbert wrote:
>> * Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
>>> AMD SEV allows a guest owner to inject a secret blob
>>> into the memory of a virtual machine. The secret is
>>> encrypted with
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: qemu-ri...@nongnu.org
Cc: qemu-devel@nongnu.org
---
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/vexpress.c | 14 --
1 file changed, 8 insertions(+), 6
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Laurent Vivier
Cc: Amit Shah
Cc: qemu-devel@nongnu.org
---
backends/rng-random.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Note: "its" is currently registered conditionally, but this makes
the feature be registered unconditionally. The only side effect
is that it will be now possible to set its=on on
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: qemu-devel@nongnu.org
---
hw/misc/tmp421.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Gerd Hoffmann
Cc: qemu-devel@nongnu.org
---
ui/input-barrier.c | 44 ++--
1 file changed, 22
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
target/arm/cpu64.c | 16 ++--
1 file changed, 6 insertions(+),
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: qemu-devel@nongnu.org
---
target/i386/cpu.c | 66
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Laurent Vivier
Cc: Amit Shah
Cc: qemu-devel@nongnu.org
---
backends/rng-egd.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Laurent Vivier
Cc: Amit Shah
Cc: qemu-devel@nongnu.org
---
backends/rng.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: "Gonglei (Arei)"
Cc: qemu-devel@nongnu.org
---
backends/cryptodev.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/virt.c | 76 +++
1
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Gerd Hoffmann
Cc: qemu-devel@nongnu.org
---
ui/input-linux.c | 27 ++-
1 file changed, 14 insertions(+), 13
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: "Michael S. Tsirkin"
Cc: qemu-devel@nongnu.org
---
backends/vhost-user.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Class properties make QOM introspection simpler and easier, as it
doesn't require an object to be instantiated. This series
converts a few existing object_property_add*() calls to register
class properties instead.
Eduardo Habkost (24):
cryptodev-vhost-user: Register "chardev" as class
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/vexpress.c | 11 ++-
1 file changed, 6 insertions(+), 5
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost
---
Cc: "Gonglei (Arei)"
Cc: qemu-devel@nongnu.org
---
backends/cryptodev-vhost-user.c | 13 +
1 file changed, 5 insertions(+), 8
On 9/17/20 5:19 AM, Max Reitz wrote:
temporary over NBD, referring to a bitmap that lives only in Active is
less effort than having to copy a bitmap into temporary [1]. So the
testsuite additions in this patch check both where bitmaps get
allocated (the qemu-img info output), and, when NOT
Patchew URL: https://patchew.org/QEMU/20200921162949.553863-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
> -Original Message-
> From: Keith Busch
> Sent: Friday, September 18, 2020 5:10 PM
> To: Klaus Jensen
> Cc: Dmitry Fomichev ; Fam Zheng
> ; Kevin Wolf ; Damien Le Moal
> ; qemu-bl...@nongnu.org; Niklas Cassel
> ; Klaus Jensen ; qemu-
> de...@nongnu.org; Alistair Francis ; Philippe
>
Patchew URL: https://patchew.org/QEMU/20200921162949.553863-1-phi...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200921162949.553863-1-phi...@redhat.com
Subject: [PATCH 0/6] block/nvme: Map doorbells
glib offers thread pools and it seems to support "exclusive" and "shared"
thread pools.
https://developer.gnome.org/glib/stable/glib-Thread-Pools.html#g-thread-pool-new
Currently we use "exlusive" thread pools but its performance seems to be
poor. I tried using "shared" thread pools and
On 9/21/20 11:23 AM, Stefan Hajnoczi wrote:
clang's C11 atomic_fetch_*() functions only take a C11 atomic type
pointer argument. QEMU uses direct types (int, etc) and this causes a
compiler error when a QEMU code calls these functions in a source file
that also included via a system header
Patchew URL:
https://patchew.org/QEMU/20200921162346.188997-1-stefa...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200921162346.188997-1-stefa...@redhat.com
Subject: [PATCH] qemu/atomic.h: prefix
On 2020-09-21 15:16, Dr. David Alan Gilbert wrote:
* Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
AMD SEV allows a guest owner to inject a secret blob
into the memory of a virtual machine. The secret is
encrypted with the SEV Transport Encryption Key and
integrity is guaranteed with
On Fri, Sep 18, 2020 at 12:34:28PM +0200, Thomas Huth wrote:
> The total runtime of all Travis jobs is very long and we are testing
> all softmmu targets in the gitlab-CI already - so we can speed up the
> Travis testing a little bit by not testing the softmmu targets here
> anymore.
>
>
On Fri, Sep 18, 2020 at 12:34:27PM +0200, Thomas Huth wrote:
> GCC 9.3.0 on Ubuntu complains:
>
> In file included from /usr/include/string.h:495,
> from /home/travis/build/huth/qemu/include/qemu/osdep.h:87,
> from ../migration/global_state.c:13:
> In function
On Fri, Sep 18, 2020 at 05:34:36PM -0400, Vivek Goyal wrote:
> Hi All,
>
> virtiofsd default thread pool size is 64. To me it feels that in most of
> the cases thread pool size 1 performs better than thread pool size 64.
>
> I ran virtiofs-tests.
>
> https://github.com/rhvgoyal/virtiofs-tests
Hi Phil,
Just two small typos in the commit message.
On 9/21/20 9:56 AM, Philippe Mathieu-Daudé wrote:
The firmware load address depends of the SoC ("processor id") used,
"depends on"
not of the version of the board.
"not on"
Otherwise:
Reviewed-by: Luc Michel
Signed-off-by: Philippe
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
The SYS_timer is not directly wired to the ARM core, but to the
SoC (peripheral) interrupt controller.
Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
On 9/21/20 9:56 AM, Philippe Mathieu-Daudé wrote:
The 'first_cpu' is more a QEMU accelerator-related concept
than a variable the machine requires to use.
Since the machine is aware of its CPUs, directly use the
first one to load the firmware.
Signed-off-by: Philippe Mathieu-Daudé
On 9/21/20 12:29 PM, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> Instead of creating GStrings and passing them into log_disas,
>> just print the annotations directly in tb_gen_code.
>>
>> Fix the annotations for the slow paths of the TB, after the
>> part implementing the final guest
On 9/21/20 9:56 AM, Philippe Mathieu-Daudé wrote:
The arm_boot_info structure belong to the machine,
move it to RaspiMachineState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/arm/raspi.c | 30 +++---
1 file changed, 15 insertions(+), 15
On Sep 21 09:50, Keith Busch wrote:
> On Fri, Sep 18, 2020 at 10:36:07PM +0200, Klaus Jensen wrote:
> > @@ -466,15 +476,21 @@ static void nvme_post_cqes(void *opaque)
> > break;
> > }
> >
> > -QTAILQ_REMOVE(>req_list, req, entry);
> > sq = req->sq;
> >
On 9/21/20 9:56 AM, Philippe Mathieu-Daudé wrote:
Display the board revision in the machine description.
Before:
$ qemu-system-aarch64 -M help | fgrep raspi
raspi2 Raspberry Pi 2B
raspi3 Raspberry Pi 3B
After:
raspi2 Raspberry Pi 2B
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
Add trace events for GPU and CPU IRQs.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/intc/bcm2835_ic.c | 4 +++-
hw/intc/trace-events | 4
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
The variable holding the CTRL_STATUS register is misnamed
'status'. Rename it 'ctrl_status' to make it more obvious
this register is also used to control the peripheral.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
Use the BCM2835_SYSTIMER_COUNT definition instead of the
magic '4' value.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/timer/bcm2835_systmr.h | 4 +++-
hw/timer/bcm2835_systmr.c | 3 ++-
2 files
Hi Phil,
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
This peripheral has 1 free-running timer and 4 compare registers.
Only the free-running timer is implemented. Add support the
COMPARE registers (each register is wired to an IRQ).
Reference: "BCM2835 ARM Peripherals" datasheet [*]
Richard Henderson writes:
> Use the routines we have already instead of open-coding.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Richard Henderson writes:
> Rename several functions, dropping "generic" and making "host"
> vs "target" clearer. Make a bunch of functions static that are
> not used outside this file. Replace INIT_DISASSEMBLE_INFO with
> a trio of functions.
"Also clean up a bunch of CODING_STYLE
Richard Henderson writes:
> Instead of creating GStrings and passing them into log_disas,
> just print the annotations directly in tb_gen_code.
>
> Fix the annotations for the slow paths of the TB, after the
> part implementing the final guest instruction.
>
> Reviewed-by: Thomas Huth
>
I think we can just bite the bullet and bump the version number. Just like
not all boards are created equal in terms of migration compatibility,
neither are all devices.
Unfortunately pflash is among those that need some care, but we have much
more leeway with sdhci-pci.
Paolo
Il lun 21 set
Other than the comments on patches 3 and 9, the rest of the series looks
good to me.
Reviewed-by: Keith Busch
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