The microblaze kernel does not support these, and uses
only rt style signal frames.
Tested-by: Edgar E. Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
linux-user/microblaze/target_signal.h | 1 -
linux-user/microblaze/signal.c| 97
Unlike glibc, musl does not use transparent unions to hide
the different structures that overlap struct sockaddr.
Add an explicit cast to work around this.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tests/tcg/multiarch/linux-test.c | 2 +-
1 file changed, 1
Allows microblaze to pass tests/tcg/multiarch/linux-test.c.
Tested-by: Edgar E. Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
linux-user/microblaze/signal.c | 91 ++
1 file changed, 82 insertions(+), 9 deletions(-)
diff --git
The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4:
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request'
into staging (2020-10-14 13:56:06 +0100)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-mb
On Thu, Oct 15, 2020 at 6:19 AM Bruce Rogers wrote:
>
> It isn't necessarily the case that use of iconv requires an additional
> library. For that reason we shouldn't conditionalize iconv detection on
> libiconv.found.
>
> Fixes: 5285e593c33 (configure: Fixes ncursesw detection under msys2/mingw
Add '-drive' support to OTP device. Allow users to assign a raw file
as OTP image.
test commands for 16k otp.img filled with zero:
$ dd if=/dev/zero of=./otp.img bs=1k count=16
$ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
-kernel
patch [1/2] - add write function and wrire-once feature
patch [2/2] - add file backend support
Test Steps: (should work even only 1/2 is applied)
1) Follow instructions to prepare fw_payload -
https://github.com/riscv/opensbi/blob/master/docs/platform/sifive_fu540.md
a) build 1-round
- Add write operation to update fuse data bit when PWE bit is on.
- Add array, fuse_wo, to store the 'written' status for all bits
of OTP to block the write operation.
Signed-off-by: Green Wan
Reviewed-by: Alistair Francis
---
hw/misc/sifive_u_otp.c | 30
Hi Maxim,
Thanks for your emphasis. It's much clearer.
Best,
Harry
Hi Paolo and Sean,
It is clear to me now. Thanks much for your reply and help.
Best regards,
Harry
On 10/14/20 4:16 PM, Jason Thorpe wrote:
>
>> On Oct 14, 2020, at 2:52 PM, Richard Henderson
>> wrote:
>>
>> I'm certainly open to these changes. But it'll need to be split up -- one
>> patch per bullet, basically.
>
> That's fine. What's the convention for patches that stack on top of one
Hi Alistair,
That's correct. Once you configure 'CONFIG_SIFIVE_OTP=y', the uboot
driver performs some read/write during booting.
And I'll also include the test steps by using the 'misc' testing patch
shared by Bin.
Regards,
-
Green
On Thu, Oct 15, 2020 at 2:51 AM Alistair Francis wrote:
>
>
On Tue, Oct 13, 2020 at 05:08:54PM -0700, Sean Christopherson wrote:
> On Tue, Oct 13, 2020 at 01:19:30PM +0800, Yang Weijiang wrote:
> > With more components in XSS being developed on Intel platform,
> > it's necessary to clean up existing XSAVE related feature words to
> > make the name clearer.
On Wed, Oct 14, 2020 at 3:17 PM Bin Meng wrote:
>
> Hi Green,
>
> On Wed, Oct 14, 2020 at 3:02 PM Green Wan wrote:
> >
> > On Wed, Oct 14, 2020 at 1:37 PM Bin Meng wrote:
> > >
> > > Hi Green,
> > >
> > > On Mon, Sep 28, 2020 at 6:12 PM Green Wan wrote:
> > > >
> > > > - Add write operation
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
Cc valentin
-Original Message-
From: Qemu-devel
[mailto:qemu-devel-bounces+prime.zeng=hisilicon@nongnu.org]
On Behalf Of Ying Fang
Sent: Thursday, September 17, 2020 11:20 AM
> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Thursday, October 15, 2020 3:12 AM
> To: Richard Henderson
> Cc: Jiangyifei ; qemu-devel@nongnu.org;
> qemu-ri...@nongnu.org; Zhanghailiang ;
> sag...@eecs.berkeley.edu; kbast...@mail.uni-paderborn.de;
> -Original Message-
> From: Richard Henderson [mailto:richard.hender...@linaro.org]
> Sent: Thursday, October 15, 2020 4:22 AM
> To: Jiangyifei ; qemu-devel@nongnu.org;
> qemu-ri...@nongnu.org
> Cc: pal...@dabbelt.com; alistair.fran...@wdc.com;
> sag...@eecs.berkeley.edu;
On Wed, Oct 14, 2020 at 05:14:01PM -0400, Cleber Rosa wrote:
> On Wed, Oct 14, 2020 at 06:46:55PM +0100, Daniel P. Berrangé wrote:
> >
> > This bug links to
> >
> > https://bugs.launchpad.net/ubuntu/+source/libssh/+bug/1847514
> >
> > which is marked as fixed. So I'm thinking we can drop the
> On Oct 14, 2020, at 2:52 PM, Richard Henderson
> wrote:
>
> I'm certainly open to these changes. But it'll need to be split up -- one
> patch per bullet, basically.
That's fine. What's the convention for patches that stack on top of one
another?
-- thorpej
There's about 40 instances of *code_ptr or code_ptr[i] changed to
TCG_CODE_PTR_RW(s, code_ptr). It's around 2 instances per function, so
if I go with a local variable, that would be ~20 extra LOC.
Another alternative is two separate functions: tcg_code_ptr_insn_rw()
which returns tcg_insn_unit *
This won't prevent the docs from being built, but will let people
know Sphinx 3.x is not fully supported yet.
Signed-off-by: Eduardo Habkost
---
docs/conf.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/docs/conf.py b/docs/conf.py
index 00e1b750e2..1d92e65d12 100644
---
It isn't necessarily the case that use of iconv requires an additional
library. For that reason we shouldn't conditionalize iconv detection on
libiconv.found.
Fixes: 5285e593c33 (configure: Fixes ncursesw detection under msys2/mingw by
convert them to meson)
Signed-off-by: Bruce Rogers
---
On 10/6/20 8:24 PM, Jason Thorpe wrote:
> Along with the previous patch set for qemu-palcode, these changes
> allow NetBSD/alpha to run in qemu-system-alpha.
>
> - Allow a the minimum PCI device number to be passed to typhoon_init().
> Use this to specify a minimum PCI device number of 1 in the
On 10/6/20 7:52 PM, Jason Thorpe wrote:
> There are additional changes in Qemu itself. Those will be sent as
> a follow-up.
>
> - Change the $a2 value at VM start from "cpu count" to "config word". Bits
> 0-5 are cpu count, and bit 6 communicates the "-nographic" option from
> the VM.
> -
I just stumbled upon this when editing .travis.yml, and I'm
trying to understand how the $CACHE_NAME trick is supposed to
work.
If I understood the Travis documentation correctly, all
environment variables will affect the cache id (including
$CONFIG, in the case below). This would mean the two
On 10/14/20 1:58 PM, Joelle van Dyne wrote:
> Much of the code that uses the macro is like the following (from
> aarch64/tcg-include.inc.c)
>
> *TCG_CODE_PTR_RW(s, code_ptr) =
> deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset);
>
> Before the change, it was just
On 10/14/20 1:54 PM, BALATON Zoltan wrote:
>> static inline void *tcg_code_ptr_rw(TCGContext *s, void *rx)
>> {
>> #ifdef CONFIG_IOS_JIT
>> return rx + s->code_rw_mirror_diff;
>
> This looks better but can you add to void *? I think some compilers may
> complain about that so may need to cast
The time to transmit a char is expressed in nanoseconds, not in ticks.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/strongarm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index d7133eea6f9..ca7c385f313 100644
---
On Wed, Oct 14, 2020 at 06:46:55PM +0100, Daniel P. Berrangé wrote:
> On Wed, Oct 14, 2020 at 01:21:40AM -0400, Cleber Rosa wrote:
> > The QEMU project has two machines (aarch64 and s390) that can be used
> > for jobs that do build and run tests. This introduces those jobs,
> > which are a
On Wed, 14 Oct 2020, Joelle van Dyne wrote:
Much of the code that uses the macro is like the following (from
aarch64/tcg-include.inc.c)
*TCG_CODE_PTR_RW(s, code_ptr) =
deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset);
Before the change, it was just *code_ptr. I'm
Much of the code that uses the macro is like the following (from
aarch64/tcg-include.inc.c)
*TCG_CODE_PTR_RW(s, code_ptr) =
deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset);
Before the change, it was just *code_ptr. I'm saying the alternative
was to have to write
On Wed, 14 Oct 2020, Richard Henderson wrote:
On 10/14/20 9:03 AM, Joelle van Dyne wrote:
static int encode_search(TranslationBlock *tb, uint8_t *block)
{
-uint8_t *highwater = tcg_ctx->code_gen_highwater;
-uint8_t *p = block;
+uint8_t *highwater;
+uint8_t *p;
int i, j, n;
On Wed, Oct 14, 2020 at 1:20 PM Victor Kamensky (kamensky)
wrote:
>
> In order just to keep on the same thread, here is piece of information
> I found:
>
> I looked at "MIPS32® 34Kf™ Processor Core Datasheet" [1]
>
> Page 8 in "Joint TLB (JTLB)" section says:
>
> "The JTLB is a fully associative
On 10/14/20 2:05 PM, Philippe Mathieu-Daudé wrote:
On 10/14/20 4:29 PM, John Snow wrote:
Add short readmes to python/, python/qemu/, and python/qemu/core that
explain the directory hierarchy. These readmes are visible when browsing
Maybe readmes -> READMEs
If you want it to match the
On 14.10.2020 15:51, Max Reitz wrote:
On 12.10.20 19:43, Andrey Shinkevich wrote:
If the flag BDRV_REQ_PREFETCH was set, pass it further to the
COR-driver to skip unneeded reading. It can be taken into account for
the COR-algorithms optimization. That check is being made during the
block stream
On Wed, Oct 14, 2020 at 09:54:14AM -0400, Paolo Bonzini wrote:
> ninja is included in the CentOS PowerTools repository.
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/docker/dockerfiles/centos8.docker | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
On 10/14/20 9:03 AM, Joelle van Dyne wrote:
>>> static int encode_search(TranslationBlock *tb, uint8_t *block)
>>> {
>>> -uint8_t *highwater = tcg_ctx->code_gen_highwater;
>>> -uint8_t *p = block;
>>> +uint8_t *highwater;
>>> +uint8_t *p;
>>> int i, j, n;
>>>
>>> +highwater
On 10/14/20 3:17 AM, Yifei Jiang wrote:
> +if (fault_pte_addr) {
> +*fault_pte_addr = (base + idx * ptesize) >> 2;
The shift is wrong. It should be exactly like...
> +}
> +return TRANSLATE_G_STAGE_FAIL;
> }
>
>
In order just to keep on the same thread, here is piece of information
I found:
I looked at "MIPS32® 34Kf™ Processor Core Datasheet" [1]
Page 8 in "Joint TLB (JTLB)" section says:
"The JTLB is a fully associative TLB cache containing 16, 32,
or 64-dual-entries mapping up to 128 virtual pages to
On Wed, Oct 14, 2020 at 3:18 AM Yifei Jiang wrote:
>
> VS-stage translation at get_physical_address needs to translate pte
> address by G-stage translation. But the G-stage translation error
> can not be distinguished from VS-stage translation error in
> riscv_cpu_tlb_fill. On migration,
> The if is redundant, since that will have been done in
cpu_get_tb_cpu_state while assigning pm_enabled.
I totally agree here, however I tried to do explicit checks, so this
functionality is available only if a special option is supplied.
But if you think that's too much and I could do just
On 14.10.2020 15:22, Max Reitz wrote:
On 12.10.20 19:43, Andrey Shinkevich wrote:
Modify the comment for the flag BDRV_REQ_PREFETCH as we are going to
use it alone and pass it to the COR-filter driver for further
processing.
Signed-off-by: Andrey Shinkevich
---
include/block/block.h | 7
> I suggest adding a stub version of this function to patch 5, and then
swap patch 4 and patch 5.
Thanks, will do.
>This bakes in values from ENV without adding any way to verify that those
values are still current.
If I correctly get your idea, you're talking about the situation, when
I believe we shouldn't be conditionalizing running the iconv c program detection
on the iconv library having been found. At least that's my semi-uninformed
analysis so far.
- Bruce
From: 罗勇刚(Yonggang Luo)
Sent: Wednesday, October 14, 2020 1:17 PM
To:
On 10/14/20 12:23 PM, Claudio Fontana wrote:
> +++ b/accel/tcg/tcg-cpus-mttcg.h
> @@ -10,14 +10,4 @@
> #ifndef TCG_CPUS_MTTCG_H
> #define TCG_CPUS_MTTCG_H
>
> -/*
> - * Multi-threaded TCG
> - *
> - * In the multi-threaded case each vCPU has its own thread. The TLS
> - * variable current_cpu
On Sun, Oct 11, 2020 at 07:29:25PM +0100, Peter Maydell wrote:
> > Migration:
> > Dirtyrate measurement API cleanup
> > Postcopy recovery fixes
> >
> > Virtiofsd:
> > Missing qemu_init_exec_dir call
> > Support for setting the group on socket creation
> > Stop a gcc warning
> > Avoid
On Tue, Oct 13, 2020 at 3:11 AM Alex Bennée wrote:
>
>
> Edgar E. Iglesias writes:
>
> > On Mon, Oct 12, 2020 at 05:02:57PM +0100, Alex Bennée wrote:
> >>
> >> Alistair Francis writes:
> >>
> >> > On Fri, Oct 9, 2020 at 10:07 AM Alex Bennée
> >> > wrote:
> >> >>
> >> >> Hi,
> >> >>
> >> >>
First of all thank you so much for reviewing these patches!
>RVJ.
Thanks, I missed this typo, will fix it.
>Probably you only want to dump the set that's current.
I don't know for sure how anyone would be using this while debugging PM
related code, but I like the idea, so I'll try to do it,
On Tue, Oct 13, 2020 at 10:41 AM Gerd Hoffmann wrote:
>
> On Tue, Oct 13, 2020 at 12:19:40AM -0700, Paul Zimmerman wrote:
> > I sent you a patch to fix up several assert()s, including that one, about a
> > month ago. Did you miss it?
> >
On Tue, Oct 13, 2020 at 10:23 AM Georg Kotheimer
wrote:
>
> The HLVX.WU instruction is supposed to read a machine word,
> but prior to this change it read a byte instead.
>
> Signed-off-by: Georg Kotheimer
Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
On Tue, Oct 13, 2020 at 10:31 AM Georg Kotheimer
wrote:
>
> The hstatus.GVA bit was not set if the faulting guest virtual address
> was zero.
>
> Signed-off-by: Georg Kotheimer
Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu_helper.c
On 10/14/20 12:23 PM, Claudio Fontana wrote:
> split up the CpusAccel tcg_cpus into three TCG variants:
>
> tcg_cpus_rr (single threaded, round robin cpus)
> tcg_cpus_icount (same as rr, but with instruction counting enabled)
> tcg_cpus_mttcg (multi-threaded cpus)
>
> Suggested-by: Richard
On Tue, Oct 13, 2020 at 8:11 AM Georg Kotheimer
wrote:
>
> When trapping from virt into HS mode, hstatus.SPVP was set to
> the value of sstatus.SPP, as according to the specification both
> flags should be set to the same value.
> However, the assignment of SPVP takes place before SPP itself is
>
On Wed, 14 Oct 2020 17:25:35 +0200
Christian Schoenebeck wrote:
> On Donnerstag, 8. Oktober 2020 20:34:56 CEST Christian Schoenebeck wrote:
> > All existing 9pfs test cases are using the 'synth' fs driver so far, which
> > means they are not accessing real files, but a purely simulated (in RAM
>
On 10/14/20 9:33 PM, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
Use of 0x%d - make up our mind as 0x%x
Uh...
Reviewed-by: Philippe Mathieu-Daudé
(hw/arm/... in subject)
Signed-off-by: Dr. David Alan Gilbert
---
hw/arm/trace-events | 2 +-
1 file changed, 1
On 10/14/20 9:23 PM, Claudio Fontana wrote:
Signed-off-by: Claudio Fontana
---
accel/tcg/tcg-cpus-icount.c | 24 ++--
accel/tcg/tcg-cpus-icount.h | 6 +--
accel/tcg/tcg-cpus-mttcg.c | 10 ++---
accel/tcg/tcg-cpus-rr.c | 74 ++---
On 10/14/20 9:23 PM, Claudio Fontana wrote:
split up the CpusAccel tcg_cpus into three TCG variants:
tcg_cpus_rr (single threaded, round robin cpus)
tcg_cpus_icount (same as rr, but with instruction counting enabled)
tcg_cpus_mttcg (multi-threaded cpus)
Suggested-by: Richard Henderson
* Bihong Yu (yubih...@huawei.com) wrote:
> Signed-off-by: Bihong Yu
> Reviewed-by: Chuan Zheng
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/rdma.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/migration/rdma.c b/migration/rdma.c
> index 0eb42b7..ca4d315
From: "Dr. David Alan Gilbert"
Use of 0x%d - make up our mind as 0x%x
Signed-off-by: Dr. David Alan Gilbert
---
hw/arm/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index c8a4d80f6b..a335ee891d 100644
---
* Bihong Yu (yubih...@huawei.com) wrote:
> Signed-off-by: Bihong Yu
> Reviewed-by: Chuan Zheng
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/block.c | 2 +-
> migration/ram.c | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/migration/block.c
after the initial split into 3 tcg variants, we proceed to also
split tcg_start_vcpu_thread.
We actually split it in 2 this time, since the icount variant
just uses the round robin function.
Suggested-by: Richard Henderson
Signed-off-by: Claudio Fontana
---
accel/tcg/tcg-all.c | 5
On 10/14/20 10:01 AM, Alexey Baturo wrote:
> +if (has_ext(ctx, RVJ)) {
> +src1 = apply_pointer_masking(ctx, src1);
> +}
The if is redundant, since that will have been done in cpu_get_tb_cpu_state
while assigning pm_enabled.
The test for pm_enabled is in gen_pm_adjust_address.
On Wed, Oct 14, 2020 at 02:59:58PM -0400, Cleber Rosa wrote:
> On Wed, Oct 14, 2020 at 06:30:09PM +0100, Daniel P. Berrangé wrote:
> >
> > This needs updating to add meson, and with Paolo's series today you
> > might as well go ahead and add ninja-build immediately too
> >
I replied too quickly,
On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
wrote:
>
> On 10/14/20 3:21 AM, Jiangyifei wrote:
> >> Would this be a good time to expand mstatus to uint64_t instead of
> >> target_ulong so that it can be saved as one unit and reduce some ifdefs in
> >> the
> >> code base?
> >>
> >> Similarly
split up the CpusAccel tcg_cpus into three TCG variants:
tcg_cpus_rr (single threaded, round robin cpus)
tcg_cpus_icount (same as rr, but with instruction counting enabled)
tcg_cpus_mttcg (multi-threaded cpus)
Suggested-by: Richard Henderson
Signed-off-by: Claudio Fontana
---
If iconv installed then it's the meson's probme that didn't found the iconv
properly
On Thu, Oct 15, 2020 at 2:22 AM Bruce Rogers wrote:
>
> On Wed, 2020-10-14 at 10:21 +0200, Gerd Hoffmann wrote:
> > From: Yonggang Luo
> >
> > The mingw pkg-config are showing following absolute path and
On Tue, Oct 13, 2020 at 1:31 AM Bin Meng wrote:
>
> Since sifive_plic.h is used by hw/intc/sifive_plic.c,
> it has to be in the public include directory. Move it.
>
> Fixes: 84fcf3c15111 ("hw/riscv: Move sifive_plic model to hw/intc")
> Signed-off-by: Bin Meng
> Reviewed-by: Philippe
Signed-off-by: Claudio Fontana
---
accel/tcg/tcg-cpus-icount.c | 24 ++--
accel/tcg/tcg-cpus-icount.h | 6 +--
accel/tcg/tcg-cpus-mttcg.c | 10 ++---
accel/tcg/tcg-cpus-rr.c | 74 ++---
accel/tcg/tcg-cpus-rr.h | 2 +-
accel/tcg/tcg-cpus.c
The purpose of this series is to split the tcg-cpus into
3 variants:
tcg_cpus_mttcg(multithreaded tcg vcpus)
tcg_cpus_rr (single threaded round robin vcpus)
tcg_cpus_icount (same as RR, but using icount)
Ciao,
Claudio
v1 -> v2:
* fixed file preambles to be clearer (Philippe)
*
* Bihong Yu (yubih...@huawei.com) wrote:
> Signed-off-by: Bihong Yu
> Reviewed-by: Chuan Zheng
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/ram.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/migration/ram.c b/migration/ram.c
> index
* Bihong Yu (yubih...@huawei.com) wrote:
> Signed-off-by: Bihong Yu
> Reviewed-by: Chuan Zheng
OK, sometimes I find initialisation clearer
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/ram.c| 2 +-
> migration/savevm.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
On 10/14/20 10:01 AM, Alexey Baturo wrote:
> +static TCGv_i64 apply_pointer_masking(DisasContext *s, TCGv_i64 addr)
> +{
> +gen_pm_adjust_address(s, addr, addr);
> +return addr;
> +}
This function is unused in this patch, which means the series as a whole is
non-bisectable.
Rather than
Because you didn't install the iconv.
On Thu, Oct 15, 2020 at 2:22 AM Bruce Rogers wrote:
>
> On Wed, 2020-10-14 at 10:21 +0200, Gerd Hoffmann wrote:
> > From: Yonggang Luo
> >
> > The mingw pkg-config are showing following absolute path and contains
> > : as the separator,
> >
> >
* Bihong Yu (yubih...@huawei.com) wrote:
> Signed-off-by: Bihong Yu
> Reviewed-by: Chuan Zheng
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/rdma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/migration/rdma.c b/migration/rdma.c
> index ca4d315..00eac34
On Wed, Oct 14, 2020 at 06:30:09PM +0100, Daniel P. Berrangé wrote:
> On Wed, Oct 14, 2020 at 01:21:38AM -0400, Cleber Rosa wrote:
> > To run basic jobs on custom runners, the environment needs to be
> > properly set up. The most common requirement is having the right
> > packages installed.
> >
On 14.10.2020 15:01, Max Reitz wrote:
On 12.10.20 19:43, Andrey Shinkevich wrote:
Limit COR operations by the base node in the backing chain when the
overlay base node name is given. It will be useful for a block stream
job when the COR-filter is applied. The overlay base node is passed as
the
On Wed, Oct 14, 2020 at 8:02 AM Bin Meng wrote:
>
> Hi Alistair,
>
> On Wed, Oct 14, 2020 at 10:46 PM Alistair Francis
> wrote:
> >
> > On Wed, Sep 30, 2020 at 12:10 AM Green Wan wrote:
> > >
> > > On Wed, Sep 30, 2020 at 1:08 AM Alistair Francis
> > > wrote:
> > > >
> > > > On Mon, Sep 28,
On 10/14/20 10:01 AM, Alexey Baturo wrote:
> +if (riscv_has_ext(env, RVH)) {
RVJ.
> +qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte", env->mmte);
> +qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", env->upmbase);
> +qemu_fprintf(f, " %s " TARGET_FMT_lx
Hello together,
build with enable-docs and install the required packages now it works
with man qemu.
Many thanks for you help
Problem resolved :-)
Best regards
Damian
** Changed in: qemu
Status: Incomplete => Confirmed
** Changed in: qemu
Status: Confirmed => Fix Released
--
On Wed, 2020-10-14 at 10:21 +0200, Gerd Hoffmann wrote:
> From: Yonggang Luo
>
> The mingw pkg-config are showing following absolute path and contains
> : as the separator,
>
> -D_XOPEN_SOURCE=600 -D_POSIX_C_SOURCE=199506L -IC:/CI-
>
On 10/14/20 7:56 PM, Ben Widawsky wrote:
On 20-10-14 13:52:29, Michael S. Tsirkin wrote:
On Wed, Oct 14, 2020 at 10:18:53AM -0700, Ben Widawsky wrote:
This patch informs future developers working on root complexes, root
ports, or bridges that also wish to implement a BAR for those. PCI type
1
On 10/14/20 4:29 PM, John Snow wrote:
Signed-off-by: John Snow
---
python/.isort.cfg | 7 ---
python/setup.cfg | 8
2 files changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/14/20 4:29 PM, John Snow wrote:
move python/qemu/*.py to python/qemu/core/*.py and update import
directives across the tree.
This is done to create a PEP420 namespace package, in which we may
create subpackages. To do this, the namespace directory ("qemu") should
not have any modules in
From: "Dr. David Alan Gilbert"
Map xattr names coming from the server, i.e. the host filesystem;
currently this is only from listxattr.
Signed-off-by: Dr. David Alan Gilbert
---
tools/virtiofsd/passthrough_ll.c | 89
1 file changed, 89 insertions(+)
diff
On 10/14/20 4:29 PM, John Snow wrote:
Add short readmes to python/, python/qemu/, and python/qemu/core that
explain the directory hierarchy. These readmes are visible when browsing
Maybe readmes -> READMEs
Otherwise:
Reviewed-by: Philippe Mathieu-Daudé
the source on e.g. gitlab/github and
From: "Dr. David Alan Gilbert"
Add a few examples of xattrmaps to the documentation.
Signed-off-by: Dr. David Alan Gilbert
---
docs/tools/virtiofsd.rst | 50
1 file changed, 50 insertions(+)
diff --git a/docs/tools/virtiofsd.rst
From: "Dr. David Alan Gilbert"
The mapping rule system implemented in the last few patches is
extremely flexible, but not easy to use. Add a simple
'map' type as a sprinkling of sugar to make it easy.
e.g.
-o xattrmap=":map::user.virtiofs.:"
would be sufficient to prefix all xattr's
or
From: "Dr. David Alan Gilbert"
Map xattr names originating at the client; from get/set/remove xattr.
Signed-off-by: Dr. David Alan Gilbert
---
tools/virtiofsd/passthrough_ll.c | 101 ++-
1 file changed, 98 insertions(+), 3 deletions(-)
diff --git
From: "Dr. David Alan Gilbert"
Add an option to define mappings of xattr names so that
the client and server filesystems see different views.
This can be used to have different SELinux mappings as
seen by the guest, to run the virtiofsd with less privileges
(e.g. in a case where it can't set
From: "Dr. David Alan Gilbert"
This is a 3rd cut of an xattr name mapping option for virtiofsd.
It allows the user of virtiofsd to define a fairly flexible mapping
from the view of the xattr names the host fs has and the ones that the
guest sees.
The hope is this allows things like:
a)
On 10/13/20 2:46 PM, Rohit Shinde wrote:
Hey John,
Sorry for the late reply! I was in the midst of a job change and
couldn't get time to get to this.
The work sounds interesting! I have a couple of questions regarding this:
1. How do I actually build this part? I am familiar with building
On 20-10-14 13:52:29, Michael S. Tsirkin wrote:
> On Wed, Oct 14, 2020 at 10:18:53AM -0700, Ben Widawsky wrote:
> > This patch informs future developers working on root complexes, root
> > ports, or bridges that also wish to implement a BAR for those. PCI type
> > 1 headers only support 2 base
On Wed, Oct 14, 2020 at 01:21:39PM -0400, Raphael Norwitz wrote:
> On Wed, Oct 14, 2020 at 12:26 PM Michael S. Tsirkin wrote:
> >
> > On Wed, Oct 14, 2020 at 12:11:34PM -0400, Raphael Norwitz wrote:
> > > On Wed, Oct 14, 2020 at 3:08 AM Michael S. Tsirkin
> > > wrote:
> > > >
> > > > On Tue,
On Wed, Oct 14, 2020 at 10:18:53AM -0700, Ben Widawsky wrote:
> This patch informs future developers working on root complexes, root
> ports, or bridges that also wish to implement a BAR for those. PCI type
> 1 headers only support 2 base address registers. It is incorrect and
> difficult to
On Wed, Oct 14, 2020 at 01:21:40AM -0400, Cleber Rosa wrote:
> The QEMU project has two machines (aarch64 and s390) that can be used
> for jobs that do build and run tests. This introduces those jobs,
> which are a mapping of custom scripts used for the same purpose.
>
> Signed-off-by: Cleber
On 14.10.2020 14:59, Max Reitz wrote:
On 12.10.20 19:43, Andrey Shinkevich wrote:
Limit COR operations by the base node in the backing chain when the
overlay base node name is given. It will be useful for a block stream
job when the COR-filter is applied. The overlay base node is passed as
the
On Wed, Oct 14, 2020 at 01:21:39AM -0400, Cleber Rosa wrote:
> To have the jobs dispatched to custom runners, gitlab-runner must
> be installed, active as a service and properly configured. The
> variables file and playbook introduced here should help with those
> steps.
>
> The playbook
On Wed, Oct 14, 2020 at 01:21:38AM -0400, Cleber Rosa wrote:
> To run basic jobs on custom runners, the environment needs to be
> properly set up. The most common requirement is having the right
> packages installed.
>
> The playbook introduced here covers a number of different Linux
>
On Wed, Oct 14, 2020 at 01:21:37AM -0400, Cleber Rosa wrote:
> As described in the included documentation, the "custom runner" jobs
> extend the GitLab CI jobs already in place.
>
> Those jobs are intended to run on hardware and/or Operating Systems
> not provided by GitLab's shared runners.
>
>
On Wed, Oct 14, 2020 at 12:26 PM Michael S. Tsirkin wrote:
>
> On Wed, Oct 14, 2020 at 12:11:34PM -0400, Raphael Norwitz wrote:
> > On Wed, Oct 14, 2020 at 3:08 AM Michael S. Tsirkin wrote:
> > >
> > > On Tue, Oct 13, 2020 at 08:58:59PM -0400, Raphael Norwitz wrote:
> > > > On Tue, Oct 6, 2020
1 - 100 of 350 matches
Mail list logo
