Hi Keith:
Thanks for the patch, I've verified with newlib semihosting support
which is contributed by Craig Blackmore from embecosm,
and I would like to add semihosting to user mode, do you mind add this
patch into this patch series?
On Thu, Nov 26, 2020 at 5:41 AM Keith Packard via wrote:
>
>
On 12/9/20 7:07 AM, zhouyang wrote:
> I found some style problems while check the code using checkpatch.pl.
> This commit fixs the issue below:
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: zhouyang
> ---
> fsdev/9p-marshal.h | 12
>
On 08.12.2020 18:47, Peter Xu wrote:
On Fri, Dec 04, 2020 at 12:31:00PM +0300, Andrey Gruzdev wrote:
+static
+WriteTrackingSupport migrate_query_write_tracking(void)
+{
+static WriteTrackingSupport wt_support = WT_SUPPORT_UNKNOWN;
Better to be non-static - consider uncompatible memory can
This patch is to avoid executing migrations twice, which causes
coredump. After the migration has been completed, guest is in postmigrated
status on source host and the block device is inactive. If executing
migration again, it will cause coredump and a block error. For exmaple,
executing
On 08.12.2020 21:24, Peter Xu wrote:
On Fri, Dec 04, 2020 at 12:30:59PM +0300, Andrey Gruzdev wrote:
This patch series is a kind of 'rethinking' of Denis Plotnikov's ideas he's
implemented in his series '[PATCH v0 0/4] migration: add background snapshot'.
Currently the only way to make
> -Original Message-
> From: zhukeqian
> Sent: Wednesday, December 9, 2020 10:57 AM
> To: Peter Maydell ; Igor Mammedov
> ; Eduardo Habkost
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; Wanghaibin (D)
> ; Chenqun (kuhn)
> ; Chenzhendong (alex)
> ; zhukeqian
> Subject: [PATCH] bugfix:
CC for Stefan (nvme block driver co-maintainer).
On Dec 9 05:04, Dmitry Fomichev wrote:
> Define values and structures that are needed to support Zoned
> Namespace Command Set (NVMe TP 4053).
>
> Signed-off-by: Dmitry Fomichev
> ---
> include/block/nvme.h | 114
I found some style problems while check the code using checkpatch.pl.
This commit fixs the issue below:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: zhouyang
---
fsdev/9p-marshal.h | 12
fsdev/file-op-9p.h | 3 +--
2 files changed, 5 insertions(+), 10
This patch addresses this issue:
When accessing a volume on an NFS filesystem without supporting the file lock,
tools, like qemu-img, will complain "Failed to lock byte 100".
In the original code, the qemu_has_ofd_lock will test the lock on the
"/dev/null" pseudo-file. Actually, the file.locking
Hi all,
I want to implement a new USB HID device in QEMU. I found that there exists
`hw/usb/dev-hid.c` on the source tree, but I did not find any further
documentation.
Would you please guide me how I should proceed?
Regards,
Ali
On Wed, Nov 4, 2020 at 21:29 Eduardo Habkost wrote:
> On Sat, Oct 31, 2020 at 09:51:38PM +0530, Ani Sinha wrote:
> > On Thu, Oct 15, 2020 at 10:22 PM Eduardo Habkost
> wrote:
> > >
> > > On Mon, Sep 21, 2020 at 03:03:25PM +0530, Ani Sinha wrote:
> > > > Object property insertion code iterates
在 2020/12/8 上午8:37, Philippe Mathieu-Daudé 写道:
Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
We decode the branch instructions, and all instructions based
on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Double checked opcode
Kevin Wolf 于2020年12月8日周二 下午10:38写道：
>
> Am 08.12.2020 um 13:59 hat Li Feng geschrieben:
> > This patch addresses this issue:
> > When accessing a volume on an NFS filesystem without supporting the file
> > lock,
> > tools, like qemu-img, will complain "Failed to lock byte 100".
> >
> > In the
在 2020/12/8 上午8:36, Philippe Mathieu-Daudé 写道:
Finally, we use decodetree with the MIPS target.
Starting easy with the MSA ASE. 2700+ lines extracted
from helper.h and translate.c, now built as an new
object: mod-msa_translate.o.
While the diff stat is positive by 86 lines, we actually
Daniel P. Berrangé 于2020年12月8日周二 下午9:45写道：
>
> On Tue, Dec 08, 2020 at 08:59:37PM +0800, Li Feng wrote:
> > This patch addresses this issue:
> > When accessing a volume on an NFS filesystem without supporting the file
> > lock,
> > tools, like qemu-img, will complain "Failed to lock byte 100".
>
I found some style problems whil check the code using checkpatch.pl.
This commit fixs the issue below:
ERROR: that open brace { should be on the previous line
Signed-off-by: zhouyang
---
contrib/plugins/howvec.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the issue below:
ERROR: spaces required around that '*'
Signed-off-by: zhouyang
---
contrib/ivshmem-server/main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
v1 -> v2:
Changed the "From:" and "Signed-off-by:" lines from "zhouyang (T)"
to my real name "zhouyang".
I found some style problems while check the code using checkpatch.pl
and fixed them, please review.
zhouyang (5):
contrib: Don't use '#' flag of printf format
contrib: Fix some code
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the misuse of
'#' flag of printf format
Signed-off-by: zhouyang
---
contrib/plugins/hotblocks.c | 2 +-
contrib/plugins/hotpages.c | 2 +-
contrib/plugins/howvec.c| 2
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the issue below:
ERROR: space required after that ','
Signed-off-by: zhouyang
---
contrib/plugins/howvec.c | 12 ++--
1 file changed, 6 insertions(+), 6
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the issue below:
ERROR: "foo * bar" should be "foo *bar"
Signed-off-by: zhouyang
---
contrib/plugins/howvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
In host_memory_backend_get_host_nodes, we build host_nodes
list and output it to v (a StringOutputVisitor) but forget
to free the list. This fixes the memory leak.
The memory leak stack:
==qemu-kvm==209357==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 32 byte(s) in 2 object(s)
Kindly ping!
Hi all,
This series has been sunk for a long time.
Could someone pick them up？
Six patches are sunk here:
qga/channel-posix: Plug memory leak in ga_channel_write_all()
elf2dmp/qemu_elf: Plug memleak in QEMU_Elf_init
elf2dmp/pdb: Plug memleak in pdb_init_from_file
Hi Peter,
Thanks for having a look at it.
On 2020/12/8 23:16, Peter Xu wrote:
Hi, Zenghui,
On Tue, Dec 08, 2020 at 07:40:13PM +0800, Zenghui Yu wrote:
The kernel KVM_CLEAR_DIRTY_LOG interface has align requirement on both the
start and the size of the given range of pages. We have been
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> /* ISA Extensions */
> +#if defined(TARGET_MIPS64)
> +if (ase_msa_available(env) && decode_msa64(ctx, ctx->opcode)) {
> +return;
> +}
> +#endif /* TARGET_MIPS64 */
> if (ase_msa_available(env) && decode_msa32(ctx,
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> +++ b/target/mips/translate_addr_const.c
> @@ -0,0 +1,54 @@
> +/*
> + * Address Computation and Large Constant Instructions
> + */
Missing license. Otherwise,
Reviewed-by: Richard Henderson
r~
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> Missed in previous "Convert MSA to decodetree" series.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 8 +++-
> target/mips/translate.c | 4 ++--
> 2 files changed, 9 insertions(+), 3 deletions(-)
Ack.
r~
On 12/7/20 6:37 PM, Philippe Mathieu-Daudé wrote:
> Now that we can decode the MSA ASE opcodes with decode_msa32(),
> use it and remove the unreachable code.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/fpu_translate.h | 10 --
> target/mips/translate.h | 2
On 12/7/20 6:37 PM, Philippe Mathieu-Daudé wrote:
> Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
>
> We decode the branch instructions, and all instructions based
> on the MSA opcode.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 1
On 12/8/20 6:01 PM, Richard Henderson wrote:
> On 12/8/20 5:56 PM, Richard Henderson wrote:
>> On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
>>> Make gen_msa() and gen_msa_branch() public declarations
>>> so we can keep calling them once extracted from the big
>>> translate.c in the next
On 12/8/20 5:56 PM, Richard Henderson wrote:
> On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
>> Make gen_msa() and gen_msa_branch() public declarations
>> so we can keep calling them once extracted from the big
>> translate.c in the next commit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>>
On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
> Make gen_msa() and gen_msa_branch() public declarations
> so we can keep calling them once extracted from the big
> translate.c in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 2 ++
>
On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
> translate_init.c.inc mostly contains CPU definitions.
> msa_reset() doesn't belong here, move it with the MSA
> helpers.
>
> One comment style is updated to avoid checkpatch.pl warning.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On 12/8/20 12:15 PM, Peter Maydell wrote:
> It's common to want to print a human-readable indication of a clock's
> frequency. Provide a utility function in the clock API to return a
> string which is a displayable representation of the frequency,
> and use it in qdev-monitor.c.
>
> Before:
>
>
On 12/8/20 12:15 PM, Peter Maydell wrote:
> Remove the now-unused clock_get_ns() API and the CLOCK_PERIOD_TO_NS()
> macro that only it was using.
>
> Signed-off-by: Peter Maydell
> ---
> docs/devel/clocks.rst | 17 +
> include/hw/clock.h| 6 --
> 2 files changed, 13
On 12/8/20 12:15 PM, Peter Maydell wrote:
> Currently the MIPS code uses the old clock_get_ns() API to
> calculate a time length in nanoseconds:
> cpu->cp0_count_rate * clock_get_ns(MIPS_CPU(cpu)->clock)
>
> This relies on the clock having a period which is an exact number
> of nanoseconds.
>
>
On 12/8/20 12:15 PM, Peter Maydell wrote:
> The clock_get_ns() API claims to return the period of a clock in
> nanoseconds. Unfortunately since it returns an integer and a
> clock's period is represented in units of 2^-32 nanoseconds,
> the result is often an approximation, and calculating a clock
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 4 +-
target/riscv/csr.c | 182 +---
2 files changed, 97 insertions(+), 89 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 24b24c69c5..1337269ae8 100644
---
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a2787b1d48..1fc9273cea 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
target/riscv/cpu.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 47b738c314..254cd83f8b 100644
--- a/target/riscv/cpu.c
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/spike.c | 45 -
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 875f371f0f..3e47e4579d 100644
--- a/hw/riscv/spike.c
+++
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
include/hw/riscv/virt.h | 6 --
hw/riscv/virt.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b4ed9a32eb..84b7a3848f 100644
The helper functions defined in helper.h specify that the argument is of
type target_long. Let's change the implementation to match the header
definition.
Signed-off-by: Alistair Francis
---
target/riscv/fpu_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9c064f3094..6339e84819 100644
--- a/target/riscv/cpu.h
+++
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/fpu_helper.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
The RISC-V QEMU port currently has lot of preprocessor directives that
check if we are targetting a 32-bit or 64-bit CPU. This means that the
64-bit RISC-V target can not run 32-bit CPUs. This is different to most
other QEMU architectures and doesn't allow us to mix xlens (such as when
running
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 55 -
1 file changed, 30 insertions(+), 25 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d550befadb..7216329237 100644
--- a/hw/riscv/sifive_u.c
+++
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6f032122..47b738c314 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Some FPU translation functions / registers can be used by
> ISA / ASE / extensions out of the big translate.c file.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/fpu_translate.h | 25 +
>
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
hw/riscv/virt.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f8c5509f13..915e9ae216 100644
--- a/hw/riscv/virt.c
+++
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
target/riscv/cpu.c | 33 +++--
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32a6916b8a..7d6f032122 100644
---
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Some CPU translation functions / registers / macros and
> definitions can be used by ISA / ASE / extensions out of
> the big translate.c file. Declare them in "translate.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/spike.h | 6 --
hw/riscv/spike.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index cddeca2e77..cdd1a13011 100644
---
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
include/hw/riscv/boot.h | 8 +++---
hw/riscv/boot.c | 55 ++---
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 3 ++-
hw/riscv/virt.c | 2 +-
5 files
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
target/riscv/cpu.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c0a326c843..9c064f3094 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -44,6
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> This file is not TCG specific, contains CPU definitions
> and is consumed by cpu.c. Rename it as such.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> cpu-defs.c still contains fpu_init()/mvp_init()/msa_reset().
> They are moved out in
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Extract DisasContext to a new 'translate.h' header so
> different translation files (ISA, ASE, extensions)
> can use it.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 50 +
>
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Nothing TCG specific there, move to common cpu code.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/internal.h | 4 -
> target/mips/cpu.c | 243
> target/mips/translate.c | 240
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote:
>
> Currently, host cpu is inherited simply.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> target/riscv/cpu.c | 6 ++
> target/riscv/cpu.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c
On Thu, Dec 3, 2020 at 4:58 AM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
This doesn't seem right. Why do we need to do this? Other
architectures don't seem to do
On 12/8/20 9:00 PM, Philippe Mathieu-Daudé wrote:
> On 12/8/20 8:48 PM, Claudio Fontana wrote:
>> v8 -> v9: move additional methods to CPUClass->tcg_ops
>>
>> do_unaligned_access, transaction_failed and do_interrupt.
>>
>> do_interrupt is a bit tricky, as the same code is reused
>> (albeit not
On 12/7/20 3:52 PM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
> target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
> target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument
Reviewed-by: Richard Henderson
r~
On Thu, Nov 26, 2020 at 07:56:05PM +0100, Klaus Jensen wrote:
> From: Gollu Appalanaidu
>
> Add the Compare command.
>
> This implementation uses a bounce buffer to read in the data from
> storage and then compare with the host supplied buffer.
>
> Signed-off-by: Gollu Appalanaidu
>
On Tue, Dec 8, 2020 at 12:52 PM Claudio Fontana wrote:
>
> for now only TCG is allowed as an accelerator for riscv,
> so remove the CONFIG_TCG use.
>
> Signed-off-by: Claudio Fontana
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 3 +--
> 1 file changed, 1 insertion(+),
On Tue, Dec 08, 2020 at 03:18:54PM -0600, Richard Henderson wrote:
> As for modifying the fast path cases, the code is quite delicate,
> and you run into problems with live registers. Which could be
> worked around in each backend, but... why?
Perhaps thinking that working at IR level would
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> We are going to move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate_init.c.inc | 36
> 1 file changed, 18 insertions(+), 18 deletions(-)
Reviewed-by:
Patchew URL: https://patchew.org/QEMU/20201208194839.31305-1-cfont...@suse.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201208194839.31305-1-cfont...@suse.de
Subject: [RFC v9 00/22] i386 cleanup
=== TEST
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> This file contains functions related to TLB management,
> rename it as 'tlb_helper.c'.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Maybe I missed some functions not TLB specific...
> ---
> target/mips/{helper.c => tlb_helper.c} | 2 +-
>
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> We are very close to build with '--enable-kvm --disable-tcg' :)
> ---
> target/mips/meson.build | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
Aaron Lindsay writes:
> On Dec 08 17:56, Alex Bennée wrote:
>> Aaron Lindsay writes:
>> > On Dec 08 12:17, Alex Bennée wrote:
>> >> For registers I think there needs to be some re-factoring of QEMU's
>> >> internals to do it cleanly. Currently we have each front-end providing
>> >>
On Thu, Dec 3, 2020 at 4:47 AM Yifei Jiang wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> hw/intc/sifive_plic.c| 31 ++-
> target/riscv/kvm.c | 19 +++
>
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> To help understand ifdef'ry, add comment after #endif.
This does more than that.
> @@ -550,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr
> addr)
> }
> return phys_addr;
> }
> -#endif
>
> -#if
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c | 20
> 1 file changed, 8 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c| 33 +
> target/mips/helper.c | 33 -
> 2 files changed, 33 insertions(+), 33 deletions(-)
Reviewed-by: Richard
On Thu, Dec 3, 2020 at 4:57 AM Yifei Jiang wrote:
>
> Currently, time base frequency was fixed as SIFIVE_CLINT_TIMEBASE_FREQ.
> Here introduce "time-frequency" property to set time base frequency
> dynamically
> of which default value is still SIFIVE_CLINT_TIMEBASE_FREQ. The virt machine
> uses
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Move cpu_supports*() and cpu_set_exception_base() from
> translate.c to cpu.c.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c | 18 ++
> target/mips/translate.c | 18 --
> 2 files
On 12/7/20 4:10 AM, Stephane Duverger wrote:
> This leads me to that simple reflection:
>
> If we want to filter on every memory accesses, *out of the fast-path*,
> the most natural place to do so would be in store_helper() and
> load_helper() from accel/tcg/cputlb.c. By doing so, every target
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/fpu_helper.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> target/riscv/kvm.c | 27 ++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/internal.h | 1 +
> target/mips/tlb_helper.c | 46 ++
> target/mips/translate_init.c.inc | 48
> 3 files
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Address translation is an architectural thing (not hardware
> related). Move the helpers from hw/ to target/.
>
> As physical address and KVM are specific to system mode
> emulation, restrict this file to softmmu, so it doesn't
> get compiled
On Tue, Dec 08, 2020 at 10:16:58AM +0100, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Commit 37712e00b1f0 ("hw/block/nvme: factor out pmr setup") changed the
> control flow such that the CAP register is erronously cleared after
> nvme_init_pmr() has configured it. Since the entire NvmeCtrl
On Tue, Dec 08, 2020 at 09:33:39AM +0100, Klaus Jensen wrote:
> +static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *req)
> +{
> +for (i = 0; i < nr; i++) {
> +uint32_t _nlb = le16_to_cpu(range[i].nlb) + 1;
> +if (_nlb > le16_to_cpu(ns->id_ns.mssrl)) {
> +return
On 12/8/2020 2:58 PM, Paolo Bonzini wrote:
On 08/12/20 20:57, Paolo Bonzini wrote:
On 08/12/20 20:14, Alejandro Jimenez wrote:
##
+# @reboot-set-action:
+#
+# Set reboot action
+#
+# Since: 6.0
+##
+{ 'command': 'reboot-set-action', 'data' : {'action':
'RebootAction'} }
+
+##
+#
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> mips_cpu_do_transaction_failed() requires MemTxAttrs
> and MemTxResult declarations.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/internal.h | 1 +
> target/mips/kvm.c | 1 -
> 2 files changed, 1 insertion(+), 1
Add command-line option that lets the SMBIOS entry point type to
be configured.
SMBIOS 3.0 support is necessary to allow us to support more
than 720 VCPUs in x86_64, due to SMBIOS 2.1 table size limits.
Note that it's still up to firmware to decide whether to generate
SMBIOS 2.1 and/or 3.0 entry
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/kvm.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> The rest of helper.c is TLB related. Extract the non TLB
> specific functions to a new file, so we can rename helper.c
> as tlb_helper.c in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Any better name? xxx_helper.c are
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Remove unused headers and add missing "qemu/log.h" since
> qemu_log() is called.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cp0_helper.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips64r6.decode | 6 ++
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/op_helper.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 10:46 PM, LIU Zhiwei wrote:
> For SIMD fcmla(by element), if the number of elements is less than
> the number of elements within one segment，i.e. 4H arrangement,
> we should not calculate the entire segment.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/arm/vec_helper.c | 8
>
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 29 +
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/target/mips/translate.c
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 2 ++
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of
the QEMU 5.2.0 release. This release contains 3200+ commits from 216
authors.
A note from the maintainer:
This is the final release of v5.2.0; there are no changes since rc4.
Note that QEMU has switched build
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h| 8 +
target/mips/translate.c| 35 +++
target/mips/translate_addr_const.c | 54
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 5
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 3 +++
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