On 2020/12/29 21:50, Igor Mammedov wrote:
> On Wed, 23 Dec 2020 17:08:34 +0800
> Jiahui Cen wrote:
> subj
> s/by default//
> s/enable/compile/
>
>> PXB is now supported on ARM, so let's enable it by default.
> s/it by default/for arm_virt machine/
> s/enable/compile/
Thanks for your review.
I
On 2020/12/31 5:17, Michael S. Tsirkin wrote:
> On Tue, Dec 29, 2020 at 02:47:35PM +0100, Igor Mammedov wrote:
>> On Wed, 23 Dec 2020 17:08:33 +0800
>> Jiahui Cen wrote:
>>
>>> The overlap check of IO resource window would fail when Linux kernel
>>> registers an IO resource [b, c) earlier than
On Tue, Dec 29, 2020 at 05:56:17PM +, Mark Cave-Ayland wrote:
> The OpenPIC device is located within the macio device on real hardware so
> make it
> a child of the macio-newworld device. This also removes the need for setting
> and
> checking a separate PIC object property link on the macio-
On Tue, Dec 29, 2020 at 05:56:16PM +, Mark Cave-Ayland wrote:
> In order to move the OpenPIC device to the macio device, the PCI bus needs to
> be
> initialised before the macio device and also before wiring the OpenPIC IRQs.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: David Gibson
>
For some device state having some fields of VMS_ALLOC flag, they
don't free memory allocated for the fields in vmstate_save_state
and vmstate_load_state. We add funcs or sentences of free memory
before and after VM saves or loads device state to avoid memory leak.
v2
- Drop patch1-3,6-8 of v1
-
When VM migrate VMState of configuration, the fields(name and capabilities)
of configuration having a flag of VMS_ALLOC need to allocate memory. If the
src doesn't free memory of capabilities in SaveState after save VMState of
configuration, or the dst doesn't free memory of name and capabilities i
Some memory allocated for fields having a flag of VMS_ALLOC in SaveState
may not free before VM load vmsd in migration. So we pre-free memory before
allocation in vmstate_handle_alloc() to avoid memleaks.
Reported-by: Euler Robot
Signed-off-by: Jinhao Gao
Signed-off-by: Michael S. Tsirkin
---
When VM migrate VMState of spapr_pci, the field(msi_devs) of spapr_pci
having a flag of VMS_ALLOC need to allocate memory. If the src doesn't free
memory of msi_devs in SaveStateEntry of spapr_pci after QEMUFile save
VMState of spapr_pci, it may result in memory leak of msi_devs. We add the
post_sa
On 2020/12/29 21:41, Igor Mammedov wrote:
> On Wed, 23 Dec 2020 17:08:31 +0800
> Jiahui Cen wrote:
>
>> There may be some differences in pci resource assignment between guest os
>> and firmware.
>>
>> Eg. A Bridge with Bus [d2]
>> -+-[:d2]---01.0-[d3]01.0
>>
>> where [d2:01.00]
On 2020/12/29 21:36, Igor Mammedov wrote:
> On Wed, 23 Dec 2020 17:08:30 +0800
> Jiahui Cen wrote:
>
>> AML needs Address Translation offset to describe how a bridge translates
>> addresses accross the bridge when using an address descriptor, and
>> especially on ARM, the translation offset of
kindly ping
On 2020/12/17 11:44, zhouyang (T) wrote:
> kindly ping
>
>> v1 -> v2:
>> Changed the "From:" and "Signed-off-by:" lines from "zhouyang (T)"
>> to my real name "zhouyang".
>>
>> I found some style problems while check the code using checkpatch.pl
>> and fixed them, please review.
>>
>>
On Tue, Dec 22, 2020 at 2:30 PM Bin Meng wrote:
>
> On Thu, Dec 17, 2020 at 1:28 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
> >
> > 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in
> > second word.
>
On Tue, Dec 22, 2020 at 2:24 PM Bin Meng wrote:
>
> On Wed, Dec 16, 2020 at 6:24 PM Bin Meng wrote:
> >
> > Hi Alistair, Peter,
> >
> > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Avoid using a magic number (4) everywhere for the number of chip
> > > s
On 12/30/20 2:10 PM, Richard Henderson wrote:
> On 12/18/20 6:33 AM, remi.denis.courm...@huawei.com wrote:
>> From: Rémi Denis-Courmont
>>
>> Signed-off-by: Rémi Denis-Courmont
>> ---
>> target/arm/helper.c | 14 ++
>> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> The patch do
On 12/18/20 6:33 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 12/18/20 6:33 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> This adds for the Small Translation tables extension in AArch64 state.
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/cpu.h| 5 +
> target/arm/helper.c | 13 ++---
> 2 files c
Chris Hofstaedtler, le mer. 30 déc. 2020 23:17:27 +0100, a ecrit:
> Without this, meson fails with "curses package not usable" when using ncurses
> 6.2. Apparently the wide functions (addwstr, etc) are hidden behind the extra
> define, and meson does not define it at that detection stage.
>
> Regr
Without this, meson fails with "curses package not usable" when using ncurses
6.2. Apparently the wide functions (addwstr, etc) are hidden behind the extra
define, and meson does not define it at that detection stage.
Regression from b01a4fd3bd7d6f2 ("configure: Define NCURSES_WIDECHAR if we're
us
Cocoa support was always shown as "no", even it if was enabled.
Fixes: b4e312e953b ("configure: move cocoa option to Meson")
Cc: Paolo Bonzini
Cc: Peter Maydell
Cc: Philippe Mathieu-Daudé
Signed-off-by: Chris Hofstaedtler
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Qemu's ACPI table generation sets the fields OEM ID and OEM table ID
to "BOCHS " and "BXPC" where "" is replaced by the ACPI
table name.
Some games like Red Dead Redemption 2 seem to check the ACPI OEM ID
and OEM table ID for the strings "BOCHS" and "BXPC" and if they are
found, the game c
On 12/18/20 6:33 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/helper.c | 14 ++
> 1 file changed, 6 insertions(+), 8 deletions(-)
The patch does more than what is described above.
>
> diff --git a/
On Dec 08 14:44, Aaron Lindsay wrote:
> On Dec 08 17:56, Alex Bennée wrote:
> > Aaron Lindsay writes:
> > > On Dec 08 12:17, Alex Bennée wrote:
> > >> Aaron Lindsay writes:
> > >> Memory is a little trickier because you can't know at any point if a
> > >> given virtual address is actually map
On Tue, Dec 29, 2020 at 02:41:42PM +0100, Igor Mammedov wrote:
> On Wed, 23 Dec 2020 17:08:31 +0800
> Jiahui Cen wrote:
>
> > There may be some differences in pci resource assignment between guest os
> > and firmware.
> >
> > Eg. A Bridge with Bus [d2]
> > -+-[:d2]---01.0-[d3]01.0
>
On Tue, Dec 29, 2020 at 02:47:35PM +0100, Igor Mammedov wrote:
> On Wed, 23 Dec 2020 17:08:33 +0800
> Jiahui Cen wrote:
>
> > The overlap check of IO resource window would fail when Linux kernel
> > registers an IO resource [b, c) earlier than another resource [a, b).
> > Though this incorrect ch
Patch fixing strrchr:
https://patchew.org/QEMU/20201230172522.33629-1-richard.hender...@linaro.org/
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1908551
Title:
aarch64 SVE emulation breaks strnlen
There was an inconsistency between encoding, which uses
SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS.
This happened to be ok, until e2e7168a214, which reduced
the size of SIMD_OPRSZ_BITS, which lead to truncating all
predicate vector lengths.
Cc: qemu-sta...@nongnu.org
Buglink: https:/
On Tue, 29 Dec 2020 at 10:38, Thomas Huth wrote:
> On 26/12/2020 10.06, John Paul Adrian Glaubitz wrote:
> > I mean, the whole point of an emulator is being able to run existing code
> > on modern hardware,
> > usually because the old hardware is no longer available. And as long as the
> > targe
On Mon, 28 Dec 2020 at 15:52, Chris Hofstaedtler
wrote:
>
> Without this, meson fails with "curses package not usable"
> when using ncurses 6.2. Apparently the wide functions
> (addwstr, etc) are hidden behind the extra define, and
> meson does not define it at that detection stage.
>
> Signed-off
This eliminates the last user of the PDMA-specific pdma_cur variable which can
now be removed.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 23 ---
include/hw/scsi/esp.h | 1 -
2 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/
Now that PDMA SCSI commands are accumulated in cmdbuf in the same way as normal
commands, the existing logic for locating the start of the SCSI command in
cmdbuf via cmdlen can be used. This enables the PDMA-specific pdma_start and
also get_pdma_buf() to be removed.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 50 --
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 6a3a4cbc80..2b307341ad 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -153,22 +153,45 @
The ESP device already keeps track of the remaining bytes left to transfer via
its TC (transfer counter) register which is decremented for each byte that
is transferred across the SCSI bus.
Switch the transfer logic to use the value of TC instead of dma_left and then
remove dma_left completely.
I
Now that all data is transferred via the FIFO (ti_buf) there is no need to track
the source buffer being used for the data transfer. This also eliminates the
need for a separate subsection for PDMA state migration.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 74 +-
The cmdbuf is really just a copy of FIFO data (including extra message phase
bytes) so its pdma_origin is effectively TI. Fortunately we already know when
we are receiving a SCSI command since do_cmd == 1 which enables us to
distinguish between the two cases in esp_pdma_read()/esp_pdma_write().
Si
Real hardware simply counts down using the in-built TC to determine when the
the PDMA request is complete. Use the TC to determine the PDMA transfer length
which then enables us to remove the redundant pdma_len variable.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 28
This simplifies reading and writing the TC register value without having to
manually shift each individual 8-bit value.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 34 ++
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/sc
PDMA as implemented on the Quadra 800 uses DREQ to load data into the FIFO
up to a maximum of 16 bytes at a time. The MacOS toolbox ROM requires this
because it mixes FIFO and PDMA transfers whilst checking the FIFO status
and counter registers to ensure success.
Signed-off-by: Mark Cave-Ayland
-
The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to
and from the target.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 773fe09c49..b356a65f5c 100
The transfer direction is currently determined by checking the sign of ti_size
but as this series progresses ti_size can be zero at the end of the transfer.
Use the SCSI phase to determine the transfer direction as used in other SCSI
controller implementations.
Signed-off-by: Mark Cave-Ayland
--
This is the first step in removing get_pdma_buf() from esp.c.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 34 --
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 80f7f73002..6a3a4cbc80 100644
--- a/hw/scsi/
Here the updates to async_len and ti_size are moved into the corresponding
esp_pdma_read()/esp_pdma_write() function to eliminate the reference to
pdma_cur in do_dma_pdma_cb().
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 24 ++--
1 file changed, 14 insertions(+), 10 d
Currently the target selection for PDMA is done after the SCSI command has been
delivered which is not correct. Perform target selection as part of the initial
get_cmd() call when the command is submitted: if no target is present, don't
raise DRQ.
If the target is present then switch to the comman
This will become more useful later when trying to debug mixed FIFO and PDMA
requests.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c| 6 ++
hw/scsi/trace-events | 4
2 files changed, 10 insertions(+)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index df15e3e7cf..619c3e9e28 100
ESP SCSI commands are already accumulated in cmdbuf and so there is no need to
keep a separate pdma_buf buffer. Accumulate SCSI commands for PDMA transfers in
cmdbuf instead of pdma_buf so update cmdlen accordingly and change pdma_origin
for PDMA transfers to CMD which allows the PDMA origin to be
The value of dma_counter is set once at the start of the transfer and remains
the same until the transfer is complete. This allows the check in
esp_transfer_data
to be simplified since dma_left will always be non-zero until the transfer is
completed.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/
This better describes the purpose of the function.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 33e3cf657b..50bddc7d68 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -199,7
This simplifies reading the STC register value without having to manually shift
each individual 8-bit value.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 42cbc1da9b..c716
Move the trace event to the end of the function so that it correctly reports
the returned value if it doesn't come directly from the rregs array.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/scsi/esp.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 39c5eeb57c..80f7f73002 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -151,6 +151,20 @@ static uint8_t *get_pd
Perform the length adjustment whereby a value of 0 in the STC represents
a transfer length of 0x1 at the point where the TC is loaded at the
start of a DMA command rather than just when a TI (Transfer Information)
command is executed. This better matches the description as given in the
datashee
This patch series comes from an experimental branch that I've been working on
to try and boot a MacOS toolbox ROM under the QEMU q800 machine. The effort is
far from complete, but it seems worth submitting these patches separately since
they are limited to the ESP device and form a substantial part
The limiting of DMA transfers to the maximum size of the available data is
already
handled by esp_do_dma() and do_dma_pdma_cb().
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
inde
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 52 ++-
1 file changed, 31 insertions(+), 21 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index b84e0fe33e..7073166ad1 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -241,8 +241,9 @@
This enables us to determine whether the command being issued is for a DMA or a
non-DMA transfer.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c| 1 +
hw/scsi/trace-events | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 7073166ad1..5f2c352029
During drive mirror, if the target VM exits abnormally (e.g. killed),
the nbd client (source VM) will receive EOF, finalize the previous
connection (set s->ioc to NULL), and start the reconnect process. After
that, if the source VM tries to cancel the drive mirror, it could
receive signal SIGSEGV
On Thu, Dec 24, 2020 at 06:22:55PM +0100, Greg Kurz wrote:
> Have PSERIES to select XICS and XIVE, and directly check PSERIES
> in hw/intc/meson.build to enable build of the XICS and XIVE sPAPR
> backends, like POWERNV already does. This allows to get rid of the
> intermediate XICS_SPAPR and XIVE_S
On Thu, Dec 24, 2020 at 06:23:03PM +0100, Greg Kurz wrote:
> qemu-system-ppc64 built with --without-default-devices crashes:
>
> Type 'pnv-phb4-root-port' is missing its parent 'pcie-root-port-base'
> Aborted (core dumped)
>
> Have POWERNV to select PCIE_PORT. This is done through a
> new PCI_POW
On Thu, Dec 24, 2020 at 06:22:47PM +0100, Greg Kurz wrote:
> Linking of the qemu-system-ppc64 fails on a POWER9 host when
> --without-default-devices is passed to configure:
>
> $ ./configure --without-default-devices \
> --target-list=ppc64-softmmu && make
>
> ...
>
> libqemu-ppc6
>From a79128e87b0eb1ef4ef0f046ea943a212e62eb6e Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Wed, 30 Dec 2020 10:54:45 +
Subject: [PATCH] osdep: define MADV_DO/DONTDUMP on FreeBSD.
Signed-off-by: David Carlier
---
include/qemu/osdep.h | 4
1 file changed, 4 insertions(+)
diff --g
On Wed, Dec 30, 2020 at 4:25 PM Sylvain Pelissier
wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus
> GDB won't set it properly when attached. The patch implements the target
> description response.
>
> Signed-off-by: Sylvain Pelissier
> ---
> target/riscv
Target description is not currently implemented in RISC-V architecture.
Thus GDB won't set it properly when attached. The patch implements the
target description response.
Signed-off-by: Sylvain Pelissier
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/t
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