12.01.2021 19:42, Kevin Wolf wrote:
+def find_tests(self, groups: Optional[List[str]] = None,
+ exclude_groups: Optional[List[str]] = None,
+ tests: Optional[List[str]] = None,
group and tests seem to be read-only, so this can be simplified to
'groups:
During smart critical warning injection by setting property from QMP
command, also try to trigger asynchronous event.
Signed-off-by: zhenwei pi
---
hw/block/nvme.c | 47 ---
1 file changed, 40 insertions(+), 7 deletions(-)
diff --git
There is a very low probability that hitting physical NVMe disk
hardware critical warning case, it's hard to write & test a monitor
agent service.
For debugging purposes, add a new 'smart_critical_warning' property
to emulate this situation.
The orignal version of this change is implemented by
After PMR initialization, bar.cap should not be clear in function
nvme_init_ctrl. Otherwise the PMR cap would be always disabled.
Signed-off-by: zhenwei pi
---
hw/block/nvme.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 27d2c72716..f361103bb4
According to NVMe spec 1.4 section
, introduce bit 5
for "Persistent Memory Region has become read-only or unreliable".
Signed-off-by: zhenwei pi
---
include/block/nvme.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 3e02d9ca98..f68a88c712
v2 -> v3:
- Introduce "Persistent Memory Region has become read-only or
unreliable"
- Fix overwritten bar.cap
- Check smart critical warning value from QOM.
- Trigger asynchronous event during smart warning injection.
v1 -> v2:
- Suggested by Philippe & Klaus, set/get smart_critical_warning
When building qemu with GCC 11, compiling eth.c file produce following warning:
warning: array subscript 'struct ip6_ext_hdr_routing[0]' is partly outside
array bounds of 'struct ip6_ext_hdr[1]' [-Warray-bounds]
This is caused by retyping from ip6_ext_hdr to ip6_ext_hdr_routing that has more
Compiling qemu using GCC 11 we got several new warnings. To allow
build with --enable-werror, we need to solve issues generating these
warnings.
Signed-of-by: Miroslav Rezanina
v2:
- Patch 2 rewrite to use strpadcpy
- removed Patch 3 (different version sent by Philippe Mathieu-Daudé)
v3:
Using strncpy with length equal to the size of target array, GCC 11
reports following warning:
warning: '__builtin_strncpy' specified bound 256 equals destination size
[-Wstringop-truncation]
We can prevent this warning by using strpadcpy that copies string
up to specified length, zeroes
On 2021/1/14 6:03, Warner Losh wrote:
> While these changes look good, can you submit this against the bsd-user
> repository? White space changes like this in mainline make rebasing harder
> than needed.
>
> https://github.com/qemu-bsd-user/qemu-bsd-user
>
On 13/01/2021 22.56, Michael Forney wrote:
Prior to 2a4b472c3c, sys/signal.h was only included on OpenBSD
(apart from two .c files). The POSIX standard location for this
header is just and in fact, OpenBSD's signal.h includes
sys/signal.h itself.
Unconditionally including on musl causes
On Thu, Jan 14, 2021 at 12:17 AM Michael S. Tsirkin wrote:
>
> On Wed, Jan 13, 2021 at 11:45:40PM +0800, Cindy Lu wrote:
> > Add call back function for configure interrupt.
> > Set the notifier's fd to the kernel driver when vdpa start.
> > also set -1 when vdpa stop. then the kernel will release
14.01.2021 09:14, Vladimir Sementsov-Ogievskiy wrote:
12.01.2021 20:36, Kevin Wolf wrote:
Am 09.01.2021 um 13:26 hat Vladimir Sementsov-Ogievskiy geschrieben:
Add TestEnv class, which will handle test environment in a new python
iotests running framework.
Difference with current ./check
On Thu, Jan 14, 2021 at 12:36 PM Jason Wang wrote:
>
>
> On 2021/1/13 下午11:45, Cindy Lu wrote:
> > Add configure interrupt support in vdpa_vhost. qemu will use the irqfd
> > process to support this feature.
> >
> > These code are all tested in vp-vdpa (support configure interrupt)
> > vdpa_sim
12.01.2021 20:36, Kevin Wolf wrote:
Am 09.01.2021 um 13:26 hat Vladimir Sementsov-Ogievskiy geschrieben:
Add TestEnv class, which will handle test environment in a new python
iotests running framework.
Difference with current ./check interface:
- -v (verbose) option dropped, as it is unused
-
On Thu, Jan 14, 2021 at 12:46 PM Jason Wang wrote:
>
>
> On 2021/1/13 下午11:45, Cindy Lu wrote:
> > Add call back function for configure interrupt.
> > Set the notifier's fd to the kernel driver when vdpa start.
> > also set -1 when vdpa stop. then the kernel will release
> > the related聽resource聽
On Thu, Jan 14, 2021 at 12:43 PM Jason Wang wrote:
>
>
> On 2021/1/13 下午11:45, Cindy Lu wrote:
> > Add support for configure interrupt, use kvm_irqfd_assign and set the
> > gsi to kernel. When the configure notifier was eventfd_signal by host
> > kernel, this will finally inject an msix interrupt
On Thu, Jan 14, 2021 at 12:34 PM Jason Wang wrote:
>
>
> On 2021/1/13 下午11:45, Cindy Lu wrote:
> > Add configure notifier and virtio_set_config_notifier_fd_handler
> > in virtio
> >
> > Signed-off-by: Cindy Lu
> > ---
> > hw/virtio/virtio.c | 25 +
> >
14.01.2021 01:10, Eric Blake wrote:
Commit 54aa3de72e switched multiple sites to use QAPI_LIST_PREPEND
instead of open-coding, but missed a couple of spots.
Signed-off-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
14.01.2021 01:10, Eric Blake wrote:
On first glance, the loop in qmp_query_rx_filter() has early return
paths that could leak any allocation of filter_list from a previous
iteration. But on closer inspection, it is obvious that all of the
early exits are guarded by has_name, and that the bulk
On 2021/1/13 涓嬪崍11:45, Cindy Lu wrote:
Add call back function for configure interrupt.
Set the notifier's fd to the kernel driver when vdpa start.
also set -1 when vdpa stop. then the kernel will release
the related鑱絩esource鑱�
Signed-off-by: Cindy Lu
---
hw/virtio/trace-events|
On 2021/1/13 下午11:45, Cindy Lu wrote:
Add support for configure interrupt, use kvm_irqfd_assign and set the
gsi to kernel. When the configure notifier was eventfd_signal by host
kernel, this will finally inject an msix interrupt to guest
Signed-off-by: Cindy Lu
---
hw/virtio/virtio-pci.c
On 2021/1/13 下午11:45, Cindy Lu wrote:
Add configure interrupt support in vdpa_vhost. qemu will use the irqfd
process to support this feature.
These code are all tested in vp-vdpa (support configure interrupt)
vdpa_sim (not support configure interrupt)
Cindy Lu (4):
virtio:add support in
I hit this today on QEMU head. The problem appears to crop up when:
1. Decoding a VEX instruction (see [1]) that uses the 0x66 mandatory
prefix; and
2. The OSFXSR bit in CR4 is clear (that is, SSE is disabled)
This means that x86_64 instructions such as:
c4 e2 f9 f7 c0
On 2021/1/13 下午11:45, Cindy Lu wrote:
Add configure notifier and virtio_set_config_notifier_fd_handler
in virtio
Signed-off-by: Cindy Lu
---
hw/virtio/virtio.c | 25 +
include/hw/virtio/virtio.h | 5 +
2 files changed, 30 insertions(+)
diff --git
09.01.2021 15:26, Vladimir Sementsov-Ogievskiy wrote:
Add TestEnv class, which will handle test environment in a new python
iotests running framework.
Difference with current ./check interface:
- -v (verbose) option dropped, as it is unused
- -xdiff option is dropped, until somebody complains
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1770724
Title:
e1000
I think there is a difference between doing checkpoints in COLO and live
migration.
The feature of auto-converge is to ensure the success of live migration even
though the dirty page generation speed is faster than data transfer.
but for COLO, we will force the VM to stop when something is doing
ping?
This patch set is submmitted a month ago, and have received no replies.
Did I miss any replies?
The link follows:
http://patchwork.ozlabs.org/project/qemu-devel/cover/20201222082340.67405-1-zhangha...@huawei.com/
Improve expand_vec_shi to use sign-extraction for MO_32.
This allows a single VSPLTISB instruction to load all of
the valid shift constants.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 44
1 file changed, 27 insertions(+), 17
The normal movi opcodes are going away. We need something
for TCI to use internally.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8
tcg/tci.c| 4 ++--
tcg/tci/tcg-target.c.inc | 4 ++--
3 files changed, 12 insertions(+), 4
ping?
This patch set was submitted two weeks ago,and 2 of patches ([1/4], [4/4]) has
been reviewd.
Whose tree should it go via?
Other patches receive no replies.
Did I miss any response?
The link follows:
There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5b0e42be91..8f8badb61c
From: Philippe Mathieu-Daudé
When decodetree.py was added in commit 568ae7efae7, QEMU was
using Python 2 which happily reads UTF-8 files in text mode.
Python 3 requires either UTF-8 locale or an explicit encoding
passed to open(). Now that Python 3 is required, explicit
UTF-8 encoding for
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 108 ++---
1 file changed, 49 insertions(+), 59 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 49bf1386c7..bda727d5ed 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -178,37
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 13 +--
tcg/tcg-op.c | 227 ---
2 files changed, 109 insertions(+), 131 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 901b19f32a..ed8de045e2 100644
---
These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 4
tcg/tcg-op-vec.c | 20
2 files changed, 24 deletions(-)
diff --git a/include/tcg/tcg-op.h
Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hosts.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 9 -
tcg/tcg-op-vec.c | 39 ++-
We must do this before we adjust tcg_out_movi_i32, lest the
under-the-hood poking that we do for icount be broken.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1706b7c776..050f3cb0b1 100644
---
These are now completely covered by mov from a
TYPE_CONST temporary.
Reviewed-by: Alex Bennée
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 3 ---
tcg/optimize.c | 4
tcg/tcg-op-vec.c | 1 -
tcg/tcg.c
Do not allocate a large block for indexing. Instead, allocate
for each temporary as they are seen.
In general, this will use less memory, if we consider that most
TBs do not touch every target register. This also allows us to
allocate TempOptInfo for new temps created during optimization.
Fix this name vs our coding style.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index
Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to
"t1 = -v2, t2 = c - v2". This avoids a serial dependency
between t1 and t2.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 49 +++---
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 51580d51a0..e5dc9d0ca9 100644
---
Prefer TEMP_CONST over anything else.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 16b0aa7229..e42f9c89a8 100644
--- a/tcg/optimize.c
+++
This will reduce the differences between 32-bit and 64-bit hosts,
allowing full 64-bit constants to be created with the same interface.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
tcg/tcg.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.
Not used yet, this is all infrastructure.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 24 -
tcg/optimize.c| 13 ++-
tcg/tcg.c | 224
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg-op-gvec.c | 129 ++
tcg/tcg.c | 8 +++
3 files changed, 60 insertions(+), 78 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index eeeb70ad43..504c5e9bb0
This propagates the extended value of TCGTemp.val that we did before.
In addition, it will be required for vector constants.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 40 +---
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git
In most, but not all, places that we check for TEMP_FIXED,
we are really testing that we do not modify the temporary.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 5 +
tcg/tcg.c | 21 ++---
2
The temp_fixed, temp_global, temp_local bits are all related.
Combine them into a single enumeration.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 20 +---
tcg/optimize.c| 8 +--
tcg/tcg.c | 126
While we don't store more than tcg_target_long in TCGTemp,
we shouldn't be limited to that for code generation. We will
be able to use this for INDEX_op_dup2_vec with 2 constants.
Also pass along the minimal vece that may be said to apply
to the constant. This allows some simplification in the
Having dupi pass though movi is confusing and arguably wrong.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 6 +++-
tcg/aarch64/tcg-target.c.inc | 7
tcg/i386/tcg-target.c.inc| 63
The following changes since commit 45240eed4f064576d589ea60ebadf3c11d7ab891:
Merge remote-tracking branch 'remotes/armbru/tags/pull-yank-2021-01-13' into
staging (2021-01-13 14:19:24 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210113
No because of macOS weirdness you still have to map with RWX and MAP_JIT
before you can use this. Split w^x is only useful in iOS where they don’t
provide this functionality.
-j
On Wednesday, January 13, 2021, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/12/21 5:28 PM, Roman
loongson3_virt has KVM SMP support in kenrel.
This patch adds TCG SMP support by enable IPI controller
for machine.
Note that TCG SMP can only support up to 4 CPUs as we
didn't implement multi-node support.
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.h | 1 +
On 1/12/21 5:28 PM, Roman Bolshakov wrote:
> Pages can't be both write and executable at the same time on Apple
> Silicon. macOS provides public API to switch write protection [1] for
> JIT applications, like TCG.
So... considering that split w^x is now upstream, can we just call this once
per
Loongson IPI controller is a MMIO based simple level triggered
interrupt controller. It will trigger IRQ to it's upstream
processor when set register is written.
It also has 4 64bit mailboxes to pass boot information to
secondary processor.
Signed-off-by: Jiaxun Yang
---
v2:
- Use enum instead of define (f4bug)
- Comment about num mbox (f4bug)
- Use trace instead of log (f4bug)
- Correct register size (f4bug)
Jiaxun Yang (2):
hw/intc: Add Loongson Inter Processor Interrupt controller
hw/mips/loongson3_virt: Add TCG SMP support
hw/mips/loongson3_bootp.h
Hi Michael,
On 2021/1/13 22:00, Michael S. Tsirkin wrote:
> On Thu, Jan 07, 2021 at 07:40:37PM +0800, Jiahui Cen wrote:
>> Commit fe1127da11 ("unit-test: Add the binary file and clear diff.h") does
>> not
>> use the up-to-date expected file for pxb for ARM virt.
>>
>> Fix the expected DSDT.pxb
On 1/13/21 7:29 PM, Eduardo Habkost wrote:
On Wed, Jan 13, 2021 at 06:04:29PM -0500, John Snow wrote:
On 1/13/21 11:12 AM, Markus Armbruster wrote:
John Snow writes:
...
I think we need to, yes; or we probably really, really want to. Making the
info parameter optional really adds a lot
On Wed, Jan 13, 2021 at 06:04:29PM -0500, John Snow wrote:
> On 1/13/21 11:12 AM, Markus Armbruster wrote:
> > John Snow writes:
> >
> > > Signed-off-by: John Snow
> > >
> > > ---
> > >
> > > The event_enum_members change might become irrelevant after a
> > > forthcoming (?) patch by Markus,
On 1/13/21 7:24 AM, Philippe Mathieu-Daudé wrote:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld8s_i64:
> -tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
> +tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2);
> tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
On 1/13/21 6:45 PM, BALATON Zoltan wrote:
Please don't. That would break all scripts that already call qemu using
single dash options. Forcing everyone to edit their scripts is not nice.
How about also accepting single dash in qemu-img for consistency then
you can use whatever you want in
On 1/13/21 6:20 PM, Eric Blake wrote:
On 1/9/21 6:26 AM, Vladimir Sementsov-Ogievskiy wrote:
Just use classes introduced in previous three commits. Behavior
difference is described in these three commits.
Drop group file, as it becomes unused.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
On Thu, Dec 31, 2020 at 3:53 AM Bin Meng wrote:
>
> From: Bin Meng
>
> Add RISC-V system emulator documentation for generic information.
> `Board-specific documentation` and `RISC-V CPU features` are only
> a placeholder and will be added in the future.
>
> Signed-off-by: Bin Meng
This is
At least some s390 cpu models support "Protected Virtualization" (PV),
a mechanism to protect guests from eavesdropping by a compromised
hypervisor.
This is similar in function to other mechanisms like AMD's SEV and
POWER's PEF, which are controlled by the "confidential-guest-support"
machine
While we've abstracted some (potential) differences between mechanisms for
securing guest memory, the initialization is still specific to SEV. Given
that, move it into x86's kvm_arch_init() code, rather than the generic
kvm_init() code.
Signed-off-by: David Gibson
---
accel/kvm/kvm-all.c |
On Thu, Dec 31, 2020 at 3:42 AM Bin Meng wrote:
>
> From: Bin Meng
>
> This adds detailed documentation for RISC-V `sifive_u` machine,
> including the following information:
>
> - Supported devices
> - Hardware configuration information
> - Boot options
> - Machine-specific options
> - Running
We haven't yet implemented the fairly involved handshaking that will be
needed to migrate PEF protected guests. For now, just use a migration
blocker so we get a meaningful error if someone attempts this (this is the
same approach used by AMD SEV).
Signed-off-by: David Gibson
Reviewed-by: Dr.
On Fri, Nov 6, 2020 at 2:36 AM Alex Bennée wrote:
>
>
> Palmer Dabbelt writes:
>
> > On Thu, 22 Oct 2020 17:56:38 PDT (-0700), alistai...@gmail.com wrote:
> >> On Thu, Oct 22, 2020 at 4:58 PM Moises Arreola
> >> wrote:
> >>>
> >>> Hello everyone, my name is Moses and I'm trying to set up a VM
On Wed, Jan 13, 2021 at 10:30:47AM +0300, Maxim Uvarov wrote:
> - the same size for secure and non secure gpio. Arm doc says that
> secure memory is also split on 4k pages. So one page here has to be
> ok.
To be clear, does that means 4k pages must be used? I'm not concerned
with the size, but
The platform specific details of mechanisms for implementing
confidential guest support may require setup at various points during
initialization. Thus, it's not really feasible to have a single cgs
initialization hook, but instead each mechanism needs its own
initialization calls in arch or
Some upcoming POWER machines have a system called PEF (Protected
Execution Facility) which uses a small ultravisor to allow guests to
run in a way that they can't be eavesdropped by the hypervisor. The
effect is roughly similar to AMD SEV, although the mechanisms are
quite different.
Most of the
The default behaviour for virtio devices is not to use the platforms normal
DMA paths, but instead to use the fact that it's running in a hypervisor
to directly access guest memory. That doesn't work if the guest's memory
is protected from hypervisor access, such as with AMD's SEV or POWER's PEF.
On Wed, Jan 13, 2021 at 07:57:41AM +0100, Christian Borntraeger wrote:
>
>
> On 13.01.21 01:57, David Gibson wrote:
> > On Tue, Jan 12, 2021 at 12:36:07PM +0100, Cornelia Huck wrote:
> > 65;6201;1c> On Tue, 12 Jan 2021 09:15:26 +0100
> >> Christian Borntraeger wrote:
> >>
> >>> On 12.01.21
When the "memory-encryption" property is set, we also disable KSM
merging for the guest, since it won't accomplish anything.
We want that, but doing it in the property set function itself is
thereoretically incorrect, in the unlikely event of some configuration
environment that set the property
Now that we've implemented a generic machine option for configuring various
confidential guest support mechanisms:
1. Update docs/amd-memory-encryption.txt to reference this rather than
the earlier SEV specific option
2. Add a docs/confidential-guest-support.txt to cover the generalities
This allows failures to be reported richly and idiomatically.
Signed-off-by: David Gibson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Cornelia Huck
---
accel/kvm/kvm-all.c | 4 +++-
accel/kvm/sev-stub.c | 2 +-
include/sysemu/sev.h | 2 +-
From: Greg Kurz
Global properties have an @optional field, which allows to apply a given
property to a given type even if one of its subclasses doesn't support
it. This is especially used in the compat code when dealing with the
"disable-modern" and "disable-legacy" properties and the
Currently the "memory-encryption" property is only looked at once we
get to kvm_init(). Although protection of guest memory from the
hypervisor isn't something that could really ever work with TCG, it's
not conceptually tied to the KVM accelerator.
In addition, the way the string property is
A number of hardware platforms are implementing mechanisms whereby the
hypervisor does not have unfettered access to guest memory, in order
to mitigate the security impact of a compromised hypervisor.
AMD's SEV implements this with in-cpu memory encryption, and Intel has
its own memory encryption
When AMD's SEV memory encryption is in use, flash memory banks (which are
initialed by pc_system_flash_map()) need to be encrypted with the guest's
key, so that the guest can read them.
That's abstracted via the kvm_memcrypt_encrypt_data() callback in the KVM
state.. except, that it doesn't
Several architectures have mechanisms which are designed to protect guest
memory from interference or eavesdropping by a compromised hypervisor. AMD
SEV does this with in-chip memory encryption and Intel's MKTME can do
similar things. POWER's Protected Execution Framework (PEF) accomplishes a
On Thu, 7 Jan 2021 14:34:23 +0100
David Hildenbrand wrote:
> We support coordinated discarding of RAM using the RamDiscardMgr. Let's
> unlock support for coordinated discards, keeping uncoordinated discards
> (e.g., via virtio-balloon) disabled.
>
> This unlocks virtio-mem + vfio. Note that
On Wed, 13 Jan 2021, John Snow wrote:
On 1/13/21 5:15 PM, Eric Blake wrote:
On 1/13/21 3:42 PM, John Snow wrote:
On 1/13/21 4:48 AM, Stefan Hajnoczi wrote:
QEMU options are single dash with double dash accepted for
compatibility but
help and other docs have single dash so these (and below)
On Thu, 7 Jan 2021 14:34:18 +0100
David Hildenbrand wrote:
> Although RamDiscardMgr can handle running into the maximum number of
> DMA mappings by propagating errors when creating a DMA mapping, we want
> to sanity check and warn the user early that there is a theoretical setup
> issue and
On Thu, 7 Jan 2021 14:34:17 +0100
David Hildenbrand wrote:
> Let's query the maximum number of possible DMA mappings by querying the
> available mappings when creating the container (before any mappings are
> created). We'll use this informaton soon to perform some sanity checks
> and warn the
Cc'ing qemu-trivial@
On 1/13/21 11:08 PM, John Snow wrote:
> On 10/30/20 11:34 AM, John Snow wrote:
>>
>>
>> John Snow (2):
>> MAINTAINERS: Remove Ben Warren
>> MAINTAINERS: Make status spellings consistent
>>
>> MAINTAINERS | 13 ++---
>> 1 file changed, 6 insertions(+), 7
On Thu, 7 Jan 2021 14:34:16 +0100
David Hildenbrand wrote:
> Implement support for RamDiscardMgr, to prepare for virtio-mem
> support. Instead of mapping the whole memory section, we only map
> "populated" parts and update the mapping when notified about
> discarding/population of memory via
On 1/12/21 3:05 PM, Wainer dos Santos Moschetta wrote:
> Hi,
>
> On 1/11/21 11:07 PM, Jiaxun Yang wrote:
>> Test booting of PMON bootloader on loongson3-virt platform.
>>
>> $ (venv) AVOCADO_ALLOW_UNTRUSTED_CODE=1 \
>> avocado --show=app,console \
>> run -t machine:loongson3-virt
On 1/9/21 6:26 AM, Vladimir Sementsov-Ogievskiy wrote:
> Just use classes introduced in previous three commits. Behavior
> difference is described in these three commits.
>
> Drop group file, as it becomes unused.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> tests/qemu-iotests/check
On 1/9/21 6:26 AM, Vladimir Sementsov-Ogievskiy wrote:
> Add python script with new logic of searching for tests:
>
> Current ./check behavior:
> - tests are named [0-9][0-9][0-9]
> - tests must be registered in group file (even if test doesn't belong
>to any group, like 142)
>
>
> This
On 1/13/21 5:15 PM, Eric Blake wrote:
On 1/13/21 3:42 PM, John Snow wrote:
On 1/13/21 4:48 AM, Stefan Hajnoczi wrote:
QEMU options are single dash with double dash accepted for
compatibility but
help and other docs have single dash so these (and below) should be
-trace.
(Also a bit less typing
Hi Jiaxun,
On 1/12/21 4:32 AM, Jiaxun Yang wrote:
> Loongson IPI controller is a MMIO based simple level triggered
> interrupt controller. It will trigger IRQ to it's upstream
> processor when set register is written.
>
> It also has 8 32bit mailboxes to pass boot information to
> secondary
On 1/13/21 11:12 AM, Markus Armbruster wrote:
John Snow writes:
Signed-off-by: John Snow
---
The event_enum_members change might become irrelevant after a
forthcoming (?) patch by Markus, but didn't have it in-hand at time of
publishing.
It's in my "[PATCH 00/11] Drop support for QAPIGen
On 1/9/21 6:26 AM, Vladimir Sementsov-Ogievskiy wrote:
> We are going to drop group file. Define group in tests as a preparatory
> step.
>
> The patch is generated by
>
> cd tests/qemu-iotests
>
> grep '^[0-9]\{3\} ' group | while read line; do
> file=$(awk '{print $1}' <<<
On 1/9/21 6:26 AM, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> tests/qemu-iotests/294 | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Eric Blake
>
> diff --git a/tests/qemu-iotests/294 b/tests/qemu-iotests/294
> index 87da35db49..4c375ed609
On 1/9/21 6:26 AM, Vladimir Sementsov-Ogievskiy wrote:
> All other test files are executable. Fix these.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> tests/qemu-iotests/283 | 0
> tests/qemu-iotests/298 | 0
> tests/qemu-iotests/299 | 0
> 3 files changed, 0 insertions(+), 0
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