On 02/02/21 01:18, Eduardo Habkost wrote:
On Tue, Feb 02, 2021 at 12:28:38AM +0100, Paolo Bonzini wrote:
Il mar 2 feb 2021, 00:05 Eduardo Habkost ha scritto:
On Mon, Feb 01, 2021 at 11:59:48PM +0100, Paolo Bonzini wrote:
Il lun 1 feb 2021, 23:54 Eduardo Habkost ha
scritto:
Not having a
The following changes since commit 74208cd252c5da9d867270a178799abd802b9338:
Merge remote-tracking branch
'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-01-29
19:51:25 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git
Kevin Wolf writes:
> Am 01.02.2021 um 17:15 hat Markus Armbruster geschrieben:
>> monitor_qmp_dispatcher_co() needs to resume the monitor if
>> handle_qmp_command() suspended it. Two cases:
>>
>> 1. OOB enabled: suspended if mon->qmp_requests has no more space
>>
>> 2. OOB disabled: suspended
On 02.02.2021 10:27, Marc-André Lureau wrote:
Hi
On Tue, Feb 2, 2021 at 11:18 AM Pavel Dovgalyuk
mailto:pavel.dovgal...@ispras.ru>> wrote:
This patch checks that ioc is not null before
using it in tcp socket tcp_chr_add_watch function.
Signed-off-by: Pavel Dovgalyuk
Hi
On Tue, Feb 2, 2021 at 11:18 AM Pavel Dovgalyuk
wrote:
> This patch checks that ioc is not null before
> using it in tcp socket tcp_chr_add_watch function.
>
> Signed-off-by: Pavel Dovgalyuk
>
Do you have a backtrace or a reproducer when this happens?
thanks
---
> chardev/char-socket.c |
Apologies.
Host OS is Big Sur Mac OS X latest - with Xcode latest. Qemu is 5.2 - tar ball
directly from the website.
- Compile Qemu on Mac OS/Big Sur - completely stock build : install Ninja,
mkdir build && cd build && ../configure && make && make install
- But also the issue is with the
Apologies.
Host OS is Big Sur Mac OS X latest - with Xcode latest. Qemu is 5.2 - tar ball
directly from the website.
- Compile Qemu on Mac OS/Big Sur - completely stock build : install Ninja,
mkdir build && cd build && ../configure && make && make install
- But also the issue is with the
This patch checks that ioc is not null before
using it in tcp socket tcp_chr_add_watch function.
Signed-off-by: Pavel Dovgalyuk
---
chardev/char-socket.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/chardev/char-socket.c b/chardev/char-socket.c
index 213a4c8dd0..cef1d9438f 100644
02.02.2021 05:56, Eric Blake wrote:
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
We want 64bit write-zeroes, and for this, convert all io functions to
64bit.
We chose signed type, to be consistent with off_t (which is signed) and
with possibility for signed return type
On Sunday, 31 January, 2021, 08:48:26 pm IST, Philippe Mathieu-Daudé
wrote:
>Forwarding to qemu-security@ to see if this issue is worth a CVE.
>
> | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote:
> | > Per the ARM Generic Interrupt Controller Architecture specification
> | > (document "ARM
> Subject: [PATCH 1/1] virtiofsd: Allow to build it without the tools
>
> This changed the Meson build script to allow virtiofsd be built even
> though the tools build is disabled, thus honoring the --enable-virtiofsd
> option.
>
> Signed-off-by: Wainer dos Santos Moschetta
I misunderstood
SHA-1: 94c13c1048378cbffe552b6fe5c960dc04eaefb2
* gcrypt: test_tls_psk_init should write binary file instead text file.
On windows, if open file with "w", it's will automatically convert
"\n" to "\r\n" when writing to file.
Signed-off-by: Yonggang Luo
Is this related?
On Wed, Jan 27, 2021 at
Please provide more information: How did you compile QEMU? Which version
did you exactly use? And most important: How do you *run* QEMU? System
emulation? User mode? What kind of FTP are you doing??
** Changed in: qemu
Status: New => Incomplete
--
You received this bug notification
On Fri, Jan 29, 2021 at 09:53:27AM +, Daniel P. Berrangé wrote:
> On Fri, Jan 29, 2021 at 11:43:32AM +0300, Roman Bolshakov wrote:
> > On Wed, Jan 27, 2021 at 06:59:17PM +, Daniel P. Berrangé wrote:
> > > On Wed, Jan 27, 2021 at 07:56:16PM +0100, Stefan Weil wrote:
> > > > Am 27.01.21 um
BTW, the RISC-V MMU code _does_ get this right and the model could be
followed by the x86 version - - something like
https://github.com/vsrinivas/qemu/commit/1efa7dc689c4572d8fe0880ddbe44ec22f8f4348,
(but with more compiling + working) might solve this problem and more
closely model h/w.
--
You
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1903752
Title:
At least some s390 cpu models support "Protected Virtualization" (PV),
a mechanism to protect guests from eavesdropping by a compromised
hypervisor.
This is similar in function to other mechanisms like AMD's SEV and
POWER's PEF, which are controlled by the "confidential-guest-support"
machine
Some upcoming POWER machines have a system called PEF (Protected
Execution Facility) which uses a small ultravisor to allow guests to
run in a way that they can't be eavesdropped by the hypervisor. The
effect is roughly similar to AMD SEV, although the mechanisms are
quite different.
Most of the
This allows failures to be reported richly and idiomatically.
Signed-off-by: David Gibson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Cornelia Huck
---
accel/kvm/kvm-all.c | 4 +++-
accel/kvm/sev-stub.c | 2 +-
include/sysemu/sev.h | 2 +-
We haven't yet implemented the fairly involved handshaking that will be
needed to migrate PEF protected guests. For now, just use a migration
blocker so we get a meaningful error if someone attempts this (this is the
same approach used by AMD SEV).
Signed-off-by: David Gibson
Reviewed-by: Dr.
The default behaviour for virtio devices is not to use the platforms normal
DMA paths, but instead to use the fact that it's running in a hypervisor
to directly access guest memory. That doesn't work if the guest's memory
is protected from hypervisor access, such as with AMD's SEV or POWER's PEF.
While we've abstracted some (potential) differences between mechanisms for
securing guest memory, the initialization is still specific to SEV. Given
that, move it into x86's kvm_arch_init() code, rather than the generic
kvm_init() code.
Signed-off-by: David Gibson
Reviewed-by: Cornelia Huck
Currently the "memory-encryption" property is only looked at once we
get to kvm_init(). Although protection of guest memory from the
hypervisor isn't something that could really ever work with TCG, it's
not conceptually tied to the KVM accelerator.
In addition, the way the string property is
The platform specific details of mechanisms for implementing
confidential guest support may require setup at various points during
initialization. Thus, it's not really feasible to have a single cgs
initialization hook, but instead each mechanism needs its own
initialization calls in arch or
Now that we've implemented a generic machine option for configuring various
confidential guest support mechanisms:
1. Update docs/amd-memory-encryption.txt to reference this rather than
the earlier SEV specific option
2. Add a docs/confidential-guest-support.txt to cover the generalities
When the "memory-encryption" property is set, we also disable KSM
merging for the guest, since it won't accomplish anything.
We want that, but doing it in the property set function itself is
thereoretically incorrect, in the unlikely event of some configuration
environment that set the property
From: Greg Kurz
Global properties have an @optional field, which allows to apply a given
property to a given type even if one of its subclasses doesn't support
it. This is especially used in the compat code when dealing with the
"disable-modern" and "disable-legacy" properties and the
Several architectures have mechanisms which are designed to protect
guest memory from interference or eavesdropping by a compromised
hypervisor. AMD SEV does this with in-chip memory encryption and
Intel's TDX can do similar things. POWER's Protected Execution
Framework (PEF) accomplishes a
When AMD's SEV memory encryption is in use, flash memory banks (which are
initialed by pc_system_flash_map()) need to be encrypted with the guest's
key, so that the guest can read them.
That's abstracted via the kvm_memcrypt_encrypt_data() callback in the KVM
state.. except, that it doesn't
A number of hardware platforms are implementing mechanisms whereby the
hypervisor does not have unfettered access to guest memory, in order
to mitigate the security impact of a compromised hypervisor.
AMD's SEV implements this with in-cpu memory encryption, and Intel has
its own memory encryption
在 2021/1/27 下午2:54, Jiaxun Yang 写道:
v2:
A big reconstruction. rewrite helpers with CPU feature and sepreate
changesets.
v3:
respin
ping?
Jiaxun Yang (4):
hw/mips: Add a bootloader helper
hw/mips: Use bl_gen_kernel_jump to generate bootloaders
hw/mips/malta: Use bootloader helper to
Running #qemu-system-i386 test.img -monitor stdio -incoming tcp:0.0.0.0:1234
(qemu) savevm
we get:
before the patch:
bdrv_co_pwritev: Assertion `!(bs->open_flags & 0x0800)' failed.
Aborted
after:
Error: Guest is waiting for an incoming migration
Signed-off-by: lichun
---
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_physical_address() calls get_seg_physical_address() and
get_segctl_physical_address() passing a MMUAccessType type.
Let the prototypes use it as argument, as it is stricter than
an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by:
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_seg_physical_address() calls CPUMIPSTLBContext::map_address()
handlers passing a MMUAccessType type. Update the prototype
handlers to take a MMUAccessType argument, as it is stricter than
an integer.
Signed-off-by: Philippe Mathieu-Daudé
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
All these functions:
- mips_cpu_get_phys_page_debug()
- cpu_mips_translate_address()
- mips_cpu_tlb_fill()
- page_table_walk_refill()
- walk_directory()
call get_physical_address() passing a MMUAccessType type. Let the
prototype use it as argument,
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass
MMUAccessType to raise_mmu_exception(). Let the prototype use it
as argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
The single caller, do_translate_address(), passes MMUAccessType
to cpu_mips_translate_address(). Let the prototype use it as
argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
The single caller, HELPER_LD_ATOMIC(), passes MMUAccessType to
do_translate_address(). Let the prototype use it as argument,
as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
The single caller, mips_cpu_tlb_fill(), passes MMUAccessType
to page_table_walk_refill(). Let the prototype use it as
argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/op_helper.c | 2 +-
target/mips/tlb_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/op_helper.c
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
Remove these confusing and unused definitions.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/cpu.h | 16
1 file changed, 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
On 2021/2/1 下午4:28, Eugenio Perez Martin wrote:
On Mon, Feb 1, 2021 at 7:13 AM Jason Wang wrote:
On 2021/1/30 上午4:54, Eugenio Pérez wrote:
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost.h | 1 +
hw/virtio/vhost.c | 17 +
2 files changed, 18
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 22 +-
1 file changed, 9
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_segctl_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 20 ++--
1 file changed, 10
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_seg_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
TLB map_address() handlers don't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/internal.h | 8
target/mips/tlb_helper.c | 15
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> We want 64bit write-zeroes, and for this, convert all io functions to
> 64bit.
>
> We chose signed type, to be consistent with off_t (which is signed) and
> with possibility for signed return type (where negative value means
On Tue, Jan 19, 2021 at 09:16:08AM +0100, Cornelia Huck wrote:
> On Mon, 18 Jan 2021 19:47:30 +
> "Dr. David Alan Gilbert" wrote:
>
> > * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > > The platform specific details of mechanisms for implementing
> > > confidential guest support may
Patchew URL:
https://patchew.org/QEMU/20210202005948.241655-1-ben.widaw...@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210202005948.241655-1-ben.widaw...@intel.com
Subject: [RFC PATCH v3 00/31] CXL 2.0
Hi Philippe,
On 2021/2/1 23:14, Philippe Mathieu-Daudé wrote:
> Hi,
>
> On 12/17/20 2:49 AM, Keqian Zhu wrote:
>> The parameters start and size are transfered from QEMU memory
>> emulation layer. It can promise that they are TARGET_PAGE_SIZE
>> aligned. However, KVM needs they are
This patch allows initializing the primary host bridge as a CXL capable
hostbridge.
Signed-off-by: Ben Widawsky
--
This patch is WIP.
---
hw/arm/virt.c| 1 +
hw/core/machine.c| 26 ++
hw/i386/acpi-build.c | 8 +++-
hw/i386/microvm.c| 1 +
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
---
hw/cxl/cxl-mailbox-utils.c | 65 ++
1 file changed, 65
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
We are currently in the process of trying to define a new definition for
_OSC. See later work for an
Signed-off-by: Ben Widawsky
---
tests/qtest/cxl-test.c | 93 +
tests/qtest/meson.build | 4 ++
2 files changed, 97 insertions(+)
create mode 100644 tests/qtest/cxl-test.c
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
new file mode 100644
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a normal PCIe device,
In a bare metal CXL capable system, system firmware will program
physical address ranges on the host. This is done by programming
internal registers that aren't typically known to OS. These address
ranges might be contiguous or interleaved across host bridges.
For a QEMU guest a new construct is
Signed-off-by: Ben Widawsky
---
hw/cxl/cxl-mailbox-utils.c | 50 +
hw/mem/cxl_type3.c | 56 -
include/hw/cxl/cxl_device.h | 9 ++
3 files changed, 114 insertions(+), 1 deletion(-)
diff --git
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to a
specific CXL host
Scope (_SB)
{
Device (PCI0)
{
Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
-Name (_ADR, Zero) // _ADR: Address
Name (_UID, Zero) // _UID: Unique ID
+Name (_ADR, Zero) // _ADR: Address
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
---
hw/cxl/cxl-mailbox-utils.c | 4
hw/mem/cxl_type3.c | 24 +---
include/hw/cxl/cxl.h| 1 -
include/hw/cxl/cxl_device.h | 24
For all host bridges, reserve MMIO space with _CRS. The MMIO for the
host bridge lives in a magically hard coded space in the system's
physical address space. The standard mechanism to tell the OS about
regions which can't be used for host bridges is _CRS.
Signed-off-by: Ben Widawsky
---
Signed-off-by: Ben Widawsky
---
tests/data/acpi/pc/CEDT | 0
tests/data/acpi/q35/CEDT| 0
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
3 files changed, 2 insertions(+)
create mode 100644 tests/data/acpi/pc/CEDT
create mode 100644
Signed-off-by: Ben Widawsky
---
tests/qtest/bios-tables-test-allowed-diff.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..5c695cdf37 100644
---
Signed-off-by: Ben Widawsky
---
tests/data/acpi/pc/CEDT | Bin 0 -> 36 bytes
tests/data/acpi/q35/CEDT| Bin 0 -> 36 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 files changed, 2 deletions(-)
diff --git a/tests/data/acpi/pc/CEDT
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct
This cleanup will make it easier to add support for CXL to the mix.
Signed-off-by: Ben Widawsky
---
hw/i386/acpi-build.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f56d699c7f..cf6eb54c22
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an operating system that
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware software
is able to
Per spec, timestamp appears to be a free-running counter from a value
set by the host via the Set Timestamp command (0301h). There are
references to the epoch, which seem like a red herring. Therefore, the
implementation implements the timestamp as freerunning counter from the
last value that was
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
commands are supported. It
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky
---
hw/pci-bridge/pci_expander_bridge.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly program
the HDMs,
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignment are managed by
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulated may want to handle
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO.
Signed-off-by: Ben Widawsky
--
It's arbitrarily chosen here to pick 0xD000 as the base for the host
bridge MMIO. I'm not sure what the right way to find free space for
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically catered towards the
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit communication
between
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky
---
hw/cxl/cxl-mailbox-utils.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git
Currently, QEMU makes _UID equivalent to the bus number (_BBN). While
there is nothing wrong with doing it this way, CXL spec has a heavy
reliance on _UID to identify host bridges and there is no link to the
bus number. Having a distinct UID solves two problems. The first is it
gets us around the
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of as a PCIe device
Major changes since v2 [1]:
* Removed all register endian/alignment/size checking. Using core functionality
instead. This untested on big endian hosts, but Should Work(tm).
* Fix component capability header generation (off by 1).
* Fixed HDM programming (multiple issues).
* Fixed timestamp
A CXL 2.0 component is any entity in the CXL topology. All components
have a analogous function in PCIe. Except for the CXL host bridge, all
have a PCIe config space that is accessible via the common PCIe
mechanisms. CXL components are enumerated via DVSEC fields in the
extended PCIe header space.
On Tue, Feb 02, 2021 at 12:28:38AM +0100, Paolo Bonzini wrote:
> Il mar 2 feb 2021, 00:05 Eduardo Habkost ha scritto:
>
> > On Mon, Feb 01, 2021 at 11:59:48PM +0100, Paolo Bonzini wrote:
> > > Il lun 1 feb 2021, 23:54 Eduardo Habkost ha
> > scritto:
> > >
> > > > Not having a feature name in
Peter Maydell writes:
> On Mon, 1 Feb 2021 at 20:09, Alex Bennée wrote:
>>
>>
>> Peter Maydell writes:
>>
>> > On Thu, 28 Jan 2021 at 18:53, Alex Bennée wrote:
>> >>
>> >> The wiki and the web are curiously absent of the right runes to boot a
>> >> vexpress model so I had to work from first
Il mar 2 feb 2021, 00:05 Eduardo Habkost ha scritto:
> On Mon, Feb 01, 2021 at 11:59:48PM +0100, Paolo Bonzini wrote:
> > Il lun 1 feb 2021, 23:54 Eduardo Habkost ha
> scritto:
> >
> > > Not having a feature name in feature_word_info breaks error
> > > reporting and query-cpu-model-expansion.
On Mon, Feb 01, 2021 at 11:59:48PM +0100, Paolo Bonzini wrote:
> Il lun 1 feb 2021, 23:54 Eduardo Habkost ha scritto:
>
> > Not having a feature name in feature_word_info breaks error
> > reporting and query-cpu-model-expansion. Add the missing feature
> > name to
Il lun 1 feb 2021, 22:15 Wainer dos Santos Moschetta
ha scritto:
> Not too long ago (QEMU 5.0) it was possible to configure with
> --disable-tools
> and still have virtiofsd built. With the recent port of the build system to
> Meson, it is now built together with the tools though.
>
> The Kata
This is intentional, because there's no way that any hypervisor can run if
this feature is disabled.
Paolo
Il lun 1 feb 2021, 23:54 Eduardo Habkost ha scritto:
> Not having a feature name in feature_word_info breaks error
> reporting and query-cpu-model-expansion. Add the missing feature
>
Forgetting to adding feature names to the feature array
seems to be a very common mistake.
Examples:
- Missing name for MSR_VMX_EPT_WB
commit 0723cc8a5558 ("target/i386: add VMX features to named CPU models")
- Missing name for "ibrs" at
All CPU models must refer only to features that have their names
defined in feature_word_info[].feat_names, otherwise error
reporting and query-cpu-model-expansion will break.
Validate CPU feature flags in x86_cpudef_validate(), we can catch
mistakes more easily.
Signed-off-by: Eduardo Habkost
Additional sanity checks will be added to the code, so move the
existing asserts to a separate function.
Wrap the whole function in `#ifndef NDEBUG` because the checks
will become more complex than trivial assert() calls.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 16
Not having a feature name in feature_word_info breaks error
reporting and query-cpu-model-expansion. Add the missing feature
name to feature_word_info[FEAT_VMX_EPT_VPID_CAPS].feat_names[14].
Fixes: 0723cc8a5558 ("target/i386: add VMX features to named CPU models")
Signed-off-by: Eduardo Habkost
In order to keep track of the alternate setting that should be used for
a given interface, the USBDevice struct keeps an array of alternate
setting values, which is indexed by the interface number. In
usb_host_set_interface, when this array is updated, usb_host_ep_update
is called as a result.
Eduardo,
Please hold off on this patch. I need to update this patch.
Actually We need to add one more bit to SVM
feature(CPUID_SVM_SVME_ADDR_CHK). I was planning to do that this week.
Got busy with some other priority. Will send it this week, Sorry about it.
thanks
Babu
On 2/1/21 4:16 PM,
On Mon, Feb 01, 2021 at 04:29:50PM -0600, Babu Moger wrote:
> Eduardo,
> Please hold off on this patch. I need to update this patch.
> Actually We need to add one more bit to SVM
> feature(CPUID_SVM_SVME_ADDR_CHK). I was planning to do that this week.
> Got busy with some other priority. Will send
On Fri, Jan 22, 2021 at 10:36:27AM -0600, Babu Moger wrote:
> Adds the support for AMD 3rd generation processors. The model
> display for the new processor will be EPYC-Milan.
>
> Adds the following new feature bits on top of the feature bits from
> the first and second generation EPYC models.
>
On 2/1/21 11:01 PM, Cédric Le Goater wrote:
> Hello,
>
>>> FYI, aspeed machines successfully boot on top of 16G emmc disk images.
>>> I merged some of xilinx patches on top of the aspeed-6.0 branch to
>>> improve the model completeness but only the one fixing powerup was
>>> really necessary.
Historically the parisc linux port tried to be compatible with HP-UX
userspace and as such defined the O_NONBLOCK constant to 024 to
emulate separate NDELAY & NONBLOCK values.
Since parisc was the only Linux platform which had two bits set, this
produced various userspace issues. Finally it
Hello,
>> FYI, aspeed machines successfully boot on top of 16G emmc disk images.
>> I merged some of xilinx patches on top of the aspeed-6.0 branch to
>> improve the model completeness but only the one fixing powerup was
>> really necessary.
>>
>> The initial diffstat is rather small.
>>
>>
On Jan 29 10:15, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Add support for TP 4065a ("Simple Copy Command"), v2020.05.04
> ("Ratified").
>
> The implementation uses a bounce buffer to first read in the source
> logical blocks, then issue a write of that bounce buffer. The default
> maximum
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