[Bug 1914849] [NEW] mprotect fails after MacOS 11.2 on arm mac
Public bug reported: I got the following error when I ran qemu on arm mac(MacOS 11.2). ``` $ ./qemu-system-x86_64 qemu-system-x86_64: qemu_mprotect__osdep: mprotect failed: Permission denied ** ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) Bail out! ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) [1]34898 abort ./qemu-system-x86_64 ``` I tested the same version of qemu on intel mac(MacOS 11.2), but it works fine. And my friend told me that they did not have this error with MacOS 11.1. So, I think it is CPU architecture or an OS version dependent error. Environment: Qemu commit id: d0dddab40e472ba62b5f43f11cc7dba085dabe71 OS: MacOS 11.2(20D64) Hardware: MacBook Air (M1, 2020) How to build: ``` mkdir build/ cd build/ ../configure --target-list=aarch64-softmmu,x86_64-softmmu make ``` How to reproduce: ``` ./qemu-system-x86_64 ``` Error message: ``` $ ./qemu-system-x86_64 qemu-system-x86_64: qemu_mprotect__osdep: mprotect failed: Permission denied ** ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) Bail out! ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) [1]34898 abort ./qemu-system-x86_64 ``` ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1914849 Title: mprotect fails after MacOS 11.2 on arm mac Status in QEMU: New Bug description: I got the following error when I ran qemu on arm mac(MacOS 11.2). ``` $ ./qemu-system-x86_64 qemu-system-x86_64: qemu_mprotect__osdep: mprotect failed: Permission denied ** ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) Bail out! ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) [1]34898 abort ./qemu-system-x86_64 ``` I tested the same version of qemu on intel mac(MacOS 11.2), but it works fine. And my friend told me that they did not have this error with MacOS 11.1. So, I think it is CPU architecture or an OS version dependent error. Environment: Qemu commit id: d0dddab40e472ba62b5f43f11cc7dba085dabe71 OS: MacOS 11.2(20D64) Hardware: MacBook Air (M1, 2020) How to build: ``` mkdir build/ cd build/ ../configure --target-list=aarch64-softmmu,x86_64-softmmu make ``` How to reproduce: ``` ./qemu-system-x86_64 ``` Error message: ``` $ ./qemu-system-x86_64 qemu-system-x86_64: qemu_mprotect__osdep: mprotect failed: Permission denied ** ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) Bail out! ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) [1]34898 abort ./qemu-system-x86_64 ``` To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1914849/+subscriptions
[PATCH 6/6] hw/block/nvme: support namespace attachment command
This patch supports Namespace Attachment command for the pre-defined
nvme-ns device nodes. Of course, attach/detach namespace should only be
supported in case 'subsys' is given. This is because if we detach a
namespace from a controller, somebody needs to manage the detached, but
allocated namespace in the NVMe subsystem.
Signed-off-by: Minwoo Im
---
hw/block/nvme-subsys.h | 10 +++
hw/block/nvme.c| 59 ++
hw/block/nvme.h| 5
hw/block/trace-events | 2 ++
include/block/nvme.h | 5
5 files changed, 81 insertions(+)
diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h
index 14627f9ccb41..ef4bec928eae 100644
--- a/hw/block/nvme-subsys.h
+++ b/hw/block/nvme-subsys.h
@@ -30,6 +30,16 @@ typedef struct NvmeSubsystem {
int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
int nvme_subsys_register_ns(NvmeNamespace *ns, Error **errp);
+static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys,
+uint32_t cntlid)
+{
+if (!subsys) {
+return NULL;
+}
+
+return subsys->ctrls[cntlid];
+}
+
/*
* Return allocated namespace of the specified nsid in the subsystem.
*/
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 697368a6ae0c..769436722c7e 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -183,6 +183,7 @@ static const uint32_t nvme_cse_acs[256] = {
[NVME_ADM_CMD_SET_FEATURES] = NVME_CMD_EFF_CSUPP,
[NVME_ADM_CMD_GET_FEATURES] = NVME_CMD_EFF_CSUPP,
[NVME_ADM_CMD_ASYNC_EV_REQ] = NVME_CMD_EFF_CSUPP,
+[NVME_ADM_CMD_NS_ATTACHMENT]= NVME_CMD_EFF_CSUPP,
};
static const uint32_t nvme_cse_iocs_none[256];
@@ -3766,6 +3767,62 @@ static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req)
return NVME_NO_COMPLETE;
}
+static void __nvme_select_ns_iocs(NvmeCtrl *n, NvmeNamespace *ns);
+static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
+{
+NvmeNamespace *ns;
+NvmeCtrl *ctrl;
+uint16_t list[NVME_CONTROLLER_LIST_SIZE] = {};
+uint32_t nsid = le32_to_cpu(req->cmd.nsid);
+uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);
+bool attach = !(dw10 & 0xf);
+uint16_t *nr_ids = [0];
+uint16_t *ids = [1];
+uint16_t ret;
+int i;
+
+trace_pci_nvme_ns_attachment(nvme_cid(req), dw10 & 0xf);
+
+ns = nvme_subsys_ns(n->subsys, nsid);
+if (!ns) {
+return NVME_INVALID_FIELD | NVME_DNR;
+}
+
+ret = nvme_dma(n, (uint8_t *)list, 4096,
+ DMA_DIRECTION_TO_DEVICE, req);
+if (ret) {
+return ret;
+}
+
+if (!*nr_ids) {
+return NVME_NS_CTRL_LIST_INVALID | NVME_DNR;
+}
+
+for (i = 0; i < *nr_ids; i++) {
+ctrl = nvme_subsys_ctrl(n->subsys, ids[i]);
+if (!ctrl) {
+return NVME_NS_CTRL_LIST_INVALID | NVME_DNR;
+}
+
+if (attach) {
+if (nvme_ns_is_attached(ctrl, ns)) {
+return NVME_NS_ALREADY_ATTACHED | NVME_DNR;
+}
+
+nvme_ns_attach(n, ns);
+__nvme_select_ns_iocs(n, ns);
+} else {
+if (!nvme_ns_is_attached(ctrl, ns)) {
+return NVME_NS_NOT_ATTACHED | NVME_DNR;
+}
+
+nvme_ns_detach(n, ns);
+}
+}
+
+return NVME_SUCCESS;
+}
+
static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
{
trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode,
@@ -3797,6 +3854,8 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest
*req)
return nvme_get_feature(n, req);
case NVME_ADM_CMD_ASYNC_EV_REQ:
return nvme_aer(n, req);
+case NVME_ADM_CMD_NS_ATTACHMENT:
+return nvme_ns_attachment(n, req);
default:
assert(false);
}
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 1c7796b20996..5a1ab857d166 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -222,6 +222,11 @@ static inline void nvme_ns_attach(NvmeCtrl *n,
NvmeNamespace *ns)
n->namespaces[nvme_nsid(ns) - 1] = ns;
}
+static inline void nvme_ns_detach(NvmeCtrl *n, NvmeNamespace *ns)
+{
+n->namespaces[nvme_nsid(ns) - 1] = NULL;
+}
+
static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
{
NvmeSQueue *sq = req->sq;
diff --git a/hw/block/trace-events b/hw/block/trace-events
index b6e972d733a6..bf67fe7873d2 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -80,6 +80,8 @@ pci_nvme_aer(uint16_t cid) "cid %"PRIu16""
pci_nvme_aer_aerl_exceeded(void) "aerl exceeded"
pci_nvme_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask
0x%"PRIx8""
pci_nvme_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type
0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8""
+pci_nvme_ns_attachment(uint16_t cid, uint8_t sel) "cid %"PRIu16",
sel=0x%"PRIx8""
+pci_nvme_ns_attachment_attach(uint16_t cntlid, uint32_t nsid)
"cntlid=0x%"PRIx16", nsid=0x%"PRIx32""
pci_nvme_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type
0x%"PRIx8" info
[PATCH 5/6] hw/block/nvme: refactor nvme_select_ns_iocs
This patch has no functional changes. This patch just refactored
nvme_select_ns_iocs() to iterate the attached namespaces of the
controlller and make it invoke __nvme_select_ns_iocs().
Signed-off-by: Minwoo Im
---
hw/block/nvme.c | 36 +---
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index d1761a82731f..697368a6ae0c 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -3896,6 +3896,25 @@ static void nvme_ctrl_shutdown(NvmeCtrl *n)
}
}
+static void __nvme_select_ns_iocs(NvmeCtrl *n, NvmeNamespace *ns)
+{
+ns->iocs = nvme_cse_iocs_none;
+switch (ns->csi) {
+case NVME_CSI_NVM:
+if (NVME_CC_CSS(n->bar.cc) != NVME_CC_CSS_ADMIN_ONLY) {
+ns->iocs = nvme_cse_iocs_nvm;
+}
+break;
+case NVME_CSI_ZONED:
+if (NVME_CC_CSS(n->bar.cc) == NVME_CC_CSS_CSI) {
+ns->iocs = nvme_cse_iocs_zoned;
+} else if (NVME_CC_CSS(n->bar.cc) == NVME_CC_CSS_NVM) {
+ns->iocs = nvme_cse_iocs_nvm;
+}
+break;
+}
+}
+
static void nvme_select_ns_iocs(NvmeCtrl *n)
{
NvmeNamespace *ns;
@@ -3906,21 +3925,8 @@ static void nvme_select_ns_iocs(NvmeCtrl *n)
if (!ns) {
continue;
}
-ns->iocs = nvme_cse_iocs_none;
-switch (ns->csi) {
-case NVME_CSI_NVM:
-if (NVME_CC_CSS(n->bar.cc) != NVME_CC_CSS_ADMIN_ONLY) {
-ns->iocs = nvme_cse_iocs_nvm;
-}
-break;
-case NVME_CSI_ZONED:
-if (NVME_CC_CSS(n->bar.cc) == NVME_CC_CSS_CSI) {
-ns->iocs = nvme_cse_iocs_zoned;
-} else if (NVME_CC_CSS(n->bar.cc) == NVME_CC_CSS_NVM) {
-ns->iocs = nvme_cse_iocs_nvm;
-}
-break;
-}
+
+__nvme_select_ns_iocs(n, ns);
}
}
--
2.17.1
[PATCH 4/6] hw/block/nvme: support allocated namespace type
>From NVMe spec 1.4b "6.1.5. NSID and Namespace Relationships" defines
valid namespace types:
- Unallocated: Not exists in the NVMe subsystem
- Allocated: Exists in the NVMe subsystem
- Inactive: Not attached to the controller
- Active: Attached to the controller
This patch added support for allocated, but not attached namespace type:
!nvme_ns(n, nsid) && nvme_subsys_ns(n->subsys, nsid)
nvme_ns() returns attached namespace instance of the given controller
and nvme_subsys_ns() returns allocated namespace instance in the
subsystem.
Signed-off-by: Minwoo Im
---
hw/block/nvme-subsys.h | 13 +
hw/block/nvme.c| 63 +++---
2 files changed, 60 insertions(+), 16 deletions(-)
diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h
index 8a0732b22316..14627f9ccb41 100644
--- a/hw/block/nvme-subsys.h
+++ b/hw/block/nvme-subsys.h
@@ -30,4 +30,17 @@ typedef struct NvmeSubsystem {
int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
int nvme_subsys_register_ns(NvmeNamespace *ns, Error **errp);
+/*
+ * Return allocated namespace of the specified nsid in the subsystem.
+ */
+static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys,
+uint32_t nsid)
+{
+if (!subsys) {
+return NULL;
+}
+
+return subsys->namespaces[nsid];
+}
+
#endif /* NVME_SUBSYS_H */
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index a1e930f7c8e4..d1761a82731f 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -3124,7 +3124,7 @@ static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n,
NvmeRequest *req)
return NVME_INVALID_FIELD | NVME_DNR;
}
-static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
+static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req, bool active)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)>cmd;
@@ -3138,7 +3138,14 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n,
NvmeRequest *req)
ns = nvme_ns(n, nsid);
if (unlikely(!ns)) {
-return nvme_rpt_empty_id_struct(n, req);
+if (!active) {
+ns = nvme_subsys_ns(n->subsys, nsid);
+if (!ns) {
+return nvme_rpt_empty_id_struct(n, req);
+}
+} else {
+return nvme_rpt_empty_id_struct(n, req);
+}
}
if (c->csi == NVME_CSI_NVM && nvme_csi_has_nvm_support(ns)) {
@@ -3149,7 +3156,8 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest
*req)
return NVME_INVALID_CMD_SET | NVME_DNR;
}
-static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req)
+static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req,
+bool active)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)>cmd;
@@ -3163,7 +3171,14 @@ static uint16_t nvme_identify_ns_csi(NvmeCtrl *n,
NvmeRequest *req)
ns = nvme_ns(n, nsid);
if (unlikely(!ns)) {
-return nvme_rpt_empty_id_struct(n, req);
+if (!active) {
+ns = nvme_subsys_ns(n->subsys, nsid);
+if (!ns) {
+return nvme_rpt_empty_id_struct(n, req);
+}
+} else {
+return nvme_rpt_empty_id_struct(n, req);
+}
}
if (c->csi == NVME_CSI_NVM && nvme_csi_has_nvm_support(ns)) {
@@ -3176,7 +3191,8 @@ static uint16_t nvme_identify_ns_csi(NvmeCtrl *n,
NvmeRequest *req)
return NVME_INVALID_FIELD | NVME_DNR;
}
-static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
+static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req,
+bool active)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)>cmd;
@@ -3201,7 +3217,14 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n,
NvmeRequest *req)
for (i = 1; i <= n->num_namespaces; i++) {
ns = nvme_ns(n, i);
if (!ns) {
-continue;
+if (!active) {
+ns = nvme_subsys_ns(n->subsys, i);
+if (!ns) {
+continue;
+}
+} else {
+continue;
+}
}
if (ns->params.nsid <= min_nsid) {
continue;
@@ -3215,7 +3238,8 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n,
NvmeRequest *req)
return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req);
}
-static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req)
+static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req,
+bool active)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)>cmd;
@@ -3241,7 +3265,14 @@ static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n,
NvmeRequest *req)
for (i = 1; i <= n->num_namespaces; i++) {
ns = nvme_ns(n, i);
if (!ns) {
-continue;
+if (!active) {
+ns = nvme_subsys_ns(n->subsys, i);
+if (!ns) {
+continue;
+}
+}
[PATCH 3/6] hw/block/nvme: fix allocated namespace list to 256
Expand allocated namespace list (subsys->namespaces) to have 256 entries
which is a value lager than at least NVME_MAX_NAMESPACES which is for
attached namespace list in a controller.
Allocated namespace list should at least larger than attached namespace
list.
n->num_namespaces = NVME_MAX_NAMESPACES;
The above line will set the NN field by id->nn so that the subsystem
should also prepare at least this number of namespace list entries.
Signed-off-by: Minwoo Im
---
hw/block/nvme-subsys.h | 2 +-
hw/block/nvme.h| 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h
index 574774390c4c..8a0732b22316 100644
--- a/hw/block/nvme-subsys.h
+++ b/hw/block/nvme-subsys.h
@@ -14,7 +14,7 @@
OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS)
#define NVME_SUBSYS_MAX_CTRLS 32
-#define NVME_SUBSYS_MAX_NAMESPACES 32
+#define NVME_SUBSYS_MAX_NAMESPACES 256
typedef struct NvmeCtrl NvmeCtrl;
typedef struct NvmeNamespace NvmeNamespace;
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index bde0ed7c2679..1c7796b20996 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -10,6 +10,12 @@
#define NVME_DEFAULT_ZONE_SIZE (128 * MiB)
#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
+/*
+ * Subsystem namespace list for allocated namespaces should be larger than
+ * attached namespace list in a controller.
+ */
+QEMU_BUILD_BUG_ON(NVME_MAX_NAMESPACES > NVME_SUBSYS_MAX_NAMESPACES);
+
typedef struct NvmeParams {
char *serial;
uint32_t num_queues; /* deprecated since 5.1 */
--
2.17.1
[PATCH 1/6] hw/block/nvme: support namespace detach
Given that now we have nvme-subsys device supported, we can manage
namespace allocated, but not attached: detached. This patch introduced
a parameter for nvme-ns device named 'detached'. This parameter
indicates whether the given namespace device is detached from
a entire NVMe subsystem('subsys' given case, shared namespace) or a
controller('bus' given case, private namespace).
- Allocated namespace
1) Shared ns in the subsystem 'subsys0':
-device nvme-ns,id=ns1,drive=blknvme0,nsid=1,subsys=subsys0,detached=true
2) Private ns for the controller 'nvme0' of the subsystem 'subsys0':
-device nvme-subsys,id=subsys0
-device nvme,serial=foo,id=nvme0,subsys=subsys0
-device nvme-ns,id=ns1,drive=blknvme0,nsid=1,bus=nvme0,detached=true
3) (Invalid case) Controller 'nvme0' has no subsystem to manage ns:
-device nvme,serial=foo,id=nvme0
-device nvme-ns,id=ns1,drive=blknvme0,nsid=1,bus=nvme0,detached=true
Signed-off-by: Minwoo Im
---
hw/block/nvme-ns.c | 1 +
hw/block/nvme-ns.h | 1 +
hw/block/nvme-subsys.h | 1 +
hw/block/nvme.c| 41 +++--
hw/block/nvme.h| 22 ++
5 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c
index c3b513b0fc78..cdcb81319fb5 100644
--- a/hw/block/nvme-ns.c
+++ b/hw/block/nvme-ns.c
@@ -393,6 +393,7 @@ static Property nvme_ns_props[] = {
DEFINE_BLOCK_PROPERTIES(NvmeNamespace, blkconf),
DEFINE_PROP_LINK("subsys", NvmeNamespace, subsys, TYPE_NVME_SUBSYS,
NvmeSubsystem *),
+DEFINE_PROP_BOOL("detached", NvmeNamespace, params.detached, false),
DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
DEFINE_PROP_UUID("uuid", NvmeNamespace, params.uuid),
DEFINE_PROP_UINT16("mssrl", NvmeNamespace, params.mssrl, 128),
diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h
index 7af6884862b5..b0c00e115d81 100644
--- a/hw/block/nvme-ns.h
+++ b/hw/block/nvme-ns.h
@@ -26,6 +26,7 @@ typedef struct NvmeZone {
} NvmeZone;
typedef struct NvmeNamespaceParams {
+bool detached;
uint32_t nsid;
QemuUUID uuid;
diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h
index ccf6a71398d3..890d118117dc 100644
--- a/hw/block/nvme-subsys.h
+++ b/hw/block/nvme-subsys.h
@@ -23,6 +23,7 @@ typedef struct NvmeSubsystem {
uint8_t subnqn[256];
NvmeCtrl*ctrls[NVME_SUBSYS_MAX_CTRLS];
+/* Allocated namespaces for this subsystem */
NvmeNamespace *namespaces[NVME_SUBSYS_MAX_NAMESPACES];
} NvmeSubsystem;
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 6b84e34843f5..a1e930f7c8e4 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -23,7 +23,7 @@
* max_ioqpairs=, \
* aerl=, aer_max_queued=, \
* mdts=,zoned.append_size_limit=, \
- * subsys= \
+ * subsys=,detached=
* -device nvme-ns,drive=,bus=,nsid=,\
* zoned=, \
* subsys=
@@ -78,6 +78,13 @@
* controllers in the subsystem. Otherwise, `bus` must be given to attach
* this namespace to a specified single controller as a non-shared namespace.
*
+ * - `detached`
+ * Not to attach the namespace device to controllers in the NVMe subsystem
+ * during boot-up. If not given, namespaces are all attahced to all
+ * controllers in the subsystem by default.
+ * It's mutual exclusive with 'bus' parameter. It's only valid in case
+ * `subsys` is provided.
+ *
* Setting `zoned` to true selects Zoned Command Set at the namespace.
* In this case, the following namespace properties are available to configure
* zoned operation:
@@ -4521,6 +4528,20 @@ static void nvme_init_state(NvmeCtrl *n)
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
}
+static int nvme_attach_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
+{
+if (nvme_ns_is_attached(n, ns)) {
+error_setg(errp,
+ "namespace %d is already attached to controller %d",
+ nvme_nsid(ns), n->cntlid);
+return -1;
+}
+
+nvme_ns_attach(n, ns);
+
+return 0;
+}
+
int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
{
uint32_t nsid = nvme_nsid(ns);
@@ -4552,7 +4573,23 @@ int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace
*ns, Error **errp)
trace_pci_nvme_register_namespace(nsid);
-n->namespaces[nsid - 1] = ns;
+/*
+ * If subsys is not given, namespae is always attached to the controller
+ * because there's no subsystem to manage namespace allocation.
+ */
+if (!n->subsys) {
+if (ns->params.detached) {
+error_setg(errp,
+ "detached needs nvme-subsys specified nvme or nvme-ns");
+return -1;
+}
+
+return nvme_attach_namespace(n, ns, errp);
+} else {
+if (!ns->params.detached) {
+return
[PATCH 2/6] hw/block/nvme: fix namespaces array to 1-based
subsys->namespaces array used to be sized to NVME_SUBSYS_MAX_NAMESPACES.
But subsys->namespaces are being accessed with 1-based namespace id
which means the very first array entry will always be empty(NULL).
Signed-off-by: Minwoo Im
---
hw/block/nvme-subsys.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h
index 890d118117dc..574774390c4c 100644
--- a/hw/block/nvme-subsys.h
+++ b/hw/block/nvme-subsys.h
@@ -24,7 +24,7 @@ typedef struct NvmeSubsystem {
NvmeCtrl*ctrls[NVME_SUBSYS_MAX_CTRLS];
/* Allocated namespaces for this subsystem */
-NvmeNamespace *namespaces[NVME_SUBSYS_MAX_NAMESPACES];
+NvmeNamespace *namespaces[NVME_SUBSYS_MAX_NAMESPACES + 1];
} NvmeSubsystem;
int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
--
2.17.1
[PATCH 0/6] hw/block/nvme: support namespace attachment
Hello, This series supports namespace attachment: attach and detach. It means that this series also introduced a scheme for allocated namespace which is detached, but allocated in a NVMe subsystem. Given that now we have nvme-subsys device to specify a NVMe subsystem, it can manage detached namespaces from controllers in the subsystem itself. Tested: -device nvme-subsys,id=subsys0 \ -device nvme,serial=foo,id=nvme0,subsys=subsys0 \ -device nvme-ns,id=ns1,drive=drv0,nsid=1,subsys=subsys0,zoned=false \ -device nvme-ns,id=ns2,drive=drv1,nsid=2,subsys=subsys0,zoned=true \ -device nvme-ns,id=ns3,drive=drv2,nsid=3,subsys=subsys0,detached=true,zoned=false \ -device nvme-ns,id=ns4,drive=drv3,nsid=4,subsys=subsys0,detached=true,zoned=true \ root@vm:~# nvme list Node SN Model Namespace Usage Format FW Rev - - -- /dev/nvme0n1 foo QEMU NVMe Ctrl 1 268.44 MB / 268.44 MB512 B + 0 B 1.0 /dev/nvme0n2 foo QEMU NVMe Ctrl 2 268.44 MB / 268.44 MB512 B + 0 B 1.0 root@vm:~# nvme attach-ns /dev/nvme0 --namespace-id=3 --controllers=0 attach-ns: Success, nsid:3 root@vm:~# nvme attach-ns /dev/nvme0 --namespace-id=4 --controllers=0 attach-ns: Success, nsid:4 root@vm:~# echo 1 > /sys/class/nvme/nvme0/rescan_controller root@vm:~# nvme list Node SN Model Namespace Usage Format FW Rev - - -- /dev/nvme0n1 foo QEMU NVMe Ctrl 1 268.44 MB / 268.44 MB512 B + 0 B 1.0 /dev/nvme0n2 foo QEMU NVMe Ctrl 2 268.44 MB / 268.44 MB512 B + 0 B 1.0 /dev/nvme0n3 foo QEMU NVMe Ctrl 3 268.44 MB / 268.44 MB512 B + 0 B 1.0 /dev/nvme0n4 foo QEMU NVMe Ctrl 4 268.44 MB / 268.44 MB512 B + 0 B 1.0 root@vm:~# nvme detach-ns /dev/nvme0 --namespace-id=3 --controllers=0 detach-ns: Success, nsid:3 root@vm:~# nvme detach-ns /dev/nvme0 --namespace-id=4 --controllers=0 detach-ns: Success, nsid:4 root@vm:~# echo 1 > /sys/class/nvme/nvme0/rescan_controller root@vm:~# nvme list Node SN Model Namespace Usage Format FW Rev - - -- /dev/nvme0n1 foo QEMU NVMe Ctrl 1 268.44 MB / 268.44 MB512 B + 0 B 1.0 /dev/nvme0n2 foo QEMU NVMe Ctrl 2 268.44 MB / 268.44 MB512 B + 0 B 1.0 Thanks, Minwoo Im (6): hw/block/nvme: support namespace detach hw/block/nvme: fix namespaces array to 1-based hw/block/nvme: fix allocated namespace list to 256 hw/block/nvme: support allocated namespace type hw/block/nvme: refactor nvme_select_ns_iocs hw/block/nvme: support namespace attachment command hw/block/nvme-ns.c | 1 + hw/block/nvme-ns.h | 1 + hw/block/nvme-subsys.h | 28 +- hw/block/nvme.c| 199 ++--- hw/block/nvme.h| 33 +++ hw/block/trace-events | 2 + include/block/nvme.h | 5 ++ 7 files changed, 234 insertions(+), 35 deletions(-) -- 2.17.1
[PULL 46/46] accel: introduce AccelCPUClass extending CPUClass
From: Claudio Fontana
add a new optional interface to CPUClass, which allows accelerators
to extend the CPUClass with additional accelerator-specific
initializations.
This will allow to separate the target cpu code that is specific
to each accelerator, and register it automatically with object
hierarchy lookup depending on accelerator code availability,
as part of the accel_init_interfaces() initialization step.
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-19-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/accel-cpu.h | 38
include/hw/core/cpu.h | 4
accel/accel-common.c| 44 +
MAINTAINERS | 1 +
4 files changed, 87 insertions(+)
create mode 100644 include/hw/core/accel-cpu.h
diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
new file mode 100644
index 00..24a6697412
--- /dev/null
+++ b/include/hw/core/accel-cpu.h
@@ -0,0 +1,38 @@
+/*
+ * Accelerator interface, specializes CPUClass
+ * This header is used only by target-specific code.
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_CPU_H
+#define ACCEL_CPU_H
+
+/*
+ * This header is used to define new accelerator-specific target-specific
+ * accelerator cpu subclasses.
+ * It uses CPU_RESOLVING_TYPE, so this is clearly target-specific.
+ *
+ * Do not try to use for any other purpose than the implementation of new
+ * subclasses in target/, or the accel implementation itself in accel/
+ */
+
+#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
+#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
+typedef struct AccelCPUClass AccelCPUClass;
+DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
+
+typedef struct AccelCPUClass {
+/*< private >*/
+ObjectClass parent_class;
+/*< public >*/
+
+void (*cpu_class_init)(CPUClass *cc);
+void (*cpu_instance_init)(CPUState *cpu);
+void (*cpu_realizefn)(CPUState *cpu, Error **errp);
+} AccelCPUClass;
+
+#endif /* ACCEL_CPU_H */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4f6c6b18c9..38d813c389 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -79,6 +79,9 @@ struct TranslationBlock;
/* see tcg-cpu-ops.h */
struct TCGCPUOps;
+/* see accel-cpu.h */
+struct AccelCPUClass;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -187,6 +190,7 @@ struct CPUClass {
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+struct AccelCPUClass *accel_cpu;
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
diff --git a/accel/accel-common.c b/accel/accel-common.c
index 6b59873419..9901b0531c 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#include "cpu.h"
+#include "hw/core/accel-cpu.h"
+
#ifndef CONFIG_USER_ONLY
#include "accel-softmmu.h"
#endif /* !CONFIG_USER_ONLY */
@@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
+{
+CPUClass *cc = CPU_CLASS(klass);
+AccelCPUClass *accel_cpu = opaque;
+
+cc->accel_cpu = accel_cpu;
+if (accel_cpu->cpu_class_init) {
+accel_cpu->cpu_class_init(cc);
+}
+}
+
+/* initialize the arch-specific accel CpuClass interfaces */
+static void accel_init_cpu_interfaces(AccelClass *ac)
+{
+const char *ac_name; /* AccelClass name */
+char *acc_name; /* AccelCPUClass name */
+ObjectClass *acc;/* AccelCPUClass */
+
+ac_name = object_class_get_name(OBJECT_CLASS(ac));
+g_assert(ac_name != NULL);
+
+acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
+acc = object_class_by_name(acc_name);
+g_free(acc_name);
+
+if (acc) {
+object_class_foreach(accel_init_cpu_int_aux,
+ CPU_RESOLVING_TYPE, false, acc);
+}
+}
+
void accel_init_interfaces(AccelClass *ac)
{
#ifndef CONFIG_USER_ONLY
accel_init_ops_interfaces(ac);
#endif /* !CONFIG_USER_ONLY */
+
+accel_init_cpu_interfaces(ac);
}
+static const TypeInfo accel_cpu_type = {
+.name = TYPE_ACCEL_CPU,
+.parent = TYPE_OBJECT,
+.abstract = true,
+.class_size = sizeof(AccelCPUClass),
+};
+
static void register_accel_types(void)
{
type_register_static(_type);
+type_register_static(_cpu_type);
}
type_init(register_accel_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index 2e63561ad0..8d8b0bf966 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -440,6 +440,7 @@ R: Paolo Bonzini
S: Maintained
F: include/qemu/accel.h
F: include/sysemu/accel-ops.h
+F:
[PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass
From: Claudio Fontana
This will allow us to centralize the registration of
the cpus.c module accelerator operations (in accel/accel-softmmu.c),
and trigger it automatically using object hierarchy lookup from the
new accel_init_interfaces() initialization step, depending just on
which accelerators are available in the code.
Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c,
kvm-accel-ops.c, etc, matching the object type names.
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-18-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
accel/accel-softmmu.h | 15 ++
accel/kvm/kvm-cpus.h | 2 -
...g-cpus-icount.h => tcg-accel-ops-icount.h} | 2 +
accel/tcg/tcg-accel-ops-mttcg.h | 19
.../tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h} | 0
accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} | 6 +--
include/qemu/accel.h | 2 +
include/sysemu/accel-ops.h| 45 ++
include/sysemu/cpus.h | 26 ++
.../i386/hax/{hax-cpus.h => hax-accel-ops.h} | 2 -
target/i386/hax/hax-windows.h | 2 +-
.../i386/hvf/{hvf-cpus.h => hvf-accel-ops.h} | 2 -
.../whpx/{whpx-cpus.h => whpx-accel-ops.h}| 2 -
accel/accel-common.c | 11 +
accel/accel-softmmu.c | 44 +++--
accel/kvm/{kvm-cpus.c => kvm-accel-ops.c} | 28 ---
accel/kvm/kvm-all.c | 2 -
accel/qtest/qtest.c | 23 ++---
...g-cpus-icount.c => tcg-accel-ops-icount.c} | 21 +++--
...tcg-cpus-mttcg.c => tcg-accel-ops-mttcg.c} | 14 ++
.../tcg/{tcg-cpus-rr.c => tcg-accel-ops-rr.c} | 13 ++---
accel/tcg/{tcg-cpus.c => tcg-accel-ops.c} | 47 ++-
accel/tcg/tcg-all.c | 12 -
accel/xen/xen-all.c | 24 ++
bsd-user/main.c | 3 +-
linux-user/main.c | 1 +
softmmu/cpus.c| 12 ++---
softmmu/vl.c | 7 ++-
.../i386/hax/{hax-cpus.c => hax-accel-ops.c} | 33 +
target/i386/hax/hax-all.c | 5 +-
target/i386/hax/hax-mem.c | 2 +-
target/i386/hax/hax-posix.c | 2 +-
target/i386/hax/hax-windows.c | 2 +-
.../i386/hvf/{hvf-cpus.c => hvf-accel-ops.c} | 29 +---
target/i386/hvf/hvf.c | 3 +-
target/i386/hvf/x86hvf.c | 2 +-
.../whpx/{whpx-cpus.c => whpx-accel-ops.c}| 33 +
target/i386/whpx/whpx-all.c | 7 +--
MAINTAINERS | 3 +-
accel/kvm/meson.build | 2 +-
accel/tcg/meson.build | 8 ++--
target/i386/hax/meson.build | 2 +-
target/i386/hvf/meson.build | 2 +-
target/i386/whpx/meson.build | 2 +-
44 files changed, 361 insertions(+), 163 deletions(-)
create mode 100644 accel/accel-softmmu.h
rename accel/tcg/{tcg-cpus-icount.h => tcg-accel-ops-icount.h} (88%)
create mode 100644 accel/tcg/tcg-accel-ops-mttcg.h
rename accel/tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h} (100%)
rename accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} (72%)
create mode 100644 include/sysemu/accel-ops.h
rename target/i386/hax/{hax-cpus.h => hax-accel-ops.h} (95%)
rename target/i386/hvf/{hvf-cpus.h => hvf-accel-ops.h} (94%)
rename target/i386/whpx/{whpx-cpus.h => whpx-accel-ops.h} (96%)
rename accel/kvm/{kvm-cpus.c => kvm-accel-ops.c} (72%)
rename accel/tcg/{tcg-cpus-icount.c => tcg-accel-ops-icount.c} (89%)
rename accel/tcg/{tcg-cpus-mttcg.c => tcg-accel-ops-mttcg.c} (92%)
rename accel/tcg/{tcg-cpus-rr.c => tcg-accel-ops-rr.c} (97%)
rename accel/tcg/{tcg-cpus.c => tcg-accel-ops.c} (63%)
rename target/i386/hax/{hax-cpus.c => hax-accel-ops.c} (69%)
rename target/i386/hvf/{hvf-cpus.c => hvf-accel-ops.c} (84%)
rename target/i386/whpx/{whpx-cpus.c => whpx-accel-ops.c} (71%)
diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h
new file mode 100644
index 00..5e192f1882
--- /dev/null
+++ b/accel/accel-softmmu.h
@@ -0,0 +1,15 @@
+/*
+ * QEMU System Emulation accel internal functions
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_SOFTMMU_H
+#define ACCEL_SOFTMMU_H
+
+void accel_init_ops_interfaces(AccelClass *ac);
+
+#endif /* ACCEL_SOFTMMU_H */
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h
index 3df732b816..bf0bd1bee4 100644
--- a/accel/kvm/kvm-cpus.h
+++ b/accel/kvm/kvm-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel kvm_cpus;
-
int kvm_init_vcpu(CPUState *cpu,
[PULL 44/46] accel: extend AccelState and AccelClass to user-mode
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-17-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/boards.h| 2 +-
include/{sysemu => qemu}/accel.h | 14 +
include/sysemu/hvf.h | 2 +-
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 2 +-
target/i386/hvf/hvf-i386.h | 2 +-
accel/accel-common.c | 50 ++
accel/{accel.c => accel-softmmu.c} | 27 ++--
accel/accel-user.c | 24 ++
accel/qtest/qtest.c| 2 +-
accel/tcg/tcg-all.c| 15 +++--
accel/xen/xen-all.c| 2 +-
bsd-user/main.c| 6 +++-
linux-user/main.c | 6 +++-
softmmu/memory.c | 2 +-
softmmu/qtest.c| 2 +-
softmmu/vl.c | 2 +-
target/i386/hax/hax-all.c | 2 +-
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86_task.c | 2 +-
target/i386/whpx/whpx-all.c| 2 +-
MAINTAINERS| 2 +-
accel/meson.build | 4 ++-
accel/tcg/meson.build | 2 +-
24 files changed, 125 insertions(+), 53 deletions(-)
rename include/{sysemu => qemu}/accel.h (95%)
create mode 100644 accel/accel-common.c
rename accel/{accel.c => accel-softmmu.c} (75%)
create mode 100644 accel/accel-user.c
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 17b1f3f0b9..85af4faf76 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -6,7 +6,7 @@
#include "exec/memory.h"
#include "sysemu/hostmem.h"
#include "sysemu/blockdev.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qapi/qapi-types-machine.h"
#include "qemu/module.h"
#include "qom/object.h"
diff --git a/include/sysemu/accel.h b/include/qemu/accel.h
similarity index 95%
rename from include/sysemu/accel.h
rename to include/qemu/accel.h
index e08b8ab8fa..fac4a18703 100644
--- a/include/sysemu/accel.h
+++ b/include/qemu/accel.h
@@ -20,8 +20,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#ifndef HW_ACCEL_H
-#define HW_ACCEL_H
+#ifndef QEMU_ACCEL_H
+#define QEMU_ACCEL_H
#include "qom/object.h"
#include "exec/hwaddr.h"
@@ -37,8 +37,8 @@ typedef struct AccelClass {
/*< public >*/
const char *name;
-#ifndef CONFIG_USER_ONLY
int (*init_machine)(MachineState *ms);
+#ifndef CONFIG_USER_ONLY
void (*setup_post)(MachineState *ms, AccelState *accel);
bool (*has_memory)(MachineState *ms, AddressSpace *as,
hwaddr start_addr, hwaddr size);
@@ -67,11 +67,13 @@ typedef struct AccelClass {
OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL)
AccelClass *accel_find(const char *opt_name);
+AccelState *current_accel(void);
+
+#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
/* Called just before os_setup_post (ie just before drop OS privs) */
void accel_setup_post(MachineState *ms);
+#endif /* !CONFIG_USER_ONLY */
-AccelState *current_accel(void);
-
-#endif
+#endif /* QEMU_ACCEL_H */
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index f893768df9..c98636bc81 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -13,7 +13,7 @@
#ifndef HVF_H
#define HVF_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef CONFIG_HVF
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index bb5d5cf497..739682f3c3 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -17,7 +17,7 @@
#include "qemu/queue.h"
#include "hw/core/cpu.h"
#include "exec/memattrs.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef NEED_CPU_H
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 65740806da..ccb8869f01 100644
--- a/include/sysemu/kvm_int.h
+++ b/include/sysemu/kvm_int.h
@@ -10,7 +10,7 @@
#define QEMU_KVM_INT_H
#include "exec/memory.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/kvm.h"
typedef struct KVMSlot
diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
index e0edffd077..50b914fd67 100644
--- a/target/i386/hvf/hvf-i386.h
+++ b/target/i386/hvf/hvf-i386.h
@@ -16,7 +16,7 @@
#ifndef HVF_I386_H
#define HVF_I386_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/hvf.h"
#include "cpu.h"
#include "x86.h"
diff --git a/accel/accel-common.c b/accel/accel-common.c
new file mode 100644
index 00..ddec8cb5ae
--- /dev/null
+++ b/accel/accel-common.c
@@ -0,0 +1,50 @@
+/*
+ * QEMU accel class, components common to system emulation and user mode
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+
[PULL 40/46] physmem: make watchpoint checking code TCG-only
From: Claudio Fontana
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-13-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
softmmu/physmem.c | 141 +++---
1 file changed, 72 insertions(+), 69 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 60760a3bdc..51ed600bf9 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -840,6 +840,7 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
}
}
+#ifdef CONFIG_TCG
/* Return true if this watchpoint address matches the specified
* access (ie the address range covered by the watchpoint overlaps
* partially or completely with the address range covered by the
@@ -873,6 +874,77 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr
addr, vaddr len)
return ret;
}
+/* Generate a debug exception if a watchpoint has been hit. */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra)
+{
+CPUClass *cc = CPU_GET_CLASS(cpu);
+CPUWatchpoint *wp;
+
+assert(tcg_enabled());
+if (cpu->watchpoint_hit) {
+/*
+ * We re-entered the check after replacing the TB.
+ * Now raise the debug interrupt so that it will
+ * trigger after the current instruction.
+ */
+qemu_mutex_lock_iothread();
+cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
+qemu_mutex_unlock_iothread();
+return;
+}
+
+addr = cc->adjust_watchpoint_address(cpu, addr, len);
+QTAILQ_FOREACH(wp, >watchpoints, entry) {
+if (watchpoint_address_matches(wp, addr, len)
+&& (wp->flags & flags)) {
+if (replay_running_debug()) {
+/*
+ * Don't process the watchpoints when we are
+ * in a reverse debugging operation.
+ */
+replay_breakpoint();
+return;
+}
+if (flags == BP_MEM_READ) {
+wp->flags |= BP_WATCHPOINT_HIT_READ;
+} else {
+wp->flags |= BP_WATCHPOINT_HIT_WRITE;
+}
+wp->hitaddr = MAX(addr, wp->vaddr);
+wp->hitattrs = attrs;
+if (!cpu->watchpoint_hit) {
+if (wp->flags & BP_CPU &&
+!cc->debug_check_watchpoint(cpu, wp)) {
+wp->flags &= ~BP_WATCHPOINT_HIT;
+continue;
+}
+cpu->watchpoint_hit = wp;
+
+mmap_lock();
+tb_check_watchpoint(cpu, ra);
+if (wp->flags & BP_STOP_BEFORE_ACCESS) {
+cpu->exception_index = EXCP_DEBUG;
+mmap_unlock();
+cpu_loop_exit_restore(cpu, ra);
+} else {
+/* Force execution of one insn next time. */
+cpu->cflags_next_tb = 1 | curr_cflags();
+mmap_unlock();
+if (ra) {
+cpu_restore_state(cpu, ra, true);
+}
+cpu_loop_exit_noexc(cpu);
+}
+}
+} else {
+wp->flags &= ~BP_WATCHPOINT_HIT;
+}
+}
+}
+
+#endif /* CONFIG_TCG */
+
/* Called from RCU critical section */
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
{
@@ -2359,75 +2431,6 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr)
return block->offset + offset;
}
-/* Generate a debug exception if a watchpoint has been hit. */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra)
-{
-CPUClass *cc = CPU_GET_CLASS(cpu);
-CPUWatchpoint *wp;
-
-assert(tcg_enabled());
-if (cpu->watchpoint_hit) {
-/*
- * We re-entered the check after replacing the TB.
- * Now raise the debug interrupt so that it will
- * trigger after the current instruction.
- */
-qemu_mutex_lock_iothread();
-cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
-qemu_mutex_unlock_iothread();
-return;
-}
-
-addr = cc->adjust_watchpoint_address(cpu, addr, len);
-QTAILQ_FOREACH(wp, >watchpoints, entry) {
-if (watchpoint_address_matches(wp, addr, len)
-&& (wp->flags & flags)) {
-if (replay_running_debug()) {
-/*
- * Don't process the watchpoints when we are
- * in a reverse debugging operation.
- */
-replay_breakpoint();
-return;
-}
-if (flags == BP_MEM_READ) {
-wp->flags |= BP_WATCHPOINT_HIT_READ;
-} else {
-wp->flags |= BP_WATCHPOINT_HIT_WRITE;
-}
-wp->hitaddr =
[PULL 41/46] cpu: move adjust_watchpoint_address to tcg_ops
From: Claudio Fontana
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-14-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 6 +-
hw/core/cpu.c | 6 --
softmmu/physmem.c | 5 -
target/arm/cpu.c | 2 +-
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 063814eaa4..832dd26e92 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -136,6 +136,11 @@ typedef struct TcgCpuOperations {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
+/**
+ * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+ */
+vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+
} TcgCpuOperations;
/**
@@ -244,7 +249,6 @@ struct CPUClass {
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
-vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 57542b6906..3d5bf9fe02 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -383,11 +383,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
-static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
-{
-return addr;
-}
-
static Property cpu_common_props[] = {
#ifndef CONFIG_USER_ONLY
/* Create a memory property for softmmu CPU object,
@@ -421,7 +416,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
-k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 51ed600bf9..3d9a9c39bd 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -894,7 +894,10 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr
len,
return;
}
-addr = cc->adjust_watchpoint_address(cpu, addr, len);
+if (cc->tcg_ops.adjust_watchpoint_address) {
+/* this is currently used only by ARM BE32 */
+addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
+}
QTAILQ_FOREACH(wp, >watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)
&& (wp->flags & flags)) {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index aa264eec0a..2a14431065 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2284,7 +2284,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
-cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
--
2.25.1
[PULL 35/46] cpu: Move debug_excp_handler to tcg_ops
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-8-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/s390x/cpu.c| 2 +-
target/xtensa/cpu.c | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 94236b68d7..ff82eae939 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -117,6 +117,8 @@ typedef struct TcgCpuOperations {
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+/** @debug_excp_handler: Callback for handling debug exceptions */
+void (*debug_excp_handler)(CPUState *cpu);
} TcgCpuOperations;
@@ -161,7 +163,6 @@ typedef struct TcgCpuOperations {
* @gdb_write_register: Callback for letting GDB write a register.
* @debug_check_watchpoint: Callback: return true if the architectural
* watchpoint whose address has matched should really fire.
- * @debug_excp_handler: Callback for handling debug exceptions.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -224,7 +225,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
-void (*debug_excp_handler)(CPUState *cpu);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 953f050698..e7e54fd75d 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -512,8 +512,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
-if (cc->debug_excp_handler) {
-cc->debug_excp_handler(cpu);
+if (cc->tcg_ops.debug_excp_handler) {
+cc->tcg_ops.debug_excp_handler(cpu);
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 27a16c1950..66ac210b0c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2280,7 +2280,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
-cc->debug_excp_handler = arm_debug_excp_handler;
+cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 85b69224a9..6c1ebbdcc6 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -67,6 +67,6 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.initialize = tcg_x86_init;
cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
-cc->debug_excp_handler = breakpoint_handler;
+cc->tcg_ops.debug_excp_handler = breakpoint_handler;
#endif
}
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 76dc728858..bbe1405e32 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
-cc->debug_excp_handler = lm32_debug_excp_handler;
+cc->tcg_ops.debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
cc->tcg_ops.initialize = lm32_translate_init;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index ceee62ddca..8ade66178e 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -509,7 +509,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
-cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
+cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e764dbeb73..b6f13ceb32 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void
*data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
-
[PULL 42/46] cpu: move debug_check_watchpoint to tcg_ops
From: Claudio Fontana
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-15-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 9 ++---
accel/tcg/user-exec.c | 3 ++-
hw/core/cpu.c | 9 -
softmmu/physmem.c | 4 ++--
target/arm/cpu.c | 4 ++--
5 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 832dd26e92..e76a49754d 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -141,6 +141,12 @@ typedef struct TcgCpuOperations {
*/
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+/**
+ * @debug_check_watchpoint: return true if the architectural
+ * watchpoint whose address has matched should really fire, used by ARM
+ */
+bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
+
} TcgCpuOperations;
/**
@@ -177,8 +183,6 @@ typedef struct TcgCpuOperations {
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @debug_check_watchpoint: Callback: return true if the architectural
- * watchpoint whose address has matched should really fire.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -232,7 +236,6 @@ struct CPUClass {
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
-bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5509dd53e9..9e6e188d19 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -187,7 +187,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t
*info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
-cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false,
pc);
+cc->tcg_ops.tlb_fill(cpu, address, 0, access_type,
+ MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 3d5bf9fe02..00330ba07d 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -186,14 +186,6 @@ static int cpu_common_gdb_write_register(CPUState *cpu,
uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
-{
-/* If no extra check is required, QEMU watchpoint match can be considered
- * as an architectural match.
- */
-return true;
-}
-
static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
{
return target_words_bigendian();
@@ -415,7 +407,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
-k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 3d9a9c39bd..9e64cf7adf 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -917,8 +917,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr
len,
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
-if (wp->flags & BP_CPU &&
-!cc->debug_check_watchpoint(cpu, wp)) {
+if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoint &&
+!cc->tcg_ops.debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2a14431065..c9a66d3103 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2280,12 +2280,12 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
-cc->debug_check_watchpoint = arm_debug_check_watchpoint;
#if !defined(CONFIG_USER_ONLY)
+
[PULL 37/46] cpu: move cc->do_interrupt to tcg_ops
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-10-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c| 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 4 ++--
target/arm/cpu_tcg.c| 9 -
target/avr/cpu.c| 2 +-
target/avr/helper.c | 4 ++--
target/cris/cpu.c | 12 ++--
target/cris/helper.c| 4 ++--
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 ++--
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c| 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
27 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index ff82eae939..60cf20bf05 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -105,6 +105,8 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+/** @do_interrupt: Callback for interrupt handling. */
+void (*do_interrupt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
@@ -129,7 +131,6 @@ typedef struct TcgCpuOperations {
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_interrupt: Callback for interrupt handling.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
* @do_transaction_failed: Callback for handling failed memory transactions
@@ -199,7 +200,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
-void (*do_interrupt)(CPUState *cpu);
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index e7e54fd75d..633ee3ef9e 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -547,7 +547,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int
*ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
-cc->do_interrupt(cpu);
+cc->tcg_ops.do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;
@@ -556,7 +556,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int
*ret)
if (replay_exception()) {
CPUClass *cc = CPU_GET_CLASS(cpu);
qemu_mutex_lock_iothread();
-cc->do_interrupt(cpu);
+cc->tcg_ops.do_interrupt(cpu);
qemu_mutex_unlock_iothread();
cpu->exception_index = -1;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 9f36f824fd..66f1166672 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void
*data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
-cc->do_interrupt = alpha_cpu_do_interrupt;
+cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 66ac210b0c..dfb2398392 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -590,7 +590,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
-cc->do_interrupt(cs);
+cc->tcg_ops.do_interrupt(cs);
return true;
}
@@ -2261,7 +2261,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
-cc->do_interrupt = arm_cpu_do_interrupt;
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
[PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped target code in CONFIG_TCG, reworded comments]
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-5-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 22 +-
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 4 +++-
target/avr/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c| 2 +-
target/rx/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c| 2 +-
target/tricore/cpu.c | 2 +-
13 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d0b17dcc4c..8cf5585db7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -86,6 +86,19 @@ typedef struct TcgCpuOperations {
* Called when the first CPU is realized.
*/
void (*initialize)(void);
+/**
+ * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
+ *
+ * This is called when we abandon execution of a TB before starting it,
+ * and must set all parts of the CPU state which the previous TB in the
+ * chain may not have updated.
+ * By default, when this is NULL, a call is made to @set_pc(tb->pc).
+ *
+ * If more state needs to be restored, the target must implement a
+ * function to restore all the state, and register it here.
+ */
+void (*synchronize_from_tb)(CPUState *cpu,
+const struct TranslationBlock *tb);
} TcgCpuOperations;
@@ -119,13 +132,6 @@ typedef struct TcgCpuOperations {
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @synchronize_from_tb: Callback for synchronizing state from a TCG
- * #TranslationBlock. This is called when we abandon execution
- * of a TB before starting it, and must set all parts of the CPU
- * state which the previous TB in the chain may not have updated.
- * This always includes at least the program counter; some targets
- * will need to do more. If this hook is not implemented then the
- * default is to call @set_pc(tb->pc).
* @tlb_fill: Callback for handling a softmmu tlb miss or user-only
* address fault. For system mode, if the access is valid, call
* tlb_set_page and return true; if the access is invalid, and
@@ -202,8 +208,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
-void (*synchronize_from_tb)(CPUState *cpu,
-const struct TranslationBlock *tb);
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5628a156d1..12b6a91d62 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -213,8 +213,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int
*tb_exit)
TARGET_FMT_lx "] %s\n",
last_tb->tc.ptr, last_tb->pc,
lookup_symbol(last_tb->pc));
-if (cc->synchronize_from_tb) {
-cc->synchronize_from_tb(cpu, last_tb);
+if (cc->tcg_ops.synchronize_from_tb) {
+cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
} else {
assert(cc->set_pc);
cc->set_pc(cpu, last_tb->pc);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fa4d4ba4eb..140cb33f07 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -70,6 +71,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs,
env->regs[15] = tb->pc;
}
}
+#endif /* CONFIG_TCG */
static bool arm_cpu_has_work(CPUState *cs)
{
@@ -2257,7 +2259,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
-cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -2277,6 +2278,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->disas_set_info = arm_disas_set_info;
#ifdef
[PULL 39/46] cpu: move do_unaligned_access to tcg_ops
From: Claudio Fontana
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[claudio: make the field presence in cpu.h unconditional, removing the ifdefs]
Message-Id: <20210204163931.7358-12-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 13 +++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 2 +-
target/hppa/cpu.c | 4 +++-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 3 ++-
target/nios2/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/s390x/excp_helper.c | 2 +-
target/sh4/cpu.c| 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
14 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 41ce1daefc..063814eaa4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -130,6 +130,12 @@ typedef struct TcgCpuOperations {
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+/**
+ * @do_unaligned_access: Callback for unaligned access handling
+ */
+void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+MMUAccessType access_type,
+int mmu_idx, uintptr_t retaddr);
} TcgCpuOperations;
/**
@@ -139,8 +145,6 @@ typedef struct TcgCpuOperations {
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_unaligned_access: Callback for unaligned access handling, if
- * the target defines #TARGET_ALIGNED_ONLY.
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -206,9 +210,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
-void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
-MMUAccessType access_type,
-int mmu_idx, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -887,7 +888,7 @@ static inline void cpu_unaligned_access(CPUState *cpu,
vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
-cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index a1696bebeb..0710298e5a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -226,7 +226,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void
*data)
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
-cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
+cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = _alpha_cpu;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bd1882944c..aa264eec0a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2281,9 +2281,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
-cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
+cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 68233acf53..fd7f849a1c 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -71,6 +71,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs,
disassemble_info *info)
info->print_insn = print_insn_hppa;
}
+#ifndef CONFIG_USER_ONLY
static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
[PULL 34/46] cpu: Move tlb_fill to tcg_ops
From: Eduardo Habkost
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-7-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 21 -
accel/tcg/cputlb.c | 7 ---
accel/tcg/user-exec.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 2 +-
target/avr/cpu.c| 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c| 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c| 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
26 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 532984e016..94236b68d7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -105,6 +105,18 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+/**
+ * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
+ *
+ * For system mode, if the access is valid, call tlb_set_page
+ * and return true; if the access is invalid, and probe is
+ * true, return false; otherwise raise an exception and do
+ * not return. For user-only mode, always raise an exception
+ * and do not return.
+ */
+bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
} TcgCpuOperations;
@@ -138,12 +150,6 @@ typedef struct TcgCpuOperations {
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
- * address fault. For system mode, if the access is valid, call
- * tlb_set_page and return true; if the access is invalid, and
- * probe is true, return false; otherwise raise an exception and
- * do not return. For user-only mode, always raise an exception
- * and do not return.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @get_phys_page_attrs_debug: Callback for obtaining a physical address and
the
* associated memory transaction attributes to use for the access.
@@ -211,9 +217,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
-bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 7a69726ba4..b7717803b8 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1305,7 +1305,8 @@ static void tlb_fill(CPUState *cpu, target_ulong addr,
int size,
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
-ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+ok = cc->tcg_ops.tlb_fill(cpu, addr, size,
+ access_type, mmu_idx, false, retaddr);
assert(ok);
}
@@ -1576,8 +1577,8 @@ static int probe_access_internal(CPUArchState *env,
target_ulong addr,
CPUState *cs = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cs);
-if (!cc->tlb_fill(cs, addr, fault_size, access_type,
- mmu_idx, nonfault, retaddr)) {
+if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
[PULL 24/46] tcg/tci: Implement 64-bit division
Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c| 28 ++-- tcg/tci/tcg-target.c.inc | 10 -- 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index bb784e018e..7fc349a3de 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -100,8 +100,8 @@ #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_ext8s_i641 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 25329345cf..5c84a1c979 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -894,14 +894,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri64(regs, _ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: -case INDEX_op_divu_i64: -case INDEX_op_rem_i64: -case INDEX_op_remu_i64: -TODO(); +t0 = *tb_ptr++; +t1 = tci_read_ri64(regs, _ptr); +t2 = tci_read_ri64(regs, _ptr); +tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); +break; +case INDEX_op_divu_i64: +t0 = *tb_ptr++; +t1 = tci_read_ri64(regs, _ptr); +t2 = tci_read_ri64(regs, _ptr); +tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); +break; +case INDEX_op_rem_i64: +t0 = *tb_ptr++; +t1 = tci_read_ri64(regs, _ptr); +t2 = tci_read_ri64(regs, _ptr); +tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); +break; +case INDEX_op_remu_i64: +t0 = *tb_ptr++; +t1 = tci_read_ri64(regs, _ptr); +t2 = tci_read_ri64(regs, _ptr); +tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; -#endif case INDEX_op_and_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, _ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6dc5bac2f3..3327ce3072 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -577,6 +577,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_sar_i64: case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ +case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ +case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ +case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ +case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); tcg_out_ri64(s, const_args[2], args[2]); @@ -590,12 +594,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_debug_assert(args[4] <= UINT8_MAX); tcg_out8(s, args[4]); break; -case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ -case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ -case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ -case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ -TODO(); -break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); -- 2.25.1
[PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly
From: Claudio Fontana
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture state in a
similar way where userspace code has identified that it needs to
deliver an exception to the guest.
In the case of ARM, that includes:
1) the vcpu thread got a SIGBUS indicating a memory error,
and we need to deliver a Synchronous External Abort to the guest to
let it know about the error.
2) the kernel told us about a debug exception (breakpoint, watchpoint)
but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
so it must be a breakpoint the guest itself has set up, therefore
we need to deliver it to the guest.
So in order to reuse code, the same arm_do_interrupt function is used.
This is all fine, but we need to avoid calling it using the callback
registered in CPUClass, since that one is now TCG-only.
Fortunately this is easily solved by replacing calls to
CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Cc: Peter Maydell
Message-Id: <20210204163931.7358-9-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 4
target/arm/kvm64.c | 6 ++
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 47e266d7e6..1a64bd748c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9969,6 +9969,10 @@ static void handle_semihosting(CPUState *cs)
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
+ *
+ * Note: this is used for both TCG (as the do_interrupt tcg op),
+ * and KVM to re-inject guest debug exceptions, and to
+ * inject a Synchronous-External-Abort.
*/
void arm_cpu_do_interrupt(CPUState *cs)
{
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 3c37fc4fb6..dff85f6db9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -946,7 +946,6 @@ static void kvm_inject_arm_sea(CPUState *c)
{
ARMCPU *cpu = ARM_CPU(c);
CPUARMState *env = >env;
-CPUClass *cc = CPU_GET_CLASS(c);
uint32_t esr;
bool same_el;
@@ -962,7 +961,7 @@ static void kvm_inject_arm_sea(CPUState *c)
env->exception.syndrome = esr;
-cc->do_interrupt(c);
+arm_cpu_do_interrupt(c);
}
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
@@ -1493,7 +1492,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct
kvm_debug_exit_arch *debug_exit)
{
int hsr_ec = syn_get_ec(debug_exit->hsr);
ARMCPU *cpu = ARM_CPU(cs);
-CPUClass *cc = CPU_GET_CLASS(cs);
CPUARMState *env = >env;
/* Ensure PC is synchronised */
@@ -1547,7 +1545,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct
kvm_debug_exit_arch *debug_exit)
env->exception.vaddress = debug_exit->far;
env->exception.target_el = 1;
qemu_mutex_lock_iothread();
-cc->do_interrupt(cs);
+arm_cpu_do_interrupt(cs);
qemu_mutex_unlock_iothread();
return false;
--
2.25.1
[PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
From: Claudio Fontana
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-16-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 103 ++--
include/hw/core/tcg-cpu-ops.h | 97 ++
target/arm/internals.h | 6 ++
accel/tcg/cpu-exec.c| 27 +
accel/tcg/cputlb.c | 35 +--
accel/tcg/user-exec.c | 9 +--
hw/mips/jazz.c | 7 ++-
softmmu/physmem.c | 13 ++--
target/alpha/cpu.c | 21 +--
target/arm/cpu.c| 41 -
target/arm/cpu64.c | 7 +--
target/arm/cpu_tcg.c| 28 +++--
target/avr/cpu.c| 19 --
target/avr/helper.c | 5 +-
target/cris/cpu.c | 43 -
target/cris/helper.c| 5 +-
target/hppa/cpu.c | 22 ---
target/i386/tcg/tcg-cpu.c | 26
target/lm32/cpu.c | 19 --
target/m68k/cpu.c | 19 --
target/microblaze/cpu.c | 25 +---
target/mips/cpu.c | 36 +++
target/moxie/cpu.c | 15 -
target/nios2/cpu.c | 18 --
target/openrisc/cpu.c | 17 --
target/riscv/cpu.c | 23 ---
target/rx/cpu.c | 20 +--
target/s390x/cpu.c | 33 ++
target/sh4/cpu.c| 21 +--
target/sparc/cpu.c | 25 +---
target/tilegx/cpu.c | 17 --
target/tricore/cpu.c| 12 +++-
target/unicore32/cpu.c | 17 --
target/xtensa/cpu.c | 23 ---
target/ppc/translate_init.c.inc | 33 ++
MAINTAINERS | 1 +
36 files changed, 582 insertions(+), 306 deletions(-)
create mode 100644 include/hw/core/tcg-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e76a49754d..4f6c6b18c9 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,78 +76,8 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
-/**
- * struct TcgCpuOperations: TCG operations specific to a CPU class
- */
-typedef struct TcgCpuOperations {
-/**
- * @initialize: Initalize TCG state
- *
- * Called when the first CPU is realized.
- */
-void (*initialize)(void);
-/**
- * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
- *
- * This is called when we abandon execution of a TB before starting it,
- * and must set all parts of the CPU state which the previous TB in the
- * chain may not have updated.
- * By default, when this is NULL, a call is made to @set_pc(tb->pc).
- *
- * If more state needs to be restored, the target must implement a
- * function to restore all the state, and register it here.
- */
-void (*synchronize_from_tb)(CPUState *cpu,
-const struct TranslationBlock *tb);
-/** @cpu_exec_enter: Callback for cpu_exec preparation */
-void (*cpu_exec_enter)(CPUState *cpu);
-/** @cpu_exec_exit: Callback for cpu_exec cleanup */
-void (*cpu_exec_exit)(CPUState *cpu);
-/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
-bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
-/** @do_interrupt: Callback for interrupt handling. */
-void (*do_interrupt)(CPUState *cpu);
-/**
- * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
- *
- * For system mode, if the access is valid, call tlb_set_page
- * and return true; if the access is invalid, and probe is
- * true, return false; otherwise raise an exception and do
- * not return. For user-only mode, always raise an exception
- * and do not return.
- */
-bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
-/** @debug_excp_handler: Callback for handling debug exceptions */
-void (*debug_excp_handler)(CPUState *cpu);
-
-/**
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
- */
-void
[PULL 33/46] cpu: Move cpu_exec_* to tcg_ops
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-6-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 12 ++--
accel/tcg/cpu-exec.c| 12 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 2 +-
target/arm/cpu64.c | 5 -
target/arm/cpu_tcg.c| 7 ++-
target/avr/cpu.c| 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 6 +++---
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c| 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 16 ++--
25 files changed, 54 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8cf5585db7..532984e016 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -99,6 +99,12 @@ typedef struct TcgCpuOperations {
*/
void (*synchronize_from_tb)(CPUState *cpu,
const struct TranslationBlock *tb);
+/** @cpu_exec_enter: Callback for cpu_exec preparation */
+void (*cpu_exec_enter)(CPUState *cpu);
+/** @cpu_exec_exit: Callback for cpu_exec cleanup */
+void (*cpu_exec_exit)(CPUState *cpu);
+/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
} TcgCpuOperations;
@@ -168,9 +174,6 @@ typedef struct TcgCpuOperations {
* @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
* gdb stub. Returns a pointer to the XML contents for the specified XML file
* or NULL if the CPU doesn't have a dynamically generated content for it.
- * @cpu_exec_enter: Callback for cpu_exec preparation.
- * @cpu_exec_exit: Callback for cpu_exec cleanup.
- * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
* @disas_set_info: Setup architecture specific components of disassembly info
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
@@ -233,9 +236,6 @@ struct CPUClass {
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
-void (*cpu_exec_enter)(CPUState *cpu);
-void (*cpu_exec_exit)(CPUState *cpu);
-bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 12b6a91d62..953f050698 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -262,8 +262,8 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
-if (cc->cpu_exec_enter) {
-cc->cpu_exec_enter(cpu);
+if (cc->tcg_ops.cpu_exec_enter) {
+cc->tcg_ops.cpu_exec_enter(cpu);
}
}
@@ -271,8 +271,8 @@ static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
-if (cc->cpu_exec_exit) {
-cc->cpu_exec_exit(cpu);
+if (cc->tcg_ops.cpu_exec_exit) {
+cc->tcg_ops.cpu_exec_exit(cpu);
}
}
@@ -655,8 +655,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
-if (cc->cpu_exec_interrupt &&
-cc->cpu_exec_interrupt(cpu, interrupt_request)) {
+if (cc->tcg_ops.cpu_exec_interrupt &&
+cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d66f0351a9..d9ced1635a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,7 +218,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void
*data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
-cc->cpu_exec_interrupt =
[PULL 29/46] cpu: Introduce TCGCpuOperations struct
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost
[claudio: move TCGCpuOperations inside include/hw/core/cpu.h]
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-2-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 16 +++-
cpu.c | 6 +-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 2 +-
target/avr/cpu.c| 2 +-
target/cris/cpu.c | 12 ++--
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c| 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c| 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 48 insertions(+), 30 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 140fa32a5e..26b89fd7a4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,6 +76,19 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
+/**
+ * struct TcgCpuOperations: TCG operations specific to a CPU class
+ */
+typedef struct TcgCpuOperations {
+/**
+ * @initialize: Initalize TCG state
+ *
+ * Called when the first CPU is realized.
+ */
+void (*initialize)(void);
+
+} TcgCpuOperations;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -222,12 +235,13 @@ struct CPUClass {
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
-void (*tcg_initialize)(void);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+
+TcgCpuOperations tcg_ops;
};
/*
diff --git a/cpu.c b/cpu.c
index 0b245cda2e..79a2bf12b3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -159,14 +159,18 @@ void cpu_exec_initfn(CPUState *cpu)
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+#ifdef CONFIG_TCG
static bool tcg_target_initialized;
+#endif /* CONFIG_TCG */
cpu_list_add(cpu);
+#ifdef CONFIG_TCG
if (tcg_enabled() && !tcg_target_initialized) {
tcg_target_initialized = true;
-cc->tcg_initialize();
+cc->tcg_ops.initialize();
}
+#endif /* CONFIG_TCG */
tlb_init(cpu);
qemu_plugin_vcpu_init_hook(cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b3fd6643e8..d66f0351a9 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -231,7 +231,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void
*data)
dc->vmsd = _alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
-cc->tcg_initialize = alpha_translate_init;
+cc->tcg_ops.initialize = alpha_translate_init;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 40142ac141..fa4d4ba4eb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2276,7 +2276,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
-cc->tcg_initialize = arm_translate_init;
+cc->tcg_ops.initialize = arm_translate_init;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 6f3d5a9e4a..fb66695fbb 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = _avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
-cc->tcg_initialize = avr_cpu_tcg_init;
+cc->tcg_ops.initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c
[PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn
From: Claudio Fontana
move away TCG-only code, make it compile only on TCG.
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-4-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 11 +--
include/hw/core/cpu.h | 2 ++
accel/tcg/cpu-exec.c | 28 +
cpu.c | 70 --
hw/core/cpu.c | 6 +++-
5 files changed, 77 insertions(+), 40 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 4b5408c341..cfb1d79331 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -410,19 +410,26 @@ static inline bool tlb_hit(target_ulong tlb_addr,
target_ulong addr)
}
#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
void dump_drift_info(void);
+/* accel/tcg/translate-all.c */
void dump_exec_info(void);
void dump_opcount_info(void);
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
+#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
+int cpu_exec(CPUState *cpu);
+void tcg_exec_realizefn(CPUState *cpu, Error **errp);
+void tcg_exec_unrealizefn(CPUState *cpu);
+#endif /* CONFIG_TCG */
+
/* Returns: 0 on success, -1 on error */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
void *ptr, target_ulong len, bool is_write);
-int cpu_exec(CPUState *cpu);
-
/**
* cpu_set_cpustate_pointers(cpu)
* @cpu: The cpu object
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 26b89fd7a4..d0b17dcc4c 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1126,6 +1126,8 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, int
asidx);
void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
+
+/* $(top_srcdir)/cpu.c */
void cpu_exec_initfn(CPUState *cpu);
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 6d017e46dd..5628a156d1 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -828,6 +828,34 @@ int cpu_exec(CPUState *cpu)
return ret;
}
+void tcg_exec_realizefn(CPUState *cpu, Error **errp)
+{
+static bool tcg_target_initialized;
+CPUClass *cc = CPU_GET_CLASS(cpu);
+
+if (!tcg_target_initialized) {
+cc->tcg_ops.initialize();
+tcg_target_initialized = true;
+}
+tlb_init(cpu);
+qemu_plugin_vcpu_init_hook(cpu);
+
+#ifndef CONFIG_USER_ONLY
+tcg_iommu_init_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+}
+
+/* undo the initializations in reverse order */
+void tcg_exec_unrealizefn(CPUState *cpu)
+{
+#ifndef CONFIG_USER_ONLY
+tcg_iommu_free_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+
+qemu_plugin_vcpu_exit_hook(cpu);
+tlb_destroy(cpu);
+}
+
#ifndef CONFIG_USER_ONLY
void dump_drift_info(void)
diff --git a/cpu.c b/cpu.c
index 79a2bf12b3..bfbe5a66f9 100644
--- a/cpu.c
+++ b/cpu.c
@@ -124,12 +124,34 @@ const VMStateDescription vmstate_cpu_common = {
};
#endif
-void cpu_exec_unrealizefn(CPUState *cpu)
+void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
-tlb_destroy(cpu);
-cpu_list_remove(cpu);
+cpu_list_add(cpu);
+
+#ifdef CONFIG_TCG
+/* NB: errp parameter is unused currently */
+if (tcg_enabled()) {
+tcg_exec_realizefn(cpu, errp);
+}
+#endif /* CONFIG_TCG */
+
+#ifdef CONFIG_USER_ONLY
+assert(cc->vmsd == NULL);
+#else
+if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+vmstate_register(NULL, cpu->cpu_index, _cpu_common, cpu);
+}
+if (cc->vmsd != NULL) {
+vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+}
+#endif /* CONFIG_USER_ONLY */
+}
+
+void cpu_exec_unrealizefn(CPUState *cpu)
+{
+CPUClass *cc = CPU_GET_CLASS(cpu);
#ifdef CONFIG_USER_ONLY
assert(cc->vmsd == NULL);
@@ -140,8 +162,15 @@ void cpu_exec_unrealizefn(CPUState *cpu)
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, _cpu_common, cpu);
}
-tcg_iommu_free_notifier_list(cpu);
#endif
+#ifdef CONFIG_TCG
+/* NB: errp parameter is unused currently */
+if (tcg_enabled()) {
+tcg_exec_unrealizefn(cpu);
+}
+#endif /* CONFIG_TCG */
+
+cpu_list_remove(cpu);
}
void cpu_exec_initfn(CPUState *cpu)
@@ -156,39 +185,6 @@ void cpu_exec_initfn(CPUState *cpu)
#endif
}
-void cpu_exec_realizefn(CPUState *cpu, Error **errp)
-{
-CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_TCG
-static bool tcg_target_initialized;
-#endif /* CONFIG_TCG */
-
-cpu_list_add(cpu);
-
-#ifdef CONFIG_TCG
-if (tcg_enabled() && !tcg_target_initialized) {
-tcg_target_initialized = true;
-cc->tcg_ops.initialize();
-}
-#endif /* CONFIG_TCG */
-tlb_init(cpu);
-
-qemu_plugin_vcpu_init_hook(cpu);
[PULL 38/46] cpu: move cc->transaction_failed to tcg_ops
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
avoiding its use in headers used by common_ss code (should be poisoned).
Note: need to be careful with the use of CONFIG_USER_ONLY,
Message-Id: <20210204163931.7358-11-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 28 +---
hw/mips/jazz.c| 9 +++--
target/alpha/cpu.c| 2 +-
target/arm/cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c| 2 +-
target/riscv/cpu_helper.c | 2 +-
target/sparc/cpu.c| 2 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c| 4 ++--
12 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 60cf20bf05..41ce1daefc 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -122,6 +122,14 @@ typedef struct TcgCpuOperations {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+/**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
} TcgCpuOperations;
/**
@@ -133,8 +141,6 @@ typedef struct TcgCpuOperations {
* @has_work: Callback for checking if there is work to do.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -203,10 +209,6 @@ struct CPUClass {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
-void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -879,9 +881,6 @@ CPUState *cpu_by_arch_id(int64_t id);
void cpu_interrupt(CPUState *cpu, int mask);
-#ifdef NEED_CPU_H
-
-#ifdef CONFIG_SOFTMMU
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -900,14 +899,13 @@ static inline void cpu_transaction_failed(CPUState *cpu,
hwaddr physaddr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
-if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed)
{
-cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
+if (!cpu->ignore_memory_transaction_failures &&
+cc->tcg_ops.do_transaction_failed) {
+cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx, attrs,
+ response, retaddr);
}
}
-#endif
-
-#endif /* NEED_CPU_H */
/**
* cpu_set_pc:
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index f9442731dd..46c71a0ac8 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE
\
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -137,6 +139,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs,
hwaddr physaddr,
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
[PULL 25/46] tcg/tci: Remove TODO as unused
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 8
1 file changed, 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 5c84a1c979..e0d815e4b2 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -33,14 +33,6 @@
#include "tcg/tcg-op.h"
#include "qemu/compiler.h"
-/* Marker for missing code. */
-#define TODO() \
-do { \
-fprintf(stderr, "TODO %s:%u: %s()\n", \
-__FILE__, __LINE__, __func__); \
-tcg_abort(); \
-} while (0)
-
#if MAX_OPC_PARAM_IARGS != 6
# error Fix needed, number of supported input arguments changed!
#endif
--
2.25.1
[PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented. Shortly, we will
rearrange the encoding which will make 32 regs impossible.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 32 +---
tcg/tci/tcg-target.c.inc | 26 --
2 files changed, 5 insertions(+), 53 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 7fc349a3de..8f7ed676fc 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -133,11 +133,8 @@
#define TCG_TARGET_HAS_mulu2_i321
#endif /* TCG_TARGET_REG_BITS == 64 */
-/* Number of registers available.
- For 32 bit hosts, we need more than 8 registers (call arguments). */
-/* #define TCG_TARGET_NB_REGS 8 */
+/* Number of registers available. */
#define TCG_TARGET_NB_REGS 16
-/* #define TCG_TARGET_NB_REGS 32 */
/* List of registers which are used by TCG. */
typedef enum {
@@ -149,7 +146,6 @@ typedef enum {
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
@@ -158,33 +154,15 @@ typedef enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
-#if TCG_TARGET_NB_REGS >= 32
-TCG_REG_R16,
-TCG_REG_R17,
-TCG_REG_R18,
-TCG_REG_R19,
-TCG_REG_R20,
-TCG_REG_R21,
-TCG_REG_R22,
-TCG_REG_R23,
-TCG_REG_R24,
-TCG_REG_R25,
-TCG_REG_R26,
-TCG_REG_R27,
-TCG_REG_R28,
-TCG_REG_R29,
-TCG_REG_R30,
-TCG_REG_R31,
-#endif
-#endif
+
+TCG_AREG0 = TCG_REG_R14,
+TCG_REG_CALL_STACK = TCG_REG_R15,
+
/* Special value UINT8_MAX is used by TCI to encode constant values. */
TCG_CONST = UINT8_MAX
} TCGReg;
-#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
-
/* Used for function call generation. */
-#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
#define TCG_TARGET_CALL_STACK_OFFSET0
#define TCG_TARGET_STACK_ALIGN 16
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 3327ce3072..7e3bed811e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
@@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
-#endif
};
#if MAX_OPC_PARAM_IARGS != 6
@@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] = {
#if TCG_TARGET_REG_BITS == 32
/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
TCG_REG_R12,
-#else
-# error Too few input registers available
-#endif
#endif
};
@@ -245,7 +239,6 @@ static const char *const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r05",
"r06",
"r07",
-#if TCG_TARGET_NB_REGS >= 16
"r08",
"r09",
"r10",
@@ -254,25 +247,6 @@ static const char *const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r13",
"r14",
"r15",
-#if TCG_TARGET_NB_REGS >= 32
-"r16",
-"r17",
-"r18",
-"r19",
-"r20",
-"r21",
-"r22",
-"r23",
-"r24",
-"r25",
-"r26",
-"r27",
-"r28",
-"r29",
-"r30",
-"r31"
-#endif
-#endif
};
#endif
--
2.25.1
[PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64}
Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6819c97792..fe935e71a3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -618,7 +618,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); *(uint8_t *)(t1 + t2) = t0; break; -case INDEX_op_st16_i32: +CASE_32_64(st16) t0 = tci_read_r16(regs, _ptr); t1 = tci_read_r(regs, _ptr); t2 = tci_read_s32(_ptr); @@ -874,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; -case INDEX_op_st16_i64: -t0 = tci_read_r16(regs, _ptr); -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -*(uint16_t *)(t1 + t2) = t0; -break; case INDEX_op_st32_i64: t0 = tci_read_r32(regs, _ptr); t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG
From: Claudio Fontana for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana Reviewed-by: Alistair Francis Reviewed-by: Alex Bennée Message-Id: <20210204163931.7358-3-cfont...@suse.de> Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 567f6790a9..60d0b43153 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -617,10 +617,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; -#ifdef CONFIG_TCG cc->tcg_ops.initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -#endif + device_class_set_props(dc, riscv_cpu_properties); } -- 2.25.1
[PULL 22/46] tcg/tci: Use g_assert_not_reached
Three TODO instances are never happen cases.
Other uses of tcg_abort are also indicating unreachable cases.
Tested-by: Alex Bennée
Reviewed-by: Stefan Weil
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index eb70672efb..36d594672f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -362,7 +362,7 @@ static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond
condition)
result = (u0 > u1);
break;
default:
-TODO();
+g_assert_not_reached();
}
return result;
}
@@ -404,7 +404,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond
condition)
result = (u0 > u1);
break;
default:
-TODO();
+g_assert_not_reached();
}
return result;
}
@@ -1114,7 +1114,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tmp32 = qemu_ld_beul;
break;
default:
-tcg_abort();
+g_assert_not_reached();
}
tci_write_reg(regs, t0, tmp32);
break;
@@ -1163,7 +1163,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tmp64 = qemu_ld_beq;
break;
default:
-tcg_abort();
+g_assert_not_reached();
}
tci_write_reg(regs, t0, tmp64);
if (TCG_TARGET_REG_BITS == 32) {
@@ -1191,7 +1191,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
qemu_st_bel(t0);
break;
default:
-tcg_abort();
+g_assert_not_reached();
}
break;
case INDEX_op_qemu_st_i64:
@@ -1221,7 +1221,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
qemu_st_beq(tmp64);
break;
default:
-tcg_abort();
+g_assert_not_reached();
}
break;
case INDEX_op_mb:
@@ -1229,8 +1229,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
smp_mb();
break;
default:
-TODO();
-break;
+g_assert_not_reached();
}
tci_assert(tb_ptr == old_code_ptr + op_size);
}
--
2.25.1
[PULL 28/46] tcg/tci: Remove TCG_CONST
Restrict all operands to registers. All constants will be forced
into registers by the middle-end. Removing the difference in how
immediate integers were encoded will allow more code to be shared
between 32-bit and 64-bit operations.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target-con-set.h | 6 +-
tcg/tci/tcg-target.h | 3 -
tcg/tci.c| 189 +--
tcg/tci/tcg-target.c.inc | 85
4 files changed, 89 insertions(+), 194 deletions(-)
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
index 38e82f7535..f51b7bcb13 100644
--- a/tcg/tci/tcg-target-con-set.h
+++ b/tcg/tci/tcg-target-con-set.h
@@ -10,16 +10,12 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I2(r, r)
-C_O0_I2(r, ri)
C_O0_I3(r, r, r)
-C_O0_I4(r, r, ri, ri)
C_O0_I4(r, r, r, r)
C_O1_I1(r, r)
C_O1_I2(r, 0, r)
-C_O1_I2(r, ri, ri)
C_O1_I2(r, r, r)
-C_O1_I2(r, r, ri)
-C_O1_I4(r, r, r, ri, ri)
+C_O1_I4(r, r, r, r, r)
C_O2_I1(r, r, r)
C_O2_I2(r, r, r, r)
C_O2_I4(r, r, r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 8f7ed676fc..9c0021a26f 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -157,9 +157,6 @@ typedef enum {
TCG_AREG0 = TCG_REG_R14,
TCG_REG_CALL_STACK = TCG_REG_R15,
-
-/* Special value UINT8_MAX is used by TCI to encode constant values. */
-TCG_CONST = UINT8_MAX
} TCGReg;
/* Used for function call generation. */
diff --git a/tcg/tci.c b/tcg/tci.c
index 935eb87330..fb3c97aaf1 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -255,61 +255,6 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint8_t
**tb_ptr)
return taddr;
}
-/* Read indexed register or constant (native size) from bytecode. */
-static tcg_target_ulong
-tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
-tcg_target_ulong value;
-TCGReg r = **tb_ptr;
-*tb_ptr += 1;
-if (r == TCG_CONST) {
-value = tci_read_i(tb_ptr);
-} else {
-value = tci_read_reg(regs, r);
-}
-return value;
-}
-
-/* Read indexed register or constant (32 bit) from bytecode. */
-static uint32_t tci_read_ri32(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
-uint32_t value;
-TCGReg r = **tb_ptr;
-*tb_ptr += 1;
-if (r == TCG_CONST) {
-value = tci_read_i32(tb_ptr);
-} else {
-value = tci_read_reg32(regs, r);
-}
-return value;
-}
-
-#if TCG_TARGET_REG_BITS == 32
-/* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
-static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
-uint32_t low = tci_read_ri32(regs, tb_ptr);
-return tci_uint64(tci_read_ri32(regs, tb_ptr), low);
-}
-#elif TCG_TARGET_REG_BITS == 64
-/* Read indexed register or constant (64 bit) from bytecode. */
-static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
-uint64_t value;
-TCGReg r = **tb_ptr;
-*tb_ptr += 1;
-if (r == TCG_CONST) {
-value = tci_read_i64(tb_ptr);
-} else {
-value = tci_read_reg64(regs, r);
-}
-return value;
-}
-#endif
-
static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
{
tcg_target_ulong label = tci_read_i(tb_ptr);
@@ -504,7 +449,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
switch (opc) {
case INDEX_op_call:
-t0 = tci_read_ri(regs, _ptr);
+t0 = tci_read_i(_ptr);
tci_tb_ptr = (uintptr_t)tb_ptr;
#if TCG_TARGET_REG_BITS == 32
tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
@@ -539,7 +484,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, _ptr);
-t2 = tci_read_ri32(regs, _ptr);
+t2 = tci_read_r32(regs, _ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
@@ -547,7 +492,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
case INDEX_op_setcond2_i32:
t0 = *tb_ptr++;
tmp64 = tci_read_r64(regs, _ptr);
-v64 = tci_read_ri64(regs, _ptr);
+v64 = tci_read_r64(regs, _ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
break;
@@ -555,7 +500,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, _ptr);
-t2 = tci_read_ri64(regs, _ptr);
+t2 = tci_read_r64(regs, _ptr);
condition = *tb_ptr++;
tci_write_reg(regs,
[PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64}
Eliminating a TODO for ld16s_i64. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index b64d611ec9..259a8538bf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -599,7 +599,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; -case INDEX_op_ld16s_i32: +CASE_32_64(ld16s) t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); t2 = tci_read_s32(_ptr); @@ -861,9 +861,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (64 bit). */ -case INDEX_op_ld16s_i64: -TODO(); -break; case INDEX_op_ld32u_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage
This was removed from tcg_target_reg_alloc_order and
tcg_target_call_iarg_regs on the assumption that it
was the stack. This was incorrectly copied from i386.
For tci, the stack is R15.
By adding R4 back to tcg_target_call_iarg_regs, adjust the other
entries so that 6 (or 12) entries are still present in the array,
and adjust the numbers in the interpreter.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c| 8
tcg/tci/tcg-target.c.inc | 7 +--
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e0d815e4b2..935eb87330 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -511,14 +511,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_read_reg(regs, TCG_REG_R1),
tci_read_reg(regs, TCG_REG_R2),
tci_read_reg(regs, TCG_REG_R3),
+ tci_read_reg(regs, TCG_REG_R4),
tci_read_reg(regs, TCG_REG_R5),
tci_read_reg(regs, TCG_REG_R6),
tci_read_reg(regs, TCG_REG_R7),
tci_read_reg(regs, TCG_REG_R8),
tci_read_reg(regs, TCG_REG_R9),
tci_read_reg(regs, TCG_REG_R10),
- tci_read_reg(regs, TCG_REG_R11),
- tci_read_reg(regs, TCG_REG_R12));
+ tci_read_reg(regs, TCG_REG_R11));
tci_write_reg(regs, TCG_REG_R0, tmp64);
tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32);
#else
@@ -526,8 +526,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_read_reg(regs, TCG_REG_R1),
tci_read_reg(regs, TCG_REG_R2),
tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R5),
- tci_read_reg(regs, TCG_REG_R6));
+ tci_read_reg(regs, TCG_REG_R4),
+ tci_read_reg(regs, TCG_REG_R5));
tci_write_reg(regs, TCG_REG_R0, tmp64);
#endif
break;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 7e3bed811e..aba7f75ad1 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -181,9 +181,7 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
-#if 0 /* used for TCG_REG_CALL_STACK */
TCG_REG_R4,
-#endif
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
@@ -206,19 +204,16 @@ static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
-#if 0 /* used for TCG_REG_CALL_STACK */
TCG_REG_R4,
-#endif
TCG_REG_R5,
-TCG_REG_R6,
#if TCG_TARGET_REG_BITS == 32
/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
+TCG_REG_R6,
TCG_REG_R7,
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
-TCG_REG_R12,
#endif
};
--
2.25.1
[PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}
Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ee2cd7dfa2..eb70672efb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -625,6 +625,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, *(uint16_t *)(t1 + t2) = t0; break; case INDEX_op_st_i32: +CASE_64(st32) t0 = tci_read_r32(regs, _ptr); t1 = tci_read_r(regs, _ptr); t2 = tci_read_s32(_ptr); @@ -873,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; -case INDEX_op_st32_i64: -t0 = tci_read_r32(regs, _ptr); -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -*(uint32_t *)(t1 + t2) = t0; -break; case INDEX_op_st_i64: t0 = tci_read_r64(regs, _ptr); t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*
We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c| 12 tcg/tci/tcg-target.c.inc | 8 2 files changed, 20 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 36d594672f..25329345cf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -652,7 +652,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri32(regs, _ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(regs, _ptr); @@ -677,12 +676,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri32(regs, _ptr); tci_write_reg(regs, t0, t1 % t2); break; -#elif TCG_TARGET_HAS_div2_i32 -case INDEX_op_div2_i32: -case INDEX_op_divu2_i32: -TODO(); -break; -#endif case INDEX_op_and_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(regs, _ptr); @@ -908,11 +901,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_remu_i64: TODO(); break; -#elif TCG_TARGET_HAS_div2_i64 -case INDEX_op_div2_i64: -case INDEX_op_divu2_i64: -TODO(); -break; #endif case INDEX_op_and_i64: t0 = *tb_ptr++; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 82efb9af60..6dc5bac2f3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -596,10 +596,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ TODO(); break; -case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ -case INDEX_op_divu2_i64:/* Optional (TCG_TARGET_HAS_div2_i64). */ -TODO(); -break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); @@ -639,10 +635,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_ri32(s, const_args[1], args[1]); tcg_out_ri32(s, const_args[2], args[2]); break; -case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ -case INDEX_op_divu2_i32:/* Optional (TCG_TARGET_HAS_div2_i32). */ -TODO(); -break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: -- 2.25.1
[PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64}
Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0f56702b93..7e108bcbb3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -455,6 +455,18 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) # define qemu_st_beq(X) stq_be_p(g2h(taddr), X) #endif +#if TCG_TARGET_REG_BITS == 64 +# define CASE_32_64(x) \ +case glue(glue(INDEX_op_, x), _i64): \ +case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ +case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ +case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + /* Interpret pseudo code in tb. */ /* * Disable CFI checks. @@ -569,7 +581,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (32 bit). */ -case INDEX_op_ld8u_i32: +CASE_32_64(ld8u) t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); t2 = tci_read_s32(_ptr); @@ -843,12 +855,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (64 bit). */ -case INDEX_op_ld8u_i64: -t0 = *tb_ptr++; -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); -break; case INDEX_op_ld8s_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 20/46] tcg/tci: Move stack bounds check to compile-time
The existing check was incomplete:
(1) Only applied to two of the 7 stores, and not to the loads at all.
(2) Only checked the upper, but not the lower bound of the stack.
Doing this at compile time means that we don't need to do it
at runtime as well.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c| 2 --
tcg/tci/tcg-target.c.inc | 13 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index fe935e71a3..ee2cd7dfa2 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -628,7 +628,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = tci_read_r32(regs, _ptr);
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint32_t *)(t1 + t2) = t0;
break;
@@ -884,7 +883,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = tci_read_r64(regs, _ptr);
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint64_t *)(t1 + t2) = t0;
break;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index f0f6b13112..82efb9af60 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -375,10 +375,20 @@ static void tci_out_label(TCGContext *s, TCGLabel *label)
}
}
+static void stack_bounds_check(TCGReg base, target_long offset)
+{
+if (base == TCG_REG_CALL_STACK) {
+tcg_debug_assert(offset < 0);
+tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long)));
+}
+}
+
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2)
{
uint8_t *old_code_ptr = s->code_ptr;
+
+stack_bounds_check(arg1, arg2);
if (type == TCG_TYPE_I32) {
tcg_out_op_t(s, INDEX_op_ld_i32);
tcg_out_r(s, ret);
@@ -514,6 +524,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
+stack_bounds_check(args[1], args[2]);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_debug_assert(args[2] == (int32_t)args[2]);
@@ -716,6 +727,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg
arg, TCGReg arg1,
intptr_t arg2)
{
uint8_t *old_code_ptr = s->code_ptr;
+
+stack_bounds_check(arg1, arg2);
if (type == TCG_TYPE_I32) {
tcg_out_op_t(s, INDEX_op_st_i32);
tcg_out_r(s, arg);
--
2.25.1
[PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64}
Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 55863f76a7..6819c97792 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -612,7 +612,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; -case INDEX_op_st8_i32: +CASE_32_64(st8) t0 = tci_read_r8(regs, _ptr); t1 = tci_read_r(regs, _ptr); t2 = tci_read_s32(_ptr); @@ -874,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; -case INDEX_op_st8_i64: -t0 = tci_read_r8(regs, _ptr); -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -*(uint8_t *)(t1 + t2) = t0; -break; case INDEX_op_st16_i64: t0 = tci_read_r16(regs, _ptr); t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64}
Eliminating a TODO for ld16u_i32. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c31be1a1f4..b64d611ec9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -593,8 +593,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; -case INDEX_op_ld16u_i32: -TODO(); +CASE_32_64(ld16u) +t0 = *tb_ptr++; +t1 = tci_read_r(regs, _ptr); +t2 = tci_read_s32(_ptr); +tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; case INDEX_op_ld16s_i32: t0 = *tb_ptr++; @@ -858,12 +861,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (64 bit). */ -case INDEX_op_ld16u_i64: -t0 = *tb_ptr++; -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); -break; case INDEX_op_ld16s_i64: TODO(); break; -- 2.25.1
[PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers
Note that we had two functions of the same name: a 32-bit version
which took two register numbers and a 64-bit version which was a
no-op wrapper for tcg_write_reg. After this, we are left with
only the 32-bit version.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 60 +--
1 file changed, 27 insertions(+), 33 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 39ad00663f..0f56702b93 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -124,12 +124,6 @@ static void tci_write_reg64(tcg_target_ulong *regs,
uint32_t high_index,
tci_write_reg(regs, low_index, value);
tci_write_reg(regs, high_index, value >> 32);
}
-#elif TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value)
-{
-tci_write_reg(regs, index, value);
-}
#endif
#if TCG_TARGET_REG_BITS == 32
@@ -559,7 +553,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t1 = tci_read_r64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
condition = *tb_ptr++;
-tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition));
+tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
#endif
case INDEX_op_mov_i32:
@@ -839,12 +833,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, _ptr);
-tci_write_reg64(regs, t0, t1);
+tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(_ptr);
-tci_write_reg64(regs, t0, t1);
+tci_write_reg(regs, t0, t1);
break;
/* Load/store operations (64 bit). */
@@ -886,7 +880,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2));
+tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st8_i64:
t0 = tci_read_r8(regs, _ptr);
@@ -920,19 +914,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 + t2);
+tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 - t2);
+tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 * t2);
+tci_write_reg(regs, t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
@@ -951,19 +945,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 & t2);
+tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 | t2);
+tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 ^ t2);
+tci_write_reg(regs, t0, t1 ^ t2);
break;
/* Shift/rotate operations (64 bit). */
@@ -972,32 +966,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 << (t2 & 63));
+tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, t1 >> (t2 & 63));
+tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, _ptr);
t2 = tci_read_ri64(regs, _ptr);
-tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63)));
+
[PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}
Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 259a8538bf..55863f76a7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -606,6 +606,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: +CASE_64(ld32u) t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); t2 = tci_read_s32(_ptr); @@ -861,12 +862,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (64 bit). */ -case INDEX_op_ld32u_i64: -t0 = *tb_ptr++; -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); -break; case INDEX_op_ld32s_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e8023b5384..740244cc54 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,11 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index,
tcg_target_ulong value)
regs[index] = value;
}
-static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
-{
-tci_write_reg(regs, index, value);
-}
-
#if TCG_TARGET_REG_BITS == 64
static void
tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
@@ -598,7 +593,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
+tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i32:
TODO();
@@ -872,7 +867,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
+tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
t0 = *tb_ptr++;
--
2.25.1
[PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 740244cc54..005d2946c4 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index,
tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
-{
-tci_write_reg(regs, index, value);
-}
-#endif
-
static void
tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
{
@@ -879,7 +871,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2));
+tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break;
case INDEX_op_ld16s_i64:
TODO();
--
2.25.1
[PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers
For a 64-bit TCI, the upper bits of a 32-bit operation are
undefined (much like a native ppc64 32-bit operation). It
simplifies everything if we don't force-extend the result.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 66 +--
1 file changed, 30 insertions(+), 36 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 005d2946c4..39ad00663f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,12 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index,
tcg_target_ulong value)
regs[index] = value;
}
-static void
-tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
-{
-tci_write_reg(regs, index, value);
-}
-
#if TCG_TARGET_REG_BITS == 32
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
@@ -549,7 +543,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t1 = tci_read_r32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
condition = *tb_ptr++;
-tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition));
+tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
@@ -557,7 +551,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tmp64 = tci_read_r64(regs, _ptr);
v64 = tci_read_ri64(regs, _ptr);
condition = *tb_ptr++;
-tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition));
+tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
@@ -571,12 +565,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
case INDEX_op_mov_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, _ptr);
-tci_write_reg32(regs, t0, t1);
+tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i32:
t0 = *tb_ptr++;
t1 = tci_read_i32(_ptr);
-tci_write_reg32(regs, t0, t1);
+tci_write_reg(regs, t0, t1);
break;
/* Load/store operations (32 bit). */
@@ -603,7 +597,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2));
+tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_st8_i32:
t0 = tci_read_r8(regs, _ptr);
@@ -631,44 +625,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, t1 + t2);
+tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, t1 - t2);
+tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, t1 * t2);
+tci_write_reg(regs, t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i32
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2);
+tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, t1 / t2);
+tci_write_reg(regs, t0, t1 / t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2);
+tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, _ptr);
t2 = tci_read_ri32(regs, _ptr);
-tci_write_reg32(regs, t0, t1 % t2);
+tci_write_reg(regs, t0, t1 % t2);
break;
#elif TCG_TARGET_HAS_div2_i32
case INDEX_op_div2_i32:
@@ -680,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 =
[PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64}
Eliminating a TODO for ld8s_i32. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 7e108bcbb3..c31be1a1f4 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -587,8 +587,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_s32(_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; -case INDEX_op_ld8s_i32: -TODO(); +CASE_32_64(ld8s) +t0 = *tb_ptr++; +t1 = tci_read_r(regs, _ptr); +t2 = tci_read_s32(_ptr); +tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; case INDEX_op_ld16u_i32: TODO(); @@ -855,12 +858,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (64 bit). */ -case INDEX_op_ld8s_i64: -t0 = *tb_ptr++; -t1 = tci_read_r(regs, _ptr); -t2 = tci_read_s32(_ptr); -tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); -break; case INDEX_op_ld16u_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, _ptr); -- 2.25.1
[PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local
Each thread must have its own pc, even under TCI.
Remove the GETPC ifdef, because GETPC is always available for
helpers, and thus is always required. Move the assignment
under INDEX_op_call, because the value is only visible when
we make a call to a helper function.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-Id: <20210204014509.882821-6-richard.hender...@linaro.org>
---
include/exec/exec-all.h | 2 +-
tcg/tcg-common.c| 4
tcg/tci.c | 7 +++
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 125000bcf7..f933c74c44 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -544,7 +544,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n,
uintptr_t addr);
/* GETPC is the true target of the return instruction that we'll execute. */
#if defined(CONFIG_TCG_INTERPRETER)
-extern uintptr_t tci_tb_ptr;
+extern __thread uintptr_t tci_tb_ptr;
# define GETPC() tci_tb_ptr
#else
# define GETPC() \
diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c
index 7e1992e79e..aa0c4f60c9 100644
--- a/tcg/tcg-common.c
+++ b/tcg/tcg-common.c
@@ -25,10 +25,6 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
-#if defined(CONFIG_TCG_INTERPRETER)
-uintptr_t tci_tb_ptr;
-#endif
-
TCGOpDef tcg_op_defs[] = {
#define DEF(s, oargs, iargs, cargs, flags) \
{ #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
diff --git a/tcg/tci.c b/tcg/tci.c
index 3fc82d3c79..b3f9531a73 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,6 +57,8 @@ typedef uint64_t (*helper_function)(tcg_target_ulong,
tcg_target_ulong,
tcg_target_ulong, tcg_target_ulong);
#endif
+__thread uintptr_t tci_tb_ptr;
+
static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg
index)
{
tci_assert(index < TCG_TARGET_NB_REGS);
@@ -526,16 +528,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
#endif
TCGMemOpIdx oi;
-#if defined(GETPC)
-tci_tb_ptr = (uintptr_t)tb_ptr;
-#endif
-
/* Skip opcode and size entry. */
tb_ptr += 2;
switch (opc) {
case INDEX_op_call:
t0 = tci_read_ri(regs, _ptr);
+tci_tb_ptr = (uintptr_t)tb_ptr;
#if TCG_TARGET_REG_BITS == 32
tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
tci_read_reg(regs, TCG_REG_R1),
--
2.25.1
[PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32
From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reported-by: Alex Bennée Signed-off-by: Stefan Weil Message-Id: <20210128024814.2056958-1...@weilnetz.de> Signed-off-by: Richard Henderson --- tcg/tci.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tcg/tci.c b/tcg/tci.c index b3f9531a73..2ba97da189 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -615,7 +615,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, TODO(); break; case INDEX_op_ld16s_i32: -TODO(); +t0 = *tb_ptr++; +t1 = tci_read_r(regs, _ptr); +t2 = tci_read_s32(_ptr); +tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: t0 = *tb_ptr++; -- 2.25.1
[PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index c3a8511dfe..e8023b5384 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index,
tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value)
-{
-tci_write_reg(regs, index, value);
-}
-#endif
-
static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
{
tci_write_reg(regs, index, value);
@@ -907,7 +899,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, _ptr);
t2 = tci_read_s32(_ptr);
-tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2));
+tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
--
2.25.1
[PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd
argument is an integer, not a temporary, which now tickles
an assert added in e89b28a6350.
Previously, the value computed into v2 would be garbage for
rotli_vec, but as the value was unused it caused no harm.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 3c1ee39fd4..1376cdc404 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2488,7 +2488,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
v0 = temp_tcgv_vec(arg_temp(a0));
v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
a2 = va_arg(va, TCGArg);
-v2 = temp_tcgv_vec(arg_temp(a2));
+va_end(va);
switch (opc) {
case INDEX_op_rotli_vec:
@@ -2502,6 +2502,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
/* Right shifts are negative left shifts for AArch64. */
+v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
tcg_gen_neg_vec(vece, t1, v2);
opc = (opc == INDEX_op_shrv_vec
@@ -2512,6 +2513,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
break;
case INDEX_op_rotlv_vec:
+v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
tcg_gen_sub_vec(vece, t1, v2, c1);
@@ -2525,6 +2527,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
break;
case INDEX_op_rotrv_vec:
+v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
t2 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
@@ -2543,8 +2546,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
default:
g_assert_not_reached();
}
-
-va_end(va);
}
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
--
2.25.1
[PULL 04/46] configure: Fix --enable-tcg-interpreter
The configure option was backward, and we failed to
pass the value on to meson.
Fixes: 23a77b2d18b ("build-system: clean up TCG/TCI configury")
Tested-by: Stefan Weil
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
configure | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index e85d6baf8f..a34f91171d 100755
--- a/configure
+++ b/configure
@@ -1110,9 +1110,9 @@ for opt do
;;
--enable-whpx) whpx="enabled"
;;
- --disable-tcg-interpreter) tcg_interpreter="true"
+ --disable-tcg-interpreter) tcg_interpreter="false"
;;
- --enable-tcg-interpreter) tcg_interpreter="false"
+ --enable-tcg-interpreter) tcg_interpreter="true"
;;
--disable-cap-ng) cap_ng="disabled"
;;
@@ -6417,6 +6417,7 @@ NINJA=$ninja $meson setup \
-Dvhost_user_blk_server=$vhost_user_blk_server \
-Dfuse=$fuse -Dfuse_lseek=$fuse_lseek
-Dguest_agent_msi=$guest_agent_msi \
$(if test "$default_features" = no; then echo
"-Dauto_features=disabled"; fi) \
+ -Dtcg_interpreter=$tcg_interpreter \
$cross_arg \
"$PWD" "$source_path"
--
2.25.1
[PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility
From: Philippe Mathieu-Daudé
The code is currently comparing c2 to the type promotion of
uint32_t and int32_t. That is, the conversion rules are as:
(common_type) c2 == (common_type) (uint32_t)
(is_unsigned
? (uint32_t)c2
: (uint32_t)(int32_t)c2)
In the signed case we lose the desired sign extensions because
of the argument promotion rules of the ternary operator.
Solve the problem by doing the round-trip parsing through the
intermediate type and back to the desired common type (all at
one expression).
Fixes: a534bb15f30 ("tcg/s390: Use constant pool for cmpi")
Tested-by: Richard W.M. Jones
Reviewed-by: David Hildenbrand
Reported-by: Miroslav Rezanina
Reported-by: Richard W.M. Jones
Suggested-by: David Hildenbrand
Suggested-by: Eric Blake
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210204182902.1742826-1-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index b67470137c..695d7ee652 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -1067,7 +1067,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond
c, TCGReg r1,
op = (is_unsigned ? RIL_CLFI : RIL_CFI);
tcg_out_insn_RIL(s, op, r1, c2);
goto exit;
-} else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) {
+} else if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 :
(TCGArg)(int32_t)c2)) {
op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
tcg_out_insn_RIL(s, op, r1, c2);
goto exit;
--
2.25.1
[PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64
From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reported-by: Alex Bennée Signed-off-by: Stefan Weil Message-Id: <20210128020425.2055454-1...@weilnetz.de> Signed-off-by: Richard Henderson --- tcg/tci.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tcg/tci.c b/tcg/tci.c index 2ba97da189..c3a8511dfe 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -883,7 +883,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: -TODO(); +t0 = *tb_ptr++; +t1 = tci_read_r(regs, _ptr); +t2 = tci_read_s32(_ptr); +tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; case INDEX_op_ld16u_i64: t0 = *tb_ptr++; -- 2.25.1
[PULL 02/46] exec/cpu-defs: Remove TCG backends dependency
From: Philippe Mathieu-Daudé "exec/cpu-defs.h" contains generic CPU definitions for the TCG frontends (mostly related to TLB). TCG backends definitions aren't relevant here. See tcg/README description: 4) Backend tcg-target.h contains the target specific definitions. tcg-target.c.inc contains the target specific code; it is #included by tcg/tcg.c, rather than being a standalone C file. So far only "tcg/tcg.h" requires these headers. Remove the "target-tcg.h" header dependency on TCG frontends, so we don't have to rebuild all frontends when hacking a single backend. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210204191423.1754158-1-f4...@amsat.org> Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index d1f5e3fc3d..ba3cd32a1e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -25,9 +25,6 @@ #include "qemu/host-utils.h" #include "qemu/thread.h" -#ifdef CONFIG_TCG -#include "tcg-target.h" -#endif #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif -- 2.25.1
[PULL 00/46] tcg patch queue
The following changes since commit d0dddab40e472ba62b5f43f11cc7dba085dabe71:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2021-02-05 15:27:02 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210205
for you to fetch changes up to fb6916dd6ca8bb4b42d44baba9c67ecaf2279577:
accel: introduce AccelCPUClass extending CPUClass (2021-02-05 10:24:15 -1000)
TCGCPUOps cleanups (claudio)
tcg/s390 compare fix (phil)
tcg/aarch64 rotli_vec fix
tcg/tci cleanups and fixes
Claudio Fontana (13):
target/riscv: remove CONFIG_TCG, as it is always TCG
accel/tcg: split TCG-only code from cpu_exec_realizefn
target/arm: do not use cc->do_interrupt for KVM directly
cpu: move cc->do_interrupt to tcg_ops
cpu: move cc->transaction_failed to tcg_ops
cpu: move do_unaligned_access to tcg_ops
physmem: make watchpoint checking code TCG-only
cpu: move adjust_watchpoint_address to tcg_ops
cpu: move debug_check_watchpoint to tcg_ops
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
accel: extend AccelState and AccelClass to user-mode
accel: replace struct CpusAccel with AccelOpsClass
accel: introduce AccelCPUClass extending CPUClass
Eduardo Habkost (5):
cpu: Introduce TCGCpuOperations struct
cpu: Move synchronize_from_tb() to tcg_ops
cpu: Move cpu_exec_* to tcg_ops
cpu: Move tlb_fill to tcg_ops
cpu: Move debug_excp_handler to tcg_ops
Philippe Mathieu-Daudé (2):
tcg/s390: Fix compare instruction from extended-immediate facility
exec/cpu-defs: Remove TCG backends dependency
Richard Henderson (24):
tcg/aarch64: Do not convert TCGArg to temps that are not temps
configure: Fix --enable-tcg-interpreter
tcg/tci: Make tci_tb_ptr thread-local
tcg/tci: Inline tci_write_reg32s into the only caller
tcg/tci: Inline tci_write_reg8 into its callers
tcg/tci: Inline tci_write_reg16 into the only caller
tcg/tci: Inline tci_write_reg32 into all callers
tcg/tci: Inline tci_write_reg64 into 64-bit callers
tcg/tci: Merge INDEX_op_ld8u_{i32,i64}
tcg/tci: Merge INDEX_op_ld8s_{i32,i64}
tcg/tci: Merge INDEX_op_ld16u_{i32,i64}
tcg/tci: Merge INDEX_op_ld16s_{i32,i64}
tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}
tcg/tci: Merge INDEX_op_st8_{i32,i64}
tcg/tci: Merge INDEX_op_st16_{i32,i64}
tcg/tci: Move stack bounds check to compile-time
tcg/tci: Merge INDEX_op_{st_i32,st32_i64}
tcg/tci: Use g_assert_not_reached
tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*
tcg/tci: Implement 64-bit division
tcg/tci: Remove TODO as unused
tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
tcg/tci: Fix TCG_REG_R4 misusage
tcg/tci: Remove TCG_CONST
Stefan Weil (2):
tcg/tci: Implement INDEX_op_ld16s_i32
tcg/tci: Implement INDEX_op_ld8s_i64
configure | 5 +-
accel/accel-softmmu.h | 15 +
accel/kvm/kvm-cpus.h | 2 -
.../{tcg-cpus-icount.h => tcg-accel-ops-icount.h} | 2 +
accel/tcg/tcg-accel-ops-mttcg.h| 19 +
accel/tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h}| 0
accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} | 6 +-
include/exec/cpu-all.h | 11 +-
include/exec/cpu-defs.h| 3 -
include/exec/exec-all.h| 2 +-
include/hw/boards.h| 2 +-
include/hw/core/accel-cpu.h| 38 ++
include/hw/core/cpu.h | 86 +---
include/hw/core/tcg-cpu-ops.h | 97 +
include/{sysemu => qemu}/accel.h | 16 +-
include/sysemu/accel-ops.h | 45 ++
include/sysemu/cpus.h | 26 +-
include/sysemu/hvf.h | 2 +-
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 2 +-
target/arm/internals.h | 6 +
target/i386/hax/{hax-cpus.h => hax-accel-ops.h}| 2 -
target/i386/hax/hax-windows.h | 2 +-
target/i386/hvf/{hvf-cpus.h => hvf-accel-ops.h}| 2 -
target/i386/hvf/hvf-i386.h | 2 +-
target/i386/whpx/{whpx-cpus.h => whpx-accel-ops.h} | 2 -
tcg/tci/tcg-target-con-set.h | 6 +-
tcg/tci/tcg-target.h | 37 +-
accel/accel-common.c | 105 +
accel/{accel.c => accel-softmmu.c} | 61 ++-
accel/accel-user.c
Re: [PULL v3 00/27] Block patches
On Fri, 5 Feb 2021 at 16:45, Stefan Hajnoczi wrote:
>
> The following changes since commit e2c5093c993ef646e4e28f7aa78429853bcc06ac:
>
> iotests: 30: drop from auto group (and effectively from make check)
> (2021-02-05 15:16:13 +)
>
> are available in the Git repository at:
>
> https://gitlab.com/stefanha/qemu.git tags/block-pull-request
>
> for you to fetch changes up to b07011f375bda3319cf72eee7cb18d310078387b:
>
> docs: fix Parallels Image "dirty bitmap" section (2021-02-05 16:36:36 +)
>
>
> Pull request
>
> v3:
> * Replace {0} array initialization with {} to make clang happy [Peter]
>
>
Fails 'make check' on s390x host:
socket_accept failed: Resource temporarily unavailable
**
ERROR:../../tests/qtest/libqtest.c:308:qtest_init_without_qmp_handshake:
assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)
../../tests/qtest/libqtest.c:181: kill_qemu() detected QEMU death from
signal 6 (Aborted) (core dumped)
socket_accept failed: Resource temporarily unavailable
**
ERROR:../../tests/qtest/libqtest.c:308:qtest_init_without_qmp_handshake:
assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)
../../tests/qtest/libqtest.c:181: kill_qemu() detected QEMU death from
signal 6 (Aborted) (core dumped)
ERROR qtest-s390x/pxe-test - Bail out!
ERROR:../../tests/qtest/libqtest.c:308:qtest_init_without_qmp_handshake:
assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)
ERROR qtest-s390x/test-netfilter - Bail out!
ERROR:../../tests/qtest/libqtest.c:308:qtest_init_without_qmp_handshake:
assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)
Makefile.mtest:3121: recipe for target 'run-test-388' failed
make: *** [run-test-388] Error 1
make: *** Waiting for unfinished jobs
Makefile.mtest:3113: recipe for target 'run-test-387' failed
thanks
-- PMM
Re: [Avocado-devel] acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?
Hi all, I will try to give my two cents: On Fri, Feb 05, 2021 at 03:31:40PM -0500, John Snow wrote: > On 2/5/21 11:43 AM, Philippe Mathieu-Daudé wrote: > > Cc'ing Avocado team & John (Python inferior exit delay?). > > > > On 1/28/21 11:10 AM, Thomas Huth wrote: > > > On 28/01/2021 10.45, Claudio Fontana wrote: > > > > > > > > is it just me, or is the CI sometimes failing with timeout? > > > > > > > > Fedora: > > > > https://gitlab.com/hw-claudio/qemu/-/jobs/986936506 > > > > > > I've sent a patch for that issue just yesterday: > > > > > > https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg06852.html > > > > > > > CentOS: > > > > https://gitlab.com/hw-claudio/qemu/-/jobs/980769080 > > > > > > Never seen that one before - if you hit it again, could you please save > > > the artifacts and have a look at the log file in there to see what's > > > exactly the problem? > > > > https://gitlab.com/philmd/qemu/-/jobs/1008007125 > > > > (28/36) > > tests/acceptance/replay_kernel.py:ReplayKernelNormal.test_ppc_mac99: > > ERROR: Test reported status but did not finish (90.09 s) > > > > Attached debug.log. > > > > ¯\_(ツ)_/¯ > > I don't know what "reported status but did not finish" means. > > The debug log looks like it passes, too, so... I don't know that this has > much do with code I maintain yet. I'm sure the Avocado team will find me if > I am wrong :) Afaict, this happen when the process exceeds the deadline to finish. Sometimes the test is finished but the "post test" stage is stucked because of some reason. Maybe setting 'runner.timeout.process_alive' to a higher number could help here: $ avocado config reference | grep process_alive -A 6 runner.timeout.process_alive The amount of time to wait after a test has reported status but the test process has not finished * Default: 60 * Type: But I might be wrong. I know that Cleber was working with this, so probably he could help here too. -- Beraldo
Re: Help with Windows XP in qemu-system-i386
> On Feb 5, 2021, at 3:49 PM, Michael S. Tsirkin wrote: > > On Fri, Feb 05, 2021 at 03:25:00PM -0500, Programmingkid wrote: >> Hi, I'm noticing that my Windows XP Service Pack 3 VM is causing >> qemu-system-i386 to experience 100% host cpu usage even when the guest is at >> idle. I was wondering if you are seeing this issue as well on any version of >> Windows guest? Windows 2000 doesn't seem to have this problem so I'm >> wondering if this is a bug with QEMU or a problem with my VM. Any help would >> be appreciated. >> >> Thank you. > > Just tried an xp guest, stays below 10% for me. Suggest discussing this > on the mailing list. Thank you for the reply. Which service pack is your Windows XP VM using?
Re: acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?
On 2/5/21 11:43 AM, Philippe Mathieu-Daudé wrote: Cc'ing Avocado team & John (Python inferior exit delay?). On 1/28/21 11:10 AM, Thomas Huth wrote: On 28/01/2021 10.45, Claudio Fontana wrote: is it just me, or is the CI sometimes failing with timeout? Fedora: https://gitlab.com/hw-claudio/qemu/-/jobs/986936506 I've sent a patch for that issue just yesterday: https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg06852.html CentOS: https://gitlab.com/hw-claudio/qemu/-/jobs/980769080 Never seen that one before - if you hit it again, could you please save the artifacts and have a look at the log file in there to see what's exactly the problem? https://gitlab.com/philmd/qemu/-/jobs/1008007125 (28/36) tests/acceptance/replay_kernel.py:ReplayKernelNormal.test_ppc_mac99: ERROR: Test reported status but did not finish (90.09 s) Attached debug.log. ¯\_(ツ)_/¯ I don't know what "reported status but did not finish" means. The debug log looks like it passes, too, so... I don't know that this has much do with code I maintain yet. I'm sure the Avocado team will find me if I am wrong :) --js
Re: [PATCH v2] qemu-nbd: Use SOMAXCONN for socket listen() backlog
On Fri, Feb 05, 2021 at 12:57:05PM -0600, Eric Blake wrote:
> Our default of a backlog of 1 connection is rather puny, particularly
> for scenarios where we expect multiple listeners to connect (such as
> qemu-nbd -e X). This is especially important for Unix sockets, as a
> definite benefit to clients: at least on Linux, a client trying to
> connect to a Unix socket with a backlog gets an EAGAIN failure with no
> way to poll() for when the backlog is no longer present short of
> sleeping an arbitrary amount of time before retrying.
>
> See https://bugzilla.redhat.com/1925045 for a demonstration of where
> our low backlog prevents libnbd from connecting as many parallel
> clients as it wants.
>
> Reported-by: Richard W.M. Jones
> Signed-off-by: Eric Blake
> ---
>
> v2: target the correct API used by qemu-nbd, rather than an unrelated
> legacy wrapper [Dan]
>
> qemu-nbd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/qemu-nbd.c b/qemu-nbd.c
> index 608c63e82a25..cd20ee73be19 100644
> --- a/qemu-nbd.c
> +++ b/qemu-nbd.c
> @@ -965,7 +965,8 @@ int main(int argc, char **argv)
> server = qio_net_listener_new();
> if (socket_activation == 0) {
> saddr = nbd_build_socket_address(sockpath, bindto, port);
> -if (qio_net_listener_open_sync(server, saddr, 1, _err) < 0) {
> +if (qio_net_listener_open_sync(server, saddr, SOMAXCONN,
> + _err) < 0) {
> object_unref(OBJECT(server));
> error_report_err(local_err);
> exit(EXIT_FAILURE);
This one works:
Tested-by: Richard W.M. Jones
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-top is 'top' for virtual machines. Tiny program with many
powerful monitoring features, net stats, disk stats, logging, etc.
http://people.redhat.com/~rjones/virt-top
Re: [PATCH v16 23/23] accel-cpu: make cpu_realizefn return a bool
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> overall, all devices' realize functions take an Error **errp, but return void.
>
> hw/core/qdev.c code, which realizes devices, therefore does:
>
> local_err = NULL;
> dc->realize(dev, _err);
> if (local_err != NULL) {
> goto fail;
> }
>
> However, we can improve at least accel_cpu to return a meaningful bool value.
>
> Signed-off-by: Claudio Fontana
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Alex Bennée
> ---
> include/hw/core/accel-cpu.h | 2 +-
> include/qemu/accel.h| 2 +-
> target/i386/host-cpu.h | 2 +-
> accel/accel-common.c| 6 +++---
> cpu.c | 5 +++--
> target/i386/host-cpu.c | 5 +++--
> target/i386/kvm/kvm-cpu.c | 4 ++--
> target/i386/tcg/tcg-cpu.c | 6 --
> 8 files changed, 18 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson
r~
Re: [PATCH v16 00/23] i386 cleanup PART 2
On 2/4/21 6:39 AM, Claudio Fontana wrote: > Claudio Fontana (18): > target/riscv: remove CONFIG_TCG, as it is always TCG > accel/tcg: split TCG-only code from cpu_exec_realizefn > target/arm: do not use cc->do_interrupt for KVM directly > cpu: move cc->do_interrupt to tcg_ops > cpu: move cc->transaction_failed to tcg_ops > cpu: move do_unaligned_access to tcg_ops > physmem: make watchpoint checking code TCG-only > cpu: move adjust_watchpoint_address to tcg_ops > cpu: move debug_check_watchpoint to tcg_ops > cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass > accel: extend AccelState and AccelClass to user-mode > accel: replace struct CpusAccel with AccelOpsClass > accel: introduce AccelCPUClass extending CPUClass > i386: split cpu accelerators from cpu.c, using AccelCPUClass > cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn > accel: introduce new accessor functions > target/i386: fix host_cpu_adjust_phys_bits error handling > accel-cpu: make cpu_realizefn return a bool > > Eduardo Habkost (5): > cpu: Introduce TCGCpuOperations struct > cpu: Move synchronize_from_tb() to tcg_ops > cpu: Move cpu_exec_* to tcg_ops > cpu: Move tlb_fill to tcg_ops > cpu: Move debug_excp_handler to tcg_ops Queuing patches 1-18 to tcg-next. r~
Re: [PATCH v16 22/23] target/i386: fix host_cpu_adjust_phys_bits error handling
On 2/4/21 6:39 AM, Claudio Fontana wrote: > move the check for phys_bits outside of host_cpu_adjust_phys_bits, > because otherwise it is impossible to return an error condition > explicitly. > > Signed-off-by: Claudio Fontana > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Alex Bennée > --- > target/i386/host-cpu.c | 22 -- > 1 file changed, 12 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 2/4] hw/block/fdc: Remove the check_media_rate property
On 2/5/21 1:37 AM, Thomas Huth wrote:
On 05/02/2021 01.40, John Snow wrote:
On 2/3/21 12:18 PM, Thomas Huth wrote:
This was only required for the pc-1.0 and earlier machine types.
Now that these have been removed, we can also drop the corresponding
code from the FDC device.
Signed-off-by: Thomas Huth
---
hw/block/fdc.c | 17 ++---
tests/qemu-iotests/172.out | 35 ---
2 files changed, 2 insertions(+), 50 deletions(-)
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
index 292ea87805..198940e737 100644
--- a/hw/block/fdc.c
+++ b/hw/block/fdc.c
@@ -874,7 +874,6 @@ struct FDCtrl {
FloppyDriveType type;
} qdev_for_drives[MAX_FD];
int reset_sensei;
- uint32_t check_media_rate;
I am a bit of a dunce when it comes to the compatibility properties...
does this mess with the migration format?
I guess it doesn't, since it's not in the VMSTATE declaration.
H, alright.
I think that should be fine, yes.
FloppyDriveType fallback; /* type=auto failure fallback */
/* Timers state */
uint8_t timer0;
@@ -1021,18 +1020,10 @@ static const VMStateDescription
vmstate_fdrive_media_changed = {
}
};
-static bool fdrive_media_rate_needed(void *opaque)
-{
- FDrive *drive = opaque;
-
- return drive->fdctrl->check_media_rate;
-}
-
static const VMStateDescription vmstate_fdrive_media_rate = {
.name = "fdrive/media_rate",
.version_id = 1,
.minimum_version_id = 1,
- .needed = fdrive_media_rate_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT8(media_rate, FDrive),
VMSTATE_END_OF_LIST()
@@ -1689,8 +1680,7 @@ static void fdctrl_start_transfer(FDCtrl
*fdctrl, int direction)
/* Check the data rate. If the programmed data rate does not match
* the currently inserted medium, the operation has to fail. */
- if (fdctrl->check_media_rate &&
- (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
+ if ((fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
fdctrl->dsr & FD_DSR_DRATEMASK,
cur_drv->media_rate);
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
@@ -2489,8 +2479,7 @@ static void fdctrl_result_timer(void *opaque)
cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
}
/* READ_ID can't automatically succeed! */
- if (fdctrl->check_media_rate &&
- (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
+ if ((fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
fdctrl->dsr & FD_DSR_DRATEMASK,
cur_drv->media_rate);
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
@@ -2895,8 +2884,6 @@ static Property isa_fdc_properties[] = {
DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
DEFINE_PROP_DRIVE("driveA", FDCtrlISABus,
state.qdev_for_drives[0].blk),
DEFINE_PROP_DRIVE("driveB", FDCtrlISABus,
state.qdev_for_drives[1].blk),
- DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus,
state.check_media_rate,
- 0, true),
Could you theoretically set this via QOM commands in QMP, and claim
that this is a break in behavior?
Though, it's ENTIRELY undocumented, so ... it's probably fine, I
think. Probably. (Please soothe my troubled mind.)
A user actually could mess with this property even on the command line,
e.g. by using:
qemu-system-x86_64 -global isa-fdc.check_media_rate=false
... but, as you said, it's completely undocumented, the property is
really just there for the internal use of machine type compatibility.
We've done such clean-ups in the past already, see e.g.
c6026998eef382d7ad76 or 2a4dbaf1c0db2453ab78f, so I think this should be
fine. But if you disagree, I could replace this by a patch that adds
this property to the list of deprecated features instead, so we could at
least remove it after it has been deprecated for two releases?
I don't think it's necessary, personally -- just wanted to make sure I
knew the exact stakes here.
Reviewed-by: John Snow
Acked-by: John Snow
Re: [PATCH v16 21/23] accel: introduce new accessor functions
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> @@ -6725,10 +6722,8 @@ static void x86_cpu_initfn(Object *obj)
> x86_cpu_load_model(cpu, xcc->model);
> }
>
> -/* if required, do the accelerator-specific cpu initialization */
> -if (cc->accel_cpu) {
> -cc->accel_cpu->cpu_instance_init(CPU(obj));
> -}
> +/* if required, do accelerator-specific cpu initializations */
> +accel_cpu_instance_init(CPU(obj));
> }
Why is this only done for x86?
r~
Re: [PATCH v16 19/23] i386: split cpu accelerators from cpu.c, using AccelCPUClass
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> +static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data)
> +{
> +AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
> +
> +acc->cpu_realizefn = host_cpu_realizefn;
> +acc->cpu_instance_init = hvf_cpu_instance_init;
> +};
Watch the stray ; after functions.
Make sure there's a blank line in between functions and file-scope structure
definitions.
> +static const TypeInfo hvf_cpu_accel_type_info = {
> +.name = ACCEL_CPU_NAME("hvf"),
> +
> +.parent = TYPE_ACCEL_CPU,
> +.class_init = hvf_cpu_accel_class_init,
> +.abstract = true,
> +};
> +static void hvf_cpu_accel_register_types(void)
> +{
> +type_register_static(_cpu_accel_type_info);
> +}
The rest looks ok, but I would like to see other i386 review.
r~
Re: [PATCH v2] qemu-nbd: Use SOMAXCONN for socket listen() backlog
On Fri, Feb 5, 2021 at 8:57 PM Eric Blake wrote:
>
> Our default of a backlog of 1 connection is rather puny, particularly
> for scenarios where we expect multiple listeners to connect (such as
> qemu-nbd -e X). This is especially important for Unix sockets, as a
> definite benefit to clients: at least on Linux, a client trying to
> connect to a Unix socket with a backlog gets an EAGAIN failure with no
> way to poll() for when the backlog is no longer present short of
> sleeping an arbitrary amount of time before retrying.
>
> See https://bugzilla.redhat.com/1925045 for a demonstration of where
> our low backlog prevents libnbd from connecting as many parallel
> clients as it wants.
>
> Reported-by: Richard W.M. Jones
> Signed-off-by: Eric Blake
> ---
>
> v2: target the correct API used by qemu-nbd, rather than an unrelated
> legacy wrapper [Dan]
>
> qemu-nbd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/qemu-nbd.c b/qemu-nbd.c
> index 608c63e82a25..cd20ee73be19 100644
> --- a/qemu-nbd.c
> +++ b/qemu-nbd.c
> @@ -965,7 +965,8 @@ int main(int argc, char **argv)
> server = qio_net_listener_new();
> if (socket_activation == 0) {
> saddr = nbd_build_socket_address(sockpath, bindto, port);
> -if (qio_net_listener_open_sync(server, saddr, 1, _err) < 0) {
> +if (qio_net_listener_open_sync(server, saddr, SOMAXCONN,
Shouldn't we use value based on --shared=N?
Using maximum value makes sense for generic server expecting to handle many
connections from different clients. qemu-nbd is typically used by one
client, and we
need to make it possible to connect a known number of connections quickly.
> + _err) < 0) {
> object_unref(OBJECT(server));
> error_report_err(local_err);
> exit(EXIT_FAILURE);
> --
> 2.30.0
>
>
Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0
> On Feb 5, 2021, at 1:49 PM, Jonathan Cameron > wrote: > > On Fri, 5 Feb 2021 09:19:36 -0800 > Ben Widawsky wrote: > >> On 21-02-05 16:09:54, Jonathan Cameron wrote: >>> On Wed, 3 Feb 2021 23:53:53 -0500 >>> Chris Browy wrote: >>> Hi Jonathan, Thanks for the review comments and we'll put out a v2 patch series based on a genuine git send-email flow in a day or so and plan to include - functionally separate patches - new MSI-X support - few bugs found in CDAT table header + checksum generation - more fully respond to review comments (thanks again!) After the SSWG responds to your email on spec clarifications we'll work on adding user-defined CDAT entries. Thanks for raising the issues with SSWG! It would be good to collaborate on how best to specify external CDAT files. One idea is to provide -device command line property for filenames. Files could be ascii format specifying the CDAT struct instances with named fields and value pairs. Some checks could be adding when reading in the files. Users could specify the CDAT structure types in any order and have multiple instances. >>> >>> I'd keep away from ascii files for this. Whilst it is horrible in some ways >>> we should stick to command line ops. If we need a more structured format >>> then >>> similar to was proposed with hmat, via libvirt. >>> >>> Alternatively we could use compiled tables though we'd end up having to >>> parse >>> them to some degree. >>> >> >> Why parse? Initially (6 months ago), I was thinking CDAT could just be a >> blob. >> The thing I liked about that approach was that when real devices came along, >> we >> could dump their CDATs and use it directly. > > See the CXL SSWG thread. Need to break it up into entries. So trivial bit of > walking to find the starts of the different entries (not really parsing I > guess) Right we do need to extract each CDAT Structure[n] to generate the response. Is blob The same as using IASL/AML Data Table Compiler in a manner consistent with how the non-IASL/AML tables (like SRAT) are compiled? 1.1 Data Table Compiler The Data Table compiler is used to compile the “non-ASL/AML” ACPI tables such as the FADT, MADT, SRAT, etc. These tables are not compiled to AML byte code, but are compiled to simple binary data, usually with the standard ACPI table header (signature, length, checksum, etc.) Seems that they may have intended given the CDAT table header is consistent with ACPI table header. Jonathan will you clarify this topic in the ECN? > >> Just like you we feel what's most important is to have DOE supported so that UEFI and Linux kernel and drivers can progress. We're also contributing to writing compliance tests for the CXL Compliance Software Development WG. >>> >>> Great. >> >> Is anyone doing the kernel enabling for it? > > Planning to look at this but plenty of other things on my todo list if someone > else gets to it first. > > Generic DOE support should be straight forward (the infrastructure). > Parsing CDAT also straight forward. > Doing something with the results is hard unless we just provide an interface > for > userspace to query them for a given device - or dump the table > (I think we do want to be able to that). > > What I'm really not sure on is how to handle NUMA domains that are created > late > in the kernel boot sequence. The ACPI flow is set up with the assumption > that we can get them from SRAT very early in boot. Need to figure out how to > work around that. (e.g. preallocate a bunch of spare nodes for example though > that's > ugly). Note IIRC the kernel doesn't do runtime update of any of the ACPI > performance parameters yet (_SLI, _HMA) so there probably isn't any > infrastructure > that we can reuse. > > There is also the firmware based enumeration and description option (OS not > necessarily > aware of CXL) in which this is all up to EDK2 and the kernel gets it all > presented > as standard tables. Do we know who’s on this as part of the EDK2 development? It would be great if they could address the SRAT/HMAT generation from reading CDAT. EDK2 does address CXL 1.1 now. > > As you can perhaps tell from my half done reviews, this week disappeared in > other things so bit of catch up for me to do next week. > > Thanks, > > Joanthan > > > > >> >>> Note your email did not post to lore.kernel.org/qemu-devel despite being CC’d. Maybe a --in-replies-to issue. I’ve restored that here in this email reply. >>> >>> Thanks Chris. The rejection was due to an unintended attachment. Please >>> ignore. >>> >>> Thanks, >>> >>> Jonathan >>> >>> >>> Best Regards, Chris On 2/3/21, 12:19 PM, "Jonathan Cameron" wrote: On Tue, 2 Feb 2021 15:43:28 -0500 Chris Browy
Re: [PATCH 00/24] hw/arm: New board model mps3-an524
On Fri, 5 Feb 2021 at 19:31, Philippe Mathieu-Daudé wrote: > > On Fri, Feb 5, 2021 at 8:21 PM Peter Maydell wrote: > > On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote: > > > On 2/5/21 5:59 PM, Peter Maydell wrote: > > > > (The selftest is part of the AN524 > > > > download so it's behind a EULA click-through and we can't put it > > > > into an acceptance test. We might be able to get something > > > > based on Zephyr or Arm TFM.) > > > > > > Wondering about that... If anyone can go/click/accepts the EULA and > > > download artifacts, then I'd like these tests to be committed to the > > > repository, with a comment containing the download link, and the test > > > can use the skipUntil(BLOB_PATH && BLOB_HASH) syntax to assert the > > > binary I downloaded is the same you used for your test. > > > > I would rather not get into that. The selftest doesn't actually > > exercise as much of the emulation as you might think anyway. > > This was clear from the previous paragraph, I was asking about the possibility > to have developers/maintainers individually accept EULA to download artifacts > for integration testing. Yes, and that is the thing I would rather we didn't get into. We should just have suitably redistributable acceptance tests where we can. -- PMM
Re: [PATCH 00/24] hw/arm: New board model mps3-an524
On Fri, Feb 5, 2021 at 8:21 PM Peter Maydell wrote: > On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote: > > On 2/5/21 5:59 PM, Peter Maydell wrote: > > > (The selftest is part of the AN524 > > > download so it's behind a EULA click-through and we can't put it > > > into an acceptance test. We might be able to get something > > > based on Zephyr or Arm TFM.) > > > > Wondering about that... If anyone can go/click/accepts the EULA and > > download artifacts, then I'd like these tests to be committed to the > > repository, with a comment containing the download link, and the test > > can use the skipUntil(BLOB_PATH && BLOB_HASH) syntax to assert the > > binary I downloaded is the same you used for your test. > > I would rather not get into that. The selftest doesn't actually > exercise as much of the emulation as you might think anyway. This was clear from the previous paragraph, I was asking about the possibility to have developers/maintainers individually accept EULA to download artifacts for integration testing. > > -- PMM
Re: runaway avocado
On Mon, 26 Oct 2020 at 22:35, Peter Maydell wrote: > > So, I somehow ended up with this process still running on my > local machine after a (probably failed) 'make check-acceptance': > > petmay01 13710 99.7 3.7 2313448 1235780 pts/16 Sl 16:10 378:00 > ./qemu-system-aarch64 -display none -vga none -chardev > socket,id=mon,path=/var/tmp/tmp5szft2yi/qemu-13290-monitor.sock -mon > chardev=mon,mode=control -machine virt -chardev > socket,id=console,path=/var/tmp/tmp5szft2yi/qemu-13290-console.sock,server,nowait > -serial chardev:console -icount > shift=7,rr=record,rrfile=/var/tmp/avocado_iv8dehpo/avocado_job_w9efukj5/32-tests_acceptance_reverse_debugging.py_ReverseDebugging_AArch64.test_aarch64_virt/replay.bin,rrsnapshot=init > -net none -drive > file=/var/tmp/avocado_iv8dehpo/avocado_job_w9efukj5/32-tests_acceptance_reverse_debugging.py_ReverseDebugging_AArch64.test_aarch64_virt/disk.qcow2,if=none > -kernel > /home/petmay01/avocado/data/cache/by_location/a00ac4ae676ef0322126abd2f7d38f50cc9cbc95/vmlinuz > -cpu cortex-a53 > > and it was continuing to log to a deleted file > /var/tmp/avocado_iv8dehpo/avocado_job_w9efukj5/32-tests_acceptance_reverse_debugging.py_ReverseDebugging_AArch64.test_aarch64_virt/replay.bin > > which was steadily eating my disk space and got up to nearly 100GB > in used disk (invisible to du, of course, since it was an unlinked > file) before I finally figured out what was going on and killed it > about six hours later... Just got hit by this test framework bug again :-( Same thing, runaway avacado record-and-replay test ate all my disk space. -- PMM
Re: [PATCH 00/24] hw/arm: New board model mps3-an524
On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote: > On 2/5/21 5:59 PM, Peter Maydell wrote: > > (The selftest is part of the AN524 > > download so it's behind a EULA click-through and we can't put it > > into an acceptance test. We might be able to get something > > based on Zephyr or Arm TFM.) > > Wondering about that... If anyone can go/click/accepts the EULA and > download artifacts, then I'd like these tests to be committed to the > repository, with a comment containing the download link, and the test > can use the skipUntil(BLOB_PATH && BLOB_HASH) syntax to assert the > binary I downloaded is the same you used for your test. I would rather not get into that. The selftest doesn't actually exercise as much of the emulation as you might think anyway. -- PMM
Re: [PATCH] arm: Update infocenter.arm.com URLs
On Fri, 5 Feb 2021 at 18:07, Philippe Mathieu-Daudé wrote: > > On 2/5/21 6:14 PM, Peter Maydell wrote: > > -/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller: > > +/* > > + * This is a model of the Arm PrimeCell PL080/PL081 DMA controller: > > * The PL080 TRM is: > > - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf > > + * https://developer.arm.com/documentation/ddi0196/latest > > Oh, /latest :) Yeah. developer will do link-to-specific-revision-of-document if you want them, but I figured /latest was probably the more generally useful URL. Not that the PL080 TRM is likely to ever get another revision :-) -- PMM
Re: [PATCH] sockets: Use SOMAXCONN for Unix socket listen()
On 2/5/21 3:55 AM, Daniel P. Berrangé wrote: >> +++ b/util/qemu-sockets.c >> @@ -1059,7 +1059,7 @@ int unix_listen(const char *str, Error **errp) >> >> saddr = g_new0(UnixSocketAddress, 1); >> saddr->path = g_strdup(str); >> -sock = unix_listen_saddr(saddr, 1, errp); >> +sock = unix_listen_saddr(saddr, SOMAXCONN, errp); >> qapi_free_UnixSocketAddress(saddr); >> return sock; >> } > > This method is a legacy back compat function, only used by the QEMU > guest agent, so this can't explain the NBD problems, which use the > QIONetListener class. > > IOW, the problem is in the qemu-nbd.c / blockdev-nbd.c code I believe D'oh. Serves me right for trying to guess the spot using just a grep on listen() rather than running under gdb with a breakpoint to find the actual backtrace. v2 posted with a slightly changed subject line, and this time tested to actually work. -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org
[PATCH v2] qemu-nbd: Use SOMAXCONN for socket listen() backlog
Our default of a backlog of 1 connection is rather puny, particularly
for scenarios where we expect multiple listeners to connect (such as
qemu-nbd -e X). This is especially important for Unix sockets, as a
definite benefit to clients: at least on Linux, a client trying to
connect to a Unix socket with a backlog gets an EAGAIN failure with no
way to poll() for when the backlog is no longer present short of
sleeping an arbitrary amount of time before retrying.
See https://bugzilla.redhat.com/1925045 for a demonstration of where
our low backlog prevents libnbd from connecting as many parallel
clients as it wants.
Reported-by: Richard W.M. Jones
Signed-off-by: Eric Blake
---
v2: target the correct API used by qemu-nbd, rather than an unrelated
legacy wrapper [Dan]
qemu-nbd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/qemu-nbd.c b/qemu-nbd.c
index 608c63e82a25..cd20ee73be19 100644
--- a/qemu-nbd.c
+++ b/qemu-nbd.c
@@ -965,7 +965,8 @@ int main(int argc, char **argv)
server = qio_net_listener_new();
if (socket_activation == 0) {
saddr = nbd_build_socket_address(sockpath, bindto, port);
-if (qio_net_listener_open_sync(server, saddr, 1, _err) < 0) {
+if (qio_net_listener_open_sync(server, saddr, SOMAXCONN,
+ _err) < 0) {
object_unref(OBJECT(server));
error_report_err(local_err);
exit(EXIT_FAILURE);
--
2.30.0
[QEMU TCG] Qeustion about the PCID Feature in TCG
Hi,
I am running QEMU in TCG mode (my server doesn't have kvm support), and I
am getting the memory traces in a x86 guest machine of all memory accesses,
including the PCID (process-context identifier, and I need that for my
current research), on a linux host. I have seen the TCG PCID feature flag
is commented out in target/i386/cpu.c, and if I directly emulate a CPU
which has PCID flag I got the warning:
warning: TCG doesn't support requested feature: CPUID.01H:ECX.pcid [bit 17]
so I uncommented the CPUID_EXT_PCID in TCG_EXT_FEATURES, and
the CPUID_7_0_EBX_INVPCID in TCG_7_0_EBX_FEATURES, in target/i386/cpu.c. I
have seen the PCID in the cr3 register in cpu get set, my question is that
I am not sure if there will be any issues with this flag. Why is it
commented out by default?
Just in case, I will put my commands here. Here are my configurations for
compiling:
*./configure --prefix=/tigress/kaifengx/sysroot/
--target-list=x86_64-softmmu,x86_64-linux-user --disable-kvm --disable-vnc
--enable-gtk --enable-plugins*
And my command for running the QEMU:
*qemu-system-x86_64 \*
*-cpu qemu64,+pcid\-m 4G \-icount shift=0 \-drive
if=virtio,file=${DISK},cache=none \-device pqii \-trace
events=`pwd`/events \-D ${LOG_FILE} \-net
user,hostfwd=tcp::10022-:22 \-net nic \-display none \
-nographic \-plugin QEMU_PATH/tests/plugin/libtlb.so,arg=inline,arg=io*
Best,
Kaifeng
Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0
On Fri, 5 Feb 2021 09:19:36 -0800 Ben Widawsky wrote: > On 21-02-05 16:09:54, Jonathan Cameron wrote: > > On Wed, 3 Feb 2021 23:53:53 -0500 > > Chris Browy wrote: > > > > > Hi Jonathan, > > > > > > Thanks for the review comments and we'll put out a v2 patch series > > > based on a genuine git send-email flow in a day or so and plan to include > > > - functionally separate patches > > > - new MSI-X support > > > - few bugs found in CDAT table header + checksum generation > > > - more fully respond to review comments (thanks again!) > > > > > > After the SSWG responds to your email on spec clarifications we'll work on > > > adding user-defined CDAT entries. Thanks for raising the issues with > > > SSWG! > > > > > > It would be good to collaborate on how best to specify external CDAT > > > files. > > > One idea is to provide -device command line property for filenames. Files > > > could be ascii format specifying the CDAT struct instances with named > > > fields and > > > value pairs. Some checks could be adding when reading in the files. > > > Users could > > > specify the CDAT structure types in any order and have multiple > > > instances. > > > > I'd keep away from ascii files for this. Whilst it is horrible in some ways > > we should stick to command line ops. If we need a more structured format > > then > > similar to was proposed with hmat, via libvirt. > > > > Alternatively we could use compiled tables though we'd end up having to > > parse > > them to some degree. > > > > Why parse? Initially (6 months ago), I was thinking CDAT could just be a blob. > The thing I liked about that approach was that when real devices came along, > we > could dump their CDATs and use it directly. See the CXL SSWG thread. Need to break it up into entries. So trivial bit of walking to find the starts of the different entries (not really parsing I guess) > > > > > > > Just like you we feel what's most important is to have DOE supported so > > > that > > > UEFI and Linux kernel and drivers can progress. We're also contributing > > > to > > > writing compliance tests for the CXL Compliance Software Development WG. > > > > Great. > > Is anyone doing the kernel enabling for it? Planning to look at this but plenty of other things on my todo list if someone else gets to it first. Generic DOE support should be straight forward (the infrastructure). Parsing CDAT also straight forward. Doing something with the results is hard unless we just provide an interface for userspace to query them for a given device - or dump the table (I think we do want to be able to that). What I'm really not sure on is how to handle NUMA domains that are created late in the kernel boot sequence. The ACPI flow is set up with the assumption that we can get them from SRAT very early in boot. Need to figure out how to work around that. (e.g. preallocate a bunch of spare nodes for example though that's ugly). Note IIRC the kernel doesn't do runtime update of any of the ACPI performance parameters yet (_SLI, _HMA) so there probably isn't any infrastructure that we can reuse. There is also the firmware based enumeration and description option (OS not necessarily aware of CXL) in which this is all up to EDK2 and the kernel gets it all presented as standard tables. As you can perhaps tell from my half done reviews, this week disappeared in other things so bit of catch up for me to do next week. Thanks, Joanthan > > > > > > > > > Note your email did not post to lore.kernel.org/qemu-devel despite being > > > CC’d. > > > Maybe a --in-replies-to issue. I’ve restored that here in this email > > > reply. > > > > Thanks Chris. The rejection was due to an unintended attachment. Please > > ignore. > > > > Thanks, > > > > Jonathan > > > > > > > > > > > > Best Regards, > > > Chris > > > > > > > > > On 2/3/21, 12:19 PM, "Jonathan Cameron" > > > wrote: > > > > > > On Tue, 2 Feb 2021 15:43:28 -0500 > > > Chris Browy wrote: > > > > > > Hi Chris, > > > > > > Whilst I appreciate that this is very much an RFC and so not in the > > > form you would eventually aim to present it in, please look for > > > a v2 to break this into a series of functionally separate patches. > > > Probably. > > > > > > 1. Introduce DOE support with no users - probably including the > > >discovery protocol > > > 2. CMA support > > > 3. CDAT support for CXL > > > 4. Compliance part. > > > > > > It's also well worth jumping through the hoops needed to get a > > > git send-email workflow up and running as you seem to have had some > > > trouble with getting the thread to send in one go etc. > > > > > > Clearly we now have two possible implementations for this > > > functionality. > > > Personally I don't care which one we take forwards - if nothing else > > > the exercise has highlighted some disagreements in spec interpretation > > >
Re: [PATCH v2] hw/scsi/scsi-disk: Fix out of bounds access in mode_sense_page()
On 04/02/21 23:50, Philippe Mathieu-Daudé wrote:
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index ed52fcd49ff..93aec483e88 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -1089,7 +1089,7 @@ static int scsi_emulate_mechanism_status(SCSIDiskState
*s, uint8_t *outbuf)
static int mode_sense_page(SCSIDiskState *s, int page, uint8_t **p_outbuf,
int page_control)
{
-static const int mode_sense_valid[0x3f] = {
+static const int mode_sense_valid[MODE_PAGE_ALLS + 1] = {
[MODE_PAGE_HD_GEOMETRY]= (1 << TYPE_DISK),
[MODE_PAGE_FLEXIBLE_DISK_GEOMETRY] = (1 << TYPE_DISK),
[MODE_PAGE_CACHING]= (1 << TYPE_DISK) | (1 <<
TYPE_ROM),
The bug is really that mode select with page 0x3f should fail, but it's
okay too. Can you also write a testcase along the lines of
test_unaligned_write_same?
Paolo
Re: [PATCH 2/9] tests/qtest: Restrict xlnx-can-test to TCG builds
On 2/5/21 5:57 PM, Peter Maydell wrote:
> On Fri, 5 Feb 2021 at 14:43, Philippe Mathieu-Daudé wrote:
>>
>> The Xilinx CAN controller test is uses the ZCU102 board which is
>> based on a ZynqMP SoC. In the default configuration - used by this
>> test - this SoC creates 2 Cortex R5F cores. Such cores are not
>> v8A archicture, thus can not be run under KVM. Therefore restrict
>> this test to TCG.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> Cc: Alistair Francis
>> Cc: "Edgar E. Iglesias"
>> Cc: Vikram Garhwal
>> ---
>> tests/qtest/meson.build | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
>> index c83bc211b6a..d8ebd5bf98e 100644
>> --- a/tests/qtest/meson.build
>> +++ b/tests/qtest/meson.build
>> @@ -159,10 +159,10 @@
>>(cpu != 'arm' ? ['bios-tables-test'] : []) +
>> \
>>(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?
>> ['tpm-tis-device-test'] : []) +\
>>(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?
>> ['tpm-tis-device-swtpm-test'] : []) + \
>> + (config_all.has_key('CONFIG_TCG') ? ['xlnx-can-test'] : []) + \
>>['arm-cpu-features',
>> 'numa-test',
>> 'boot-serial-test',
>> - 'xlnx-can-test',
>> 'migration-test']
>
> The implementation in hw/net/can/meson.build is conditioned on
> CONFIG_XLNX_ZYNQMP -- does it work to use that here too?
Yes. Thanks, clever idea :)
Re: [PATCH 00/24] hw/arm: New board model mps3-an524
Patchew URL:
https://patchew.org/QEMU/20210205170019.25319-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210205170019.25319-1-peter.mayd...@linaro.org
Subject: [PATCH 00/24] hw/arm: New board model mps3-an524
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20210205091857.845389-1-th...@redhat.com ->
patchew/20210205091857.845389-1-th...@redhat.com
* [new tag] patchew/20210205170019.25319-1-peter.mayd...@linaro.org ->
patchew/20210205170019.25319-1-peter.mayd...@linaro.org
Switched to a new branch 'test'
b6d08c9 hw/arm/mps2: Update old infocenter.arm.com URLs
90c7c16 docs/system/arm/mps2.rst: Document the new mps3-an524 board
5f3bfb9 hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
2dcefaf hw/arm/mps2-tz: Stub out USB controller for mps3-an524
73d10e6 hw/arm/mps2-tz: Add new mps3-an524 board
d7d9e95 hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
9b7abe4 hw/arm/mps2-tz: Support ROMs as well as RAMs
7c21327 hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
95cda0e hw/arm/mps2-tz: Make RAM arrangement board-specific
6b98680 hw/arm/mps2-tz: Allow boards to have different PPCInfo data
59fe34c hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
511cc99 hw/arm/mps2-tz: Move device IRQ info to data structures
c158168 hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device
interrupts
71a2a99 hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
cd14323 hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
d1e1616 hw/arm/mps2-tz: Make number of IRQs board-specific
ab0223a hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board
type
60e6b6f hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
2f73e0e hw/misc/mps2-fpgaio: Support SWITCH register
f6b999f hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
815ebc8 hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
cb75560 hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and
mps2-an511
adb2102 hw/misc/mps2-scc: Support configurable number of OSCCLK values
5ca5a46 hw/arm/mps2-tz: Make SYSCLK frequency board-specific
=== OUTPUT BEGIN ===
1/24 Checking commit 5ca5a46bfa16 (hw/arm/mps2-tz: Make SYSCLK frequency
board-specific)
2/24 Checking commit adb210220d27 (hw/misc/mps2-scc: Support configurable
number of OSCCLK values)
3/24 Checking commit cb75560589fd (hw/arm/mps2-tz: Correct the OSCCLK settings
for mps2-an505 and mps2-an511)
4/24 Checking commit 815ebc852713 (hw/arm/mps2-tz: Make the OSCCLK settings be
configurable per-board)
5/24 Checking commit f6b999f1b230 (hw/misc/mps2-fpgaio: Make number of LEDs
configurable by board)
6/24 Checking commit 2f73e0e32bbe (hw/misc/mps2-fpgaio: Support SWITCH register)
7/24 Checking commit 60e6b6f41c7e (hw/arm/mps2-tz: Make FPGAIO switch and LED
config per-board)
8/24 Checking commit ab0223afa265 (hw/arm/mps2-tz: Condition IRQ splitting on
number of CPUs, not board type)
9/24 Checking commit d1e1616e7bff (hw/arm/mps2-tz: Make number of IRQs
board-specific)
10/24 Checking commit cd143239e739 (hw/misc/mps2-scc: Implement CFG_REG5 and
CFG_REG6 for MPS3 AN524)
11/24 Checking commit 71a2a99734cd (hw/arm/mps2-tz: Correct wrong interrupt
numbers for DMA and SPI)
12/24 Checking commit c158168a5a67 (hw/arm/mps2-tz: Allow PPCPortInfo
structures to specify device interrupts)
13/24 Checking commit 511cc99a17de (hw/arm/mps2-tz: Move device IRQ info to
data structures)
WARNING: line over 80 characters
#115: FILE: hw/arm/mps2-tz.c:557:
+{ "uart0", make_uart, >uart[0], 0x4020, 0x1000, { 32,
33, 42 } },
WARNING: line over 80 characters
#116: FILE: hw/arm/mps2-tz.c:558:
+{ "uart1", make_uart, >uart[1], 0x40201000, 0x1000, { 34,
35, 43 } },
WARNING: line over 80 characters
#117: FILE: hw/arm/mps2-tz.c:559:
+{ "uart2", make_uart, >uart[2], 0x40202000, 0x1000, { 36,
37, 44 } },
WARNING: line over 80 characters
#118: FILE: hw/arm/mps2-tz.c:560:
+{ "uart3", make_uart, >uart[3], 0x40203000, 0x1000, { 38,
39, 45 } },
WARNING: line over 80 characters
#119: FILE: hw/arm/mps2-tz.c:561:
+{ "uart4", make_uart, >uart[4], 0x40204000, 0x1000, { 40,
41, 46 } },
WARNING: line over 80 characters
#137: FILE: hw/arm/mps2-tz.c:588:
+{ "dma0", make_dma, >dma[0], 0x4011, 0x1000, { 58,
56, 57 } },
WARNING: line over 80 characters
#138: FILE: hw/arm/mps2-tz.c:589:
+{ "dma1", make_dma, >dma[1], 0x40111000, 0x1000, { 61,
59, 60 } },
Re: [PATCH v2 5/5] travis.yml: Move the -fsanitize=thread testing to the gitlab-CI
Thomas Huth writes: > Use clang-10, so we can also use the --enable-tsan configure > option instead of only passing the flag via --extra-cflags. > > Signed-off-by: Thomas Huth Reviewed-by: Alex Bennée -- Alex Bennée
[PATCH v2 5/8] seccomp: Replace the word 'blacklist'
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "blacklist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Daniel P. Berrangé
Acked-by: Eduardo Otubo
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/qemu-seccomp.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/softmmu/qemu-seccomp.c b/softmmu/qemu-seccomp.c
index 377ef6937ca..4c684bc9e71 100644
--- a/softmmu/qemu-seccomp.c
+++ b/softmmu/qemu-seccomp.c
@@ -45,8 +45,8 @@ const struct scmp_arg_cmp sched_setscheduler_arg[] = {
{ .arg = 1, .op = SCMP_CMP_NE, .datum_a = SCHED_IDLE }
};
-static const struct QemuSeccompSyscall blacklist[] = {
-/* default set of syscalls to blacklist */
+static const struct QemuSeccompSyscall denylist[] = {
+/* default set of syscalls to denylist */
{ SCMP_SYS(reboot), QEMU_SECCOMP_SET_DEFAULT },
{ SCMP_SYS(swapon), QEMU_SECCOMP_SET_DEFAULT },
{ SCMP_SYS(swapoff),QEMU_SECCOMP_SET_DEFAULT },
@@ -175,18 +175,18 @@ static int seccomp_start(uint32_t seccomp_opts, Error
**errp)
goto seccomp_return;
}
-for (i = 0; i < ARRAY_SIZE(blacklist); i++) {
+for (i = 0; i < ARRAY_SIZE(denylist); i++) {
uint32_t action;
-if (!(seccomp_opts & blacklist[i].set)) {
+if (!(seccomp_opts & denylist[i].set)) {
continue;
}
-action = qemu_seccomp_get_action(blacklist[i].set);
-rc = seccomp_rule_add_array(ctx, action, blacklist[i].num,
-blacklist[i].narg, blacklist[i].arg_cmp);
+action = qemu_seccomp_get_action(denylist[i].set);
+rc = seccomp_rule_add_array(ctx, action, denylist[i].num,
+denylist[i].narg, denylist[i].arg_cmp);
if (rc < 0) {
error_setg_errno(errp, -rc,
- "failed to add seccomp blacklist rules");
+ "failed to add seccomp denylist rules");
goto seccomp_return;
}
}
--
2.26.2
[PATCH v2 2/8] tools/virtiofsd: Replace the word 'whitelist'
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the words "whitelist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Daudé
---
tools/virtiofsd/passthrough_ll.c | 6 +++---
tools/virtiofsd/passthrough_seccomp.c | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/tools/virtiofsd/passthrough_ll.c b/tools/virtiofsd/passthrough_ll.c
index 147b59338a1..5f3afe85579 100644
--- a/tools/virtiofsd/passthrough_ll.c
+++ b/tools/virtiofsd/passthrough_ll.c
@@ -3204,7 +3204,7 @@ static void setup_mounts(const char *source)
}
/*
- * Only keep whitelisted capabilities that are needed for file system operation
+ * Only keep capabilities in allowlist that are needed for file system
operation
* The (possibly NULL) modcaps_in string passed in is free'd before exit.
*/
static void setup_capabilities(char *modcaps_in)
@@ -3214,8 +3214,8 @@ static void setup_capabilities(char *modcaps_in)
capng_restore_state();
/*
- * Whitelist file system-related capabilities that are needed for a file
- * server to act like root. Drop everything else like networking and
+ * Add to allowlist file system-related capabilities that are needed for a
+ * file server to act like root. Drop everything else like networking and
* sysadmin capabilities.
*
* Exclusions:
diff --git a/tools/virtiofsd/passthrough_seccomp.c
b/tools/virtiofsd/passthrough_seccomp.c
index ea852e2e33b..62441cfcdb9 100644
--- a/tools/virtiofsd/passthrough_seccomp.c
+++ b/tools/virtiofsd/passthrough_seccomp.c
@@ -21,7 +21,7 @@
#endif
#endif
-static const int syscall_whitelist[] = {
+static const int syscall_allowlist[] = {
/* TODO ireg sem*() syscalls */
SCMP_SYS(brk),
SCMP_SYS(capget), /* For CAP_FSETID */
@@ -117,12 +117,12 @@ static const int syscall_whitelist[] = {
};
/* Syscalls used when --syslog is enabled */
-static const int syscall_whitelist_syslog[] = {
+static const int syscall_allowlist_syslog[] = {
SCMP_SYS(send),
SCMP_SYS(sendto),
};
-static void add_whitelist(scmp_filter_ctx ctx, const int syscalls[], size_t
len)
+static void add_allowlist(scmp_filter_ctx ctx, const int syscalls[], size_t
len)
{
size_t i;
@@ -153,10 +153,10 @@ void setup_seccomp(bool enable_syslog)
exit(1);
}
-add_whitelist(ctx, syscall_whitelist, G_N_ELEMENTS(syscall_whitelist));
+add_allowlist(ctx, syscall_allowlist, G_N_ELEMENTS(syscall_allowlist));
if (enable_syslog) {
-add_whitelist(ctx, syscall_whitelist_syslog,
- G_N_ELEMENTS(syscall_whitelist_syslog));
+add_allowlist(ctx, syscall_allowlist_syslog,
+ G_N_ELEMENTS(syscall_allowlist_syslog));
}
/* libvhost-user calls this for post-copy migration, we don't need it */
--
2.26.2
[PATCH v2 6/8] qemu-options: Replace the word 'blacklist'
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "blacklist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Reword (danpb)
---
qemu-options.hx | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index c09c4646e28..5f86cd2fbbf 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -4274,12 +4274,12 @@ DEF("sandbox", HAS_ARG, QEMU_OPTION_sandbox, \
"use 'obsolete' to allow obsolete system calls that are
provided\n" \
"by the kernel, but typically no longer used by
modern\n" \
"C library implementations.\n" \
-"use 'elevateprivileges' to allow or deny QEMU process to
elevate\n" \
-"its privileges by blacklisting all set*uid|gid system
calls.\n" \
+"use 'elevateprivileges' to allow or deny the QEMU process
ability\n" \
+"to elevate privileges using set*uid|gid system
calls.\n" \
"The value 'children' will deny set*uid|gid system
calls for\n" \
"main QEMU process but will allow forks and execves to
run unprivileged\n" \
"use 'spawn' to avoid QEMU to spawn new threads or
processes by\n" \
-" blacklisting *fork and execve\n" \
+" blocking *fork and execve\n" \
"use 'resourcecontrol' to disable process affinity and
schedular priority\n",
QEMU_ARCH_ALL)
SRST
--
2.26.2
[PATCH v2 1/8] ui: Replace the word 'whitelist'
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the words "whitelist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Gerd Hoffmann
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Do not use acronyms (danpb)
---
ui/console.c | 2 +-
ui/vnc-auth-sasl.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/ui/console.c b/ui/console.c
index c5d11bc7017..5a8311ced20 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1708,7 +1708,7 @@ bool dpy_gfx_check_format(QemuConsole *con,
return false;
}
} else {
-/* default is to whitelist native 32 bpp only */
+/* default is to allow native 32 bpp only */
if (format != qemu_default_pixman_format(32, true)) {
return false;
}
diff --git a/ui/vnc-auth-sasl.c b/ui/vnc-auth-sasl.c
index f67111a3662..df7dc08e9fc 100644
--- a/ui/vnc-auth-sasl.c
+++ b/ui/vnc-auth-sasl.c
@@ -288,7 +288,7 @@ static int protocol_client_auth_sasl_step(VncState *vs,
uint8_t *data, size_t le
goto authreject;
}
-/* Check username whitelist ACL */
+/* Check the username access control list */
if (vnc_auth_sasl_check_access(vs) < 0) {
goto authreject;
}
@@ -409,7 +409,7 @@ static int protocol_client_auth_sasl_start(VncState *vs,
uint8_t *data, size_t l
goto authreject;
}
-/* Check username whitelist ACL */
+/* Check the username access control list */
if (vnc_auth_sasl_check_access(vs) < 0) {
goto authreject;
}
--
2.26.2
Re: [PATCH 01/24] hw/arm/mps2-tz: Make SYSCLK frequency board-specific
On 2/5/21 5:59 PM, Peter Maydell wrote:
> The AN524 has a different SYSCLK frequency from the AN505 and AN521;
> make the SYSCLK frequency a field in the MPS2TZMachineClass rather
> than a compile-time constant so we can support the AN524.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/mps2-tz.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
> index 90caa914934..82ce6262817 100644
> --- a/hw/arm/mps2-tz.c
> +++ b/hw/arm/mps2-tz.c
> @@ -76,6 +76,7 @@ struct MPS2TZMachineClass {
> MachineClass parent;
> MPS2TZFPGAType fpga_type;
> uint32_t scc_id;
> +uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
This is what I meant in my Stellaris read-only dc[] registers
comment here:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg776770.html
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 00/24] hw/arm: New board model mps3-an524
On 2/5/21 5:59 PM, Peter Maydell wrote: > This patchseries implements a new board model in the mps2/mps3 family, > based on Application Note AN524: > https://developer.arm.com/documentation/dai0524/latest/ > > Like the other MPS models, this board is an FPGA image; the AN524 > image is based on the SSE-200, like the mps2-an521, but it is > for the MPS3 board rather than the MPS2+. The major differences > are QSPI flash and USB (which we don't model), and support for > 2GB of RAM (which we do). Since the MPS3 is very similar to the > MPS2, I've implemented mps3-an524 as a subclass of TYPE_MPS2TZ_MACHINE, > sharing most of the code with mps2-an505 and mps2-an521. > > The motivation for this model is two-fold: > * Linaro's Zephyr team would like it, so they can test their >code targeting the MPS3 on QEMU > * It's a useful stepping-stone towards a future MPS family model >which uses the SSE-300 and Cortex-M55. All the "make various bits >of mps2-tz.c be driven by per-board data structures rather than >hardcoding them" changes will be needed for that future board model. >This way they can be code-reviewed now, rather than making the >future patchseries even bigger (it will be pretty large even so, >because of all the "implement SSE-300 model" patches). > > This model can run the parts of the AN524 selftest image that > would be expected to work, i.e. the ones that don't rely on things > QEMU doesn't implement. Yes selftest are annoying when emulation :) Lot of features important for real hardware but we can happily bypass when emulation. > (The selftest is part of the AN524 > download so it's behind a EULA click-through and we can't put it > into an acceptance test. We might be able to get something > based on Zephyr or Arm TFM.) Wondering about that... If anyone can go/click/accepts the EULA and download artifacts, then I'd like these tests to be committed to the repository, with a comment containing the download link, and the test can use the skipUntil(BLOB_PATH && BLOB_HASH) syntax to assert the binary I downloaded is the same you used for your test. Then I could run locally: $ PATH_TO_EULA_ACCEPTED_ARTIFACTS=~/Private/DL avocado run ... Would it be acceptable? What is missing or should be fixed? Thanks, Phil.
[PATCH v2 0/8] misc: Replace the words 'blacklist/whitelist'
Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the words "blacklist" and "whitelist" appropriately. Since v1: - dropped qemu-guest-agent patches - addressed review comments - added R-b tags Missing review: PATCH #6 "qemu-options: Replace the word 'blacklist'" Series expected to go via the qemu-trivial@ tree. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Philippe Mathieu-Daudé (8): ui: Replace the word 'whitelist' tools/virtiofsd: Replace the word 'whitelist' scripts/tracetool: Replace the word 'whitelist' scripts/device-crash-test: Replace the word 'whitelist' seccomp: Replace the word 'blacklist' qemu-options: Replace the word 'blacklist' tests/fp/fp-test: Replace the word 'blacklist' hw/vfio/pci-quirks: Replace the word 'blacklist' hw/vfio/pci.h | 2 +- hw/vfio/pci-quirks.c | 14 ++--- hw/vfio/pci.c | 4 ++-- softmmu/qemu-seccomp.c| 16 +++--- tests/fp/fp-test.c| 8 +++ tools/virtiofsd/passthrough_ll.c | 6 +++--- tools/virtiofsd/passthrough_seccomp.c | 12 +-- ui/console.c | 2 +- ui/vnc-auth-sasl.c| 4 ++-- hw/vfio/trace-events | 2 +- qemu-options.hx | 6 +++--- scripts/device-crash-test | 30 +-- scripts/tracetool/__init__.py | 2 +- 13 files changed, 54 insertions(+), 54 deletions(-) -- 2.26.2
Re: [PATCH] arm: Update infocenter.arm.com URLs
On 2/5/21 6:14 PM, Peter Maydell wrote: > Update infocenter.arm.com URLs for various pieces of Arm > documentation to the new developer.arm.com equivalents. (There is a > redirection in place from the old URLs, but we might as well update > our comments in case the redirect ever disappears in future.) > > This patch covers all the URLs which are not MPS2/SSE-200/IoTKit > related (those are dealt with in a different patch). > > Signed-off-by: Peter Maydell > --- > include/hw/dma/pl080.h | 7 --- > include/hw/misc/arm_integrator_debug.h | 2 +- > include/hw/ssi/pl022.h | 5 +++-- > hw/arm/aspeed_ast2600.c| 2 +- > hw/arm/musca.c | 4 ++-- > hw/misc/arm_integrator_debug.c | 2 +- > hw/timer/arm_timer.c | 7 --- > 7 files changed, 16 insertions(+), 13 deletions(-) > > diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h > index 1883f042701..3c9659e4381 100644 > --- a/include/hw/dma/pl080.h > +++ b/include/hw/dma/pl080.h > @@ -10,11 +10,12 @@ > * (at your option) any later version. > */ > > -/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller: > +/* > + * This is a model of the Arm PrimeCell PL080/PL081 DMA controller: > * The PL080 TRM is: > - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf > + * https://developer.arm.com/documentation/ddi0196/latest Oh, /latest :) Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé
Re: [PATCH v4 5/5] qapi: More complex uses of QAPI_LIST_APPEND
On 1/26/21 3:31 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> These cases require a bit more thought to review; in each case, the
>> code was appending to a list, but not with a FOOList **tail variable.
>>
>> Signed-off-by: Eric Blake
>> Reviewed-by: Vladimir Sementsov-Ogievskiy
>>
>> ---
>> fix qmp_guest_network_get_interfaces [Vladimir]
>
> Fails tests/test-qga. I should've double-checked earlier.
And me, too. Looks like the culprit is:
>>
>> -address_list = >value->ip_addresses;
>> -
>> -while (*address_list && (*address_list)->next) {
>> -address_list = &(*address_list)->next;
>> -}
>> -
>> -if (!*address_list) {
>> -*address_list = address_item;
>> -} else {
>> -(*address_list)->next = address_item;
>> +address_tail = >ip_addresses;
>> +while (!*address_tail) {
>> +address_tail = &(*address_tail)->next;
>> }
>> +QAPI_LIST_APPEND(address_tail, address_item);
right here; the condition 'while (!*address_tail)' should instead be
'while (*address_tail)'. Will submit v5 now that I've identified the bug.
> I'd like to drop just this part, and merge the rest. You can then
> respin just this part as a follow-up patch. Okay?
>
> I can't test qemu-ga under Windows. Fingers crossed...
>
> [...]
>
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | libvirt.org
Re: [PATCH v2 2/5] travis.yml: Move the -fsanitize=undefined test to the gitlab-CI
Thomas Huth writes:
> Add it to the existing Clang job and also add a job that covers the
> linux-user code with this compiler flag. To make sure that the detected
> problems are not simply ignored, let's also use "-fno-sanitize-recover=..."
> now instead.
>
> Signed-off-by: Thomas Huth
> ---
> .gitlab-ci.yml | 14 --
> .travis.yml| 27 ---
> 2 files changed, 12 insertions(+), 29 deletions(-)
>
> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
> index 1070efce3f..1419eb4825 100644
> --- a/.gitlab-ci.yml
> +++ b/.gitlab-ci.yml
> @@ -433,13 +433,23 @@ build-some-softmmu-plugins:
> TARGETS: xtensa-softmmu arm-softmmu aarch64-softmmu alpha-softmmu
> MAKE_CHECK_ARGS: check-tcg
>
> -build-clang:
> +clang-system:
><<: *native_build_job_definition
>variables:
> IMAGE: fedora
> CONFIGURE_ARGS: --cc=clang --cxx=clang++
> + --extra-cflags=-fno-sanitize-recover=undefined
> TARGETS: alpha-softmmu arm-softmmu m68k-softmmu mips64-softmmu
> - ppc-softmmu s390x-softmmu arm-linux-user
> + ppc-softmmu s390x-softmmu
> +MAKE_CHECK_ARGS: check-qtest check-block check-tcg
> +
> +clang-user:
> + <<: *native_build_job_definition
> + variables:
> +IMAGE: fedora
> +CONFIGURE_ARGS: --cc=clang --cxx=clang++ --disable-system
> +
> --target-list-exclude=microblazeel-linux-user,aarch64-linux-user,armeb-linux-user,x86_64-linux-user,mipsn32el-linux-user,xtensa-linux-user
> + --extra-cflags=-fno-sanitize-recover=undefined
> MAKE_CHECK_ARGS: check
Interesting choice of things to skip. I don't think we'll get much
coverage though as check-tcg is about the only thing that exercises
linux-user to any degree and you'll want to include arches the build
system can build binaries for (arguably we should also update check-tcg
to build for ^endian variants of the main targets).
>
> # These targets are on the way out
> diff --git a/.travis.yml b/.travis.yml
> index 05fa1ca905..533a60c130 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -138,33 +138,6 @@ jobs:
> - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
>
>
> -# Test with Clang for compile portability (Travis uses clang-5.0)
> -- name: "Clang (user)"
> - env:
> -- CONFIG="--disable-system --host-cc=clang --cxx=clang++"
> -- CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default"
> - compiler: clang
> -
> -
> -- name: "Clang (main-softmmu)"
> - env:
> -- CONFIG="--target-list=${MAIN_SOFTMMU_TARGETS}
> - --host-cc=clang --cxx=clang++"
> -- CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-sanitize"
> - compiler: clang
> - before_script:
> -- mkdir -p ${BUILD_DIR} && cd ${BUILD_DIR}
> -- ${SRC_DIR}/configure ${CONFIG}
> --extra-cflags="-fsanitize=undefined -Werror" || { cat config.log
> meson-logs/meson-log.txt && exit 1; }
> -
> -
> -- name: "Clang (other-softmmu)"
> - env:
> -- CONFIG="--disable-user
> --target-list-exclude=${MAIN_SOFTMMU_TARGETS}
> - --host-cc=clang --cxx=clang++"
> -- CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default"
> - compiler: clang
> -
> -
> # Using newer GCC with sanitizers
> - name: "GCC9 with sanitizers (softmmu)"
>dist: bionic
--
Alex Bennée
Re: [PATCH v2 30/36] block: bdrv_reopen_multiple: refresh permissions on updated graph
Am 27.11.2020 um 15:45 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Move bdrv_reopen_multiple to new paradigm of permission update:
> first update graph relations, then do refresh the permissions.
>
> We have to modify reopen process in file-posix driver: with new scheme
> we don't have prepared permissions in raw_reopen_prepare(), so we
> should reconfigure fd in raw_check_perm(). Still this seems more native
> and simple anyway.
Hm... The diffstat shows that it is simpler because it needs less code.
But relying on the permission change callbacks for getting a new file
descriptor that changes more than just permissions doesn't feel
completely right either. Can we even expect the permission callbacks to
be called when the permissions aren't changed?
But then, reopen and permission updates were already a bit entangled
before. If we can guarantee that the permission functions will always be
called, even if the permissions don't change, I guess it's okay.
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> include/block/block.h | 2 +-
> block.c | 183 +++---
> block/file-posix.c| 84 +--
> 3 files changed, 70 insertions(+), 199 deletions(-)
>
> diff --git a/include/block/block.h b/include/block/block.h
> index 0f21ef313f..82271d9ccd 100644
> --- a/include/block/block.h
> +++ b/include/block/block.h
> @@ -195,7 +195,7 @@ typedef struct BDRVReopenState {
> BlockdevDetectZeroesOptions detect_zeroes;
> bool backing_missing;
> bool replace_backing_bs; /* new_backing_bs is ignored if this is false
> */
> -BlockDriverState *new_backing_bs; /* If NULL then detach the current bs
> */
> +BlockDriverState *old_backing_bs; /* keep pointer for permissions update
> */
> uint64_t perm, shared_perm;
perm and shared_perm are unused now and can be removed.
> QDict *options;
> QDict *explicit_options;
> diff --git a/block.c b/block.c
> index 617cba9547..474e624152 100644
> --- a/block.c
> +++ b/block.c
> @@ -103,8 +103,9 @@ static int bdrv_attach_child_common(BlockDriverState
> *child_bs,
> GSList **tran, Error **errp);
> static void bdrv_remove_backing(BlockDriverState *bs, GSList **tran);
>
> -static int bdrv_reopen_prepare(BDRVReopenState *reopen_state,
> BlockReopenQueue
> - *queue, Error **errp);
> +static int bdrv_reopen_prepare(BDRVReopenState *reopen_state,
> + BlockReopenQueue *queue,
> + GSList **set_backings_tran, Error **errp);
> static void bdrv_reopen_commit(BDRVReopenState *reopen_state);
> static void bdrv_reopen_abort(BDRVReopenState *reopen_state);
>
> @@ -2403,6 +2404,7 @@ static void bdrv_list_abort_perm_update(GSList *list)
> }
> }
>
> +__attribute__((unused))
> static void bdrv_abort_perm_update(BlockDriverState *bs)
> {
> g_autoptr(GSList) list = bdrv_topological_dfs(NULL, NULL, bs);
> @@ -2498,6 +2500,7 @@ char *bdrv_perm_names(uint64_t perm)
> *
> * Needs to be followed by a call to either bdrv_set_perm() or
> * bdrv_abort_perm_update(). */
> +__attribute__((unused))
> static int bdrv_check_update_perm(BlockDriverState *bs, BlockReopenQueue *q,
>uint64_t new_used_perm,
>uint64_t new_shared_perm,
> @@ -4100,10 +4103,6 @@ static BlockReopenQueue
> *bdrv_reopen_queue_child(BlockReopenQueue *bs_queue,
> bs_entry->state.explicit_options = explicit_options;
> bs_entry->state.flags = flags;
>
> -/* This needs to be overwritten in bdrv_reopen_prepare() */
> -bs_entry->state.perm = UINT64_MAX;
> -bs_entry->state.shared_perm = 0;
> -
> /*
> * If keep_old_opts is false then it means that unspecified
> * options must be reset to their original value. We don't allow
> @@ -4186,40 +4185,37 @@ BlockReopenQueue *bdrv_reopen_queue(BlockReopenQueue
> *bs_queue,
> */
> int bdrv_reopen_multiple(BlockReopenQueue *bs_queue, Error **errp)
> {
> -int ret = -1;
> +int ret = 0;
I would prefer to leave this right before the 'goto cleanup'.
Not sure if I fully understand all consequences yet, but overall, apart
from my concerns about file-posix and the potential AioContext locking
problems, this looks like a nice simplification of the process.
Come to think of it, the AioContext handling is probably wrong already
before your series. reopen_commit for one node could move the whole tree
to a different context and then the later nodes would all be processed
while holding the wrong lock.
Kevin
Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0
On 21-02-05 16:09:54, Jonathan Cameron wrote:
> On Wed, 3 Feb 2021 23:53:53 -0500
> Chris Browy wrote:
>
> > Hi Jonathan,
> >
> > Thanks for the review comments and we'll put out a v2 patch series
> > based on a genuine git send-email flow in a day or so and plan to include
> > - functionally separate patches
> > - new MSI-X support
> > - few bugs found in CDAT table header + checksum generation
> > - more fully respond to review comments (thanks again!)
> >
> > After the SSWG responds to your email on spec clarifications we'll work on
> > adding user-defined CDAT entries. Thanks for raising the issues with SSWG!
> >
> > It would be good to collaborate on how best to specify external CDAT files.
> > One idea is to provide -device command line property for filenames. Files
> > could be ascii format specifying the CDAT struct instances with named
> > fields and
> > value pairs. Some checks could be adding when reading in the files. Users
> > could
> > specify the CDAT structure types in any order and have multiple instances.
>
> I'd keep away from ascii files for this. Whilst it is horrible in some ways
> we should stick to command line ops. If we need a more structured format then
> similar to was proposed with hmat, via libvirt.
>
> Alternatively we could use compiled tables though we'd end up having to parse
> them to some degree.
>
Why parse? Initially (6 months ago), I was thinking CDAT could just be a blob.
The thing I liked about that approach was that when real devices came along, we
could dump their CDATs and use it directly.
> >
> > Just like you we feel what's most important is to have DOE supported so that
> > UEFI and Linux kernel and drivers can progress. We're also contributing to
> > writing compliance tests for the CXL Compliance Software Development WG.
>
> Great.
Is anyone doing the kernel enabling for it?
>
> >
> > Note your email did not post to lore.kernel.org/qemu-devel despite being
> > CC’d.
> > Maybe a --in-replies-to issue. I’ve restored that here in this email reply.
>
> Thanks Chris. The rejection was due to an unintended attachment. Please
> ignore.
>
> Thanks,
>
> Jonathan
>
>
>
> >
> > Best Regards,
> > Chris
> >
> >
> > On 2/3/21, 12:19 PM, "Jonathan Cameron" wrote:
> >
> > On Tue, 2 Feb 2021 15:43:28 -0500
> > Chris Browy wrote:
> >
> > Hi Chris,
> >
> > Whilst I appreciate that this is very much an RFC and so not in the
> > form you would eventually aim to present it in, please look for
> > a v2 to break this into a series of functionally separate patches.
> > Probably.
> >
> > 1. Introduce DOE support with no users - probably including the
> >discovery protocol
> > 2. CMA support
> > 3. CDAT support for CXL
> > 4. Compliance part.
> >
> > It's also well worth jumping through the hoops needed to get a
> > git send-email workflow up and running as you seem to have had some
> > trouble with getting the thread to send in one go etc.
> >
> > Clearly we now have two possible implementations for this functionality.
> > Personally I don't care which one we take forwards - if nothing else
> > the exercise has highlighted some disagreements in spec interpretation
> > that need clearing up. I've mailed one big one to the SSWG list today.
> >
> > I found a few things I definitely got wrong as well whilst reading this
> > :)
> > Always advantages in having multiple implementations given we don't have
> > hardware yet.
> >
> > Jonathan
> >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 981dc92e25..4fb865e0b3 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -1655,6 +1655,13 @@ F: docs/pci*
> > > F: docs/specs/*pci*
> > > F: default-configs/pci.mak
> > >
> > > +PCIE DOE
> > > +M: Huai-Cheng Kuo
> > > +M: Chris Browy
> > > +S: Supported
> > > +F: include/hw/pci/pcie_doe.h
> > > +F: hw/pci/pcie_doe.c
> > > +
> > > ACPI/SMBIOS
> > > M: Michael S. Tsirkin
> > > M: Igor Mammedov
> > > diff --git a/hw/cxl/cxl-component-utils.c
> > b/hw/cxl/cxl-component-utils.c
> > > index e1bcee5bdb..c49d2aa896 100644
> > > --- a/hw/cxl/cxl-component-utils.c
> > > +++ b/hw/cxl/cxl-component-utils.c
> > > @@ -195,3 +195,154 @@ void
> > cxl_component_create_dvsec(CXLComponentState *cxl, uint16_t length,
> > > range_init_nofail(>dvsecs[type], cxl->dvsec_offset,
> > length);
> > > cxl->dvsec_offset += length;
> > > }
> > > +
> > > +uint32_t cxl_doe_compliance_init(CXLComponentState *cxl_cstate)
> > > +{
> > > +PCIDevice *pci_dev = cxl_cstate->pdev;
> > > +uint32_t req;
> > > +uint32_t byte_cnt = 0;
> > > +
> > > +DOE_DBG(">> %s\n", __func__);
> > > +
> > > +req = ((struct cxl_compliance_mode_cap
> > *)pcie_doe_get_req(pci_dev))
> > > +
[PATCH 23/24] docs/system/arm/mps2.rst: Document the new mps3-an524 board
Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell --- docs/system/arm/mps2.rst | 24 ++-- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 8c5b5f1fe07..601ccea15cb 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,12 +1,15 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) - +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) += These board models all use Arm M-profile CPUs. -The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger -FPGA but is otherwise the same as the 2). Since the CPU itself -and most of the devices are in the FPGA, the details of the board -as seen by the guest depend significantly on the FPGA image. +The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a +bigger FPGA but is otherwise the same as the 2; the 3 has a bigger +FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). + +Since the CPU itself and most of the devices are in the FPGA, the +details of the board as seen by the guest depend significantly on the +FPGA image. QEMU models the following FPGA images: @@ -22,12 +25,21 @@ QEMU models the following FPGA images: Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` Dual Cortex-M33 as documented in Arm Application Note AN521 +``mps3-an524`` + Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 Differences between QEMU and real hardware: - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) +- AN524 remapping of low memory to either BRAM or to QSPI flash is + unimplemented (QEMU always maps this to BRAM, ignoring the + SCC CFG_REG0 memory-remap bit) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest visible difference is that the LAN9118 doesn't support checksum offloading +- QEMU does not model the QSPI flash in MPS3 boards as real QSPI + flash, but only as simple ROM, so attempting to rewrite the flash + from the guest will fail +- QEMU does not model the USB controller in MPS3 boards -- 2.20.1
Re: [PATCH v2 4/5] travis.yml: (Re-)move the --enable-debug jobs
Thomas Huth writes:
> We already have similar jobs in the gitlab-CI ("build-some-softmmu" and
> "build-user-plugins"), so let's switch one of them to use --enable-debug
> instead of --enable-debug-tcg, then we can simply drop these jobs from
> the Travis-CI.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Alex Bennée
--
Alex Bennée
[PATCH v2 8/8] hw/vfio/pci-quirks: Replace the word 'blacklist'
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "blacklist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Alex Williamson
Acked-by: Alex Williamson
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Daudé
---
hw/vfio/pci.h| 2 +-
hw/vfio/pci-quirks.c | 14 +++---
hw/vfio/pci.c| 4 ++--
hw/vfio/trace-events | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h
index 1574ef983f8..64777516d16 100644
--- a/hw/vfio/pci.h
+++ b/hw/vfio/pci.h
@@ -197,7 +197,7 @@ void vfio_pci_write_config(PCIDevice *pdev,
uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
-bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev);
+bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev);
void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index fc8d63c8504..81c3e30df77 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -43,19 +43,19 @@
static const struct {
uint32_t vendor;
uint32_t device;
-} romblacklist[] = {
+} rom_denylist[] = {
{ 0x14e4, 0x168e }, /* Broadcom BCM 57810 */
};
-bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev)
+bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev)
{
int i;
-for (i = 0 ; i < ARRAY_SIZE(romblacklist); i++) {
-if (vfio_pci_is(vdev, romblacklist[i].vendor, romblacklist[i].device))
{
-trace_vfio_quirk_rom_blacklisted(vdev->vbasedev.name,
- romblacklist[i].vendor,
- romblacklist[i].device);
+for (i = 0 ; i < ARRAY_SIZE(rom_denylist); i++) {
+if (vfio_pci_is(vdev, rom_denylist[i].vendor, rom_denylist[i].device))
{
+trace_vfio_quirk_rom_in_denylist(vdev->vbasedev.name,
+ rom_denylist[i].vendor,
+ rom_denylist[i].device);
return true;
}
}
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index f74be782091..759a3b1abf4 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -900,7 +900,7 @@ static void vfio_pci_size_rom(VFIOPCIDevice *vdev)
if (vdev->pdev.romfile || !vdev->pdev.rom_bar) {
/* Since pci handles romfile, just print a message and return */
-if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) {
+if (vfio_opt_rom_in_denylist(vdev) && vdev->pdev.romfile) {
warn_report("Device at %s is known to cause system instability"
" issues during option rom execution",
vdev->vbasedev.name);
@@ -927,7 +927,7 @@ static void vfio_pci_size_rom(VFIOPCIDevice *vdev)
return;
}
-if (vfio_blacklist_opt_rom(vdev)) {
+if (vfio_opt_rom_in_denylist(vdev)) {
if (dev->opts && qemu_opt_get(dev->opts, "rombar")) {
warn_report("Device at %s is known to cause system instability"
" issues during option rom execution",
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index c0e75f24b76..079f53acf28 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -49,7 +49,7 @@ vfio_pci_emulated_sub_vendor_id(const char *name, uint16_t
val) "%s 0x%04x"
vfio_pci_emulated_sub_device_id(const char *name, uint16_t val) "%s 0x%04x"
# pci-quirks.c
-vfio_quirk_rom_blacklisted(const char *name, uint16_t vid, uint16_t did) "%s
%04x:%04x"
+vfio_quirk_rom_in_denylist(const char *name, uint16_t vid, uint16_t did) "%s
%04x:%04x"
vfio_quirk_generic_window_address_write(const char *name, const char *
region_name, uint64_t data) "%s %s 0x%"PRIx64
vfio_quirk_generic_window_data_read(const char *name, const char *
region_name, uint64_t data) "%s %s 0x%"PRIx64
vfio_quirk_generic_window_data_write(const char *name, const char *
region_name, uint64_t data) "%s %s 0x%"PRIx64
--
2.26.2
[PATCH 22/24] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
The AN524 has a PL031 RTC, which we have a model of; provide it
rather than an unimplemented-device stub.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index db1afa4bd22..27feb36616e 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -59,6 +59,7 @@
#include "hw/misc/tz-msc.h"
#include "hw/arm/armsse.h"
#include "hw/dma/pl080.h"
+#include "hw/rtc/pl031.h"
#include "hw/ssi/pl022.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/net/lan9118.h"
@@ -131,8 +132,8 @@ struct MPS2TZMachineState {
UnimplementedDeviceState gpio[4];
UnimplementedDeviceState gfx;
UnimplementedDeviceState cldc;
-UnimplementedDeviceState rtc;
UnimplementedDeviceState usb;
+PL031State rtc;
PL080State dma[4];
TZMSC msc[4];
CMSDKAPBUART uart[6];
@@ -595,6 +596,23 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,
void *opaque,
return sysbus_mmio_get_region(s, 0);
}
+static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque,
+ const char *name, hwaddr size,
+ const int *irqs)
+{
+PL031State *pl031 = opaque;
+SysBusDevice *s;
+
+object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031);
+s = SYS_BUS_DEVICE(pl031);
+sysbus_realize(s, _fatal);
+/*
+ * The board docs don't give an IRQ number for the PL031, so
+ * presumably it is not connected.
+ */
+return sysbus_mmio_get_region(s, 0);
+}
+
static void create_non_mpc_ram(MPS2TZMachineState *mms)
{
/*
@@ -845,7 +863,7 @@ static void mps2tz_common_init(MachineState *machine)
{ /* port 9 reserved */ },
{ "clcd", make_unimp_dev, >cldc, 0x4130a000, 0x1000 },
-{ "rtc", make_unimp_dev, >rtc, 0x4130b000, 0x1000 },
+{ "rtc", make_rtc, >rtc, 0x4130b000, 0x1000 },
},
}, {
.name = "ahb_ppcexp0",
--
2.20.1
Re: [PATCH v2 3/5] travis.yml: Move the --enable-modules test to the gitlab-CI
Thomas Huth writes: > Simply add the flag to an existing job, no need for yet another > job here. > > Reviewed-by: Wainer dos Santos Moschetta > Signed-off-by: Thomas Huth Reviewed-by: Alex Bennée -- Alex Bennée
[PATCH v2 4/8] scripts/device-crash-test: Replace the word 'whitelist'
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "whitelist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/device-crash-test | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/scripts/device-crash-test b/scripts/device-crash-test
index 04118669ba7..6812de42f8c 100755
--- a/scripts/device-crash-test
+++ b/scripts/device-crash-test
@@ -41,18 +41,18 @@ logger = logging.getLogger('device-crash-test')
dbg = logger.debug
-# Purposes of the following whitelist:
+# Purposes of the following allowlist:
# * Avoiding verbose log messages when we find known non-fatal
# (exitcode=1) errors
# * Avoiding fatal errors when we find known crashes
# * Skipping machines/devices that are known not to work out of
# the box, when running in --quick mode
#
-# Keeping the whitelist updated is desirable, but not required,
+# Keeping the allowlist updated is desirable, but not required,
# because unexpected cases where QEMU exits with exitcode=1 will
# just trigger a INFO message.
-# Valid whitelist entry keys:
+# Valid allowlist entry keys:
# * accel: regexp, full match only
# * machine: regexp, full match only
# * device: regexp, full match only
@@ -62,7 +62,7 @@ dbg = logger.debug
# * expected: if True, QEMU is expected to always fail every time
# when testing the corresponding test case
# * loglevel: log level of log output when there's a match.
-ERROR_WHITELIST = [
+ERROR_ALLOWLIST = [
# Machines that won't work out of the box:
# MACHINE | ERROR MESSAGE
{'machine':'niagara', 'expected':True}, # Unable to load a firmware
for -M niagara
@@ -187,9 +187,9 @@ ERROR_WHITELIST = [
def whitelistTestCaseMatch(wl, t):
-"""Check if a test case specification can match a whitelist entry
+"""Check if a test case specification can match a allowlist entry
-This only checks if a whitelist entry is a candidate match
+This only checks if a allowlist entry is a candidate match
for a given test case, it won't check if the test case
results/output match the entry. See whitelistResultMatch().
"""
@@ -206,16 +206,16 @@ def whitelistTestCaseMatch(wl, t):
def whitelistCandidates(t):
"""Generate the list of candidates that can match a test case"""
-for i, wl in enumerate(ERROR_WHITELIST):
+for i, wl in enumerate(ERROR_ALLOWLIST):
if whitelistTestCaseMatch(wl, t):
yield (i, wl)
def findExpectedResult(t):
-"""Check if there's an expected=True whitelist entry for a test case
+"""Check if there's an expected=True allowlist entry for a test case
Returns (i, wl) tuple, where i is the index in
-ERROR_WHITELIST and wl is the whitelist entry itself.
+ERROR_ALLOWLIST and wl is the allowlist entry itself.
"""
for i, wl in whitelistCandidates(t):
if wl.get('expected'):
@@ -223,7 +223,7 @@ def findExpectedResult(t):
def whitelistResultMatch(wl, r):
-"""Check if test case results/output match a whitelist entry
+"""Check if test case results/output match a allowlist entry
It is valid to call this function only if
whitelistTestCaseMatch() is True for the entry (e.g. on
@@ -237,10 +237,10 @@ def whitelistResultMatch(wl, r):
def checkResultWhitelist(r):
-"""Look up whitelist entry for a given test case result
+"""Look up allowlist entry for a given test case result
Returns (i, wl) tuple, where i is the index in
-ERROR_WHITELIST and wl is the whitelist entry itself.
+ERROR_ALLOWLIST and wl is the allowlist entry itself.
"""
for i, wl in whitelistCandidates(r['testcase']):
if whitelistResultMatch(wl, r):
@@ -544,7 +544,7 @@ def main():
if f:
i, wl = checkResultWhitelist(f)
-dbg("testcase: %r, whitelist match: %r", t, wl)
+dbg("testcase: %r, allowlist match: %r", t, wl)
wl_stats.setdefault(i, []).append(f)
level = wl.get('loglevel', logging.DEBUG)
logFailure(f, level)
@@ -561,9 +561,9 @@ def main():
if args.debug:
stats = sorted([(len(wl_stats.get(i, [])), wl) for i, wl in
- enumerate(ERROR_WHITELIST)], key=lambda x: x[0])
+ enumerate(ERROR_ALLOWLIST)], key=lambda x: x[0])
for count, wl in stats:
-dbg("whitelist entry stats: %d: %r", count, wl)
+dbg("allowlist entry stats: %d: %r", count, wl)
if fatal_failures:
for f in fatal_failures:
--
2.26.2
Re: [PATCH v7 12/35] Hexagon (target/hexagon) instruction attributes
Hi Taylor,
+Eric in case I'm wrong.
On 1/30/21 12:15 AM, Taylor Simpson wrote:
On 1/20/21 4:28 AM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/attribs.h | 30 ++
> target/hexagon/attribs_def.h | 95
> 2 files changed, 125 insertions(+)
> create mode 100644 target/hexagon/attribs.h
> create mode 100644 target/hexagon/attribs_def.h
>
> diff --git a/target/hexagon/attribs.h b/target/hexagon/attribs.h
> new file mode 100644
> index 000..e88e5eb
> --- /dev/null
> +++ b/target/hexagon/attribs.h
> @@ -0,0 +1,30 @@
> +
> +enum {
> +#define DEF_ATTRIB(NAME, ...) A_##NAME,
> +#include "attribs_def.h"
Per QEMU conventions, this file has to be named "attribs_def.h.inc".
>>>
>>> Didn't know that. Which files should end in .inc?
>>
>> Oh you are right, it is not documented in CODING_STYLE.rst.
>>
>> You can see the rationale in commits:139c1837db7 and 0979ed017f0:
>>
>> meson: rename included C source files to .c.inc
>>
>> With Makefiles that have automatically generated dependencies, you
>> generated includes are set as dependencies of the Makefile, so that they
>> are built before everything else and they are available when first
>> building the .c files.
>>
>> Alternatively you can use a fine-grained dependency, e.g.
>>
>> target/arm/translate.o: target/arm/decode-neon-shared.inc.c
>>
>> With Meson you have only one choice and it is a third option, namely
>> "build at the beginning of the corresponding target"; the way you
>> express it is to list the includes in the sources of that target.
>>
>> The problem is that Meson decides if something is a source vs. a
>> generated include by looking at the extension: '.c', '.cc', '.m', '.C'
>> are sources, while everything else is considered an include---including
>> '.inc.c'.
>>
>> Use '.c.inc' to avoid this, as it is consistent with our other convention
>> of using '.rst.inc' for included reStructuredText files. The editorconfig
>> file is adjusted.
>
> OK, I understand why it's better to have files end .[ch].inc than .inc.[ch].
>
> However, I need some confirmation on which files need .inc instead of simply
> ending in .h. From what I can tell these are the guidelines
> - If a file is intended to be included in the middle of another file (as
> opposed to the top), it should end in .inc.
This has to be justified. Usually such file use macro definitions which
are defined by the file including them.
If you can not justify, there is probably a way to have your file as its
own .c/.h unit.
> - If a .inc file is intended to be included in a .h file, it should end in
> .h.inc.
Yes, no exception.
> - If a .inc file is intended to be included in a .c file, it should end in
> .c.inc.
Not necessarily, you can have .h.inc included in .c.inc:
Function prototype declarations -> .h
If generated -> .h.inc
Function body definitions -> .c
These can NOT go in .h, so if generated -> .c.inc
Inlined function body definitions -> .h/.c/.h.inc
> - The above applies to both human-written and generated files.
Yes, although it is harder to justify human-written .inc.
Also:
Header exposing subsystem X API to other subsystems go in include/..X..h
(example include/hw/sd/sd.h)
Header sharing prototypes local to a particular subsystem go in X/..h
(example hw/sd/sdmmc-internal.h)
*.inc must not go in include/
Regards (and sorry for answering late),
Phil.
