+Maciej & Laurent (the last time Aleksandar Rikalo made a comment
was 9 months ago).
On 2/15/21 7:39 AM, Thomas Huth wrote:
> On 13/02/2021 14.14, Philippe Mathieu-Daudé wrote:
>> On 2/13/21 11:05 AM, Reinoud Zandijk wrote:
>>> On Fri, Feb 12, 2021 at 10:44:55AM +0100, Philippe Mathieu-Daudé
On Sat, Feb 13, 2021 at 7:24 AM Bruce Rogers wrote:
> When qemu is built with modules, but a given module doesn't load
> qemu should handle that gracefully. When ui-spice-core.so isn't
> able to be loaded and qemu is invoked with -display spice-app or
> -spice, qemu will dereference a null
Hi,
On 2/15/21 6:26 AM, c...@etri.re.kr wrote:
> Hello,
>
> I tried “qemu-system-arm –machine help” and it gave me 75 machines.
>
> Then I tried “qemu-system-aarch64 –machine help”, and it gave me almost
> the same result except it had raspi3, sbsa-ref, xlnx-versal-virt and
> xlnx-zcu102 in
On 13/02/2021 14.14, Philippe Mathieu-Daudé wrote:
On 2/13/21 11:05 AM, Reinoud Zandijk wrote:
On Fri, Feb 12, 2021 at 10:44:55AM +0100, Philippe Mathieu-Daudé wrote:
i'd like to get the following simple patches to the MIPS/mipssim target adding
virtio-mmio devices to it.
Please submit your
On Fri, Feb 12, 2021 at 09:28:35PM +0100, BALATON Zoltan wrote:
> On Fri, 12 Feb 2021, Peter Maydell wrote:
> > For a long time now the UI layer has guaranteed that the console
> > surface is always 32 bits per pixel RGB, but some older display device
> > models still have the code to handle other
On 14/02/2021 18.59, Philippe Mathieu-Daudé wrote:
Add a job to build the MIPS r5900o32el (linux-user) target
and run the TCG tests.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 12
1 file changed, 12 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
Public bug reported:
When trying to run wine (latest devel from git) regression tests for
ntdll in a statically linked qemu-i386 (commit
392b9a74b9b621c52d05e37bc6f41f1bbab5c6f8) on arm32 (raspberry pi 4) in a
debian buster chroot, the exception tests fail at the first test with an
infinite
On 2/11/21 1:50 PM, Alessandro Di Federico via wrote:
> +{
> +r1=#0
> +r2=#0
> +}
> +{
> +r3=add(r2,r3)
> +}
Typo r3? It's uninitialized.
r~
On 2/7/21 9:45 PM, Taylor Simpson wrote:
> This series adds support for the Hexagon processor with Linux user support
>
> See patch 02 Hexagon README for detailed information.
>
> This series assumes int128_or() is implemented.
>
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Add file to default-configs
> Add hexagon to meson.build
> Add hexagon to target/meson.build
> Add target/hexagon/meson.build
> Change scripts/qemu-binfmt-conf.sh
>
> We can build a hexagon-linux-user target and run programs on the Hexagon
> scalar core.
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> ---
> tests/tcg/hexagon/fpstuff.c | 370
> ++
> tests/tcg/hexagon/Makefile.target | 1 +
> 2 files changed, 371 insertions(+)
> create mode 100644 tests/tcg/hexagon/fpstuff.c
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +/* Using volatile because we are testing atomics */
> +static inline int atomic_inc32(volatile int *x)
> +{
> +int old, dummy;
> +__asm__ __volatile__(
> +"1: %0 = memw_locked(%2)\n\t"
> +" %1 = add(%0, #1)\n\t"
> +"
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Enable multiarch tests for Hexagon
> Modify tests/tcg/configure.sh
> Add reference files to tests/tcg/hexagon
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Richard Henderson
r~
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
Drop the inline markup throughout.
> +static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
> + uint32_t words[])
> +{
> +bool found_end =
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> The imported code uses host floating point. We override them
> to use qemu softfloat
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_tcg.h | 121
> +++
> 1 file changed, 121 insertions(+)
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +#define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE
> +#define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE
> +#define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE
> +#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE;
> +#define
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
Drop all the inline markup. Let the compiler decide. It also means we get
more consistent warnings for unused functions between gcc and clang (clang will
warn for unused
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +} else if ((itype == ICLASS_V2LDST) && (GET_ATTRIB(opcode, A_STORE))) {
> +return SLOTS_01;
> +} else if ((itype == ICLASS_V2LDST) && (!GET_ATTRIB(opcode, A_STORE))) {
> +return SLOTS_01;
What's the point of this? Between the
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> macros to interface with the generator
> macros referenced in instruction semantics
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/macros.h | 592
>
> 1 file changed, 592 insertions(+)
>
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Run the C preprocessor across the instruction definition files and macro
> definition file to expand macros and prepare the semantics_generated.pyinc
> file. The resulting file contains one entry with the semantics for each
> instruction and one line
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Python script that emits the decode tree in dectree_generated.h.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/dectree.py | 351
> ++
> 1 file changed, 351 insertions(+)
> create mode 100755
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/opcodes.h | 58 +++
> target/hexagon/opcodes.c | 142
> +++
> 2 files changed, 200 insertions(+)
> create mode 100644
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +#define DF_NAN 0xULL
> +#define DF_INF 0x7ff0ULL
> +#define DF_MINUS_INF 0xfff0ULL
> +#define DF_MAXF0x7fefULL
> +#define DF_MINUS_MAXF 0xffefULL
...
> +#define
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Run the C preprocessor across the instruction definition and encoding
> files to expand macros and prepare the iset.py file. The resulting
> fill contains python data structures used to build the decode tree.
>
> Signed-off-by: Taylor Simpson
>
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Python scripts generate the following files
> helper_protos_generated.h.inc
> For each instruction we create DEF_HELPER function prototype
> helper_funcs_generated.c.inc
> For each instruction we create the helper function
From: Gollu Appalanaidu
See NVM Express 1.4, section 6.14 ("Verify Command").
Signed-off-by: Gollu Appalanaidu
[k.jensen: rebased, refactored for e2e]
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 1 +
include/block/nvme.h | 2 +
hw/block/nvme.c | 148
From: Klaus Jensen
Verify is not subject to MDTS, so a single Verify command may result in
excessive amounts of allocated memory. Impose a limit on the data size
by adding support for TP 4040 ("Non-MDTS Command Size Limits").
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 1 +
From: Minwoo Im
Format NVM admin command can make a namespace or namespaces to be
with different LBA size and metadata size with protection information
types.
This patch introduces Format NVM command with LBA format, Metadata, and
Protection Information for the device. The secure erase
From: Klaus Jensen
Introduce NvmeSg and try to deal with that pesky qsg/iov duality that
haunts all the memory-related functions.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 17 -
hw/block/nvme.c | 191 ++--
2 files changed, 117
From: Klaus Jensen
Add support for namespaces formatted with protection information. The
type of end-to-end data protection (i.e. Type 1, Type 2 or Type 3) is
selected with the `pi` nvme-ns device parameter. If the number of
metadata bytes is larger than 8, the `pil` nvme-ns device parameter may
From: Minwoo Im
This patch introduces multiple LBA formats supported with the typical
logical block sizes of 512 bytes and 4096 bytes as well as metadata
sizes of 0, 8, 16 and 64 bytes. The format will be chosed based on the
lbads and ms parameters of the nvme-ns device.
Signed-off-by: Minwoo
From: Klaus Jensen
Add support for metadata in the form of extended logical blocks as well
as a separate buffer of data. The new `ms` nvme-ns device parameter
specifies the size of metadata per logical block in bytes. The `mset`
nvme-ns device parameter controls whether metadata is transfered as
From: Klaus Jensen
The nvme_dma function doesn't just do DMA (QEMUSGList-based) memory transfers;
it also handles QEMUIOVector copies.
Introduce the NvmeTxDirection enum and rename to nvme_tx. Remove mapping
of PRPs/SGLs from nvme_tx and instead assert that they have been mapped
previously.
From: Klaus Jensen
Fix missing sign inversion.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 6ed5fbf5426d..d73dac413d4e 100644
--- a/hw/block/nvme.c
+++
From: Klaus Jensen
The 'len' member of the nvme_compare_ctx struct is redundant since the
same information is available in the 'iov' member.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
From: Klaus Jensen
This is RFC v3 of a series that adds support for metadata and end-to-end data
protection.
First, on the subject of metadata, in v1, support was restricted to
extended logical blocks, which was pretty trivial to implement, but
required special initialization and broke DULBE.
From: Klaus Jensen
A Write Zeroes commands should not be counted in either the 'Data Units
Written' or in 'Host Write Commands' SMART/Health Information Log page.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Klaus Jensen
The PRP and SGL mapping functions does not have any particular need for
the entire NvmeRequest as a parameter. Clean it up.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 61 ++-
hw/block/trace-events | 4 +--
2 files
On 2/11/21 1:50 PM, Alessandro Di Federico via wrote:
> From: Alessandro Di Federico
>
> This patchset introduces the idef-parser for target/hexagon.
> It is based on "[PATCH v8 00/35] Hexagon patch series".
>
> `idef-parser` is a build-time tool built using flex and bison. Its aim
> is to
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +uint64_t conv_sf_to_8u(float32 in, float_status *fp_status);
> +uint32_t conv_sf_to_4u(float32 in, float_status *fp_status);
> +int64_t conv_sf_to_8s(float32 in, float_status *fp_status);
> +int32_t conv_sf_to_4s(float32 in, float_status *fp_status);
> +
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c)
> +{
> +uint64_t tmpa, tmpb, tmpc;
> +tmpa = fGETUWORD(0, a);
> +tmpb = fGETUWORD(0, b);
> +tmpc = tmpa + tmpb + c;
> +tmpa = fGETUWORD(1, a);
> +tmpb = fGETUWORD(1,
Add a very quick test that runs a busybox binary in bFLT format:
$ avocado --show=app run -t linux_user tests/acceptance/load_bflt.py
JOB ID : db94d5960ce564c50904d666a7e259148c27e88f
JOB LOG: ~/avocado/job-results/job-2019-06-25T10.52-db94d59/job.log
(1/1)
On 2/8/21 1:54 PM, Philippe Mathieu-Daudé wrote:
> On 2/8/21 1:50 PM, Claudio Fontana wrote:
>> On 2/5/21 9:14 PM, Richard Henderson wrote:
>>> On 2/4/21 6:39 AM, Claudio Fontana wrote:
@@ -6725,10 +6722,8 @@ static void x86_cpu_initfn(Object *obj)
x86_cpu_load_model(cpu,
Hi Alessandro!
On 2/8/21 6:46 AM, Taylor Simpson wrote:
> From: Alessandro Di Federico
>
> Signed-off-by: Alessandro Di Federico
> Tested-by: Taylor Simpson
> ---
> .../debian-hexagon-cross-build-local.docker| 18 +++
> .../debian-hexagon-cross.build-toolchain.sh| 141
>
On Fri, 12 Feb 2021 at 23:24, Eric Blake wrote:
>
> The following changes since commit eac92d316351b855ba79eb374dd21cc367f1f9c1:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging (2021-02-11
> 19:57:50 +)
>
> are available in the Git
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/fpu/softfloat.h| 5 -
> fpu/softfloat-specialize.c.inc | 12
> 2 files changed, 4 insertions(+), 13 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Change these to sar/shl to emphasize the signed shift.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 8
> softmmu/physmem.c | 4 ++--
> target/ppc/int_helper.c | 4 ++--
> tests/test-int128.c | 44
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/hexagon/printinsn.h | 27 +
> target/hexagon/printinsn.c | 146
> +
> 2 files changed, 173 insertions(+)
> create
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +#define DECODE_MAPPED_REG(REGNO, NAME) \
> +insn->regno[REGNO] = DECODE_REGISTER_##NAME[insn->regno[REGNO]];
The macro argument is not a regno, but an operand number.
> +static inline int decode_opcode_can_jump(int opcode)
> +{
> +if
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Add an unsigned inequality operation. Do not fill in all of
> the variations until we have a call for them.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by:
On 2/14/21 6:58 PM, Philippe Mathieu-Daudé wrote:
> The R5900 CPU was removed some time ago (frankly I don't remember
> why). This series add it back, but to prove it works, we also add
> testing at the end.
>
> The main motivation is to have MIPS R5900 coverage, but to be able
> to run real
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Add a job to build the MIPS r5900o32el (linux-user) target
and run the TCG tests.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 12
1 file changed, 12 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 28a83afb914..7d7559416e3 100644
--- a/.gitlab-ci.yml
Test BusyBox on the R5900 CPU with 2 different binaries:
- o32 32-bit (statically linked)
- o32 64-bit (dynamically linked, uses multimedia instructions)
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 1 +
tests/acceptance/mips_r5900_ps2.py | 69
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 10 ++
> 1 file changed, 10 insertions(+)
Tested-by: Philippe Mathieu-Daudé
Add a job to build the Gentoo based MIPS R5900 cross-toolchain image.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/containers.yml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 587bd4ba2e3..f441e608446 100644
Run some integration tests for the r5900o32el-linux-user target.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 10 ++
1 file changed, 10 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 7d7559416e3..ba2c9ac0b4d 100644
--- a/.gitlab-ci.yml
+++
Similarly to the 'System' Test base class with methods for testing
system emulation, the QemuUserTest class contains methods useful to
test user-mode emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 15 +++
1 file changed, 15
On 2/8/21 6:46 AM, Taylor Simpson wrote:
> Enable multiarch tests for Hexagon
> Modify tests/tcg/configure.sh
> Add reference files to tests/tcg/hexagon
>
> Signed-off-by: Taylor Simpson
> ---
> tests/tcg/configure.sh| 4 +-
> tests/tcg/hexagon/Makefile.target | 30 ++
>
Pass EXTRA_FILES to tests/docker/docker.py to use its --extra-files
command line option.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/containers.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index
Make pick_default_qemu_bin() generic to find qemu-system or
qemu-user binaries.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/acceptance/avocado_qemu/__init__.py
Add a Docker image providing cross toolchain for the MIPS R5900 CPU
(used on the Sony PS2).
This image is based on Gentoo and the toolchain is built using crossdev.
Recipe from:
https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg03944.html
Suggested-by: Fredrik Noring
Signed-off-by:
Introduce the LQ opcode (Load Quadword) and remove unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 8
target/mips/translate.c | 16 ++--
target/mips/tx79_translate.c | 35 +++
3 files changed,
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/configure.sh | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index e1b70e25f23..64796ee11fc 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -57,6
MIPS o32 ABI on 64-bit CPUs looks like a ILP32-on-64bit data
model, allowing 64-bit arithmetic and data movement instructions.
Since this ABI seems to have only ever been used for the
development of the PS2 with the "Sony Linux Toolkit for
Playstation 2" targetting the R5900 CPU (little-endian),
The Avocado Test::fetch_asset() is handy to download artifacts
before running tests. The current class is named Test but only
tests system emulation. As we want to test user emulation,
refactor the common code as QemuBaseTest.
Signed-off-by: Philippe Mathieu-Daudé
---
Now that we have the minimum prerequisites to support the
R5900 CPU, we can reintroduce it.
While we are reverting commit 823f2897bdd ("Disable R5900
support"), we effectively cherry-pick commit ed4f49ba9bb
("target/mips: Define the R5900 CPU").
This reverts commit
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/hexagon/attribs.h | 35 +++
> target/hexagon/attribs_def.h.inc | 97
>
> 2 files changed, 132 insertions(+)
Now than SQ is properly implemented, we can move the RDHWR
kludge required to have usermode working with recent glibc.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 56
target/mips/tx79_translate.c | 34 +-
2
From: Fredrik Noring
The R5900 reports itself as MIPS III but does not implement DMULT.
Verify that DMULT is emulated properly in user mode by multiplying
two 64-bit numbers to produce a 128-bit number.
Signed-off-by: Fredrik Noring
Message-Id:
Signed-off-by: Philippe Mathieu-Daudé
---
From: Fredrik Noring
Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
supporting the n32 ABI.
Signed-off-by: Fredrik Noring
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-Id:
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 160 -
target/mips/tx79_translate.c | 188
Introduce the PPACW opcode (Parallel Pack to Word).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 30 ++
2 files changed, 31 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
Introduce the SQ opcode (Store Quadword).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 27 +++
2 files changed, 28 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index
We will use gen_rdhwr() outside of translate.c, make it public.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index
We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().
As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.
Signed-off-by: Philippe
Introduce the 'Parallel Compare for Equal' opcodes:
- PCEQB (Parallel Compare for Equal Byte)
- PCEQH (Parallel Compare for Equal Halfword)
- PCEQW (Parallel Compare for Equal Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 ++
target/mips/tx79_translate.c
Introduce the PROT3W opcode (Parallel Rotate 3 Words).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 28
2 files changed, 29 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
Introduce the PINTEH opcode (Parallel Interleave Even Halfword).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 45
2 files changed, 46 insertions(+)
diff --git a/target/mips/tx79.decode
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 6 +++
target/mips/translate.c | 84
Introduce the parallel logic opcodes:
- PAND (Parallel AND)
- POR (Parallel OR)
- PXOR (Parallel XOR)
- PNOR (Parallel NOR)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 4 +++
target/mips/tx79_translate.c | 54
2 files
Introduce the PEXEH (Parallel Exchange Even Halfword) and PEXEW
(Parallel Exchange Even Word) opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 2 ++
target/mips/tx79_translate.c | 70
2 files changed, 72 insertions(+)
diff
Introduce the 'Parallel Compare for Greater Than' opcodes:
- PCGTB (Parallel Compare for Greater Than Byte)
- PCGTH (Parallel Compare for Greater Than Halfword)
- PCGTW (Parallel Compare for Greater Than Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 +++
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 5 +
target/mips/translate.c | 39
target/mips/tx79_translate.c | 22
Introduce the PEXTUW opcode (Parallel Extend Upper from Word).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 4
target/mips/tx79_translate.c | 26 ++
2 files changed, 30 insertions(+)
diff --git a/target/mips/tx79.decode
Introduce the 'Parallel Subtract' opcodes:
- PSUBB (Parallel Subtract Byte)
- PSUBH (Parallel Subtract Halfword)
- PSUBW (Parallel Subtract Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 6
target/mips/tx79_translate.c | 61
Introduce the 'Parallel Extend Lower' opcodes:
- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper from Halfword)
- PEXTLW (Parallel Extend Upper from Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 ++
target/mips/tx79_translate.c |
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
v3: Use missing rt, optimize (Richard)
---
target/mips/translate.c | 34
We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 1 +
target/mips/translate.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 +++
target/mips/translate.c | 25 -
target/mips/tx79_translate.c | 14 ++
3 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/target/mips/tx79.decode
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 4
target/mips/translate.c | 18 ++
2 files changed, 22 insertions(+)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 3014c20cadb..468e29d7578 100644
--- a/target/mips/translate.h
+++
o32 ABI syscalls start at offset 4000.
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/mips64/syscall_nr.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/mips64/syscall_nr.h
TCG displays the upper halve registers with the same name
as their lower halves. Rename the upper halves with the
'[hi]' suffix.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c
The cpu::mmr[] array contains the upper halves of 128-bit GPR
registers. While they are only used by the R5900 CPU, the
concept is generic and could be used by another MIPS implementation.
Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global.
When the code is similar to the GPR lower halves,
64-bit MIPS targets lost setup_frame() during the refactor in commit
8949bef18b9. Restore it declaring TARGET_ARCH_HAS_SETUP_FRAME, to be
able to build the o32 ABI target.
Fixes: 8949bef18b9 ("linux-user: move mips/mips64 signal.c parts to mips
directory")
Reviewed-by: Richard Henderson
The R5900 CPU was removed some time ago (frankly I don't remember
why). This series add it back, but to prove it works, we also add
testing at the end.
The main motivation is to have MIPS R5900 coverage, but to be able
to run real world r5900 binaries, I had to implement more opcodes.
42 patches
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +const RegField reg_field_info[] = {
> +#define DEF_REG_FIELD(TAG, START, WIDTH)\
> + { START, WIDTH },
> +#include "reg_fields_def.h.inc"
> + { 0, 0 }
> +#undef DEF_REG_FIELD
> +};
What is the purpose of the 0,0 entry? Surely you don't
Le 14/02/2021 à 16:17, Philippe Mathieu-Daudé a écrit :
> On Thu, Nov 8, 2018 at 7:45 PM Fredrik Noring wrote:
>>
>> Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
>> supporting the n32 ABI.
>>
>> Signed-off-by: Fredrik Noring
>> ---
>> linux-user/mips64/target_elf.h | 3
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