Vladimir Sementsov-Ogievskiy writes:
> 16.02.2021 02:21, John Snow wrote:
>> On 2/15/21 5:05 PM, Eric Blake wrote:
>>> Break some long lines, and relax our type hints to be more generic to
>>> any JSON, in order to more easily permit the additional JSON depth now
>>> possible in migration
On 3/1/21 12:23 AM, Richard Henderson wrote:
> Drop helper_check_io[bwl] and expose their common
> subroutine to tcg directly.
>
> Signed-off-by: Richard Henderson
> ---
> target/i386/helper.h | 4 +---
> target/i386/tcg/seg_helper.c | 21 +++--
>
On 3/1/21 12:23 AM, Richard Henderson wrote:
> The we never allow i/o from user-only, and the tss check
> that helper_check_io does will always fail. Use an ifdef
> within gen_check_io and return false, indicating that an
> exception is known to be raised.
>
> Signed-off-by: Richard Henderson
>
On 3/1/21 12:23 AM, Richard Henderson wrote:
> With the previous patch for check_io, we now have enough for
> the compiler to dead-code eliminate all of the i/o helpers.
>
> Signed-off-by: Richard Henderson
> ---
> target/i386/helper.h | 3 +-
> target/i386/tcg/translate.c |
On 3/1/21 12:22 AM, Richard Henderson wrote:
> Currently, vex_l is either {0,1}; if in the future we implement
> AVX-512, the max value will be 2. In vex_v we store a register
> number. This is 0-15 for SSE, and 0-31 for AVX-512.
>
> Signed-off-by: Richard Henderson
> ---
>
On 3/1/21 2:36 AM, Cindy Lu wrote:
> On Mon, Mar 1, 2021 at 4:40 AM Michael S. Tsirkin wrote:
>>
>> On Thu, Feb 25, 2021 at 02:14:39PM -0500, Michael S. Tsirkin wrote:
>>> On Fri, Feb 26, 2021 at 12:55:06AM +0800, Cindy Lu wrote:
While peer is vdpa, sometime qemu get an all zero mac
On 01.03.21 08:20, Michael S. Tsirkin wrote:
> On Mon, Mar 01, 2021 at 08:12:35AM +0100, Thomas Lamprecht wrote:
>> On 28.02.21 21:43, Michael S. Tsirkin wrote:
>>> Sure. The way to do that is to tie old behaviour to old machine
>>> versions. We'll need it in stable too ...
>>
>> Yeah, using
On 2021/2/25 20:48, David Edmondson wrote:
On Tuesday, 2021-02-23 at 10:16:45 +08, Kunkun Jiang wrote:
Starting from pss->page, ram_save_host_page() will check every page
and send the dirty pages up to the end of the current host page or
the boundary of used_length of the block. If the host
On Mon, Mar 01, 2021 at 08:12:35AM +0100, Thomas Lamprecht wrote:
> On 28.02.21 21:43, Michael S. Tsirkin wrote:
> > Sure. The way to do that is to tie old behaviour to old machine
> > versions. We'll need it in stable too ...
>
> Yeah, using machine types is how its meant to be with solving
On 2021/2/27 2:47 上午, Alexander Bulekov wrote:
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
Buglink: https://bugs.launchpad.net/qemu/+bug/1910826
Signed-off-by: Alexander Bulekov
---
Although it's not a nc->info->receive() call, maybe this
On 28.02.21 21:43, Michael S. Tsirkin wrote:
> Sure. The way to do that is to tie old behaviour to old machine
> versions. We'll need it in stable too ...
Yeah, using machine types is how its meant to be with solving migration
breakage, sure.
But that means we have to permanently pin the VM, and
What output do you get when you run:
qemu-system-i386 -netdev help
It's likely that your binary has been compiled without "user" networking
(aka. "slirp") support. If so, please use a binary that has "slirp"
enabled instead.
** Changed in: qemu
Status: New => Incomplete
--
You
On Sun, Feb 28, 2021 at 03:02:32PM +0800, Bin Meng wrote:
> On Wed, Feb 24, 2021 at 5:28 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > The eTSEC node should provide an empty property in the
> > eTSEC node, otherwise of_translate_address() in the Linux kernel
> > fails to get the eTSEC
On Fri, Feb 26, 2021 at 03:29:55PM +0100, Paolo Bonzini wrote:
> On 25/02/21 22:29, Daniel Henrique Barboza wrote:
> > The pSeries machine is using QEMUTimer internals to return the timeout
> > in seconds for a timer object, in hw/ppc/spapr.c, function
> > spapr_drc_unplug_timeout_remaining_sec().
On 2021/2/9 11:37 下午, Eugenio Pérez wrote:
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 2 ++
hw/virtio/vhost-shadow-virtqueue.c | 49 ++
hw/virtio/vhost.c | 5 ++-
3 files changed, 55 insertions(+), 1 deletion(-)
Reviewed-by: Kirti Wankhede
On 2/23/2021 7:52 AM, Shenming Lu wrote:
On ARM64 the VFIO SET_IRQS ioctl is dependent on the VM interrupt
setup, if the restoring of the VFIO PCI device config space is
before the VGIC, an error might occur in the kernel.
So we move the saving of the config
On Mar 1 01:10, Minwoo Im wrote:
> If namespace inventory is changed due to some reasons (e.g., namespace
> attachment/detachment), controller can send out event notifier to the
> host to manage namespaces.
>
> This patch sends out the AEN to the host after either attach or detach
> namespaces
Expose AVX (VEX-encoded) versions of the Vector Neural Network
Instructions to guest.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 4] AVX_VNNI
The following instructions are available when this feature is
present in the guest.
1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
2.
This patch will expose AVX_VNNI features to the guest. The related
kvm/kernel patches series have been queued as below link:
https://lore.kernel.org/kvm/eee07399-df81-83ed-d410-18b42d51e...@redhat.com/
Yang Zhong (1):
i386/cpu: Expose AVX_VNNI instruction to guset
target/i386/cpu.c | 4 ++--
On 2/15/21 3:51 AM, Peter Maydell wrote:
The armv7m_load_kernel() function takes a mem_size argument which it
expects to be the size of the memory region at guest address 0. (It
uses this argument only as a limit on how large a raw image file it
can load at address zero).
Instead of hardcoding
On 2/15/21 3:51 AM, Peter Maydell wrote:
The AN505 and AN521 don't have any read-only memory, but the AN524
does; add a flag to ROMInfo to mark a region as ROM.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 6 ++
1 file changed, 6 insertions(+)
Reviewed-by: Richard Henderson
r~
On 2/15/21 3:51 AM, Peter Maydell wrote:
Instead of hardcoding the MachineClass default_ram_size and
default_ram_id fields, set them on class creation by finding the
entry in the RAMInfo array which is marked as being the QEMU system
RAM.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 24
On 2/15/21 3:51 AM, Peter Maydell wrote:
The AN505 and AN521 have the same layout of RAM; the AN524 does not.
Replace the current hard-coding of where the RAM is and which parts
of it are behind which MPCs with a data-driven approach.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 175
On 2/15/21 3:51 AM, Peter Maydell wrote:
@@ -544,7 +546,7 @@ static void mps2tz_common_init(MachineState *machine)
* + wire up the PPC's control lines to the IoTKit object
*/
-const PPCInfo ppcs[] = { {
+const PPCInfo an505_ppcs[] = { {
.name =
On 2/15/21 3:51 AM, Peter Maydell wrote:
We create an OR gate to wire together the overflow IRQs for all the
UARTs on the board; this has to have twice the number of inputs as
there are UARTs, since each UART feeds it a TX overflow and an RX
overflow interrupt line. Replace the hardcoded '10'
On 2/15/21 3:51 AM, Peter Maydell wrote:
Move the specification of the IRQ information for the uart, ethernet,
dma and spi devices to the data structures. (The other devices
handled by the PPCPortInfo structures don't have any interrupt lines
we need to wire up.)
Signed-off-by: Peter Maydell
On 2/15/21 3:51 AM, Peter Maydell wrote:
The mps2-tz code uses PPCPortInfo data structures to define what
devices are present and how they are wired up. Currently we use
these to specify device types and addresses, but hard-code the
interrupt line wiring in each make_* helper function. This
On 2/15/21 3:51 AM, Peter Maydell wrote:
On the MPS2 boards, the first 32 interrupt lines are entirely
internal to the SSE; interrupt lines for devices outside the SSE
start at 32. In the application notes that document each FPGA image,
the interrupt wiring is documented from the point of view
On 2/15/21 3:51 AM, Peter Maydell wrote:
The AN524 version of the SCC interface has different behaviour for
some of the CFG registers; implement it.
Each board in this family can have minor differences in the meaning
of the CFG registers, so rather than trying to specify all the
possible
On 2/15/21 3:51 AM, Peter Maydell wrote:
The AN524 has more interrupt lines than the AN505 and AN521; make
numirq board-specific rather than a compile-time constant.
Since the difference is small (92 on the current boards and 95 on the
new one) we don't dynamically allocate the
On 2/15/21 3:51 AM, Peter Maydell wrote:
Set the FPGAIO num-leds and have-switches properties explicitly
per-board, rather than relying on the defaults. The AN505 and AN521
both have the same settings as the default values, but the AN524 will
be different.
Signed-off-by: Peter Maydell
On 2/15/21 3:51 AM, Peter Maydell wrote:
MPS3 boards have an extra SWITCH register in the FPGAIO block which
reports the value of some switches. Implement this, governed by a
property the board code can use to specify whether whether it exists.
Signed-off-by: Peter Maydell
Reviewed-by:
On 2/15/21 3:51 AM, Peter Maydell wrote:
The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The
FPGAIO device is similar on both sets of boards, but the LED0
register has correspondingly more bits that have an effect. Add a
device property for number of LEDs.
Signed-off-by: Peter
On 2/15/21 3:51 AM, Peter Maydell wrote:
+uint32_t len_oscclk;
...
+int i;
...
+for (i = 0; i < mmc->len_oscclk; i++) {
Shouldn't mix types. I'm surprised you didn't see a warning.
Otherwise,
Reviewed-by: Richard Henderson
r~
Hi Paolo & Eduardo,
Do we have any comment for the QEMU LBR enabling patches?
https://lore.kernel.org/qemu-devel/20210201045453.240258-1-like...@linux.intel.com/
On 2021/2/1 12:54, Like Xu wrote:
The last branch recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors
On 2/15/21 3:51 AM, Peter Maydell wrote:
We were previously using the default OSCCLK settings, which are
correct for the older MPS2 boards (mps2-an385, mps2-an386,
mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511
implemented in mps2-tz.c. Now we're setting the values
On 2/15/21 3:51 AM, Peter Maydell wrote:
Currently the MPS2 SCC device implements a fixed number of OSCCLK
values (3). The variant of this device in the MPS3 AN524 board has 6
OSCCLK values. Switch to using a PROP_ARRAY, which allows board code
to specify how large the OSCCLK array should be
Hi Genius,
I am a user of QEMU v4.2.0 and stuck in an interesting bug, which may still
exist in the mainline.
Thanks in advance to heroes who can take a look and share understanding.
The qemu main thread endlessly hangs in the handle of the qmp statement:
{'execute': 'human-monitor-command',
Hi Kirti,
What's your opinion about this? Thanks.
Keqian
On 2021/1/30 14:30, Keqian Zhu wrote:
> Hi Kirti,
>
> On 2021/1/28 5:03, Kirti Wankhede wrote:
>>
>>
>> On 1/11/2021 1:04 PM, Keqian Zhu wrote:
>>> For now the switch of vfio dirty page tracking is integrated into
>>> the
Ping.
On 2/20/21 1:29 PM, Richard Henderson wrote:
I guess it has been a while since I've run aa32 risu on aa64 host.
The launchpad bug is something that should have been seen from the
beginning, but the similar aa64 operations are expanded as integer
code, not vector code. The aa32 neon code
On Mon, Mar 1, 2021 at 4:40 AM Michael S. Tsirkin wrote:
>
> On Thu, Feb 25, 2021 at 02:14:39PM -0500, Michael S. Tsirkin wrote:
> > On Fri, Feb 26, 2021 at 12:55:06AM +0800, Cindy Lu wrote:
> > > While peer is vdpa, sometime qemu get an all zero mac address from the
> > > hardware,
> > > This
Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC
IO cycles from the BMC to the host.
Expose support on the BMC side by implementing the usual MMIO
behaviours, and expose the ability to inspect the KCS registers in
"host" style by accessing QOM properties associated with
The AST2600 allocates distinct GIC IRQs for the LPC subdevices such as
the iBT device. Previously on the AST2400 and AST2500 the LPC subdevices
shared a single LPC IRQ.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed_ast2600.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Cédric Le Goater
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater
Signed-off-by: Andrew Jeffery
---
docs/system/arm/aspeed.rst | 2 +-
Hello,
This series adds support for some of the LPC[1] peripherals found in Aspeed BMC
SoCs.
v2 addresses some minor feedback from Philippe and Cédric. v1 can be found here:
https://lore.kernel.org/qemu-devel/20210226065758.547824-1-and...@aj.id.au/T/#m28b4392d0672e85fbfaaf6565a2da2e82de1691d
The datasheet says we have 197 IRQs allocated, and we need more than 128
to describe IRQs from LPC devices. Raise the value now to allow
modelling of the LPC devices.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed_ast2600.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This appears to be a requirement of the GIC model. The AST2600 allocates
197 GIC IRQs, which we will adjust shortly.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed_ast2600.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast2600.c
Patchew URL:
https://patchew.org/QEMU/20210228232321.322053-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210228232321.322053-1-richard.hender...@linaro.org
Subject: [PATCH 00/50]
On Mon, 1 Mar 2021, at 09:37, Andrew Jeffery wrote:
>
>
> On Fri, 26 Feb 2021, at 19:26, Philippe Mathieu-Daudé wrote:
> > On 2/26/21 7:57 AM, Andrew Jeffery wrote:
> > > This appears to be a requirement of the GIC model.
> >
> > If so this should be adjusted in the GIC or
On 2/18/21 3:28 PM, Philippe Mathieu-Daudé wrote:
> Hi Richard,
>
> This is your patch (#4/71 of v4 [*]) split in 5 parts for
> easier review. Please consider using this series instead of
> your original patch.
Done.
r~
The we never allow i/o from user-only, and the tss check
that helper_check_io does will always fail. Use an ifdef
within gen_check_io and return false, indicating that an
exception is known to be raised.
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 2 +-
At minimum, wrmsr can change efer, which affects HF_LMA.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 2493d39f0b..dc31d8667f 100644
---
Having the callers upcast to X86CPU is a waste, since we
don't need it. We even have to recover env in do_hlt.
Signed-off-by: Richard Henderson
---
target/i386/tcg/misc_helper.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git
Pull the svm intercept check into the translator.
Pull the entire implementation of lmsw into the translator.
Push the check for CR8LEG into the regno validation switch.
Unify the gen_io_start check between read/write.
Signed-off-by: Richard Henderson
---
target/i386/helper.h |
The param argument to helper_svm_check_intercept_param is always 0;
eliminate it and rename to helper_svm_check_intercept. Fold
gen_sve_check_intercept_param into gen_svm_check_intercept.
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 2 +-
When exiting helper_svm_check_intercept via exception, cpu_vmexit
calls cpu_restore_state, which will recover eip and cc_op via unwind.
Therefore we do not need to store eip or cc_op before the call.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 45
This function is only called from tcg/sysemu/.
There is no need for a stub in tcg/user/.
Signed-off-by: Richard Henderson
---
target/i386/tcg/helper-tcg.h | 4 +++-
target/i386/tcg/user/svm_stubs.c | 6 --
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git
Any helper that always raises an exception or interrupt,
or simply exits to the main loop, can be so marked.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 18 +-
target/i386/tcg/bpt_helper.c | 2 +-
target/i386/tcg/excp_helper.c | 18 ++
Most of the VMM instructions are already disabled for
user-only, by being usable only from ring 0.
The spec is intentionally loose for VMMCALL, allowing
the VMM to define syscalls for user-only. However,
linux does not do so; VMMCALL is illegal.
Signed-off-by: Richard Henderson
---
Sort all of the single-byte members to the same area
of the structure, eliminating 8 bytes of padding.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/target/i386/tcg/translate.c
After fixing a typo in the comment, fixup for CODING_STYLE.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
With the previous patch for check_io, we now have enough for
the compiler to dead-code eliminate all of the i/o helpers.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 3 +-
target/i386/tcg/translate.c | 6
target/i386/tcg/user/misc_stubs.c | 55
An hppa guest executing
0xe05c: ldil L%1,r4
0xe060: ldo 0(r4),r4
0xe064: sub r3,r4,sp
produces
e064 e068
sub2_i32 tmp0,tmp4,r3,$0x1,$0x1,$0x0
after folding and constant propagation. Then we hit
Pass in a pre-truncated TCGv_i32 value. We were doing the
truncation of EDX in multiple places, now only once per insn.
While all callers use s->tmp2_i32, for cleanliness of the
subroutine, use a parameter anyway.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 55
Both of these fields store the size of a single memory access,
so the range of values is 0-8.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
The user-version is a no-op. This lets us completely
remove tcg/user/svm_stubs.c.
Signed-off-by: Richard Henderson
---
target/i386/cpu.h| 8
target/i386/tcg/user/svm_stubs.c | 28
target/i386/tcg/user/meson.build | 1 -
3 files changed, 8
Drop helper_check_io[bwl] and expose their common
subroutine to tcg directly.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 4 +---
target/i386/tcg/seg_helper.c | 21 +++--
target/i386/tcg/translate.c | 14 +-
3 files changed, 5 insertions(+),
Use a single helper, flush_page, to do the work.
Use gen_svm_check_intercept.
Perform the zero-extension for invlpga inline.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 3 +--
target/i386/tcg/sysemu/misc_helper.c | 7 ++-
target/i386/tcg/sysemu/svm_helper.c
The value comes from tb->flags, which is uint32_t.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index f4af92886f..39af69585f 100644
---
Both invocations pass the start of the current instruction,
which is available as s->base.pc_next. The function sets
is_jmp, so we can eliminate a second setting.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
Use STUB_HELPER to ensure that such calls are always eliminated.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 3 +--
target/i386/tcg/translate.c | 9
target/i386/tcg/user/svm_stubs.c | 38
3 files changed, 10
The range of values is -1 (none) to 5 (R_GS).
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 39af69585f..19c2034344 100644
---
This removes an ifdef from the middle of disas_insn,
and ensures that the branch is not reachable.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c
Get cur_eip from DisasContext. Do not require the caller
to use svm_is_rep; get prefix from DisasContext. Use the
proper symbolic constants for SVM_IOIO_*.
While we're touching all call sites, return bool in
preparation for gen_check_io raising #GP.
Signed-off-by: Richard Henderson
---
It's just as easy to clear the flag with AND than assignment.
In two cases the test for the bit can be folded together with
the test for HF_INHIBIT_IRQ_MASK.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
The highest bit in this set is 0x40 (PREFIX_REX).
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 19c2034344..79f987b2cf 100644
---
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 8
target/i386/tcg/translate.c | 4
target/i386/tcg/user/misc_stubs.c | 20
3 files changed, 8 insertions(+), 24 deletions(-)
diff --git a/target/i386/helper.h
Treat this flag exactly like we treat the other rex bits.
The -1 initialization is unused; the two tests are > 0 and == 1,
so the value can be reduced to a bool.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 16 +---
1 file changed, 9 insertions(+), 7
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 92669bc142..6877873bee 100644
--- a/target/i386/tcg/translate.c
+++
LMA disables traditional segmentation, exposing a flat address space.
This means that ADDSEG is off.
Since we're adding an accessor macro, pull the value directly out
of flags otherwise.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 11 ++-
1 file changed, 6
The existing flag, x86_64_hregs, does not accurately describe
its setting. It is true if and only if a REX prefix has been
seen. Yes, that affects the "h" regs, but that's secondary.
Add PREFIX_REX and include this bit in s->prefix. Add REX_PREFIX
so that the check folds away when x86_64 is
These instructions are all privileged.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 8 ++--
target/i386/tcg/helper-tcg.h | 1 +
target/i386/tcg/misc_helper.c| 55 +---
target/i386/tcg/sysemu/misc_helper.c | 53
Change the storage from int to uint8_t since the value is in {0,8}.
For x86_64 add 0 in the macros to (1) promote the type back to int,
and (2) make the macro an rvalue.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 17 +++--
1 file changed, 7 insertions(+), 10
LMA is a pre-requisite for CODE64, so there is no way to disable it
for x86_64-linux-user, and there is no way to enable it for i386.
Since we're adding an accessor macro, pull the value directly out
of flags when we're not assuming a constant.
Signed-off-by: Richard Henderson
---
Our sysemu implementation is a stub. We can already intercept
instructions for vmexit, and raising #UD is trivial.
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 1 -
target/i386/tcg/sysemu/svm_helper.c | 7 ---
target/i386/tcg/translate.c | 7 +++
Treat this flag exactly like we treat rex_b and rex_x.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 84 -
1 file changed, 45 insertions(+), 39 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
For i386-linux-user, we can enter vm86 mode via the vm86(2) syscall.
That syscall explicitly returns to 32-bit mode, and the syscall does
not exist for a 64-bit x86_64 executable.
Since we're adding an accessor macro, pull the value directly out of
flags otherwise.
Signed-off-by: Richard
For user-only, we do not need to check for VMM intercept.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 3779da9042..cd376a2c07 100644
For x86_64 user-only, there is no way to leave 64-bit mode.
Without x86_64, there is no way to enter 64-bit mode. There is
an existing macro to aid with that; simply place it in the right
place in the ifdef chain.
Since we're adding an accessor macro, pull the value directly out
of flags when
A user-mode executable always runs in ring 3.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
For user-only, CODE32 == !VM86, because we are never in real-mode.
Since we cannot enter vm86 mode for x86_64 user-only, CODE32 is
always set.
Since we're adding an accessor macro, pull the value directly out
of flags otherwise.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c
In vm86 mode, we use the same helper as real-mode, but with
an extra check for IOPL. All non-exceptional paths set EFLAGS.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git
Currently, vex_l is either {0,1}; if in the future we implement
AVX-512, the max value will be 2. In vex_v we store a register
number. This is 0-15 for SSE, and 0-31 for AVX-512.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2
A user-mode executable is never in real-mode. Since we're adding
an accessor macro, pull the value directly out of flags for sysemu.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 69 +++--
1 file changed, 36 insertions(+), 33 deletions(-)
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 59c1212625..75ee87fe84 100644
--- a/target/i386/tcg/translate.c
+++
On real hardware, the linux kernel has the iopl(2) syscall which
can set IOPL to 3, to allow e.g. the xserver to briefly disable
interrupts while programming the graphics card.
However, QEMU cannot and does not implement this syscall, so the
IOPL is never changed from 0. Which means that all of
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index deb1e43430..f4af92886f 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -101,7 +101,6
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 68 -
1 file changed, 37 insertions(+), 31 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 6ecbbfa6c1..6af8bd219b 100644
---
Split out the check for CPL != 0 and the raising of #GP.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 79 ++---
1 file changed, 30 insertions(+), 49 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 75ee87fe84..176c95c02b 100644
--- a/target/i386/tcg/translate.c
+++
1 - 100 of 169 matches
Mail list logo
