checkfilename() doesn't always set $acpi_testexpected. Fix the following
warning:
Use of uninitialized value $acpi_testexpected in string eq at
./scripts/checkpatch.pl line 1529.
Fixes: d2f1af0e4120 ("checkpatch: don't emit warning on newly created acpi data
files")
Cc: isaku.yamah...@intel.com
在 2021/4/8 下午1:51, Dongli Zhang 写道:
On 4/6/21 7:20 PM, Jason Wang wrote:
在 2021/4/7 上午7:27, Dongli Zhang 写道:
This will answer your question that "Can it bypass the masking?".
For vhost-scsi, virtio-blk, virtio-scsi and virtio-net, to write to eventfd is
not able to bypass masking because ma
On 4/6/21 7:20 PM, Jason Wang wrote:
>
> 在 2021/4/7 上午7:27, Dongli Zhang 写道:
>>> This will answer your question that "Can it bypass the masking?".
>>>
>>> For vhost-scsi, virtio-blk, virtio-scsi and virtio-net, to write to eventfd
>>> is
>>> not able to bypass masking because masking is to unr
On 4/7/21 6:40 AM, Eduardo Habkost wrote:
> On Thu, Mar 25, 2021 at 10:44:28PM -0700, Dongli Zhang wrote:
>> The virtio device/driver (e.g., vhost-scsi or vhost-net) may hang due to
>> the loss of doorbell kick, e.g.,
>>
>> https://urldefense.com/v3/__https://lists.gnu.org/archive/html/qemu-deve
> -Original Message-
> From: Rao, Lei
> Sent: Thursday, April 1, 2021 3:47 PM
> To: Zhang, Chen ; lizhij...@cn.fujitsu.com;
> jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
> pbonz...@redhat.com; lukasstra...@web.de
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATC
> -Original Message-
> From: Rao, Lei
> Sent: Thursday, April 1, 2021 3:47 PM
> To: Zhang, Chen ; lizhij...@cn.fujitsu.com;
> jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
> pbonz...@redhat.com; lukasstra...@web.de
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATC
> -Original Message-
> From: Rao, Lei
> Sent: Thursday, April 1, 2021 3:47 PM
> To: Zhang, Chen ; lizhij...@cn.fujitsu.com;
> jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
> pbonz...@redhat.com; lukasstra...@web.de
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATC
> -Original Message-
> From: Rao, Lei
> Sent: Thursday, April 1, 2021 3:47 PM
> To: Zhang, Chen ; lizhij...@cn.fujitsu.com;
> jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
> pbonz...@redhat.com; lukasstra...@web.de
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATC
> -Original Message-
> From: Rao, Lei
> Sent: Thursday, April 1, 2021 3:47 PM
> To: Zhang, Chen ; lizhij...@cn.fujitsu.com;
> jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
> pbonz...@redhat.com; lukasstra...@web.de
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATC
+static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val,
+ Error **errp)
+{
+ERRP_GUARD();
+if (!val) {
+return; /* Disable by default */
+}
+
+if (tcg_enabled()) {
+error_setg(errp, "DAWR1 not supported in TCG.");
+
> -Original Message-
> From: Markus Armbruster
> Sent: Tuesday, April 6, 2021 4:01 PM
> To: Zhang, Chen
> Cc: Lukas Straub ; Li Zhijian
> ; Jason Wang ; qemu-
> dev ; Dr. David Alan Gilbert
> ; Zhang Chen
> Subject: Re: [PATCH V4 3/7] qapi/net: Add new QMP command for COLO
> passthrou
On Thu, Apr 08, 2021 at 11:07:22AM +0800, Bin Meng wrote:
> Hi David,
>
> On Thu, Apr 8, 2021 at 10:39 AM David Gibson
> wrote:
> >
> > On Tue, Apr 06, 2021 at 04:15:10PM +0800, Bin Meng wrote:
> > > This series bumps the u-boot.e500 to v2021.04, which fixed a long
> > > overdue broken pci issue
Hi David,
On Thu, Apr 8, 2021 at 10:39 AM David Gibson
wrote:
>
> On Tue, Apr 06, 2021 at 04:15:10PM +0800, Bin Meng wrote:
> > This series bumps the u-boot.e500 to v2021.04, which fixed a long
> > overdue broken pci issue caused by QEMU changes since Nov 2014.
> >
> > While we are here, add a re
On Fri, Apr 02, 2021 at 03:51:28PM +0530, Vaibhav Jain wrote:
> Add support for H_SCM_HEALTH hcall described at [1] for spapr
> nvdimms. This enables guest to detect the 'unarmed' status of a
> specific spapr nvdimm identified by its DRC and if its unarmed, mark
> the region backed by the nvdimm as
On Wed, Apr 07, 2021 at 10:10:41AM +0200, Greg Kurz wrote:
> On Tue, 6 Apr 2021 11:08:33 +0530
> Ravi Bangoria wrote:
>
> > As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> > availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> > DAWR is present, otherwise not.
On Wed, Apr 07, 2021 at 03:44:35PM +0200, Philippe Mathieu-Daudé wrote:
> On 4/7/21 3:11 PM, Mark Cave-Ayland wrote:
> > On 06/04/2021 09:48, Philippe Mathieu-Daudé wrote:
> >
> >> On Mac99 and newer machines, the Uninorth PCI host bridge maps
> >> the PCI hole region at 2GiB, so the RAM area besi
On Tue, Apr 06, 2021 at 04:15:10PM +0800, Bin Meng wrote:
> This series bumps the u-boot.e500 to v2021.04, which fixed a long
> overdue broken pci issue caused by QEMU changes since Nov 2014.
>
> While we are here, add a reST documentation for the ppce500 machine.
>
> Please pull the full content
On Tue, Apr 06, 2021 at 10:48:42AM +0200, Philippe Mathieu-Daudé wrote:
> On Mac99 and newer machines, the Uninorth PCI host bridge maps
> the PCI hole region at 2GiB, so the RAM area beside 2GiB is not
> accessible by the CPU. Restrict the memory to 2GiB to avoid
> problems such the one reported i
The following instructions are added
L2_loadrub_pci Rd32 = memub(Rx32++#s4:0:circ(Mu2))
L2_loadrb_pci Rd32 = memb(Rx32++#s4:0:circ(Mu2))
L2_loadruh_pci Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
L2_loadrh_pci Rd32 = memh(Rx32++#s4:1:circ(Mu2))
L2_l
Rxx32,Pe4 = vacsh(Rss32, Rtt32)
Add compare and select elements of two vectors
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 5 +++
target/hexagon/helper.h | 2 +
target/hexagon/imported/alu.idef
Rdd32 = add(Rss32, Rtt32, Px4):carry
Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
Sub with carry
Test cases in tests/tcg/hexagon/multi_result.c
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 37
target/he
The following instructions are added
L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1)
L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1)
L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6)
L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<#u2+#U6)
L4_loadali
The following instructions are added
L2_loadbzw2_io Rd32 = memubh(Rs32+#s11:1)
L2_loadbzw4_io Rdd32 = memubh(Rs32+#s11:1)
L2_loadbsw2_io Rd32 = membh(Rs32+#s11:1)
L2_loadbsw4_io Rdd32 = membh(Rs32+#s11:1)
L4_loadbzw2_ur Rd32 = memubh
Rd32,Pe4 = sfrecipa(Rs32, Rt32)
Recripocal approx
Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 26 +--
target/hexagon/a
Include size in declaration
Remove {0, 0} entry
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/reg_fields.c | 3 +--
target/hexagon/reg_fields.h | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/reg_fields.c b/target/hexago
Change #if HEX_DEBUG to if (HEX_DEBUG) so that the debug code doesn't
bit rot.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c| 72 ++--
target/hexagon/helper.h| 2 --
target/hexagon/internal.h | 11
Use the proper return for helpers that convert to unsigned
Remove target/hexagon/conv_emu.[ch]
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/conv_emu.c | 177
target/hexagon/conv_em
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 28 +++-
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index bb51f19..40b6e3d 100644
-
Similar to previous cleanup of gen_log_predicated_reg_write
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 87f5d92..07d970f 100644
Rd32,Pe4 = sfinvsqrta(Rs32)
Square root approx
The helper packs the 2 32-bit results into a 64-bit value,
and the fGEN_TCG override unpacks them into the proper results.
Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c
Reviewed-by: Richar
The following instruction is added
S2_cabacdecbinRdd32=decbin(Rss32,Rtt32)
Test cases added to tests/tcg/hexagon/misc.c
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 91 +++
target/hexago
Rdd32,Pe4 = vminub(Rtt32, Rss32)
Vector min of bytes
Test cases in tests/tcg/hexagon/multi_result.c
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 27 +++
target/hexagon/genptr.c | 22 ++
Remove hexagon_env_get_cpu and replace with env_archcpu
Replace CPU(hexagon_env_get_cpu(env)) with env_cpu(env)
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
linux-user/hexagon/cpu_loop.c | 2 +-
target/hexagon/cpu.c | 4 ++--
target/
The following instructions are added
L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev)
L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev)
L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev)
L2_loadrh_pbr Rd32 = memh(Rx32++Mu2:brev)
L2_loadri_pbr Rd32 = m
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
fpu/softfloat-specialize.c.inc | 3 +++
target/hexagon/cpu.c | 5 +
target/hexagon/op_helper.c | 47 --
3 files changed, 8 insertions(+),
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 6b74344..b87e264 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/g
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.c | 9 -
target/hexagon/decode.c| 6 +++---
target/hexagon/fma_emu.c | 39 ---
target/hexagon/op_helper.c | 37 ++
Simplify TCG generation of hex_reg_written
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr
Change (cond ? (res = x) : (res = y)) to res = (cond ? x : y)
This makes the semnatics easier to for idef-parser to deal with
The following instructions are impacted
C2_any8
C2_all8
C2_mux
C2_muxii
C2_muxir
C2_muxri
Signed-off-by: Taylor Simpson
---
target/hexagon/impo
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index 699e2cf..bb51f19 100644
--- a/target/hexagon/arch.c
+++
Multiple writes to the same preg are and'ed together. Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.
Test added to tests/tcg/hexagon/misc.c
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 13 -
target/hexagon/arch.h | 1 -
target/hexagon/macros.h | 2 --
3 files changed, 16 deletions(-)
diff --git a/target/hexagon/arch.c b/target/hexagon/arc
This patch series is a significant update for the Hexagon target
The first 16 patches address feedback from Richard Henderson
and Philippe Mathieu-Daud�
The next 10 patches add the remaining instructions for the Hexagon
scalar core
The patches are logically independent but are or
When exiting a TB, generate all the code before returning from
hexagon_tr_translate_packet so that nothing needs to be done in
hexagon_tr_tb_stop.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.c | 62 ++
Suggested-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu_bits.h | 2 +-
target/hexagon/decode.c| 80 +++---
target/hexagon/insn.h | 21 ++--
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 75
2 files changed, 80 insertions(+)
diff --git a/target/arm/cpu.
ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE.
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.
Changes from v5 to v6:
Fixed wrapping of functions in exec-all.h to avoid exceeding the
80 character limi
Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds
TLB invalidation instructions to invalidate ranges of addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 130 +++-
include/exec/exec-all.h | 46 +++
2 files changed, 173 insertions(+), 3
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 294
2 files changed, 299 insertions(+)
diff --git a/target/arm/
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+/*
+ * ADD
+ *Variables: @b, @c, @a
+ *Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD,
+ * setVFlag, OverflowADD
+ * --- code ---
+ * {
+ * cc_flag = getCCFlag ();
+ * lb = @b;
+ * lc = @c;
+
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
From: Cupertino Miranda
---
target/arc/semfunc-helper.c |13 +
target/arc/semfunc-helper.h |31 +
target/arc/semfunc-v3.c | 14653 ++
target/arc/semfunc-v3.h |55 +
4 files changed, 147
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+if(ctx->insn.limm & 0x8000)
+ ctx->insn.limm += 0x;
(1) bad braces, but
(2) use an unconditional cast to int32_t.
Qemu forces the compiler to use standard 2's compliment arithmetic. We don't
have to go
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+uint64_t helper_carry_add_flag32(uint64_t dest, uint64_t b, uint64_t c) {
+return carry_add_flag(dest, b, c, 32);
+}
+
+target_ulong helper_overflow_add_flag32(target_ulong dest, target_ulong b,
target_ulong c) {
+return overflow_add_
On Tue, Apr 6, 2021 at 4:39 PM Corey Minyard wrote:
>
> On Tue, Apr 06, 2021 at 03:21:18PM -0700, Patrick Venture wrote:
> > On Tue, Apr 6, 2021 at 11:36 AM Corey Minyard wrote:
> > >
> > > On Tue, Apr 06, 2021 at 08:55:14AM -0700, Patrick Venture wrote:
> > > > On Tue, Apr 6, 2021 at 8:41 AM Pat
I remember seeing something similar before. This was supposed to be
fixed by the linux kernel commit.
commit 841c2be09fe4f495fe5224952a419bd8c7e5b455
Author: Maxim Levitsky
Date: Wed Jul 8 14:57:31 2020 +0300
kvm: x86: replace kvm_spec_ctrl_test_value with runtime test on the host
# git descr
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
From: Cupertino Miranda
---
disas/arc.c| 51 +-
target/arc/decoder-v3.c| 1547
target/arc/decoder-v3.h| 322
target/arc/flags-v3.def| 103 +++
target/arc/oper
On 4/8/21 12:18 AM, Luis Fernando Fujita Pires wrote:
> Allow '64' to be specified for the instruction width command line params
> and use the appropriate insn/field data types, mask, extract and deposit
> functions in that case.
>
> This will be used to implement the new 64-bit Power ISA 3.1 inst
On 4/7/21 3:18 PM, Luis Fernando Fujita Pires wrote:
Allow '64' to be specified for the instruction width command line params
and use the appropriate insn/field data types, mask, extract and deposit
functions in that case.
This will be used to implement the new 64-bit Power ISA 3.1 instructions.
On 4/7/21 3:56 PM, Philippe Mathieu-Daudé wrote:
The i.MX25 PDK board has 2 banks for SDRAM, each can
address up to 256 MiB. So the total RAM usable for this
board is 512M. When we ask for more we get a misleading
error message:
$ qemu-system-arm -M imx25-pdk -m 513M
qemu-system-arm: Inval
On 4/7/21 3:30 PM, Philippe Mathieu-Daudé wrote:
We check the amount of RAM is enough, warn when it is
not, but if so we neglect to bail out. Fix that by
adding the missing exit() call.
Fixes: bda19d7bb56 ("hw/rx: Add RX GDB simulator")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rx/rx-gdbsim
The i.MX25 PDK board has 2 banks for SDRAM, each can
address up to 256 MiB. So the total RAM usable for this
board is 512M. When we ask for more we get a misleading
error message:
$ qemu-system-arm -M imx25-pdk -m 513M
qemu-system-arm: Invalid RAM size, should be 128 MiB
Update the error mess
We check the amount of RAM is enough, warn when it is
not, but if so we neglect to bail out. Fix that by
adding the missing exit() call.
Fixes: bda19d7bb56 ("hw/rx: Add RX GDB simulator")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rx/rx-gdbsim.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
This adds support for 64-bit instructions to decodetree.py.
It will be necessary to later on use decodetree to implement the new 64-bit
Power ISA 3.1 instructions.
While doing this change, I thought it would also be nice to be able to specify
different sizes for each field in arg structs and al
Allow '64' to be specified for the instruction width command line params
and use the appropriate insn/field data types, mask, extract and deposit
functions in that case.
This will be used to implement the new 64-bit Power ISA 3.1 instructions.
Signed-off-by: Luis Pires
---
docs/devel/decodetree
Ah, there's v4 now.
Tested with KASAN tests + a custom test to check unaligned accesses that
span across two granules, everything works.
Thank you!
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921
Thanks Dr Gilbert, Vivek, Stefan, Greg!
I put together the discussion into this thread and CC qemu-devel@nongnu.org.
Problem:
Current Virtio-FS does not support live migration. Even when the virtiofs
directory is not mounted on the guest, VM cannot do live migration. Any
suggestions/interest I
On Wed, 07 Apr 2021 13:00:23 -
David Ober <1915...@bugs.launchpad.net> wrote:
> I have not done any of what you are asking so not exactly sure how to
> change those values, been looking and reading but not finding what I
> want so thought it might be better to just ask how to do what yo are
>
Alex Bennée writes:
> Andrey Konovalov <1921...@bugs.launchpad.net> writes:
>
>> Is this with QEMU master without the patches mentioned in this bug?
>
> This is with Richard's latest series.
>
>>
>> Which kernel version do you use?
>
> v5.11
>
>> Could you share your kernel config?
>
> We are j
On Tue, Apr 06, 2021 at 10:40:31AM -0700, Richard Henderson wrote:
> Unfortuately, the elements of PAGE_* were not in numerical
> order and so PAGE_ANON was added to an "unused" bit.
> As an arbitrary choice, move PAGE_TARGET_{1,2} together.
>
> Cc: Laurent Vivier
> Fixes: 26bab757d41b ("linux-us
Andrey Konovalov <1921...@bugs.launchpad.net> writes:
> Is this with QEMU master without the patches mentioned in this bug?
This is with Richard's latest series.
>
> Which kernel version do you use?
v5.11
> Could you share your kernel config?
We are just testing with Richard's config and el
On 4/7/21 9:57 PM, Mark Cave-Ayland wrote:
> The code for write_response() has always used the FIFO to store the data for
> the status/message in phases, even for DMA transactions. Switch to using a
> separate buffer that can be used directly for DMA transactions and restrict
> the FIFO use to the
On Wed, 7 Apr 2021 09:29:45 +0100
Daniel P. Berrangé wrote:
> On Tue, Apr 06, 2021 at 08:15:46PM +0200, Igor Mammedov wrote:
> > On Tue, 6 Apr 2021 16:07:25 +0100
> > Daniel P. Berrangé wrote:
> >
> > > On Tue, Apr 06, 2021 at 03:54:24PM +0100, Daniel P. Berrangé wrote:
> > > > On Mon, Mar
On 4/7/21 9:57 PM, Mark Cave-Ayland wrote:
> Instead let the SCSI layer invoke the .cancel callback itself to cancel and
> reset the request state.
>
> Signed-off-by: Mark Cave-Ayland
> Tested-by: Alexander Bulekov
> ---
> hw/scsi/esp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
R
Re comments #8 and #10, I don't replicate that.
I get full pass on KASAN_UNIT_TEST with
and without virtualization enabled.
Re comment #9, if there are bugs suspected in qemu, they
need to be reported, or we'll never hear about them.
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You received this bug notification because you are a member
On 4/7/21 9:58 PM, Mark Cave-Ayland wrote:
> When a CDB has been received and is about to be submitted to the SCSI layer
> via one of the ESP select commands, ensure that do_cmd is set to zero before
> executing the command.
>
> Otherwise a guest executing 2 valid CDBs in quick sequence can invoke
On Wed, 7 Apr 2021 09:29:22 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Apr 06, 2021 at 08:15:46PM +0200, Igor Mammedov wrote:
> > On Tue, 6 Apr 2021 16:07:25 +0100
> > Daniel P. Berrangé wrote:
> >
> > > On Tue, Apr 06, 2021 at 03:54:24PM +0100, Daniel P. Berrangé wrote:
> > > > On Mon, Ma
Hi Cédric,
On 4/7/21 7:16 PM, Cédric Le Goater wrote:
> The RAM memory region is now used for DMAs accesses instead of the
> memory address space region. Mask off the top bits of the DMA address
> to reflect this change.
>
> Cc: Philippe Mathieu-Daudé
> Signed-off-by: Cédric Le Goater
> ---
>
Is this with QEMU master without the patches mentioned in this bug?
Which kernel version do you use?
Could you share your kernel config?
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https://bugs.launchpad.net/bugs/1921948
Title:
It gets further without but still spams a lot of failure messages:
The buggy address belongs to the object at ff80036a2200
which belongs to the cache kmalloc-128 of size 128
The buggy address is located 11 bytes to the right of
128-byte region [ff80036a2200, ff80036a2280)
The buggy a
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
From: Cupertino Miranda
Just an acceptance test with ARC Linux booting.
Signed-off-by: Cupertino Miranda
---
tests/acceptance/boot_linux_console.py | 55 ++
1 file changed, 55 insertions(+)
diff --git a/tests/acc
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
From: Claudiu Zissulescu
The added tests verify basic instructions execution as well
as more advanced features such as zero overhead loops interrupt
system, memory management unit and memory protection unit.
Signed-off-by: Claudiu Zissulescu
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
diff --git a/configure b/configure
index 535e6a9269..80d993fac7 100755
--- a/configure
+++ b/configure
@@ -680,6 +680,8 @@ elif check_define __arm__ ; then
cpu="arm"
elif check_define __aarch64__ ; then
cpu="aarch64"
+elif check_defin
On Wed, 2021-04-07 at 19:16 +0200, Cédric Le Goater wrote:
> When we introduced support for the AST2600 SoC, the XDMA controller
> was forgotten. It went unnoticed because it's not used under
> emulation.
> But the register layout being different, the reset procedure is bogus
> and this breaks kexe
This warning is caused by "virtualization=on" QEMU option. This is
another QEMU bug AFAIU, see [1] and [2].
[1]
https://lore.kernel.org/lkml/CAAeHK+wDz8aSLyjq1b=q3+hg9ajxxwyr6+gn_ftttmn5osm...@mail.gmail.com/
[2] https://lore.kernel.org/lkml/20210311123315.GF37303@C02TD0UTHF1T.local/T/
--
You r
Use the autogenerated fuzzer test cases as the basis for a set of am53c974
regression tests.
Signed-off-by: Mark Cave-Ayland
Tested-by: Alexander Bulekov
---
MAINTAINERS | 1 +
tests/qtest/am53c974-test.c | 216
tests/qtest/meson.build
When a CDB has been received and is about to be submitted to the SCSI layer
via one of the ESP select commands, ensure that do_cmd is set to zero before
executing the command.
Otherwise a guest executing 2 valid CDBs in quick sequence can invoke the SCSI
.transfer_data callback again before do_cmd
Instead let the SCSI layer invoke the .cancel callback itself to cancel and
reset the request state.
Signed-off-by: Mark Cave-Ayland
Tested-by: Alexander Bulekov
---
hw/scsi/esp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 782c6ee357.
If the guest tries to read a CDB using DMA and cmdfifo is not empty then it is
possible to overflow cmdfifo.
Since this can only occur by issuing deliberately incorrect instruction
sequences, ensure that the maximum length of the CDB transferred to cmdfifo is
limited to the available free space wi
Each FIFO currently has its own push functions with the only difference being
the capacity check. The original reason for this was that the fifo8
implementation doesn't have a formal API for retrieving the FIFO capacity,
however there are multiple examples within QEMU where the capacity field is
ac
On Tue, Mar 23, 2021 at 05:01:09PM -0400, John Snow wrote:
> On 3/17/21 3:16 PM, Wainer dos Santos Moschetta wrote:
> > Added John and Eduardo,
> >
> > On 3/9/21 3:52 PM, Cleber Rosa wrote:
> > > On Wed, Feb 24, 2021 at 06:26:51PM -0300, Wainer dos Santos
> > > Moschetta wrote:
> > > > Currently t
The code for write_response() has always used the FIFO to store the data for
the status/message in phases, even for DMA transactions. Switch to using a
separate buffer that can be used directly for DMA transactions and restrict
the FIFO use to the non-DMA case.
Signed-off-by: Mark Cave-Ayland
Tes
If a guest transfers the message out/command phase data using DMA with a TC
that is larger than the cmdfifo size then the cmdfifo overflows triggering
an assert. Limit the size of the transfer to the free space available in
cmdfifo.
Buglink: https://bugs.launchpad.net/qemu/+bug/1919036
Signed-off-
If the guest tries to execute a CDB when cmdfifo is not empty before the start
of the message out phase then clearing the message out phase data will cause
cmdfifo to underflow due to cmdfifo_cdb_offset being larger than the amount of
data within.
Since this can only occur by issuing deliberately
After issuing a SCSI command the SCSI layer can call the SCSIBusInfo .cancel
callback which resets both current_req and current_dev to NULL. If any data
is left in the transfer buffer (async_len != 0) then the next TI (Transfer
Information) command will attempt to reference the NULL pointer causing
When about to execute a SCSI command, ensure that cmdfifo is not empty and
current_dev is non-NULL. This can happen if the guest tries to execute a TI
(Transfer Information) command without issuing one of the select commands
first.
Buglink: https://bugs.launchpad.net/qemu/+bug/1910723
Buglink: htt
The const pointer returned by fifo8_pop_buf() lies directly within the array
used
to model the FIFO. Building with address sanitizers enabled shows that if the
caller expects a minimum number of bytes present then if the FIFO is nearly
full,
the caller may unexpectedly access past the end of the
Each FIFO currently has its own pop functions with the only difference being
the capacity check. The original reason for this was that the fifo8
implementation doesn't have a formal API for retrieving the FIFO capacity,
however there are multiple examples within QEMU where the capacity field is
acc
Recently there have been a number of issues raised on Launchpad as a result of
fuzzing the am53c974 (ESP) device. I spent some time over the past couple of
days checking to see if anything had improved since my last patchset: from
what I can tell the issues are still present, but the cmdfifo relate
On 4/7/21 11:39 AM, Alex Bennée wrote:
Richard Henderson writes:
We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags. But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses. So by the time we reach the
actual MTE check
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