Re: [PATCH 2/2] nbd/server: Use drained block ops to quiesce the server

On Tue, Jun 01, 2021 at 04:29:07PM -0500, Eric Blake wrote: > On Tue, Jun 01, 2021 at 07:57:28AM +0200, Sergio Lopez wrote: > > Before switching between AioContexts we need to make sure that we're > > fully quiesced ("nb_requests == 0" for every client) when entering the > > drained section. > >

Re: [RFC PATCH v2 3/3] plugins: cache: Added FIFO and LRU eviction policies.

On Tue, Jun 1, 2021 at 3:27 PM Alex Bennée wrote: > > Mahmoud Mandour writes: > > > Now one of the three eviction policies can be chosen as an argument. On > > not specifying an argument, LRU is used by default. > > > > Signed-off-by: Mahmoud Mandour > > --- > > contrib/plugins/cache.c | 159

Re: [RFC PATCH v2 2/3] plugins: cache: Enabled parameterization and added trace printing

On Tue, Jun 1, 2021 at 1:29 PM Alex Bennée wrote: > > (Stefan CC'ed for tracing discussion) > > Mahmoud Mandour writes: > > > Made both icache and dcache configurable through plugin arguments > > and added memory trace printing in a separate file. > > Please keep the commits discreet and single

[PATCH] target/i386: Fix decode of cr8

A recent cleanup did not recognize that there are two ways to encode cr8: one via the LOCK and the other via REX. Fixes: 7eff2e7c Resolves: https://gitlab.com/qemu-project/qemu/-/issues/380 Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 1 + 1 file changed, 1 insertion(+)

Re: [RFC PATCH 1/3] plugins: Added a new cache modelling plugin

On Tue, Jun 1, 2021 at 1:12 PM Alex Bennée wrote: > > Mahmoud Mandour writes: > > > Added a cache modelling plugin that uses a static configuration used in > > many of the commercial microprocessors and uses random eviction policy. > > > > Signed-off-by: Mahmoud Mandour > > --- > >

[PATCH v7 05/10] vhost-vdpa: add support for config interrupt call back

Add new call back function in vhost-vdpa, this call back function only supported in vhost-vdpa backend Signed-off-by: Cindy Lu --- hw/virtio/trace-events | 2 ++ hw/virtio/vhost-vdpa.c | 7 +++ 2 files changed, 9 insertions(+) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events

[PATCH v7 08/10] virtio-pci: decouple virtqueue from kvm_virtio_pci_vector_use

inorder to support configure interrupt, we need to decouple virtqueue from vector use and vector release function this patch introduce vector_release_one and vector_use_one to support one vector. Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 122 -

[PATCH v7 09/10] virtio-pci: add support for configure interrupt

Add support for configure interrupt, use kvm_irqfd_assign and set the gsi to kernel. When the configure notifier was eventfd_signal by host kernel, this will finally inject an msix interrupt to guest Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 63

[PATCH v7 04/10] vhost: add new call back function for config interrupt

To support configure interrupt, we need to add a new call back function for config interrupt. Signed-off-by: Cindy Lu --- include/hw/virtio/vhost-backend.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/virtio/vhost-backend.h b/include/hw/virtio/vhost-backend.h index

[PATCH v7 07/10] virtio-mmio: add support for configure interrupt

Add configure interrupt support for virtio-mmio bus. This interrupt will working while backend is vhost-vdpa Signed-off-by: Cindy Lu --- hw/virtio/virtio-mmio.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c

[PATCH v7 03/10] virtio: decouple virtqueue from set notifier fd handler

To support config interrupt.we need to decouple virtqueue number from virtio_queue_set_guest_notifier_fd_handler, Signed-off-by: Cindy Lu --- hw/s390x/virtio-ccw.c | 6 +++--- hw/virtio/virtio-mmio.c| 4 ++-- hw/virtio/virtio-pci.c | 4 ++-- hw/virtio/virtio.c | 17

[PATCH v7 10/10] virtio-net: add peer_deleted check in virtio_net_handle_rx

During the test, We found this function will continue running while the peer is deleted, this will cause the crash. so add check for this. this only exist in machines type microvm reproduce step : load the VM with qemu-system-x86_64 -M microvm ... -netdev

[PATCH v7 06/10] vhost:add support for configure interrupt

Add configure notifier support in vhost and virtio driver When backend support VIRTIO_NET_F_STATUS,setup the configure interrupt function in vhost_dev_start and release the related resource when vhost_dev_stop Signed-off-by: Cindy Lu --- hw/net/vhost_net.c | 9 +

[PATCH v7 02/10] virtio-pci:decouple virtqueue from interrupt setting process

Decouple virtqueue from interrupt setting process to support config interrupt Now the code for interrupt/vector are coupling with the vq number, this patch will decouple the vritqueue numbers from these functions. Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 51

[PATCH v7 01/10] virtio: introduce macro IRTIO_CONFIG_IRQ_IDX 聽

In order to support configure interrupt for vhost-vdpa introduce VIRTIO_CONFIG_IRQ_IDX -1as a queue index, then we can reuse the function guest_notifier_mask and guest_notifier_pending. we add the check of queue index, if the driver not support configure interrupt, the function will just return

[PATCH v7 00/10] vhost-vdpa: add support for configure interrupt

these patches are add the support for configure interrupt These code are all tested in vp-vdpa (support configure interrupt) vdpa_sim (not support configure interrupt) test in virtio-pci bus and virtio-mmio bus Change in v2: Add support for virtio-mmio bus active the notifier while the backend

Re: [PATCH v2 2/2] ui/vdagent: fix clipboard info memory leak in error path

On 01/06/2021 17.57, Stefan Hajnoczi wrote: If the size of a VD_AGENT_CLIPBOARD_GRAB message is invalid we leak info when returning early. Thanks to Coverity for spotting this: *** CID 1453266: Resource leaks (RESOURCE_LEAK) /qemu/ui/vdagent.c: 465 in vdagent_chr_recv_clipboard() 459

Re: [PATCH v2 1/2] vhost-user-blk-test: fix Coverity open(2) false positives

On 01/06/2021 17.57, Stefan Hajnoczi wrote: Coverity checks that the file descriptor return value of open(2) is checked and used. Normally this is helpful in identifying real bugs but vhost-user-blk-test opens /dev/null as stdin and stdout after fork. In this case we don't need to look at the

[PATCH 1/2] vhost-vdpa: don't initialize backend_features

We used to initialize backend_features during vhost_vdpa_init() regardless whether or not it was supported by vhost. This will lead the unsupported features like VIRTIO_F_IN_ORDER to be included and set to the vhost-vdpa during vhost_dev_start. Because the VIRTIO_F_IN_ORDER is not supported by

[PATCH 2/2] vhost-vdpa: remove the unused vhost_vdpa_get_acked_features()

No user for this helper, let's remove it. Signed-off-by: Jason Wang --- include/net/vhost-vdpa.h | 1 - net/vhost-vdpa.c | 9 - 2 files changed, 10 deletions(-) diff --git a/include/net/vhost-vdpa.h b/include/net/vhost-vdpa.h index 45e34b7cfc..b81f9a6f2a 100644 ---

Re: [RFC PATCH v2 3/3] plugins: cache: Added FIFO and LRU eviction policies.

On Sun, May 30, 2021 at 8:37 AM Mahmoud Mandour wrote: > Now one of the three eviction policies can be chosen as an argument. On > not specifying an argument, LRU is used by default. > > Signed-off-by: Mahmoud Mandour > --- > contrib/plugins/cache.c | 159

Re: [RFC PATCH v2 2/3] plugins: cache: Enabled parameterization and added trace printing

CC'ing Emilio On Sun, May 30, 2021 at 8:37 AM Mahmoud Mandour wrote: > Made both icache and dcache configurable through plugin arguments > and added memory trace printing in a separate file. > > Signed-off-by: Mahmoud Mandour > --- > contrib/plugins/cache.c | 68

Re: [RFC PATCH v2 1/3] plugins: Added a new cache modelling plugin

On Sun, May 30, 2021 at 8:37 AM Mahmoud Mandour wrote: > Added a cache modelling plugin that uses a static configuration used in > many of the commercial microprocessors and uses random eviction policy. > > Signed-off-by: Mahmoud Mandour > --- > contrib/plugins/Makefile | 1 + >

[PATCH] migration/rdma: Fix cm event use after free

Signed-off-by: Li Zhijian --- migration/rdma.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/migration/rdma.c b/migration/rdma.c index 1cdb4561f32..d90b29a4b51 100644 --- a/migration/rdma.c +++ b/migration/rdma.c @@ -1539,16 +1539,20 @@ static int

[PATCH] target/arm: Mark LDS{MIN,MAX} as signed operations

The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must be signed, so that the inputs are properly extended. Zero extend the result afterward, as needed. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364 Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 13

Re: [PATCH v4] i386: Add ratelimit for bus locks acquired in guest

On 6/2/2021 4:10 AM, Eduardo Habkost wrote: On Tue, Jun 01, 2021 at 02:18:37PM -0400, Eduardo Habkost wrote: On Mon, May 31, 2021 at 01:14:54PM +0800, Chenyi Qiang wrote: On 5/28/2021 5:19 AM, Eduardo Habkost wrote: On Fri, May 21, 2021 at 12:38:20PM +0800, Chenyi Qiang wrote: [...] @@

Re: [PATCH v1 2/6] KVM: introduce dirty_pages into CPUState

On Wed, Jun 02, 2021 at 08:27:19AM +0800, Hyman Huang wrote: > 在 2021/6/2 7:20, Peter Xu 写道: > > On Tue, Jun 01, 2021 at 01:04:06AM +0800, huang...@chinatelecom.cn wrote: > > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > > > index 044f668a6e..973c193501 100644 > > > ---

Re: [PATCH v1 0/6] support dirtyrate at the granualrity of vcpu

在 2021/6/2 5:54, Peter Xu 写道: On Tue, Jun 01, 2021 at 01:02:45AM +0800, huang...@chinatelecom.cn wrote: From: Hyman Huang(黄勇) Since the Dirty Ring on QEMU part has been merged recently, how to use this feature is under consideration. In the scene of migration, it is valuable to provide a

Re: [PATCH v3 0/2] target/s390x: Fix SIGILL psw.addr reporting

Patchew URL: https://patchew.org/QEMU/20210602002210.3144559-1-...@linux.ibm.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210602002210.3144559-1-...@linux.ibm.com Subject: [PATCH v3 0/2] target/s390x: Fix

Re: [PATCH v1 2/6] KVM: introduce dirty_pages into CPUState

在 2021/6/2 7:20, Peter Xu 写道: On Tue, Jun 01, 2021 at 01:04:06AM +0800, huang...@chinatelecom.cn wrote: diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 044f668a6e..973c193501 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -375,6 +375,8 @@ struct CPUState {

[PATCH v3 2/2] tests/tcg/s390x: Test SIGILL and SIGSEGV handling

Verify that s390x-specific uc_mcontext.psw.addr is reported correctly. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/signal.c| 163 2 files changed, 164 insertions(+) create mode 100644

[PATCH v3 0/2] target/s390x: Fix SIGILL psw.addr reporting

qemu-s390x puts a wrong value into SIGILL's siginfo_t's psw.addr: it should be a pointer to the instruction following the illegal instruction, but at the moment it is a pointer to the illegal instruction itself. This breaks OpenJDK, which relies on this value. Patch 1 fixes the issue, patch 2

[PATCH v3 1/2] target/s390x: Fix SIGILL psw.addr reporting

When a s390x CPU attempts to execute an illegal instruction, an operation exception is recognized. This is a suppressing exception, which means that the PSW is advanced by the length of the illegal instruction. On the real hardware or in qemu-system-s390x the kernel then raises SIGILL with

Re: [PATCH v2 4/4] Hexagon (target/hexagon) remove unused TCG variables

On 6/1/21 4:19 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c| 6 -- target/hexagon/translate.c | 11 ++- 2 files changed, 2 insertions(+), 15 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PULL 00/44] Python patches

On 6/1/21 6:36 AM, Peter Maydell wrote: On Sun, 30 May 2021 at 20:22, John Snow wrote: On 5/30/21 3:09 PM, Peter Maydell wrote: Fails to build on my machine that runs the BSD VMs, apparently before it gets to the point of launching the VM: When I have seen this error message in the past,

Re: [PATCH v2 3/4] Hexagon (target/hexagon) cleanup gen_store_conditional[48] functions

On 6/1/21 4:19 PM, Taylor Simpson wrote: Previously the store-conditional code was writing to hex_pred[prednum]. Then, the fGEN_TCG override was reading from there to the destination variable so that the packet commit logic would handle it properly. The correct implementation is to write to the

Re: GSoC Intro - TUI interface for QMP

On 5/26/21 11:35 AM, Niteesh G. S. wrote: Hello Stefan, On Mon, May 24, 2021 at 7:02 PM Stefan Hajnoczi > wrote: On Sat, May 22, 2021 at 12:32:00AM +0530, Niteesh G. S. wrote: > By end of this summer, I would like to get a basic TUI with some desirable

Re: [PATCH v2 2/4] Hexagon (target/hexagon) fix l2fetch instructions

On 6/1/21 4:19 PM, Taylor Simpson wrote: Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to

Re: [PATCH v2 1/4] Hexagon (target/hexagon) fix bug in fLSBNEW*

On 6/1/21 4:19 PM, Taylor Simpson wrote: Change fLSBNEW/fLSBNEW0/fLSBNEW1 from copy to "x & 1" Remove gen_logical_not function Clean up fLSBNEWNOT to use andi-1 followed by xori-1 Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson --- target/hexagon/macros.h| 27

[PULL v2 04/44] Python: add utility function for retrieving port redirection

From: Cleber Rosa Slightly different versions for the same utility code are currently present on different locations. This unifies them all, giving preference to the version from virtiofs_submounts.py, because of the last tweaks added to it. While at it, this adds a "qemu.utils" module to host

[PULL v2 00/44] Python patches

The following changes since commit 52848929b70dcf92a68aedcfd90207be81ba3274: Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210528-pull-request' into staging (2021-05-30 20:10:30 +0100) are available in the Git repository at: https://gitlab.com/jsnow/qemu.git

Re: [PATCH v1 2/6] KVM: introduce dirty_pages into CPUState

On Tue, Jun 01, 2021 at 01:04:06AM +0800, huang...@chinatelecom.cn wrote: > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 044f668a6e..973c193501 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -375,6 +375,8 @@ struct CPUState { > struct kvm_run

[PATCH v2 4/4] Hexagon (target/hexagon) remove unused TCG variables

Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c| 6 -- target/hexagon/translate.c | 11 ++- 2 files changed, 2 insertions(+), 15 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index bd18cb1..5dbabe0 100644 --- a/target/hexagon/genptr.c +++

[PATCH v2 3/4] Hexagon (target/hexagon) cleanup gen_store_conditional[48] functions

Previously the store-conditional code was writing to hex_pred[prednum]. Then, the fGEN_TCG override was reading from there to the destination variable so that the packet commit logic would handle it properly. The correct implementation is to write to the destination variable and don't have the

[PATCH v2 0/4] Hexagon (target/hexagon) bug fixes and cleanup

Fixes for bugs found by inspection and internal testing Tests added to tests/tcg/hexagon/misc.c *** Changes in v2 *** Added patches 3 and 4 Taylor Simpson (4): Hexagon (target/hexagon) fix bug in fLSBNEW* Hexagon (target/hexagon) fix l2fetch instructions Hexagon (target/hexagon) cleanup

[PATCH v2 1/4] Hexagon (target/hexagon) fix bug in fLSBNEW*

Change fLSBNEW/fLSBNEW0/fLSBNEW1 from copy to "x & 1" Remove gen_logical_not function Clean up fLSBNEWNOT to use andi-1 followed by xori-1 Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson --- target/hexagon/macros.h| 27 ++-

[PATCH v2 2/4] Hexagon (target/hexagon) fix l2fetch instructions

Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson ---

Re: [PATCH] hw/arm/boot: Use NUMA node ID in memory node name

Hi Drew, On 6/1/21 5:50 PM, Andrew Jones wrote: On Tue, Jun 01, 2021 at 03:30:04PM +0800, Gavin Shan wrote: We possibly populate empty nodes where memory isn't included and might be hot added at late time. The FDT memory nodes can't be created due to conflicts on their names if multiple empty

Re: [PATCH v1 0/6] support dirtyrate at the granualrity of vcpu

On Tue, Jun 01, 2021 at 01:02:45AM +0800, huang...@chinatelecom.cn wrote: > From: Hyman Huang(黄勇) > > Since the Dirty Ring on QEMU part has been merged recently, how to use > this feature is under consideration. > > In the scene of migration, it is valuable to provide a more accurante >

[RFC PATCH 0/5] target/ppc: powerpc_excp improvements - part I

This is my attempt at reducing the size of powerpc_excp and cleaning it up a bit. It has two parts: part I (this series) tackles the big switch statement that runs the interrupt emulation code. Each interrupt now gets its own callback function that is kept within QOM. The per-processor code still

[RFC PATCH 4/5] target/ppc: powerpc_excp: Standardize arguments to interrupt code

The next patches will split the big switch statement in powerpc_excp into individual functions so it would be cleaner if all variables are already grouped in a structure and their names consistent. This patch makes it so that the old values for MSR and NIP (from env) are saved at the beginning as

[RFC PATCH 2/5] target/ppc: powerpc_excp: Remove dump_syscall_vectored

This function is identical to dump_syscall, so use the latter for system call vectored as well. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 14 +- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index

[RFC PATCH 1/5] target/ppc: powerpc_excp: Move lpes code to where it is used

Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 47 +--- 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 04418054f5..5ea8503b46 100644 --- a/target/ppc/excp_helper.c +++

[RFC PATCH 5/5] target/ppc: powerpc_excp: Move interrupt raising code to QOM

This patch introduces a new way to dispatch the emulated interrupts in powerpc_excp. It leverages the QEMU object model to store the implementations for each interrupt and link them to their identifier from POWERPC_EXCP enum. The processor-specific code then uses this identifier to register which

[RFC PATCH 3/5] target/ppc: powerpc_excp: Consolidade TLB miss code

The only difference in the code for Instruction fetch, Data load and Data store TLB miss errors is that when called from an unsupported processor (i.e. not one of 602, 603, 603e, G2, 7x5 or 74xx), they abort with a message specific to the operation type (insn fetch, data load/store). If a

Re: [PATCH v3 05/33] block/nbd: BDRVNBDState: drop unused connect_err and connect_status

On Fri, Apr 16, 2021 at 11:08:43AM +0300, Vladimir Sementsov-Ogievskiy wrote: > These fields are write-only. Drop them. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > Reviewed-by: Roman Kagan > --- > block/nbd.c | 12 ++-- > 1 file changed, 2 insertions(+), 10 deletions(-) >

Re: [PATCH v3 03/33] block/nbd: ensure ->connection_thread is always valid

On Fri, Apr 16, 2021 at 11:08:41AM +0300, Vladimir Sementsov-Ogievskiy wrote: > From: Roman Kagan > > Simplify lifetime management of BDRVNBDState->connect_thread by > delaying the possible cleanup of it until the BDRVNBDState itself goes > away. > > This also reverts > 0267101af6 "block/nbd:

Re: [PATCH v3 02/33] block/nbd: fix how state is cleared on nbd_open() failure paths

On Fri, Apr 16, 2021 at 11:08:40AM +0300, Vladimir Sementsov-Ogievskiy wrote: > We have two "return error" paths in nbd_open() after > nbd_process_options(). Actually we should call nbd_clear_bdrvstate() > on these paths. Interesting that nbd_process_options() calls > nbd_clear_bdrvstate() by

Re: [PATCH 2/2] nbd/server: Use drained block ops to quiesce the server

On Tue, Jun 01, 2021 at 06:31:29PM +0200, Sergio Lopez wrote: > > Hm, how do you get more than one coroutine per client yielding in > > nbd_read_eof() at the same time? I thought the model is that you always > > have one coroutine reading the next request (which is > > client->recv_coroutine) and

Re: [PATCH 2/2] nbd/server: Use drained block ops to quiesce the server

On Tue, Jun 01, 2021 at 07:57:28AM +0200, Sergio Lopez wrote: > Before switching between AioContexts we need to make sure that we're > fully quiesced ("nb_requests == 0" for every client) when entering the > drained section. > > To do this, we set "quiescing = true" for every client on >

Re: [PATCH v2 02/26] s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)

On 5/17/21 7:27 AM, David Hildenbrand wrote: Let's use the correct name. Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 01/26] s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling

On 5/17/21 7:27 AM, David Hildenbrand wrote: @@ -634,6 +664,9 @@ uint64_t HELPER(clfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t m34) s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); +if

Re: [PATCH 1/2] block-backend: add drained_poll

On Tue, Jun 01, 2021 at 05:59:10PM +0200, Kevin Wolf wrote: > > +++ b/block/block-backend.c > > @@ -2393,8 +2393,13 @@ static void blk_root_drained_begin(BdrvChild *child) > > static bool blk_root_drained_poll(BdrvChild *child) > > { > > BlockBackend *blk = child->opaque; > > +int ret =

Re: [PATCH v6 12/14] target/ppc: Implement vcfuged instruction

On 6/1/21 12:35 PM, matheus.fe...@eldorado.org.br wrote: +++ b/target/ppc/translate/vector-impl.c.inc @@ -0,0 +1,56 @@ +/* + * Power ISA decode for Vector Facility instructions + * + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you

Re: [PATCH v6 11/14] target/ppc: Implement cfuged instruction

On 6/1/21 12:35 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h| 1 + target/ppc/insn32.decode | 4 ++ target/ppc/int_helper.c| 62 ++

Re: [Stratos-dev] [PATCH 3/5] vhost-user-rng: backend: Add RNG vhost-user daemon implementation

On Tue, Jun 01, 2021 at 08:03:20PM +, Mathieu Poirier via Stratos-dev wrote: > This patch provides the vhost-user backend implementation to work > in tandem with the vhost-user-rng implementation of the QEMU VMM. > > It uses the vhost-user API so that other VMM can re-use the interface >

Re: [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree

On 6/1/21 12:35 PM, matheus.fe...@eldorado.org.br wrote: --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1,4 +1,4 @@ -/* +/* * Power ISA decode for Fixed-Point Facility instructions Watch the whitespace errors. Otherwise,

Re: [PATCH v3 1/1] yank: Unregister function when using TLS migration

On Tue, 2021-06-01 at 10:50 -0400, Peter Xu wrote: > On Tue, Jun 01, 2021 at 02:40:31AM -0300, Leonardo Bras wrote: > > [...] > > inside migration_channel_connect() and > > migration_channel_process_incoming() move yank_register_function() > > so > > it only runs once on a TLS migration. > >

Re: [PATCH] target/ppc: fix single-step exception regression

On 6/1/21 11:02 AM, Luis Pires wrote: +if (is_jmp == DISAS_EXIT || is_jmp == DISAS_CHAIN) { +/* We have not updated nip yet, so do it now */ +gen_update_nip(ctx, nip); +} This is incorrect. Both EXIT and CHAIN *have* updated nip, but to

Re: [PATCH v2 1/2] hw/nvme: add support for boot partiotions

On Tue, Jun 01, 2021 at 09:07:56PM +0200, Klaus Jensen wrote: > On Jun 1 11:07, Keith Busch wrote: > > On Tue, Jun 01, 2021 at 07:41:34PM +0200, Klaus Jensen wrote: > > > On Jun 1 10:19, Keith Busch wrote: > > > > On Tue, Jun 01, 2021 at 08:07:48PM +0530, Gollu Appalanaidu wrote: > > > > > NVMe

Re: [PATCH v4] i386: Add ratelimit for bus locks acquired in guest

On Tue, Jun 01, 2021 at 02:18:37PM -0400, Eduardo Habkost wrote: > On Mon, May 31, 2021 at 01:14:54PM +0800, Chenyi Qiang wrote: > > > > > > On 5/28/2021 5:19 AM, Eduardo Habkost wrote: > > > On Fri, May 21, 2021 at 12:38:20PM +0800, Chenyi Qiang wrote: > > > [...] > > > > @@ -4222,6 +4247,15 @@

[PATCH 3/5] vhost-user-rng: backend: Add RNG vhost-user daemon implementation

This patch provides the vhost-user backend implementation to work in tandem with the vhost-user-rng implementation of the QEMU VMM. It uses the vhost-user API so that other VMM can re-use the interface without having to write the driver again. Signed-off-by: Mathieu Poirier ---

[PATCH 4/5] docs: Add documentation for vhost based RNG implementation

Add description and example for the vhost-user based RNG implementation. Tailored on Viresh Kumar's vhost-user-i2c documentation. Signed-off-by: Mathieu Poirier --- docs/tools/vhost-user-rng.rst | 74 +++ 1 file changed, 74 insertions(+) create mode 100644

[PATCH 5/5] MAINTAINERS: Add maintainer for vhost-user RNG implementation

This patch adds entry for the vhost-user-rng related files. Signed-off-by: Mathieu Poirier --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5f55404f2fae..6a0d61443571 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1937,6 +1937,15 @@ F:

[PATCH 2/5] vhost-user-rng-pci: Add vhost-user-rng-pci implementation

This patch provides a PCI bus interface to the vhost-user-rng backed. The implentation is similar to what was done for vhost-user-i2c-pci and vhost-user-fs-pci. Signed-off-by: Mathieu Poirier --- hw/virtio/meson.build | 1 + hw/virtio/vhost-user-rng-pci.c | 79

[PATCH 1/5] vhost-user-rng: Add vhost-user-rng implementation

Following in the footsteps of what whas done for vhost-user-i2c and virtiofsd, introduce a random number generator (RNG) backend that communicates with a vhost-user server to retrieve entropy. That way another VMM could be using the same vhost-user daemon and avoid having to write yet another RNG

[PATCH 0/5] virtio: Add vhost-user based RNG service

Hi all, This sets adds a vhost-user based random number generator (RNG), similar to what has been done for i2c and virtiofsd. In fact the implementation for vhost-user-rng and vhost-user-rng-pci follow what was done for vhost-user-i2c. Applies cleanly to git://git.qemu.org/qemu.git master

[PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree

From: Matheus Ferst Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Some CPUs are known to deviate from this specification by ignoring

[PATCH v6 13/14] target/ppc: Move addpcis to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 6 ++ target/ppc/translate.c | 9 - target/ppc/translate/fixedpoint-impl.c.inc | 7 +++ 3 files changed, 13 insertions(+), 9

[PATCH v6 11/14] target/ppc: Implement cfuged instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h| 1 + target/ppc/insn32.decode | 4 ++ target/ppc/int_helper.c| 62 ++ target/ppc/translate/fixedpoint-impl.c.inc | 12 + 4 files

[PATCH v6 12/14] target/ppc: Implement vcfuged instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 7 target/ppc/translate.c | 1 + target/ppc/translate/vector-impl.c.inc | 56 ++ 3 files changed, 64 insertions(+) create mode 100644

[PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions

From: Matheus Ferst Implements the following PowerISA v3.1 instructions: setbc: Set Boolean Condition setbcr: Set Boolean Condition Reverse setnbc: Set Negative Boolean Condition setnbcr: Set Negative Boolean Condition Reverse Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode

[PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions

From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 12 target/ppc/translate/fixedpoint-impl.c.inc | 4 2 files changed, 16 insertions(+) diff --git a/target/ppc/insn64.decode

[PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI

From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 8 target/ppc/insn64.decode | 12 ++ target/ppc/translate.c | 29 --

[PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree

From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 22 ++ target/ppc/translate.c | 85 +-

[PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions

From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 15 +++ target/ppc/translate/fixedpoint-impl.c.inc | 16 2 files changed, 31 insertions(+) diff --git a/target/ppc/insn64.decode

[PATCH v6 05/14] target/ppc: Implement PNOP

From: Richard Henderson The illegal suffix behavior matches what was observed in a POWER10 DD2.0 machine. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 67 ++ target/ppc/translate/fixedpoint-impl.c.inc | 11

[PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns

From: Richard Henderson Signed-off-by: Luis Pires Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/cpu.h | 1 + target/ppc/insn32.decode | 18 +++ target/ppc/insn64.decode | 18 +++

[PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree

From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 37 ++ target/ppc/translate.c | 147 -

[PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn

From: Richard Henderson With prefixed instructions, the number of instructions remaining until the page crossing is no longer constant. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-)

[PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions

From: Richard Henderson These will be used by the decodetree trans_* functions to early-exit when the instruction set is not enabled. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 26 ++ 1 file changed, 26 insertions(+)

[PATCH v6 00/14] Base for adding PowerPC 64-bit instructions

From: Matheus Ferst This series provides the basic infrastructure for adding the new 32/64-bit instructions in Power ISA 3.1 to target/ppc. v6: - Rebase on ppc-for-6.1; - Fix rebase error in patch 02/14; - Fix style errors; - REQUIRE_64BIT when L=1 in cmp/cmpi/cmpl/cmpli. v5: - Rebase on

Re: [PATCH v2 1/2] hw/nvme: add support for boot partiotions

On Jun 1 11:07, Keith Busch wrote: On Tue, Jun 01, 2021 at 07:41:34PM +0200, Klaus Jensen wrote: On Jun 1 10:19, Keith Busch wrote: > On Tue, Jun 01, 2021 at 08:07:48PM +0530, Gollu Appalanaidu wrote: > > NVMe Boot Partitions provides an area that may be read by the host > > without

Re: [PATCH 2/2] i386: run accel_cpu_instance_init as instance_post_init

On Sat, May 29, 2021 at 11:13:13AM +0200, Claudio Fontana wrote: > This partially fixes host and max cpu initialization, > by running the accel cpu initialization only after all instance > init functions are called for all X86 cpu subclasses. Can you describe what exactly are the initialization

Re: [PATCH 1/2] i386: reorder call to cpu_exec_realizefn in x86_cpu_realizefn

+Vitaly On Sat, May 29, 2021 at 11:13:12AM +0200, Claudio Fontana wrote: > we need to expand features first, before we attempt to check them > in the accel realizefn code called by cpu_exec_realizefn(). > > At the same time we need checks for code_urev and host_cpuid_required, > and

[RFC PATCH] target/ppc: removed usage of ppc_store_sdr1 in kvm.c

The only use of this function in kvm.c is right after using the KVM ioctl to get the registers themselves, so there is no need to do the error checks done by ppc_store_sdr1. The probable reason this was here before is because of the hack where KVM PR stores the hash table size along with the SDR1

Re: HSS Issue with GCC 10, Qemu Setup for microchip-icicle-kit

I swapped the serial_hd() index between the MMUART0 and MMUART1 , so my default qemu console is the MMUART1. I can see the U-Boot and Kernel logs now. I still need both serial consoles for HSS and UBoot/Kernel and will need your help to make the original qemu command line work with

[PULL 24/24] sev: add missing firmware error conditions

From: Connor Kuehl The SEV userspace header[1] exports a couple of other error conditions that aren't listed in QEMU's SEV implementation, so let's just round out the list. [1] linux-headers/linux/psp-sev.h Signed-off-by: Connor Kuehl Reviewed-by: Philippe Mathieu-Daudé Message-Id:

[PULL 21/24] i386: use global kvm_state in hyperv_enabled() check

From: Vitaly Kuznetsov There is no need to use vCPU-specific kvm state in hyperv_enabled() check and we need to do that when feature expansion happens early, before vCPU specific KVM state is created. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Eduardo Habkost Message-Id:

[PULL 16/24] i386: split hyperv_handle_properties() into hyperv_expand_features()/hyperv_fill_cpuids()

From: Vitaly Kuznetsov The intention is to call hyperv_expand_features() early, before vCPUs are created and use the acquired data later when we set guest visible CPUID data. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Eduardo Habkost Message-Id:

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