On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
cpu-sysemu.c:
we need this sysemu code for KVM too, so we move the code to
cpu-sysemu.c so we can reach a builable state.
There will be further split later on in dedicated
exception modules for 32 and 64bit, after we make more
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
move the TCGCPUOps interface to tcg/tcg-cpu.c
in preparation for the addition of the TCG accel-cpu class.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 1 -
target/arm/internals.h
Hi Philippe,
On 5/29/21 7:50 PM, Philippe Mathieu-Daudé wrote:
On 5/29/21 3:52 PM, Philippe Mathieu-Daudé wrote:
On Mon, Aug 20, 2018 at 8:17 PM Aleksandar Markovic
wrote:
From: Stefan Markovic
+case OPC_BPOSGE32:
+tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
+bcond_compute
On 5/29/21 7:22 PM, Philippe Mathieu-Daudé wrote:
On Mon, Aug 20, 2018 at 8:17 PM Aleksandar Markovic
wrote:
From: Stefan Markovic
Add emulation of nanoMIPS 16-bit branch instructions.
...
+/* Compare two registers */
+case OPC_BPOSGE32:
+
Hello Eric, Yubo, and other QEMU developers,
I am having a problem with links between vSMMU and PCI Host Bridge,
using ARM-VIRT (64-bit; ACPI) + SMMUv3 (nested translation) setup.
Firstly, I am very new to the areas of QEMU, PCI and ACPI. So some
of my thoughts/ideas below might not sound very
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
for "all" builds (tcg + kvm), we want to avoid doing
the psci and semihosting checks if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sysemu.c | 30
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/tcg/tcg-cpu.h| 2 +-
target/arm/cpu-sysemu.c | 2 +-
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
cpu-sysemu.c:
we need this sysemu code for KVM too, so we move the code to
cpu-sysemu.c so we can reach a builable state.
There will be further split later on in dedicated
exception modules for 32 and 64bit, after we make more
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
the exception code in tcg/ needs some adjustment before being exposed
to KVM-only builds. We need to call arm_rebuild_hflags only when
TCG is enabled, or we will error out.
The direct call to helper_rebuild_hflags_a64(env, new_el)
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
after moving the code of fp_exception_el to a sysemu-only module,
we can remove the #ifndef CONFIG_USER_ONLY.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sysemu.c | 2 --
1 file changed, 2
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/tcg/helper.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sysemu.c | 100
target/arm/cpu-user.c | 5 ++
target/arm/tcg/helper.c | 100
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Cortex-A15 is the only ARM cpu class we need in KVM too.
We will be able to move it to tcg/ once the board code and configurations
are fixed.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu32.h | 4
(Resending as my previous mail didn't go through mailing lists)
Hello Eric, Yubo, and other QEMU developers,
I am having a problem with links between vSMMU and PCI Host Bridge,
using ARM-VIRT (64-bit; ACPI) + SMMUv3 (nested translation) setup.
Firstly, I am very new to the areas of QEMU, PCI
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu32.h | 2 +-
target/arm/cpu.c | 225 -
target/arm/cpu32.c | 85 -
target/arm/cpu64.c |
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
In the ARM CPU class hierarchy, the ancestor TYPE_ARM_CPU is fundamentally
a 32 bit CPU Class. The child TYPE_AARCH64_CPU overrides the class to
make it a 64 bit CPU Class.
Explicitly put the 32bit CPU Class implementation in a
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
this function is used for kvm too, add it to the
cpu-common module.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-common.c | 11 +++
target/arm/tcg/helper.c | 11 ---
2 files changed,
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-common.c | 43 +
Introduce a function to remove everything emitted
since a given point.
Cc: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Claudio Fontana
in cpu_reset(), implemented in the common cpu.c,
add a call to a new accel_cpu_reset(), which ensures that the CPU accel
interface is also reset when the CPU is reset.
Use this first for x86/kvm, simply moving the
On 6/4/21 11:13 AM, Max Reitz wrote:
> Hi,
>
> This is the C virtiofsd equivalent to
> https://gitlab.com/virtio-fs/virtiofsd-rs/-/merge_requests/26. As such,
> the summary is pretty much the same:
>
> Storing an O_PATH file descriptor in every lo_inode object means we have
> a lot of FDs open,
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
32-bit Arm hosts") we can remove the comment / check added in
commit ab6b6a4 and directly run the bios-tables-test.
Reviewed-by: Eric Blake
Reviewed-by: Alex
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
Now that we can probe if the TCG accelerator is available
at runtime with a QMP command, do it once at the beginning
and only register the tests we can run.
We can then replace the #ifdef'ry by an assertion.
Reviewed-by: Eric
On 6/4/21 8:51 AM, Alex Bennée wrote:
if (g_str_equal(qtest_get_arch(), "ppc64") &&
(access("/sys/module/kvm_hv", F_OK) ||
- access("/dev/kvm", R_OK | W_OK))) {
+ access("/dev/kvm", R_OK | W_OK) || !qtest_has_accel("kvm"))) {
g_test_message("Skipping
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, only run these tests if TCG
is built into the QEMU binary.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
tests are now only being run if KVM is available. Drop the TCG
fallback.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
The sve_tests_sve_off_kvm() test is KVM specific.
Only run it if KVM is available.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
Use the recently added generic qtest_has_accel() method to
check if KVM is available.
Suggested-by: Claudio Fontana
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 1 +
tcg/arm/tcg-target.opc.h | 1 +
The three vector shift by vector operations are all implemented via
expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.
Reviewed-by: Peter
NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 1 +
tcg/arm/tcg-target.h | 2 +-
This is minimum and maximum, signed and unsigned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 24
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h
Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.c.inc
These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 1 +
tcg/arm/tcg-target.h | 10 +-
tcg/arm/tcg-target.c.inc
This is saturating add and subtract, signed and unsigned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 24
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index cfbadad72c..94d768f249 100644
---
Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 3 +
tcg/arm/tcg-target-con-str.h | 2 +
tcg/arm/tcg-target.h |
Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 283 +--
1 file changed, 275 insertions(+), 8 deletions(-)
diff --git
This consists of the three immediate shifts: shli, shri, sari.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 27 +++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 52 +++-
1 file changed, 46 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index c6cfb83308..a802d4b585 100644
---
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 70
1 file changed, 64 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 4770d0c537..c6cfb83308 100644
---
The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into
staging (2021-06-04 13:38:49 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604
Change the return value to bool, because that's what is should
have been from the start. Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.
Change the value argument to int64_t. We will need the extra
width for 32-bit hosts wanting to match vector
On Wed, May 05, 2021 at 10:49:57AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> We are generally moving to int64_t for both offset and bytes parameters
> on all io paths.
>
> Main motivation is realization of 64-bit write_zeroes operation for
> fast zeroing large disk chunks, up to the whole
Linux Kernel 5.12 is now unisolating CPU DRCs in the device_removal
error path, signalling that the hotunplug process wasn't successful.
This allow us to send a DEVICE_UNPLUG_ERROR in drc_unisolate_logical()
to signal this error to the management layer.
We also have another error path in
At this moment we only provide one event to report a hotunplug error,
MEM_UNPLUG_ERROR. As of Linux kernel 5.12 and QEMU 6.0.0, the pseries
machine is now able to report unplug errors for other device types, such
as CPUs.
Instead of creating a (device_type)_UNPLUG_ERROR for each new device,
Hi,
This is the v2 of a series that started with 2 events,
DEVICE_UNPLUG_ERROR and DEVICE_NOT_DELETED [1]. After discussions in v1
we reached the conclussion that the DEVICE_NOT_DELETED wasn't doing much
of anything. It was an event that was trying to say 'I think something
happen, but I'm not
On Fri, Jun 04, 2021 at 08:09:45PM +0200, Claudio Fontana wrote:
> recent refactoring of i386 broke OVMF firmware with a wrong initialization
> order for host cpu. This test covers this issue for potential regressions.
>
> For the actual fixes, see:
> commit ("i386: run accel_cpu_instance_init as
On Fri, Jun 04, 2021 at 09:28:15AM +0200, Vitaly Kuznetsov wrote:
> Eduardo Habkost writes:
>
> > On Thu, Jun 03, 2021 at 01:48:29PM +0200, Vitaly Kuznetsov wrote:
> >> Currently, the only eVMCS version, supported by KVM (and described in TLFS)
> >> is '1'. When Enlightened VMCS feature is
The default of this switch is truly unreachable.
The switch selector is 3 bits, and all 8 cases are present.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
This fprintf+assert has been in place since the beginning.
It is after to the fp_access_check, so we need to move the
check up. Fold that in to the pairwise filter.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 82 +++---
1 file changed, 50
This fprintf+assert has been in place since the beginning.
It is prior to the fp_access_check, so we're still good to
raise sigill here.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 4 ++--
1 file changed, 2
A couple of printfs left over from the beginning of time,
and asserts that are reachable because of lack of decode.
r~
Richard Henderson (3):
target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
target/arm: Remove fprintf from disas_simd_mod_imm
target/arm: Diagnose
On Wed, May 05, 2021 at 10:49:50AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> v5: rebase on master, fix block comments style and over-80 line.
> 01: s/{}/()/ in subject, so that email not to be mangled.
Don't worry too much about that; if it happens again on v6, I can
manually fix
On 6/4/21 8:51 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
We want the ARM maintainers and the qemu-arm@ list to be
notified when this file is modified. Add an entry to the
'ARM TCG CPUs' section in the MAINTAINERS file.
Acked-by: Andrew Jones
Reviewed-by: Thomas Huth
Reviewed-by: Alex
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
---
target/arm/tcg/meson.build | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/meson.build
From: Claudio Fontana
we will need this for KVM too, especially for Nested support.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/cpu-common.c | 68 +
target/arm/tcg/helper.c | 68
On Freitag, 4. Juni 2021 18:31:28 CEST Greg Kurz wrote:
> On Fri, 4 Jun 2021 17:48:49 +0200
>
> Christian Schoenebeck wrote:
> > This patch set reduces latency of Twalk handling by reducing the amount of
> > thread hops, similar to previous Treaddir optimization.
> >
> > The performance gain of
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/tcg/helper.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 8372089260..d4cafdbd95 100644
---
> On Jun 3, 2021, at 2:24 AM, Philippe Mathieu-Daudé wrote:
>
> Hi Jason,
>
> On 6/3/21 5:53 AM, Jason Thorpe wrote:
>> Only program a BAR as a 64-bit MEM BAR if it really is a 64-bit MEM BAR.
>> Fixes an issue with the CMD646 IDE controller under NetBSD.
>
> OK for this fix,
>
>>
>>
From: Claudio Fontana
move sysemu-only parts of debug_helper to sysemu/
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
---
target/arm/tcg/debug_helper.c| 27 ---
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu32.h | 2 +-
target/arm/cpu.c | 225 -
target/arm/cpu32.c | 85 -
target/arm/cpu64.c | 142
4 files
From: Claudio Fontana
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-common.c | 43 +
target/arm/tcg/helper.c | 33
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/{cpu_tcg.c => tcg/tcg-cpu-models.c} | 7 +--
From: Claudio Fontana
external functions have the cpu_sve prefix,
while for static functions it can be omitted.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sve.h | 6 +++---
target/arm/cpu-sve.c | 32
target/arm/cpu.c
currently these utility functions are present only in boot_linux_console.py,
but they are useful in general, not just for linux.
In order to reuse them for a firmware test with OVMF, make these functions
general utility functions inside avocado_qemu/ , from where we will
punctually import them.
recent refactoring of i386 broke OVMF firmware with a wrong initialization
order for host cpu. This test covers this issue for potential regressions.
For the actual fixes, see:
commit ("i386: run accel_cpu_instance_init as post_init"),
commit ("i386: reorder call to cpu_exec_realizefn"),
Cc:
This is a new acceptance test that verifies the ability to boot the OVMF
"sec" binaries, that were previously broken by the i386 refactoring,
due to improper ordering of x86_64 cpu initialization and realization.
Claudio Fontana (2):
tests/acceptance: move pkg extraction to avocado_qemu/
Reviewed-by: Vivek Kasireddy
> -Original Message-
> From: Qemu-devel On
> Behalf Of Gerd Hoffmann
> Sent: Friday, June 04, 2021 12:50 AM
> To: qemu-devel@nongnu.org
> Cc: Alexander Bulekov ; Gerd Hoffmann ;
> Michael S. Tsirkin
> Subject: [PATCH] virtio-gpu: move scanout_id sanity
On 6/4/21 5:51 PM, Alex Bennée wrote:
> From: Claudio Fontana
>
> the lack of target_user_arch makes it hard to fully leverage the
> build system in order to separate user code from sysemu code.
>
> Provide it, so that we can avoid the proliferation of #ifdef
> in target code.
>
>
Hi,
On 6/2/21 12:32 PM, Alex Bennée wrote:
This copies the behaviour of patchew's configuration to make the diff
algorithm generate a minimal diff.
I was intrigued on where you had found that configuration. Then I found
it myself here:
From: Claudio Fontana
we need this for KVM too.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/cpu-sysemu.c | 62 +++
target/arm/cpu-user.c | 5
target/arm/tcg/helper.c | 64
From: Claudio Fontana
test is TCG-only.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
tests/qtest/bios-tables-test.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index
We need this functionality due to:
/* XRAM IRQs get ORed into a single line. */
object_initialize_child(OBJECT(s), "xram-irq-orgate",
>lpd.xram.irq_orgate, TYPE_OR_IRQ);
Signed-off-by: Alex Bennée
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
---
target/arm/{ => tcg}/translate-a64.h| 0
target/arm/{ => tcg}/translate.h| 0
target/arm/{ => tcg}/a32-uncond.decode | 0
target/arm/{
From: Claudio Fontana
move the TCGCPUOps interface to tcg/tcg-cpu.c
in preparation for the addition of the TCG accel-cpu class.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 1 -
target/arm/internals.h | 5 -
target/arm/tcg/tcg-cpu.h |
There is only one user of not_same_qid() which is v9fs_walk() and the
latter is using it for comparing a client supplied path with the 9p
export root path, for the sole purpose to prevent a Twalk request
from escaping from the exported 9p tree via "..".
However for that specific purpose the
From: Claudio Fontana
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
From: Claudio Fontana
return false on error, true on success.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sve.h | 2 +-
target/arm/cpu-sve.c | 17 +
target/arm/cpu.c | 3 +--
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git
This patch set reduces latency of Twalk handling by reducing the amount of
thread hops, similar to previous Treaddir optimization.
The performance gain of this patch set is not as spectacular as previously
with Treaddir, but there is definitely a measurable difference.
The actualy performance
As we are actually only comparing the filesystem ID (i.e. device number
and inode number pair) let's use the POSIX stat buffer instead of QIDs,
because resolving QIDs requires to be done on 9p server's main thread
only as it might mutate the server state if inode remapping is enabled.
As with previous performance optimization on Treaddir handling;
reduce the overall latency, i.e. overall time spent on processing
a Twalk request by reducing the amount of thread hops between the
9p server's main thread and fs worker thread(s).
In fact this patch even reduces the thread hops for
As a convenience, since iotests is an extremely prominent user of the
qemu.qmp and qemu.machine packages and already implements a linting
regime, run those tests as well so that it's very hard to miss
regressions caused by changes to the python library.
Signed-off-by: John Snow
---
Refactor the core function of the linting configuration out of 297 and
into a new file called linters.py.
Now, linters.py represents an invocation of the linting scripts that
more resembles a "normal" execution of pylint/mypy, like you'd expect to
use if 'qemu' was a bona-fide package you
From: Claudio Fontana
modules under tcg/ are only built for CONFIG_TCG anyway.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/tcg/vfp_helper.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/arm/tcg/vfp_helper.c
Since iotests are such a heavy and prominent user of the Python qemu.qmp
and qemu.machine packages, it would be convenient if the Python linting
suite also checked this client for any possible regressions introduced
by shifting around signatures, types, or interfaces in these packages.
(Of
There is only one user of fid_to_qid() which is v9fs_walk(). Let's
open-code fid_to_qid() directly within v9fs_walk(), because
fid_to_qid() hides the POSIX stat buffer which we are going to need
in the subsequent patch.
Signed-off-by: Christian Schoenebeck
---
hw/9pfs/9p.c | 23
From: Claudio Fontana
the exception code in tcg/ needs some adjustment before being exposed
to KVM-only builds. We need to call arm_rebuild_hflags only when
TCG is enabled, or we will error out.
The direct call to helper_rebuild_hflags_a64(env, new_el) will not
be possible when extracting out
From: Claudio Fontana
after moving the code of fp_exception_el to a sysemu-only module,
we can remove the #ifndef CONFIG_USER_ONLY.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sysemu.c | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Claudio Fontana
XXX Someone who really understands which properties should be added
where should review this attentively.
What goes into cpu leaf class initialization?
What goes into arm_post_init / accel_cpu?
What goes into arm_cpu_finalize_features / aarch64_cpu_finalize_features?
There is no longer a user of root_qid, so drop it.
Signed-off-by: Christian Schoenebeck
---
hw/9pfs/9p.c | 1 -
hw/9pfs/9p.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c
index 47b000d3a9..7be07f2d68 100644
--- a/hw/9pfs/9p.c
+++ b/hw/9pfs/9p.c
@@ -1444,7
From: Claudio Fontana
The QEMU PSCI implementation is not used for KVM,
we do not need the kvm constants header.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/arm-powerctl.h | 2 --
target/arm/psci.c | 1 -
2 files changed, 3
From: Claudio Fontana
before refactoring the exception code, fix the style of the
functions being moved.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/tcg/helper.c | 17 +++--
1 file changed, 11 insertions(+), 6
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sysemu.c | 100
target/arm/cpu-user.c | 5 ++
target/arm/tcg/helper.c | 100
3 files changed, 105
While the default config works well enough it does end up enabling a
lot of stuff. For more minimal builds we can pass a slimmed down list
of devices and let Kconfig work out what we want. For example:
../../configure --without-default-features \
--target-list=arm-softmmu,aarch64-softmmu \
From: Claudio Fontana
put the KVM-specific and TCG-specific functionality
in the respective subdirectories kvm/ and tcg/
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/kvm/kvm-sve.h | 28 +++
target/arm/tcg/tcg-sve.h | 24 ++
target/arm/cpu-sve.c
From: Claudio Fontana
in cpu_reset(), implemented in the common cpu.c,
add a call to a new accel_cpu_reset(), which ensures that the CPU accel
interface is also reset when the CPU is reset.
Use this first for x86/kvm, simply moving the kvm_arch_reset_vcpu() call.
Signed-off-by: Claudio Fontana
On Fri, Jun 04, 2021 at 12:07:36PM +0200, Emanuele Giuseppe Esposito wrote:
> Extract to a separate function. Do not rely on FOREACH_SAFE, which is
> only "safe" if the *current* node is removed---not if another node is
> removed. Instead, just walk the entire list from the beginning when
>
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