On Mon, May 24, 2021 at 11:50:30PM +0300, Marian Postevca wrote:
> Introduces structure AcpiBuildOem to hold the value of OEM fields and
> uses dedicated helper functions to initialize/set the values.
> Unnecessary dynamically allocated OEM fields are re-factored to static
> allocation.
>
>
On 01/07/2021 22:21, Philippe Mathieu-Daudé wrote:
On 6/29/21 7:37 AM, Philippe Mathieu-Daudé wrote:
When using the Magnum ARC firmware we can see accesses to the
UART1 beeing rejected, because the device is not mapped:
$ qemu-system-mips64el -M magnum -d guest_errors,unimp -bios
On 01/07/2021 08:18, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
This avoids failing to initialize virgl and crashing later on, and clear
the user expectations.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-gl.c | 12
1 file changed, 12
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1342686
Title:
Windows 95
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1396052
Title:
migration
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
User mode
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** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1776478
Title:
Getting
On Fri, Jul 02, 2021 at 04:55:47PM +0200, Julia Suvorova wrote:
> On Thu, Jul 1, 2021 at 6:59 AM David Gibson
> wrote:
> >
> > On Thu, Jun 17, 2021 at 09:07:35PM +0200, Julia Suvorova wrote:
> > > Add acpi_pcihp to ich9_pm as part of
> > > 'acpi-pci-hotplug-with-bridge-support' option. Set
On Friday, July 2, 2021 3:07 PM, David Hildenbrand wrote:
> On 02.07.21 04:48, Wang, Wei W wrote:
> > On Thursday, July 1, 2021 10:22 PM, David Hildenbrand wrote:
> >> On 01.07.21 14:51, Peter Xu wrote:
>
> I think that clearly shows the issue.
>
> My theory I did not verify yet: Assume we have
icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs). The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1). The consequence is that
if a
Making the vc->gfx.ectx current before handling textures
associated with it
Signed-off-by: Dongwon Kim
---
ui/gtk-egl.c | 8
1 file changed, 8 insertions(+)
diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c
index 2a2e6d3a17..32516b806c 100644
--- a/ui/gtk-egl.c
+++ b/ui/gtk-egl.c
@@ -126,6
gd_draw_event shouldn't try to repaint if surface does not exist
for the VC.
Signed-off-by: Dongwon Kim
---
ui/gtk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/ui/gtk.c b/ui/gtk.c
index bfb95f3b4b..0a38deedc7 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -756,6 +756,9 @@ static gboolean
An old esurface should be destroyed and set to be NULL when doing
un-tab and re-tab so that a new esurface an context can be created
for the window widget that those will be bound to.
Signed-off-by: Dongwon Kim
Signed-off-by: Khairul Anuar Romli
---
ui/gtk.c | 16
1 file
[Fix Den's email address in CC]
03.07.2021 00:16, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
We've faced a dead-lock in active mirror in our Rhev-8.4 based Qemu
build. And it's reproducible on master too.
Vladimir Sementsov-Ogievskiy (3):
block/mirror: set .co for active-write MirrorOp
Hi Joanne,
Next time I recommend you to Cc the maintainers, otherwise they
might miss your patch. See:
https://wiki.qemu.org/Contribute/SubmitAPatch#CC_the_relevant_maintainer
$ ./scripts/get_maintainer.pl -f hw/sd/sdhci-internal.h
"Philippe Mathieu-Daudé" (odd fixer:SD (Secure Card))
Bin Meng
../target/ppc/mmu-hash32.c: In function 'ppc_hash32_bat_lookup':
../target/ppc/mmu-hash32.c:204:13: error: 'BATu' undeclared (first use in this
function);
204 | BATu = [i];
| ^~~~
| BATut
../target/ppc/mmu-hash32.c:205:13: error: 'BATl' undeclared
../target/ppc/mmu_helper.c: In function 'get_segment_6xx_tlb':
../target/ppc/mmu_helper.c:514:46: error: passing argument 1 of
'ppc_hash32_hpt_mask' from incompatible pointer type
[-Werror=incompatible-pointer-types]
514 | ppc_hash32_hpt_mask(env) + 0x80);
|
Some fixes for the commented-out debug options in MMU code.
Since v2:
- added a fix for DEBUG_BATS
v1: https://lists.nongnu.org/archive/html/qemu-ppc/2021-07/msg4.html
Fabiano Rosas (3):
target/ppc: Fix compilation with DUMP_PAGE_TABLES debug option
target/ppc: Fix compilation with
../target/ppc/mmu_helper.c: In function 'helper_store_ibatu':
../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1802 | PowerPCCPU *cpu = env_archcpu(env);
| ^~~
../target/ppc/mmu_helper.c: In function 'helper_store_dbatu':
Add an entry point for aqmp-tui. This will allow it to be run from
the command line using "aqmp-tui -a localhost:1234"
Signed-off-by: G S Niteesh Babu
---
python/setup.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/python/setup.cfg b/python/setup.cfg
index 4782fe5241..23e30185f4 100644
Added a draft of AQMP TUI.
Implements the follwing basic features:
1) Command transmission/reception.
2) Shows events asynchronously.
3) Shows server status in the bottom status bar.
Also added necessary pylint, mypy configurations
Signed-off-by: G S Niteesh Babu
---
Add syntax highlighting for the incoming and outgoing QMP messages.
This is achieved using the pygments module which was added in a
previous commit.
The current implementation is a really simple one which doesn't
allow for any configuration. In future this has to be improved
to allow for easier
Added dependencies for the upcoming AQMP TUI under the optional
'tui' group.
The same dependencies have also been added under the devel group
since no work around has been found for optional groups to imply
other optional groups.
Signed-off-by: G S Niteesh Babu
---
python/Pipfile.lock | 12
Added pygments as optional dependency for AQMP TUI.
This is required for the upcoming syntax highlighting feature
in AQMP TUI.
The dependency has also been added in the devel optional group.
Added mypy 'ignore_missing_imports' for pygments since it does
not have any type stubs.
Signed-off-by: G
GitLab: https://gitlab.com/niteesh.gs/qemu/-/commits/aqmp-tui-prototype-v1/
CI: https://gitlab.com/niteesh.gs/qemu/-/pipelines/330532044
Based-on: <20210701041313.1696009-1-js...@redhat.com>
[PATCH 00/20] python: introduce Asynchronous QMP package
This patch series introduces AQMP-TUI
Disable missing-docstring and fixme pylint warnings.
This is because since the AQMP is just a prototype
it is currently not documented properly and lot
of todo and fixme's are still in place.
Signed-off-by: G S Niteesh Babu
---
python/setup.cfg | 2 ++
1 file changed, 2 insertions(+)
diff
It's possible that requests start to wait each other in
mirror_wait_on_conflicts(). To avoid it let's use same technique as in
block/io.c in bdrv_wait_serialising_requests_locked() /
bdrv_find_conflicting_request(): don't wait on intersecting request if
it is already waiting for some other
This field is unused, but it very helpful for debugging.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/mirror.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/mirror.c b/block/mirror.c
index 019f6deaa5..ad6aac2f95 100644
--- a/block/mirror.c
+++ b/block/mirror.c
@@ -1343,6
Hi all!
We've faced a dead-lock in active mirror in our Rhev-8.4 based Qemu
build. And it's reproducible on master too.
Vladimir Sementsov-Ogievskiy (3):
block/mirror: set .co for active-write MirrorOp objects
iotest 151: add test-case that shows active mirror dead-lock
block/mirror: fix
There is a dead-lock in active mirror: when we have parallel
intersecting requests (note that non intersecting requests may be
considered intersecting after aligning to mirror granularity), it may
happen that request A waits request B in mirror_wait_on_conflicts() and
request B waits for A.
Look
On Fri, Jul 02, 2021 at 02:01:47PM +0200, Laurent Vivier wrote:
> Le 02/07/2021 à 12:34, Cornelia Huck a écrit :
> > On Wed, Jun 23 2021, Ilya Leoshkevich wrote:
> >
> >> qemu-s390x puts a wrong value into SIGILL's siginfo_t's psw.addr: it
> >> should be a pointer to the instruction following
On Fri, Jul 2, 2021 at 7:24 PM Ilya Dryomov wrote:
>
> This series migrates the qemu rbd driver from the old aio emulation
> to native coroutines and adds write zeroes support which is important
> for block operations.
>
> To achieve this we first bump the librbd requirement to the already
>
On 210702 1759, Philippe Mathieu-Daudé wrote:
> OSS-Fuzz found sending illegal addresses when querying the write
> protection bits triggers an assertion:
>
> qemu-fuzz-i386: hw/sd/sd.c:824: uint32_t sd_wpbits(SDState *, uint64_t):
> Assertion `wpnum < sd->wpgrps_size' failed.
> ==11578==
On 210702 1758, Philippe Mathieu-Daudé wrote:
> We report the card is in an inconsistent state, but don't precise
> in which state it is. Add this information, as it is useful when
> debugging problems.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Bin Meng
> Message-Id:
On Fri, Jul 02, 2021 at 10:43:22AM -0500, Michael Roth wrote:
> On Fri, Jul 02, 2021 at 01:14:56PM +0800, zhenwei pi wrote:
> > On 7/2/21 4:35 AM, Michael Roth wrote:
> > > Quoting Igor Mammedov (2021-07-01 03:43:13)
> > > > On Wed, 30 Jun 2021 14:18:09 -0500
> > > > Michael Roth wrote:
> > > >
On Wed, Jun 30, 2021 at 02:18:09PM -0500, Michael Roth wrote:
> Quoting Dr. David Alan Gilbert (2021-06-29 09:06:02)
> > * zhenwei pi (pizhen...@bytedance.com) wrote:
> > > A AMD server typically has cpuid level 0x10(test on Rome/Milan), it
> > > should not be changed to 0x1f in multi-dies case.
>
From: Peter Lieven
This patch wittingly sets BDRV_REQ_NO_FALLBACK and silently ignores
BDRV_REQ_MAY_UNMAP for older librbd versions.
The rationale for this is as follows (citing Ilya Dryomov current RBD
maintainer):
---8<---
a) remove the BDRV_REQ_MAY_UNMAP check in qemu_rbd_co_pwrite_zeroes()
From: Peter Lieven
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
---
block/rbd.c | 252 +++-
1 file changed, 90 insertions(+), 162 deletions(-)
diff --git a/block/rbd.c b/block/rbd.c
index e2028d3db5ff..380ad28861ad 100644
---
From: Peter Lieven
librbd supports 1 byte alignment for all aio operations.
Currently, there is no API call to query limits from the Ceph
ObjectStore backend. So drop the bdrv_refresh_limits completely
until there is such an API call.
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
From: Peter Lieven
Ceph Luminous (version 12.2.z) is almost 4 years old at this point.
Bump the requirement to get rid of the ifdef'ry in the code.
Qemu 6.1 dropped the support for RHEL-7 which was the last supported
OS that required an older librbd.
Signed-off-by: Peter Lieven
Reviewed-by:
From: Peter Lieven
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
---
block/rbd.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/block/rbd.c b/block/rbd.c
index b4b928bbb99f..1ebf8f7e4875 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -102,6
This series migrates the qemu rbd driver from the old aio emulation
to native coroutines and adds write zeroes support which is important
for block operations.
To achieve this we first bump the librbd requirement to the already
outdated luminous release of ceph to get rid of some wrappers and
From: Peter Lieven
While at it just call rbd_get_size and avoid rbd_image_info_t.
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
---
block/rbd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/block/rbd.c b/block/rbd.c
index 1ebf8f7e4875..e2028d3db5ff 100644
I'm writing a "fake" QMP server for the purposes of creating unit tests for
the python QMP library. In doing so, I am left with some esoteric questions:
(1) qemu-spec.txt, section 2.4.2, "error":
The format of an "error response" is:
> { "error": { "class": json-string, "desc": json-string },
On Mon, Jun 14, 2021 at 02:28:37PM -0600, Mathieu Poirier wrote:
> This sets adds a vhost-user based random number generator (RNG),
> similar to what has been done for i2c and virtiofsd, with the
> implementation following the patterns already set forth in those.
>
> Applies cleanly to
OSS-Fuzz found sending illegal addresses when querying the write
protection bits triggers an assertion:
qemu-fuzz-i386: hw/sd/sd.c:824: uint32_t sd_wpbits(SDState *, uint64_t):
Assertion `wpnum < sd->wpgrps_size' failed.
==11578== ERROR: libFuzzer: deadly signal
#8 0x7628e091 in
Multiple commands have to check the address requested is valid.
Extract this code pattern as a new address_in_range() helper, and
log invalid accesses as guest errors.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Message-Id: <20210624142209.1193073-3-f4...@amsat.org>
---
We report the card is in an inconsistent state, but don't precise
in which state it is. Add this information, as it is useful when
debugging problems.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Message-Id: <20210624142209.1193073-2-f4...@amsat.org>
---
hw/sd/sd.c | 3 ++-
1
Trivial fix for https://gitlab.com/qemu-project/qemu/-/issues/450
Missing review: patch #3
Philippe Mathieu-Daudé (3):
hw/sd: When card is in wrong state, log which state it is
hw/sd: Extract address_in_range() helper, log invalid accesses
hw/sd: Check for valid address range in
A couple of fixes for the commented-out debug options in mmu_helper.c
Fabiano Rosas (2):
target/ppc: Fix compilation with DUMP_PAGE_TABLES debug option
target/ppc: Fix compilation with FLUSH_ALL_TLBS debug option
target/ppc/mmu_helper.c | 10 +-
1 file changed, 1 insertion(+), 9
On Fri, Jul 02, 2021 at 07:50:03AM +0100, David Edmondson wrote:
> On Thursday, 2021-07-01 at 15:35:49 -05, Michael Roth wrote:
>
> > Quoting Igor Mammedov (2021-07-01 03:43:13)
> >> On Wed, 30 Jun 2021 14:18:09 -0500
> >> Michael Roth wrote:
> >>
> >> > Quoting Dr. David Alan Gilbert
On Fri, Jul 02, 2021 at 01:14:56PM +0800, zhenwei pi wrote:
> On 7/2/21 4:35 AM, Michael Roth wrote:
> > Quoting Igor Mammedov (2021-07-01 03:43:13)
> > > On Wed, 30 Jun 2021 14:18:09 -0500
> > > Michael Roth wrote:
> > >
> > > > Quoting Dr. David Alan Gilbert (2021-06-29 09:06:02)
> > > > > *
../target/ppc/mmu_helper.c: In function 'get_segment_6xx_tlb':
../target/ppc/mmu_helper.c:514:46: error: passing argument 1 of
'ppc_hash32_hpt_mask' from incompatible pointer type
[-Werror=incompatible-pointer-types]
514 | ppc_hash32_hpt_mask(env) + 0x80);
|
../target/ppc/mmu_helper.c: In function 'helper_store_ibatu':
../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1802 | PowerPCCPU *cpu = env_archcpu(env);
| ^~~
../target/ppc/mmu_helper.c: In function 'helper_store_dbatu':
On Fri, Jul 02, 2021 at 04:55:47PM +0200, Julia Suvorova wrote:
> > Doesn't this need to be protected by if (pm->use_acpi_hotplug_bridge)
> > ? Otherwise pm->acpi_pci_hotplug won't be initialized.
>
> Yes, you're right. Although it doesn't affect anything now, it should
> be fixed. I'll send a
On Fri, 2 Jul 2021, Philippe Mathieu-Daudé wrote:
When running the official PMON firmware for the Fuloong 2E, we see
8-bit and 16-bit accesses to PCI config space:
$ qemu-system-mips64el -M fuloong2e -bios pmon_2e.bin \
-trace -trace bonito\* -trace pci_cfg\*
pci_cfg_write vt82c686b-pm
On Fri, 02 Jul 2021 17:05:32 +0200
Christian Schoenebeck wrote:
> On Freitag, 2. Juli 2021 16:36:56 CEST Greg Kurz wrote:
> > On Fri, 4 Jun 2021 17:38:31 +0200
> >
> > Christian Schoenebeck wrote:
> > > As with previous performance optimization on Treaddir handling;
> > > reduce the overall
On 5/17/21 3:04 PM, Pavel Dovgalyuk wrote:
> virtio-net device uses bottom halves for callbacks.
> These callbacks should be deterministic, because they affect VM state.
> This patch replaces BH invocations with corresponding replay functions,
> making them deterministic in record/replay mode.
^
On Mon, May 17, 2021 at 04:04:20PM +0300, Pavel Dovgalyuk wrote:
> virtio-net device uses bottom halves for callbacks.
> These callbacks should be deterministic, because they affect VM state.
> This patch replaces BH invocations with corresponding replay functions,
> making them deterministic in
On Freitag, 2. Juli 2021 16:36:56 CEST Greg Kurz wrote:
> On Fri, 4 Jun 2021 17:38:31 +0200
>
> Christian Schoenebeck wrote:
> > As with previous performance optimization on Treaddir handling;
> > reduce the overall latency, i.e. overall time spent on processing
> > a Twalk request by reducing
On Thu, Jun 10, 2021 at 09:16:08AM -0400, Chris Browy wrote:
> From: hchkuo
>
> PCIe Data Object Exchange (DOE) implementation for QEMU referring to
> "PCIe Data Object Exchange ECN, March 12, 2020".
>
> The patch supports multiple DOE capabilities for a single PCIe device in
> QEMU. For each
> On 29 Jun 2021, at 12:50, Peter Maydell wrote:
>
> On Tue, 29 Jun 2021 at 11:41, Nick Hudson wrote:
>>
>>
>>
>>> On 29 Jun 2021, at 10:49, Peter Maydell wrote:
>>>
>>> On Tue, 29 Jun 2021 at 09:27, wrote:
Signed-off-by: Nick Hudson
---
target/arm/helper.c | 2 +-
> On 29 Jun 2021, at 12:50, Peter Maydell wrote:
>
> On Tue, 29 Jun 2021 at 11:41, Nick Hudson wrote:
>>
>>
>>
>>> On 29 Jun 2021, at 10:49, Peter Maydell wrote:
>>>
>>> On Tue, 29 Jun 2021 at 09:27, wrote:
Signed-off-by: Nick Hudson
---
target/arm/helper.c | 2 +-
On Thu, Jul 1, 2021 at 6:59 AM David Gibson wrote:
>
> On Thu, Jun 17, 2021 at 09:07:35PM +0200, Julia Suvorova wrote:
> > Add acpi_pcihp to ich9_pm as part of
> > 'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
> >
> > Signed-off-by: Julia Suvorova
> > Reviewed-by: Igor
On Wed, Jun 16, 2021 at 06:29:38PM +0200, David Hildenbrand wrote:
> Migration code now properly handles RAMBlocks which are indirectly managed
> by a RamDiscardManager. No need for manual handling via the free page
> optimization interface, let's get rid of it.
>
> Signed-off-by: David
On 6/1/21 5:40 AM, Philippe Mathieu-Daudé wrote:
> On 5/3/21 4:46 PM, Willian Rampazzo wrote:
>> On Mon, May 3, 2021 at 10:36 AM Philippe Mathieu-Daudé
>> wrote:
>>>
>>> On 5/3/21 3:12 PM, Willian Rampazzo wrote:
Hi Philippe,
On Mon, May 3, 2021 at 9:59 AM Philippe Mathieu-Daudé
On Fri, Jun 25, 2021 at 05:17:24AM -0400, Igor Mammedov wrote:
> Highlights:
> * drop pointer arithmetic in ACPI tables code
> * use endian agnostic API
> * simplifies review of tables. /in most cases just line by line comparision
> with spec/
A hue amount of work, thank you!
To make it
On 7/2/21 1:51 AM, Philippe Mathieu-Daudé wrote:
static bool trans_mul_d(DisasContext *ctx, int rd, int rj, int rk)
{
TCGv t0, t1;
check_loongarch_64(ctx);
if (a->rd == 0) {
/* Treat as NOP. */
return true;
}
t0 = tcg_temp_new();
t1 =
On Fri, Jun 25, 2021 at 05:17:28AM -0400, Igor Mammedov wrote:
> Set -smp 1,maxcpus=288 to test for ACPI code that
> deal with CPUs with large APIC ID (>255).
>
> PS:
> Test requires KVM and in-kernel irqchip support,
> so skip test if KVM is not available.
>
> Signed-off-by: Igor Mammedov
Why
On Fri, 4 Jun 2021 17:38:31 +0200
Christian Schoenebeck wrote:
> As with previous performance optimization on Treaddir handling;
> reduce the overall latency, i.e. overall time spent on processing
> a Twalk request by reducing the amount of thread hops between the
> 9p server's main thread and
On Thu, Jul 01, 2021 at 02:46:35PM +1000, David Gibson wrote:
> On Thu, Jun 17, 2021 at 09:07:35PM +0200, Julia Suvorova wrote:
> > Add acpi_pcihp to ich9_pm as part of
> > 'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
> >
> > Signed-off-by: Julia Suvorova
> > Reviewed-by:
On Thu, Jul 01, 2021 at 02:36:30PM +1000, David Gibson wrote:
> On Thu, Jun 17, 2021 at 09:07:34PM +0200, Julia Suvorova wrote:
> > Implement notifications and gpe to support q35 ACPI PCI hot-plug.
> > Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
> >
> > Signed-off-by: Julia Suvorova
On Wed, 30 Jun 2021 at 17:02, Kevin Wolf wrote:
>
> The following changes since commit 13d5f87cc3b94bfccc501142df4a7b12fee3a6e7:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-axp-20210628'
> into staging (2021-06-29 10:02:42 +0100)
>
> are available in the Git repository at:
>
From: Mark Cave-Ayland
The checksum used by MacOS to validate the PROM content is an exclusive-OR
rather than a sum over the corresponding bytes. In addition the MAC address
must be stored in bit-reversed format as indicated in comments in Linux's
macsonic.c.
With the PROM contents fixed MacOS
From: Mark Cave-Ayland
This will be required for an upcoming checksum calculation.
Signed-off-by: Mark Cave-Ayland
Tested-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210625065401.30170-7-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé
---
From: Mark Cave-Ayland
This is in preparation for each board to have its own separate bit storage
format and checksum for storing the MAC address.
Signed-off-by: Mark Cave-Ayland
Tested-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
Test the kernel from Lemote rescue image:
http://dev.lemote.com/files/resource/download/rescue/rescue-yl
Once downloaded, set the RESCUE_YL_PATH environment variable
to point to the downloaded image and test as:
$ RESCUE_YL_PATH=~/images/fuloong2e/rescue-yl \
AVOCADO_ALLOW_UNTRUSTED_CODE=1
When using the Magnum ARC firmware we can see accesses to the
UART1 being rejected, because the device is not mapped:
$ qemu-system-mips64el -M magnum -d guest_errors,unimp -bios NTPROM.RAW
Invalid access at addr 0x80007004, size 1, region '(null)', reason: rejected
Invalid access at addr
From: Mark Cave-Ayland
This is in preparation for each board to have its own separate bit storage
format and checksum for storing the MAC address.
Signed-off-by: Mark Cave-Ayland
Tested-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
When running the official PMON firmware for the Fuloong 2E, we see
8-bit and 16-bit accesses to PCI config space:
$ qemu-system-mips64el -M fuloong2e -bios pmon_2e.bin \
-trace -trace bonito\* -trace pci_cfg\*
pci_cfg_write vt82c686b-pm 05:4 @0x90 <- 0xeee1
bonito_spciconf_small_access
From: Mark Cave-Ayland
The MIPS magnum machines are available in both big endian (mips64) and little
endian (mips64el) configurations. Ensure that the dp893x big_endian property
is set accordingly using logic similar to that used for the MIPS malta
machines.
Signed-off-by: Mark Cave-Ayland
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Finn Thain
Message-Id: <20210625065401.30170-3-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c| 55
Per the datasheet section "5.7.5. Accessing PCI configuration space"
the address must be 32-bit aligned. Trace eventual accesses not
aligned to 32-bit.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210624202747.1433023-3-f4...@amsat.org>
---
hw/pci-host/bonito.c | 8
From: Mark Cave-Ayland
Since the migration stream is already broken, we can use this opportunity to
change the framebuffer so that it is migrated as a RAM memory region rather
than as an array of bytes.
In particular this helps the output of the analyze-migration.py tool which
no longer
From: Mark Cave-Ayland
According to the datasheet the dp8393x chipset does not contain any NVRAM
capable
of storing a MAC address or checksum. Now that both the MIPS jazz and m68k q800
boards generate the PROM region and checksum themselves, remove the generated
PROM from the dp8393x device
From: Mark Cave-Ayland
Also fix a simple comment typo of "constrainst" to "constraints".
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Finn Thain
Message-Id: <20210625065401.30170-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé
---
From: Mark Cave-Ayland
Currently when QEMU attempts to migrate the MIPS magnum machine it crashes due
to a mistake in the g364fb VMStateDescription configuration which expects a
G364SysBusState and not a G364State.
Resolve the issue by adding a new VMStateDescription for G364SysBusState and
Extract 1100+ lines from the huge translate.c to a new file,
'mips16e_translate.c.inc'. As there are too many inter-
dependencies we don't compile it as another object, but
keep including it in the big translate.o. We gain in code
maintainability.
Signed-off-by: Philippe Mathieu-Daudé
We want to extract the microMIPS ISA and Code Compaction ASE to
new compilation units.
We will first extract this code as included source files (.c.inc),
then make them new compilation units afterward.
The following methods are going to be used externally:
micromips_translate.c.inc:1778:
The following changes since commit 67e25eed977cb60e723b918207f0a3469baceef4:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210629' into
staging (2021-07-01 20:29:33 +0100)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20210702
Hello All,
I hope that everyone is doing well today.
Currently, I am working on a project that needs a good and stable VMM to
run a single VM at a time within a new hypervisor being designed that
will run on x86_64 hardware. (at least initially)
For this effort, I have been looking at various
On 6/25/21 6:35 PM, Mark Cave-Ayland wrote:
> I noticed whilst testing the previous dp8393x patchset that I would always
> get a segfault whilst attempting to migrate the MIPS magnum machine.
>
> A bit of detective work shows that the problem is an incorrect
> VMStateDescription
> in the g364fb
Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.
Like the long-shifts-by-immediate, these encodings sit in the
Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-15-peter.mayd...@linaro.org
Hi Mark,
On 6/25/21 8:53 AM, Mark Cave-Ayland wrote:
> Here is the next set of patches from my attempts to boot MacOS under QEMU's
> Q800 machine related to the Sonic network adapter.
>
> Patches 1 and 2 sort out checkpatch and convert from DPRINTF macros to
> trace-events.
>
> The discussion
> Am 02.07.2021 um 14:46 schrieb Ilya Dryomov :
>
> On Fri, Jul 2, 2021 at 11:09 AM Peter Lieven wrote:
>>
>> this series migrates the qemu rbd driver from the old aio emulation
>> to native coroutines and adds write zeroes support which is important
>> for block operations.
>>
>> To
Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-19-peter.mayd...@linaro.org
---
target/arm/helper-mve.h | 2 ++
target/arm/translate.h | 1 +
Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
do_urshr() is borrowed from sve_helper.c.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-12-peter.mayd...@linaro.org
---
target/arm/helper-mve.h| 10 ++
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.
The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
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