This provides standard look and feel for the about panel and reduces
code.
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 111 +++--
1 file changed, 23 insertions(+), 88 deletions(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 9f72844b079..68a6302184a 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -1888,12 +1888,12 @@ static void cocoa_clipboard_request(QemuClipboardInfo
From: Phillip Tennen
This patch implements a new netdev device, reachable via -netdev
vmnet-macos, that’s backed by macOS’s vmnet framework.
The vmnet framework provides native bridging support, and its usage in
this patch is intended as a replacement for attempts to use a tap device
via the
Hi,
My installation correctly shows the picture. Please make sure you
install it and run the installed binary (not the binary located in the
build directory). The new code should work reliably once you install
it while the old code may or may not work depending on how you execute
the binary.
On Jul 7 18:56, Klaus Jensen wrote:
On Jul 7 17:57, Hannes Reinecke wrote:
On 7/7/21 5:49 PM, Klaus Jensen wrote:
From: Klaus Jensen
Prior to this patch the nvme-ns devices are always children of the
NvmeBus owned by the NvmeCtrl. This causes the namespaces to be
unrealized when the parent
Quoting Eduardo Habkost (2021-07-02 12:35:34)
> On Fri, Jul 02, 2021 at 10:43:22AM -0500, Michael Roth wrote:
> > On Fri, Jul 02, 2021 at 01:14:56PM +0800, zhenwei pi wrote:
> > > On 7/2/21 4:35 AM, Michael Roth wrote:
> > > > Quoting Igor Mammedov (2021-07-01 03:43:13)
> > > > > On Wed, 30 Jun
On Tue, Jul 6, 2021 at 7:50 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This adds a new section in the documentation to demonstrate how to
> use the new direct kernel boot feature for Microchip Icicle Kit,
> other than the HSS bootflow, using an upstream U-Boot v2021.07 image
> as an example.
>
>
> For some reason, libpmem option setting was set to work in an opposite
> way (--enable-libpmem disabled it and vice versa). Fixing this so
> configuration works properly.
>
> Signed-off-by: Miroslav Rezanina
> ---
> configure | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff
On Tue, Jul 6, 2021 at 8:48 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present the CLINT timebase frequency is set to 10MHz on sifive_u,
> but on the real hardware the timebase frequency is 1Mhz.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
>
On Sun, Jun 27, 2021 at 06:27:13PM +0200, BALATON Zoltan wrote:
> Based-on: <20210625055155.2252896-1-...@ozlabs.ru>
> ^ That is v22 of Alexey's VOF patch
>
> With this series on top of VOF v22 I can now boot Linux and MorphOS on
> pegasos2 without a firmware blob so I hope this is enough to get
On Thu, Jun 24, 2021 at 11:48 PM Jose Martins wrote:
>
> > > +static const target_ulong vs_delegable_excps = delegable_excps &
> > > +~((1ULL << (RISCV_EXCP_S_ECALL)) |
> >
> > > +(1ULL << (RISCV_EXCP_VS_ECALL)) |
> > > +(1ULL << (RISCV_EXCP_M_ECALL)) |
> >
> > These two are both read
On Thu, Jul 08, 2021 at 01:15:10PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 08/07/2021 12:40, David Gibson wrote:
> > On Fri, Jun 25, 2021 at 03:51:55PM +1000, Alexey Kardashevskiy wrote:
[snip]
> > > +void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt)
> > > +{
> > > +
On Sun, Jun 27, 2021 at 06:27:13PM +0200, BALATON Zoltan wrote:
> Linux uses RTAS functions to access PCI devices so we need to provide
> these with VOF. Implement some of the most important functions to
> allow booting Linux with VOF. With this the board is now usable
> without a binary ROM image
[Expired for QEMU because there has been no activity for 60 days.]
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Status: Incomplete => Expired
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Title:
ARM:
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Title:
Meson:
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** Changed in: qemu
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Title:
qmp/hmp:
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Title:
qemu 5.1
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curl and
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Title:
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Title:
Aten USB
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Title:
Crash when
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Title:
Second
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Cannot
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High
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qemu-i386
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qemu git
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qemu on
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Title:
COLO's
On Thu, Jul 08, 2021 at 09:22:48AM +0800, Bin Meng wrote:
> Hi David,
>
> On Thu, Jul 8, 2021 at 9:08 AM David Gibson
> wrote:
> >
> > On Tue, Jul 06, 2021 at 12:31:24PM +0800, Bin Meng wrote:
> > > This adds eTSEC support to the PowerPC `ppce500` machine documentation.
> > >
> > >
On Sun, Jun 27, 2021 at 06:27:13PM +0200, BALATON Zoltan wrote:
> Change the assert in ppc_store_sdr1() to allow vhyp to be set on CPUs
> without HV bit. This allows using the vhyp interface for firmware
> emulation on pegasos2.
>
> Signed-off-by: BALATON Zoltan
Kind of a hack, but a simple
On Tue, Jul 06, 2021 at 03:13:21PM +1000, Nicholas Piggin wrote:
> MSR is a 32-bit register in BookE and there is no mtmsrd instruction.
>
> Cc: Christian Zigotzky
> Signed-off-by: Nicholas Piggin
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 5 +
> 1 file changed, 5
On Tue, Jun 15, 2021 at 02:41:07PM +1000, Nicholas Piggin wrote:
> There are several new L1D cache flush bits added to the hcall which reflect
> hardware security features for speculative cache access issues.
>
> These behaviours are now being specified as negative in order to simplify
> patched
On Sun, Jun 27, 2021 at 06:27:13PM +0200, BALATON Zoltan wrote:
> Add own machine state structure which will be used to store state
> needed for firmware emulation.
>
> Signed-off-by: BALATON Zoltan
> Reviewed-by: Philippe Mathieu-Daudé
Applied to ppc-for-6.1.
> ---
> hw/ppc/pegasos2.c | 50
On Wed, Jun 30, 2021 at 5:00 PM Willian Rampazzo
wrote:
> On Wed, Jun 30, 2021 at 3:46 PM Wainer dos Santos Moschetta
> wrote:
> >
> > Currently tox tests against the installed interpreters, however if any
> > supported interpreter is absent then it will return fail. It seems not
> > reasonable
On Fri, Jul 2, 2021 at 5:26 PM G S Niteesh Babu
wrote:
> Added a draft of AQMP TUI.
>
> Implements the follwing basic features:
> 1) Command transmission/reception.
> 2) Shows events asynchronously.
> 3) Shows server status in the bottom status bar.
>
> Also added necessary pylint, mypy
On 08/07/2021 12:40, David Gibson wrote:
On Fri, Jun 25, 2021 at 03:51:55PM +1000, Alexey Kardashevskiy wrote:
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration between the firmware
If the device backend is not persistent memory for the nvdimm, there is
need for explicit IO flushes on the backend to ensure persistence.
On SPAPR, the issue is addressed by adding a new hcall to request for
an explicit flush from the guest when the backend is not pmem. So, the
approach here is
On 210629 2341, Alexander Bulekov wrote:
> By default, -fsanitize=fuzzer instruments all code with coverage
> information. However, this means that libfuzzer will track coverage over
> hundreds of source files that are unrelated to virtual-devices. This
> means that libfuzzer will optimize inputs
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch.
The hcall expects the semantics such that the flush to return
with one of H_LONG_BUSY when the operation is expected to take longer
time along with a
If the device backend is not persistent memory for the nvdimm, there
is need for explicit IO flushes to ensure persistence.
On SPAPR, the issue is addressed by adding a new hcall to request for
an explicit flush from the guest when the backend is not pmem.
So, the approach here is to convey when
On Thursday, July 8, 2021 12:55 AM, Peter Xu wrote:
> On Wed, Jul 07, 2021 at 08:34:50AM +, Wang, Wei W wrote:
> > On Wednesday, July 7, 2021 1:47 AM, Peter Xu wrote:
> > > On Sat, Jul 03, 2021 at 02:53:27AM +, Wang, Wei W wrote:
> > > > + do {
> > > > +page_to_clear =
On Thursday, July 8, 2021 12:44 AM, Peter Xu wrote:
> > > Not to mention the hard migration issues are mostly with non-idle
> > > guest, in that case having the balloon in the guest will be
> > > disastrous from this pov since it'll start to take mutex for each
> > > page, while balloon would
On Fri, Jun 25, 2021 at 03:51:55PM +1000, Alexey Kardashevskiy wrote:
> The PAPR platform describes an OS environment that's presented by
> a combination of a hypervisor and firmware. The features it specifies
> require collaboration between the firmware and the hypervisor.
>
> Since the
În mie., 7 iul. 2021 la 10:32, Paolo Bonzini a scris:
> On 07/07/21 05:24, Richard Zak wrote:
> > What conditions are required for "#define CONFIG_PIPE2" to be set in
> > build/config-host.h? It prevents building for Haiku as pipe2() doesn't
> > exist. I didn't see anything in the configure
Hello!
Thanks for applying fixes for me. Is there anything else I should do?
Ziqiao
On Thu, Jul 8, 2021 at 6:24 AM Richard Henderson
wrote:
>
> From: Ziqiao Kong
>
> Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8.
> Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not
On Fri, Jul 2, 2021 at 5:26 PM G S Niteesh Babu
wrote:
> Add an entry point for aqmp-tui. This will allow it to be run from
> the command line using "aqmp-tui -a localhost:1234"
>
> Signed-off-by: G S Niteesh Babu
> ---
> python/setup.cfg | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Fri, Jul 2, 2021 at 5:26 PM G S Niteesh Babu
wrote:
> Added dependencies for the upcoming AQMP TUI under the optional
> 'tui' group.
>
> The same dependencies have also been added under the devel group
> since no work around has been found for optional groups to imply
> other optional groups.
Enhance the test to demonstrate behavior of qemu-img with a qcow2
image containing an inconsistent bitmap, and rename it now that we
support useful iotest names.
While at it, fix a missing newline in the error message thus exposed.
Signed-off-by: Eric Blake
---
block/dirty-bitmap.c
This is mostly a convenience factor as one could already use 'qemu-img
info' to learn which bitmaps are broken and then 'qemu-img bitmap
--remove' to nuke them before calling 'qemu-img convert --bitmaps',
but it does have the advantage that the copied file is usable without
extra efforts and the
The point of 'qemu-img convert --bitmaps' is to be a convenience for
actions that are already possible through a string of smaller
'qemu-img bitmap' sub-commands. One situation not accounted for
already is that if a source image contains an inconsistent bitmap (for
example, because a qemu process
Hi David,
On Thu, Jul 8, 2021 at 9:08 AM David Gibson wrote:
>
> On Tue, Jul 06, 2021 at 12:31:24PM +0800, Bin Meng wrote:
> > This adds eTSEC support to the PowerPC `ppce500` machine documentation.
> >
> > Signed-off-by: Bin Meng
>
> Applied to ppc-for-6.1, thanks.
Thanks!
Are both 2 patches
On 7/6/21 9:17 AM, Eric Auger wrote:
From: Willian Rampazzo
When running LinuxTests we may need to run the guest with
custom params. It is practical to store the pxeboot URL
and the default kernel params so that the
tests just need to fetch those and augment the kernel params.
From: Isaku Yamahata
In mch_realize(), process PAM initialization before SMRAM initialization so
that later patch can skill all the SMRAM related with a single check.
Signed-off-by: Isaku Yamahata
---
hw/pci-host/q35.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
On 7/6/21 9:17 AM, Eric Auger wrote:
From: Willian Rampazzo
As the KNOWN_DISTROS grows, more loosely methods will be created in
the avocado_qemu/__init__.py file.
Let's refactor the code so that KNOWN_DISTROS and related methods are
packaged in a class
Signed-off-by: Wainer dos Santos
From: Isaku Yamahata
Specify the initial value for RCX/R8 to be the address of the HOB.
Don't propagate the value to Qemu's cache of the registers so as to
avoid implying that the register state is valid, e.g. Qemu doesn't model
TDX-SEAM behavior for initializing other GPRs.
Signed-off-by:
On Tue, Jul 06, 2021 at 12:31:24PM +0800, Bin Meng wrote:
> This adds eTSEC support to the PowerPC `ppce500` machine documentation.
>
> Signed-off-by: Bin Meng
Applied to ppc-for-6.1, thanks.
> ---
>
> docs/system/ppc/ppce500.rst | 10 +-
> 1 file changed, 9 insertions(+), 1
From: Isaku Yamahata
TDX doesn't allow level interrupt and SMI/INIT/SIPI interrupt delivery
mode. So disallow them.
Signed-off-by: Isaku Yamahata
---
hw/i386/x86.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 24af05c313..c372403b87 100644
---
On Tue, Jul 06, 2021 at 09:33:11PM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> This new version is rebased with current master (9aef0954195cc),
> hopefully an adequate format of patch 1, and David's R-b on all
> patches.
Markus do you want to take this, or will you ack and I'll take it
From: Sean Christopherson
TDX requires x2apic and "resets" vCPUs to have x2apic enabled. Model
this in QEMU and unconditionally enable x2apic interrupt routing.
This fixes issues where interrupts from IRQFD would not get forwarded to
the guest due to KVM silently dropping the invalid routing
From: Isaku Yamahata
Add a new flag to X86Machine to disallow INIT/SIPI delivery mode of
interrupt and pass it to ioapic creation so that ioapic disallows INIT/SIPI
delivery mode.
Signed-off-by: Isaku Yamahata
---
hw/i386/microvm.c | 4 ++--
hw/i386/pc_piix.c | 2 +-
From: Isaku Yamahata
Add a q35 property to check whether or not SMM ranges, e.g. SMRAM, TSEG,
etc... exist for the target platform. TDX doesn't support SMM and doesn't
play nice with QEMU modifying related guest memory ranges.
Signed-off-by: Isaku Yamahata
Co-developed-by: Sean Christopherson
From: Sean Christopherson
Process PCIe BAR before PAM so that a future patch can skip all the SMM
related crud with a single check-and-return.
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku Yamahata
---
hw/pci-host/q35.c | 10 +-
1 file changed, 5 insertions(+), 5
From: Isaku Yamahata
Despite advertising MCE support to the guest, TDX-SEAM doesn't support
injecting #MCs into the guest. All of the associated setup is thus
rejected by KVM.
Signed-off-by: Isaku Yamahata
---
target/i386/kvm/kvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
From: Isaku Yamahata
Build the TD HOB during machine late initialization, i.e. once guest
memory is fully defined.
Signed-off-by: Isaku Yamahata
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
---
hw/i386/meson.build | 2 +-
hw/i386/tdvf-hob.c| 166
From: Sean Christopherson
Add MMIO HOB entries, which are needed to enumerate legal MMIO ranges to
early TDVF.
Note, the attribute absolutely must include UNCACHEABLE, else TDVF will
effectively consider it a bad HOB entry and ignore it.
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku
From: Isaku Yamahata
Add, and optionally measure, TDVF memory via KVM_TDX_INIT_MEM_REGION as
part of finalizing the TD.
Signed-off-by: Isaku Yamahata
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
---
target/i386/kvm/tdx.c | 17 -
1 file changed, 16
From: Isaku Yamahata
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku Yamahata
---
include/sysemu/tdx.h | 1 +
target/i386/kvm/kvm.c | 8
target/i386/kvm/tdx-stub.c | 4
target/i386/kvm/tdx.c | 20
4 files changed, 29 insertions(+),
From: Isaku Yamahata
Add a property to prevent ioapic from setting INIT/SIPI delivery mode.
Without this guard, qemu can result in unexpected behavior.
Signed-off-by: Isaku Yamahata
---
hw/intc/ioapic.c | 19 +++
hw/intc/ioapic_common.c | 21
From: Isaku Yamahata
Add support for loading TDX's Trusted Domain Virtual Firmware (TDVF) via
the generic loader. Prioritize the TDVF above plain hex to avoid false
positives with hex (TDVF has explicit metadata to confirm it's a TDVF).
Enumerate TempMem as added, private memory, i.e.
From: Isaku Yamahata
Disable S3/S4 unconditionally when TDX is enabled. Because cpu state is
protected, it's not allowed to reset cpu state. So S3/S4 can't be
supported.
Signed-off-by: Isaku Yamahata
---
target/i386/kvm/tdx.c | 20
1 file changed, 20 insertions(+)
diff
From: Isaku Yamahata
Add a property to prevent ioapic from setting SMI delivery mode. Without
this guard, qemu can result in unexpected behavior.
Signed-off-by: Isaku Yamahata
---
hw/intc/ioapic.c | 18 ++
hw/intc/ioapic_common.c | 20
From: Isaku Yamahata
Introduce a new notifier, machine_init_done_late, that is notified after
machine_init_done. This will be used by TDX to generate the HOB for its
virtual firmware, which needs to be done after all guest memory has been
added, i.e. after machine_init_done notifiers have run.
From: Isaku Yamahata
The following patch will utilize this refactoring.
Signed-off-by: Isaku Yamahata
---
hw/i386/e820_memory_layout.c | 42
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/hw/i386/e820_memory_layout.c
From: Isaku Yamahata
Add a new flag to X86Machine to disallow SMI and pass it to ioapic creation
so that ioapic disallows delivery mode of SMI.
Signed-off-by: Isaku Yamahata
---
hw/i386/microvm.c | 6 --
hw/i386/pc_piix.c | 3 ++-
hw/i386/pc_q35.c | 3 ++-
hw/i386/x86.c
From: Sean Christopherson
Add support for grabbing KVM_TDX_CAPABILITIES and use the new
kvm_get_supported_cpuid() hook to adjust the supported XCR0 bits.
Add TODOs for the remaining work.
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku Yamahata
---
target/i386/kvm/kvm.c | 2 ++
From: Isaku Yamahata
Introduce a helper function, e820_change_type(), that change
the type of subregion of e820 entry.
The following patch uses it.
Signed-off-by: Isaku Yamahata
---
hw/i386/e820_memory_layout.c | 72
hw/i386/e820_memory_layout.h | 1 +
2
From: Isaku Yamahata
When level trigger isn't supported on x86 platform, forcibly report edge
trigger in acpi tables.
Signed-off-by: Isaku Yamahata
---
hw/i386/acpi-build.c | 103 --
hw/i386/acpi-common.c | 74 ++
2 files
From: Isaku Yamahata
In TDX CPU state is also protected, thus vcpu state can't be reset by VMM.
It assumes -action reboot=shutdown instead of silently ignoring vcpu reset.
TDX module spec version 344425-002US doesn't support vcpu reset by VMM. VM
needs to be destroyed and created again to
From: Isaku Yamahata
Add constants and structs for the TD Virtual Firmware metadata, which
describes how the TDVF must be built to ensure correct functionality and
measurement. They are defined in TDVF Design Guide [1].
[1] TDVF Design Guide
From: Sean Christopherson
Ignore get/put state of TDX VMs as accessing/mutating guest state of
producation TDs is not supported.
Allow kvm_arch_get_registers() to run as normal, except for MSRs, for
debug TDs, and silently ignores attempts to read guest state for
non-debug TDs.
Signed-off-by:
From: Sean Christopherson
Add a hook for TDX to denote that the TD Virtual Firmware must be
provided via the "generic" device loader. Error out if pflash is used
in conjuction with TDX.
Suggested-by: Isaku Yamahata
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku Yamahata
---
From: Isaku Yamahata
When x86machine doesn't support eoi intercept, set
level_trigger_unsupported property of ioapic to true so that ioapic doesn't
accept configuration to use level trigger.
Signed-off-by: Isaku Yamahata
---
hw/i386/microvm.c | 5 +++--
hw/i386/pc_piix.c | 2 +-
From: Isaku Yamahata
Signed-off-by: Isaku Yamahata
---
include/sysemu/tdx.h | 1 +
target/i386/kvm/kvm.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h
index 70eb01348f..f3eced10f9 100644
--- a/include/sysemu/tdx.h
+++
From: Isaku Yamahata
Add a new bool member, eoi_intercept_unsupported, to X86MachineState with
default value false. Set true when tdx kvm type. Inability to intercept
eoi causes impossibility to emulate level triggered interrupt to be
re-injected when level is still kept active. which affects
From: Isaku Yamahata
Add definitions for literals, enums, structs, GUIDs, etc... that will be
used by TDX to build the UEFI Hand-Off Block (HOB) that is passed to the
Trusted Domain Virtual Firmware (TDVF). All values come from the UEFI
specification and TDVF design guide. [1]
Note:
From: Isaku Yamahata
According to TDX module spec version 344425-002US [1], VMM can inject
virtual interrupt only via posted interrupt and VMM can't get TDEXIT on
guest EOI to virtual x2APIC. Because posted interrupt is edge-trigger and
VMM needs to hook guest EOI to re-inject level-triggered
From: Isaku Yamahata
When creating VM with TDX_INIT_VM, three sha384 hash values are accepted
for TDX attestation.
So far they were hard coded as 0. Now allow user to specify those values
via property mrconfigid, mrowner and mrownerconfig.
string for those property are hex string of 48 * 2
From: Chenyi Qiang
Add QMP commands that can be used by libvirt to query the TDX capabilities
and TDX info. The set of capabilities that needs to be reported is only
enabled at the moment, which means TDX is enabled.
Signed-off-by: Chenyi Qiang
Co-developed-by: Isaku Yamahata
Signed-off-by:
From: Xiaoyao Li
Pull in recent TDX updates, which are not backwards compatible.
Signed-off-by: Xiaoyao Li
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku Yamahata
---
linux-headers/asm-x86/kvm.h | 60 +
From: Xiaoyao Li
Invoke KVM_TDX_FINALIZEMR to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.
Signed-off-by: Xiaoyao Li
Signed-off-by: Isaku Yamahata
---
target/i386/kvm/kvm.c | 7 +++
target/i386/kvm/tdx.c | 21 +
From: Xiaoyao Li
Introduce tdx_ioctl() to invoke TDX specific sub-ioctls of
KVM_MEMORY_ENCRYPT_OP. Use tdx_ioctl() to invoke KVM_TDX_INIT, by way
of tdx_init(), during kvm_arch_init(). KVM_TDX_INIT configures global
TD state, e.g. the canonical CPUID config, and must be executed prior to
From: Xiaoyao Li
Reuse -cpu,tsc-frequency= to get user wanted tsc frequency and pass it
to KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by SEAM module).
Signed-off-by: Xiaoyao Li
Signed-off-by: Isaku Yamahata
---
From: Sean Christopherson
Expose x86_cpu_get_supported_feature_word() outside of cpu.c so that it
can be used by TDX to setup the VM-wide CPUID configuration.
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku Yamahata
---
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 3 +++
2 files
From: Sean Christopherson
Add a machine option to disable the legacy PIC (8259), which cannot be
supported for TDX guests as TDX-SEAM doesn't allow directly interrupt
injection. Using posted interrupts for the PIC is not a viable option
as the guest BIOS/kernel will not do EOI for PIC IRQs,
From: Xiaoyao Li
Introduce a machine property, kvm-type, to allow the user to create a
Trusted Domain eXtensions (TDX) VM, a.k.a. a Trusted Domain (TD), e.g.:
# $QEMU \
-machine ...,kvm-type=tdx \
...
Only two types are supported: "legacy" and "tdx", with "legacy" being
the
From: Isaku Yamahata
Implement property_add_sha384() which converts hex string <-> uint8_t[48]
It will be used for TDX which uses sha384 for measurement.
Signed-off-by: Isaku Yamahata
---
include/qom/object.h | 17 ++
qom/object.c | 76
From: Sean Christopherson
Move the architectural (for lack of a better term) CPUID leaf generation
to a separate helper so that the generation code can be reused by TDX,
which needs to generate a canonical VM-scoped configuration.
Signed-off-by: Sean Christopherson
Signed-off-by: Isaku
From: Isaku Yamahata
This patch series is to enable TDX support. This needs corresponding KVM patch
for TDX [1]. The patch [1] requires more patches to be function. So this patch
series is RFC. For those who want to try github repo is available at [2].
Patch series is organized as follows.
From: Isaku Yamahata
Make kvm_synchronize_all_tsc() nop for TD-guest.
TDX module specification, 9.11.1 TSC Virtualization
"Virtual TSC values are consistent among all the TD;s VCPUs at the
level suppored by the CPU".
There is no need for qemu to synchronize tsc and VMM can't access
to guest
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