On Fri, Jul 9, 2021 at 2:36 PM Richard Henderson
wrote:
>
> Replace uses of tcg_const_* with the allocate and free close together.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c| 36 --
>
While some of the critical fields remain the same, there is variation in
the definition of the control register across the SoC generations.
Reserved regions are adjusted, while in other cases the mutability or
behaviour of fields change.
Introduce a callback to sanitize the value on writes to
> -Original Message-
> From: Jason Wang
> Sent: Friday, July 9, 2021 11:53 AM
> To: Zhang, Chen
> Cc: Lukas Straub ; Daniel P. Berrangé
> ; Li Zhijian ; qemu-dev
> ; Markus Armbruster ;
> Gerd Hoffmann ; Eric Blake ; Dr.
> David Alan Gilbert
> Subject: Re: [PULL V2 1/6] qapi/net: Add
On Fri, Jul 9, 2021 at 2:42 PM Richard Henderson
wrote:
>
> New helpers that do not force tcg globals into temps,
> returning a constant 0 for $zero as source and a new
> temp for $zero as destination.
>
> Use them in gen_arith_imm_{fn,tl}, gen_arith, gen_unary.
> These are simplest because no
在 2021/7/6 下午3:20, Cindy Lu 写道:
Add configure interrupt support for virtio-mmio bus. This
interrupt will working while backend is vhost-vdpa
Signed-off-by: Cindy Lu
---
hw/virtio/virtio-mmio.c | 26 ++
1 file changed, 26 insertions(+)
diff --git
在 2021/7/6 下午3:20, Cindy Lu 写道:
use the virtio_pci_get_notifier function to
get the notifer, the input of the function
will is the idx, the output is notifier and
vector
You need to describe why such decoupling is needed.
Signed-off-by: Cindy Lu
I think we need move this patch as
From: Alexey Kardashevskiy
This addresses the comments from v22.
The functional changes are (the VOF ones need retesting with Pegasos2):
(VOF) setprop will start failing if the machine class callback
did not handle it;
(VOF) unit addresses are lowered in path_offset();
(SPAPR) /chosen/bootargs
在 2021/7/6 下午3:20, Cindy Lu 写道:
Add configure notifier support in vhost and virtio driver
When backend support VIRTIO_NET_F_STATUS,setup the configure
interrupt function in vhost_net_start and release the related
resource when vhost_net_stop
Signed-off-by: Cindy Lu
---
hw/net/vhost_net.c
在 2021/7/6 下午3:20, Cindy Lu 写道:
Add new call back function in vhost-vdpa, this call back function only
supported in vhost-vdpa backend
Signed-off-by: Cindy Lu
Acked-by: Jason Wang
---
hw/virtio/trace-events | 2 ++
hw/virtio/vhost-vdpa.c | 7 +++
2 files changed, 9
Fixes: d5015b801340 ("softmmu/memory: Pass ram_flags to
qemu_ram_alloc_from_fd()")
Signed-off-by: Yang Zhong
Reviewed-by: David Hildenbrand
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pankaj Gupta
Reviewed-by: Peter Xu
---
hw/remote/memory.c | 2 +-
1 file changed, 1 insertion(+), 1
在 2021/7/6 下午3:20, Cindy Lu 写道:
Decouple virtqueue from interrupt setting process to support config interrupt
Now the code for interrupt/vector are coupling
with the vq number, this patch will decouple the vritqueue
numbers from these functions
Signed-off-by: Cindy Lu
---
From: BALATON Zoltan
Linux uses RTAS functions to access PCI devices so we need to provide
these with VOF. Implement some of the most important functions to
allow booting Linux with VOF. With this the board is now usable
without a binary ROM image and we can enable it by default as other
boards.
The logic in the handling for the control register required toggling the
enable state for writes to stick. Rework the condition chain to allow
sequential writes that do not update the enable state.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery
---
From: Nicholas Piggin
There are several new L1D cache flush bits added to the hcall which reflect
hardware security features for speculative cache access issues.
These behaviours are now being specified as negative in order to simplify
patched kernel compatibility with older firmware (a new
From: BALATON Zoltan
The pegasos2 board comes with an Open Firmware compliant ROM based on
SmartFirmware but it has some changes that are not open source
therefore the ROM binary cannot be included in QEMU. Guests running on
the board however depend on services provided by the firmware. The
Hello,
I discovered a couple of bugs in the watchdog while testing a tool to poke
Aspeed BMCs over their various AHB bridges. The immediate observation was that
the model for the 2500 wasn't signalling use of the fixed 1MHz clock, which is
resolved in the first patch. The other observation was
From: Bharata B Rao
Update to mainline commit: 79160a603bdb ("Merge tag 'usb-5.14-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb"
Signed-off-by: Bharata B Rao
Message-Id: <20210706112440.1449562-2-bhar...@linux.ibm.com>
Signed-off-by: David Gibson
---
From: "Bruno Larsen (billionai)"
Changed hash32 address translation to use the supplied mmu_idx, instead
of using what was stored in the msr, for parity purposes (radix64
already uses that) and for conceptual correctness, all the relevant
functions should always use the supplied mmu_idx, as
在 2021/7/6 下午3:20, Cindy Lu 写道:
To support configure interrupt, we need to
add a new call back function for config interrupt.
Signed-off-by: Cindy Lu
Acked-by: Jason Wang
---
include/hw/virtio/vhost-backend.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
This is obviously intended to be a mask, not a logical operation.
Signed-off-by: David Gibson
---
hw/ppc/pegasos2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index f1741a4512..cf1dc53c83 100644
--- a/hw/ppc/pegasos2.c
+++
From: Bharata B Rao
If KVM_CAP_RPT_INVALIDATE KVM capability is enabled, then
- indicate the availability of H_RPT_INVALIDATE hcall to the guest via
ibm,hypertas-functions property.
- Enable the hcall
Both the above are done only if the new sPAPR machine capability
cap-rpt-invalidate is set.
From: BALATON Zoltan
Add own machine state structure which will be used to store state
needed for firmware emulation.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<7f6d5fbf4f70c64dba001483174a2921dd616ecd.1624811233.git.bala...@eik.bme.hu>
Signed-off-by:
From: Fabiano Rosas
../target/ppc/mmu_helper.c: In function 'helper_store_ibatu':
../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1802 | PowerPCCPU *cpu = env_archcpu(env);
| ^~~
../target/ppc/mmu_helper.c: In function
From: Nicholas Piggin
MSR is a 32-bit register in BookE and there is no mtmsrd instruction.
Cc: Christian Zigotzky
Signed-off-by: Nicholas Piggin
Message-Id: <20210706051321.609046-1-npig...@gmail.com>
Signed-off-by: David Gibson
---
target/ppc/translate.c | 5 +
1 file changed, 5
From: "Lucas Mateus Castro (alqotel)"
The function ppc_tlb_invalid_all is not compiled anymore in a TCG-less
environment, and the call to that function has been disabled in this
situation
Signed-off-by: Lucas Mateus Castro (alqotel)
Message-Id:
From: Fabiano Rosas
../target/ppc/mmu_helper.c: In function 'get_segment_6xx_tlb':
../target/ppc/mmu_helper.c:514:46: error: passing argument 1 of
'ppc_hash32_hpt_mask' from incompatible pointer type
[-Werror=incompatible-pointer-types]
514 | ppc_hash32_hpt_mask(env)
From: Alexey Kardashevskiy
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration between the firmware and the hypervisor.
Since the beginning, the runtime component of the firmware (RTAS) has
From: BALATON Zoltan
Change the assert in ppc_store_sdr1() to allow vhyp to be set on CPUs
without HV bit. This allows using the vhyp interface for firmware
emulation on pegasos2.
Signed-off-by: BALATON Zoltan
Message-Id:
From: "Bruno Larsen (billionai)"
Changed hash64 address translation to use the supplied mmu_idx instead
of using the one stored in the msr, for parity purposes (other book3s
MMUs already use it).
Signed-off-by: Bruno Larsen (billionai)
Reviewed-by: Richard Henderson
Message-Id:
From: Richard Henderson
This function is used by TCGCPUOps, and is thus TCG specific.
Signed-off-by: Richard Henderson
Message-Id: <20210621125115.67717-10-bruno.lar...@eldorado.org.br>
Signed-off-by: David Gibson
---
target/ppc/mmu_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff
From: "Bruno Larsen (billionai)"
Intrudoce a header common to all BookS MMUs, that can hold code that is
common to hash32 and book3s-v3 MMUs.
Suggested-by: David Gibson
Signed-off-by: Bruno Larsen (billionai)
Message-Id: <20210706150316.21005-2-bruno.lar...@eldorado.org.br>
Signed-off-by:
From: "Bruno Larsen (billionai)"
This commit attempts to fix a technical hiccup first mentioned by Richard
Henderson in
https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html
To sumarize the hiccup here, when radix-style mmus are translating an
address, they might need to call a
From: Richard Henderson
Create one common dispatch for all of the ppc_*_xlate functions.
Use ppc64_v3_radix to directly dispatch between ppc_radix64_xlate
and ppc_hash64_xlate.
Remove the separate *_handle_mmu_fault and *_get_phys_page_debug
functions, using common code for ppc_cpu_tlb_fill and
From: Richard Henderson
Mirror the interface of ppc_radix64_xlate, putting all of
the logic for hash64 translation into a single function.
Signed-off-by: Richard Henderson
Message-Id: <20210621125115.67717-6-bruno.lar...@eldorado.org.br>
Signed-off-by: David Gibson
---
From: Bin Meng
This adds eTSEC support to the PowerPC `ppce500` machine documentation.
Signed-off-by: Bin Meng
Signed-off-by: David Gibson
---
docs/system/ppc/ppce500.rst | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/docs/system/ppc/ppce500.rst
From: Fabiano Rosas
../target/ppc/mmu-hash32.c: In function 'ppc_hash32_bat_lookup':
../target/ppc/mmu-hash32.c:204:13: error: 'BATu' undeclared (first use in this
function);
204 | BATu = [i];
| ^~~~
| BATut
../target/ppc/mmu-hash32.c:205:13:
From: Richard Henderson
Instead of returning non-zero for failure, return true for success.
Signed-off-by: Richard Henderson
Message-Id: <20210621125115.67717-5-bruno.lar...@eldorado.org.br>
Signed-off-by: David Gibson
---
target/ppc/mmu-radix64.c | 30 +++---
1 file
From: Richard Henderson
Mirror the interface of ppc_radix64_xlate, putting all of
the logic for hash32 translation into a single entry point.
Signed-off-by: Richard Henderson
Message-Id: <20210621125115.67717-7-bruno.lar...@eldorado.org.br>
Signed-off-by: David Gibson
---
From: Richard Henderson
This removes some incomplete duplication between
ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug.
The former was correct wrt SPR_HRMOR and the latter was not.
Signed-off-by: Richard Henderson
Message-Id:
From: Richard Henderson
Mirror the interface of ppc_radix64_xlate (mostly), putting all
of the logic for older mmu translation into a single entry point.
For booke, we need to add mmu_idx to the xlate-style interface.
Signed-off-by: Richard Henderson
Message-Id:
From: Alexey Kardashevskiy
QEMU reserves space for RTAS via /rtas/rtas-size which tells the client
how much space the RTAS requires to work which includes the RTAS binary
blob implementing RTAS runtime. Because pseries supports FWNMI which
requires plenty of space, QEMU reserves more than 2KB
From: Richard Henderson
These changes were waiting until we didn't need to match
the function type of PowerPCCPUClass.handle_mmu_fault.
Signed-off-by: Richard Henderson
Message-Id: <20210621125115.67717-3-bruno.lar...@eldorado.org.br>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
From: Greg Kurz
This isn't used anymore.
Signed-off-by: Greg Kurz
Message-Id: <20210622140926.677618-3-gr...@kaod.org>
Reviewed-by: Fabiano Rosas
Signed-off-by: David Gibson
---
target/ppc/cpu-qom.h | 1 -
target/ppc/cpu_init.c | 17 -
2 files changed, 18 deletions(-)
The following changes since commit 9db3065c62a983286d06c207f4981408cf42184d:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-6.1-pull-request' into staging (2021-07-08
16:30:18 +0100)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git
From: Richard Henderson
Instead, use a switch on env->mmu_model. This avoids some
replicated information in cpu setup.
Signed-off-by: Richard Henderson
Message-Id: <20210621125115.67717-2-bruno.lar...@eldorado.org.br>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
From: Greg Kurz
PowerPC CPUs use big endian by default but starting with POWER7,
server grade CPUs use the ILE bit of the LPCR special purpose
register to decide on the endianness to use when handling
interrupts. This gives a clue to QEMU on the endianness the
guest kernel is running, which is
This allows is to instantiate a vhost-user-i2c device as part of a PCI
bus. It is mostly boilerplate which looks pretty similar to the
vhost-user-fs-pci device.
Reviewed-by: Alex Bennée
Signed-off-by: Viresh Kumar
---
hw/virtio/meson.build | 1 +
hw/virtio/vhost-user-i2c-pci.c | 69
Hello,
This patchset adds vhost-user-i2c device's support in Qemu. Initially I tried to
add the backend implementation as well into Qemu, but as I was looking for a
hypervisor agnostic backend implementation, I decided to keep it outside of
Qemu. Eventually I implemented it in Rust and it works
This patch adds entry for virtio-i2c related files in MAINTAINERS.
Signed-off-by: Viresh Kumar
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 684142e12eaa..2869fb185253 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2143,6 +2143,13 @@
This creates the QEMU side of the vhost-user-i2c device which connects
to the remote daemon. It is based of vhost-user-fs code.
Signed-off-by: Viresh Kumar
---
hw/virtio/Kconfig | 5 +
hw/virtio/meson.build | 1 +
hw/virtio/vhost-user-i2c.c | 288
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Title:
On Fri, Jul 9, 2021 at 12:33 AM Bin Meng wrote:
>
> Currently the firmware dynamic info (fw_dyn) is put right after
> the reset vector, which is not 8-byte aligned on RV64. OpenSBI
> fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
> which expects fw_dyn to be on the 8-byte
Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use gpr_src, gpr_dst in the new subroutines.
Signed-off-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvh.c.inc | 264 +---
2 files
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Title:
older OS's
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Title:
Snapshots
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvf.c.inc | 131 +---
1 file changed, 49 insertions(+), 82 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index 89f78701e7..ff8e942199 100644
---
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7dedfd548b..6ad40e43b0 100644
--- a/target/riscv/translate.c
+++
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Title:
This function is now unused.
The corresponding gen_set_gpr function is still in use.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index
Introduce csrr and csrw helpers, for read-only and write-only insns.
Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other zero
write_mask another source register -- this should still raise an
exception for read-only
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https://bugs.launchpad.net/bugs/1861161
Title:
Allocate new temps to hold the source extensions, and
extend directly from the source registers.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 46 +++-
1 file changed, 22 insertions(+), 24 deletions(-)
diff --git a/target/riscv/translate.c
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 79 +++--
1 file changed, 20 insertions(+), 59 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index a8e7272487..84a45fac38 100644
---
These operations are slightly more complicated since
we need to crop the shift operand.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 68 +++-
1 file changed, 26 insertions(+), 42 deletions(-)
diff --git a/target/riscv/translate.c
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvd.c.inc | 116 +---
1 file changed, 44 insertions(+), 72 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 7e45538ae0..9bb15fdc12 100644
---
New helpers that do not force tcg globals into temps,
returning a constant 0 for $zero as source and a new
temp for $zero as destination.
Use them in gen_arith_imm_{fn,tl}, gen_arith, gen_unary.
These are simplest because no further temps required.
Signed-off-by: Richard Henderson
---
Split out gen_mulh and gen_mulhu and use the common helper.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 16
target/riscv/insn_trans/trans_rvm.c.inc | 24 ++--
2 files changed, 18 insertions(+), 22 deletions(-)
diff --git
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Title:
gtk with
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rva.c.inc | 42 +
1 file changed, 14 insertions(+), 28 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv/insn_trans/trans_rva.c.inc
index ab2ec4f0a5..5bb5bbd09c 100644
---
Narrow the scope of t0 in trans_jalr.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 9e81f6e3de..58921f3224 100644
---
[Expired for QEMU because there has been no activity for 60 days.]
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Title:
EFI GOP
Replace uses of tcg_const_* with the allocate and free close together.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 36 --
target/riscv/insn_trans/trans_rvf.c.inc | 3 +-
target/riscv/insn_trans/trans_rvv.c.inc | 65 +
3
For trans_sllw, we can just use gen_shiftw. The others use
various tricks to reduce the tcg operation count.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 82 ++---
1 file changed, 31 insertions(+), 51 deletions(-)
diff --git
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Title:
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Title:
IDE ATA
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Title:
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 45 +++--
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index a603925637..a422dc9ef4 100644
---
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Title:
x86 f1
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Title:
no sound
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Title:
qemu-img
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Title:
Deleted
Replace use of tcg_const_*, which makes a copy into a temp
which must be freed, with direct use of the constant.
Reorg handling of $zero, with different accessors for
source and destination.
Reorg handling of csrs, passing the actual write_mask
instead of a regno.
Use more helpers for RVH
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1900919
Title:
PXB
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1902267
Title:
CPU not
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1902451
Title:
incorrect
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1901359
Title:
ignore bit
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1902394
Title:
Guest
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1902262
Title:
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1903493
Title:
About
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1902365
Title:
3x 100%
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1902777
Title:
qemu with
在 2021/7/6 下午3:20, Cindy Lu 写道:
In order to support configure interrupt for vhost-vdpa
introduce VIRTIO_CONFIG_IRQ_IDX -1 as a queue index,
then we can reuse the function guest_notifier_mask and
guest_notifier_pending.
we add the check of queue index, if the driver
is not support configure
在 2021/7/1 下午5:11, Zhang Chen 写道:
Since the real user scenario does not need to monitor all traffic.
Add passthrough-filter-add and passthrough-filter-del to maintain
a network passthrough list in object with network packet processing
function. Add IPFlowSpec struct for all QMP commands.
Most
On Fri, Jul 9, 2021 at 12:33 AM Bin Meng wrote:
>
> Currently the firmware dynamic info (fw_dyn) is put right after
> the reset vector, which is not 8-byte aligned on RV64. OpenSBI
> fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
> which expects fw_dyn to be on the 8-byte
On Tue, Jul 6, 2021 at 8:48 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present the CLINT timebase frequency is set to 10MHz on sifive_u,
> but on the real hardware the timebase frequency is 1Mhz.
>
> Signed-off-by: Bin Meng
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
>
On Tue, Jul 6, 2021 at 7:50 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This adds a new section in the documentation to demonstrate how to
> use the new direct kernel boot feature for Microchip Icicle Kit,
> other than the HSS bootflow, using an upstream U-Boot v2021.07 image
> as an example.
>
>
On 09/07/2021 08:34, BALATON Zoltan wrote:
On Thu, 8 Jul 2021, Alexey Kardashevskiy wrote:
This addresses the comments from v22.
The functional changes are (the VOF ones need retesting with Pegasos2):
(VOF) setprop will start failing if the machine class callback
did not handle it;
(VOF)
OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 6 ++
2 files changed, 8 insertions(+)
diff --git
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/opentitan.h | 1 +
hw/riscv/opentitan.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 86cceef698..a488f5e8ec 100644
---
1 - 100 of 662 matches
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