[PATCH] hw/i386/acpi-build: Get NUMA information from struct NumaState

The NUMA information in PCMachineState is copied from MachineState. We get this information uniformly from struct NumaState in MachineState. Signed-off-by: Jingqi Liu --- hw/i386/acpi-build.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/i386/acpi-build.c b/

Re: [PATCH 1/1] migration: Terminate multifd threads on yank

On Fri, 30 Jul 2021 04:40:45 -0300 Leonardo Bras wrote: > From source host viewpoint, losing a connection during migration will > cause the sockets to get stuck in sendmsg() syscall, waiting for > the receiving side to reply. > > In migration, yank works by shutting-down the migration QIOChannel

Re: [PATCH 0/6] Updates for Coverity modeling file

Paolo Bonzini writes: [...] > This series is a sort of FYI; since the only way to debug the model file > is to upload it to scan.coverity.com, these changes are all already live. When I mess with Coverity, I test with my locally installed version first. Version skew and lack of the web interfa

Re: [PATCH 10/16] migration: Handle migration_incoming_setup() errors consistently

"Dr. David Alan Gilbert" writes: > * Markus Armbruster (arm...@redhat.com) wrote: >> Commit b673eab4e2 "multifd: Make multifd_load_setup() get an Error >> parameter" changed migration_incoming_setup() to take an Error ** >> argument, and adjusted the callers accordingly. It neglected to >> chang

Re: [PATCH v2 1/1] nvdimm: add 'target-node' option

Hi Igor, On 7/29/2021 8:44 PM, Igor Mammedov wrote: On Mon, 19 Jul 2021 10:01:53 +0800 Jingqi Liu wrote: Linux kernel version 5.1 brings in support for the volatile-use of persistent memory as a hotplugged memory region (KMEM DAX). When this feature is enabled, persistent memory can be seen a

Re: [PATCH 12/16] vhost: Clean up how VhostOpts method vhost_get_config() fails

Philippe Mathieu-Daudé writes: > On 7/20/21 2:54 PM, Markus Armbruster wrote: >> vhost_user_get_config() can fail without setting an error. Unclean. >> Its caller vhost_dev_get_config() compensates by substituting a >> generic error then. Goes back to commit 50de51387f "vhost: >> Distinguish er

Re: [PATCH 01/16] error: Use error_fatal to simplify obvious fatal errors (again)

Philippe Mathieu-Daudé writes: > On 7/20/21 2:53 PM, Markus Armbruster wrote: >> We did this with scripts/coccinelle/use-error_fatal.cocci before, in >> commit 50beeb68094 and 007b06578ab. This commit cleans up rarer >> variations that don't seem worth matching with Coccinelle. >> >> Cc: Thomas

Re: [PATCH] vhost: use large iotlb entry if no IOMMU translation is needed

On Tue, Aug 03, 2021 at 12:43:58PM +0800, Jason Wang wrote: > >在 2021/8/3 下午12:29, Chao Gao 写道: >> Ping. Could someone help to review this patch? >> >> Thanks >> Chao >> >> On Wed, Jul 21, 2021 at 03:54:02PM +0800, Chao Gao wrote: >> > If guest enables IOMMU_PLATFORM for virtio-net, severe networ

Re: [PATCH v2 19/55] target/xtensa: Implement do_unaligned_access for user-only

On Mon, Aug 2, 2021 at 9:15 PM Richard Henderson wrote: > > Cc: Max Filippov > Signed-off-by: Richard Henderson > --- > target/xtensa/cpu.c| 2 +- > target/xtensa/helper.c | 30 +++--- > 2 files changed, 16 insertions(+), 16 deletions(-) Acked-by: Max Filippov --

[PATCH for-6.1] qga-win/msi: fix missing libstdc++-6 DLL in MSI installer

libstdc++ is required for the qga-vss.dll that provides fsfreeze functionality. Currently it is not provided by the MSI installer, resulting in fsfreeze being disabled in guest environments where it has not been installed by other means. In the future this would be better handled via gcc-cpp Compo

[PATCH v2 55/55] target/sh4: Implement prctl_unalign_sigbus

Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 4

[PATCH v2 50/55] hw/core/cpu: Add prctl-unalign-sigbus property for user-only

Actually disabled for now. Will enable for each cpu that supports the feature. Signed-off-by: Richard Henderson --- hw/core/cpu-user.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index 62037e8669..23786865cb 100644 --- a/hw/core/c

Re: [PATCH] vhost: use large iotlb entry if no IOMMU translation is needed

在 2021/8/3 下午12:29, Chao Gao 写道: Ping. Could someone help to review this patch? Thanks Chao On Wed, Jul 21, 2021 at 03:54:02PM +0800, Chao Gao wrote: If guest enables IOMMU_PLATFORM for virtio-net, severe network performance drop is observed even if there is no IOMMU. We see such reports

[PATCH v2 48/55] linux-user: Add code for PR_GET/SET_UNALIGN

This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ linux-user/syscall.c | 21 +++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/i

[PATCH v2 45/55] linux-user: Split out do_prctl and subroutines

Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these o

[PATCH v2 54/55] target/hppa: Implement prctl_unalign_sigbus

Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 5 - hw/core/cpu-user.c | 2 +- linux-user/syscall.c| 2 +- target/hppa/

Re: [PATCH] vhost: use large iotlb entry if no IOMMU translation is needed

Ping. Could someone help to review this patch? Thanks Chao On Wed, Jul 21, 2021 at 03:54:02PM +0800, Chao Gao wrote: >If guest enables IOMMU_PLATFORM for virtio-net, severe network >performance drop is observed even if there is no IOMMU. And disabling >vhost can mitigate the perf issue. Finally,

[Bug 1878054] Re: Hang with high CPU usage in sdhci_data_transfer

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1878054 Title: Hang with h

[PATCH v2 40/55] target/arm: Use cpu_*_mmu instead of helper_*_mmu

The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Cc: qemu-...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Hender

[PATCH v2 51/55] target/alpha: Reorg fp memory operations

Pass in the context to each mini-helper, instead of an incorrectly named "flags". Separate gen_load_fp and gen_store_fp, away from the integer helpers. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 83 +++- 1 file changed, 57 insertions(+),

[PATCH v2 49/55] hw/core/cpu: Move cpu properties to cpu-sysemu.c

The comment in cpu-common.c is absolutely correct, we can't rely on the ifdef in a file built once. This was only "working" because we used ifndef. Signed-off-by: Richard Henderson --- hw/core/cpu-common.h | 17 + hw/core/cpu-common.c | 18 ++ hw/core/cpu-sysemu.

[PATCH v2 53/55] target/alpha: Implement prctl_unalign_sigbus

Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 5 + hw/core/cpu-user.c | 2 +- linux-user/syscall.c | 2 +- target/al

[PATCH v2 34/55] accel/tcg: Add cpu_{ld,st}*_mmu interfaces

These functions are much closer to the softmmu helper functions, in that they take the complete MemOpIdx, and from that they may enforce required alignment. The previous cpu_ldst.h functions did not have alignment info, and so did not enforce it. Retain this by adding MO_UNALN to the MemOp that w

[PATCH v2 43/55] tcg/i386: Support raising sigbus for user-only

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 - tcg/i386/tcg-target.c.inc | 114 -- 2 files changed, 110 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b00a6da293..3b2c9437a0 100644 --- a/

[PATCH v2 47/55] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass

Despite the comment, the members were not kept at the end. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bc864564ce..b7d5bc1200 100644 --- a/include/hw

[PATCH v2 52/55] target/alpha: Reorg integer memory operations

Pass in the MemOp instead of a callback. Drop the fp argument; add a locked argument. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 104 +++ 1 file changed, 40 insertions(+), 64 deletions(-) diff --git a/target/alpha/translate.c b/target/alp

[PATCH v2 30/55] target/i386: Use MO_128 for 16 byte atomics

Signed-off-by: Richard Henderson --- target/i386/tcg/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 0fd696f9c1..a207e624cb 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper

[PATCH v2 42/55] tcg: Add helper_unaligned_mmu for user-only sigbus

To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 5 + accel/tcg/user-exec.c | 7 +++ 2 files changed, 12 insertions(+) diff --gi

[PATCH v2 46/55] linux-user: Disable more prctl subcodes

Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Signed-off-by: Richard Henderson --- linux-

[PATCH v2 44/55] tests/tcg/multiarch: Add sigbus.c

A mostly generic test for unaligned access raising SIGBUS. Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 68 1 file changed, 68 insertions(+) create mode 100644 tests/tcg/multiarch/sigbus.c diff --git a/tests/tcg/multiarch/sigbus.c b/t

[PATCH v2 28/55] trace: Split guest_mem_before

There is no point in encoding load/store within a bit of the memory trace info operand. Represent atomic operations as a single read-modify-write tracepoint. Use MemOpIdx instead of inventing a form specifically for traces. Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h |

[PATCH v2 38/55] target/s390x: Use cpu_*_mmu instead of helper_*_mmu

The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Cc: qemu-s3...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Hend

[PATCH v2 36/55] target/mips: Use cpu_*_data_ra for msa load/store

We should not have been using the helper_ret_* set of functions, as they are supposed to be private to tcg. Nor should we have been using the plain cpu_*_data set of functions, as they do not handle unwinding properly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tar

[PATCH v2 41/55] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h

These functions have been replaced by cpu_*_mmu as the most proper interface to use from target code. Hide these declarations from code that should not use them. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 74 +++

[PATCH v2 25/55] trace/mem: Pass MemOpIdx to trace_mem_get_info

We (will) often have the complete MemOpIdx handy, so use that. Signed-off-by: Richard Henderson --- trace/mem.h | 32 +- accel/tcg/cputlb.c| 12 -- accel/tcg/user-exec.c | 42 +++ tcg/tcg-op.c

[PATCH v2 37/55] target/mips: Use 8-byte memory ops for msa load/store

Rather than use 4-16 separate operations, use 2 operations plus some byte reordering as necessary. Cc: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 201 +-- 1 file changed, 71 insertions(+), 130 deletions(-) diff --g

[PATCH v2 39/55] target/sparc: Use cpu_*_mmu instead of helper_*_mmu

The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c |

[PATCH v2 31/55] target/ppc: Use MO_128 for 16 byte atomics

Cc: qemu-...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/translate.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..540efa858f 100644 --- a/targe

[PATCH v2 26/55] accel/tcg: Pass MemOpIdx to atomic_trace_*_post

We will shortly use the MemOpIdx directly, but in the meantime re-compute the trace meminfo. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 48 +-- accel/tcg/atomic_common.c.inc | 30 +++---

[PATCH v2 32/55] target/s390x: Use MO_128 for 16 byte atomics

Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ec88f5dbb0..3782c1c09

[PATCH v2 35/55] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h

The previous placement in tcg/tcg.h was not logical. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 87 +++ include/tcg/tcg.h | 87 --- target/arm/helper-a64.c

[PATCH v2 23/55] tcg: Rename TCGMemOpIdx to MemOpIdx

We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 24 +-- include/tcg/tcg.h | 74 - accel/tcg/cputlb.c

[PATCH v2 29/55] target/arm: Use MO_128 for 16 byte atomics

Cc: qemu-...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 13d1e3f808..f06399f351 100644 --- a/target/

[PATCH v2 27/55] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb

Use the MemOpIdx directly, rather than the rearrangement of the same bits currently done by the trace infrastructure. Pass in enum qemu_plugin_mem_rw so that we are able to treat read-modify-write operations as a single operation. Signed-off-by: Richard Henderson --- include/qemu/plugin.h

[PATCH v2 33/55] target/hexagon: Implement cpu_mmu_index

The function is trivial for user-only, but still must be present. Reviewed-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/cpu.h | 9 + 1 file changed, 9 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h i

[PATCH v2 18/55] target/sparc: Implement do_unaligned_access for user-only

Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 11 +++ target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 4 +++- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_l

[PATCH v2 22/55] tcg: Expand MO_SIZE to 3 bits

We have lacked expressive support for memory sizes larger than 64-bits for a while. Fixing that requires adjustment to several points where we used this for array indexing, and two places that develop -Wswitch warnings after the change. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard

[PATCH v2 19/55] target/xtensa: Implement do_unaligned_access for user-only

Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/cpu.c| 2 +- target/xtensa/helper.c | 30 +++--- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 58ec3a0862..41816d91f6 100644 --- a/t

[PATCH v2 24/55] tcg: Split out MemOpIdx to exec/memopidx.h

Move this code from tcg/tcg.h to its own header. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/memopidx.h | 55 + include/tcg/tcg.h | 39 + 2 files changed, 56 insertions(+), 38 del

[PATCH v2 17/55] target/sparc: Set fault address in sparc_cpu_do_unaligned_access

We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 --

[PATCH v2 20/55] accel/tcg: Report unaligned atomics for user-only

Use the newly exposed cpu_unaligned_access for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exe

[PATCH v2 21/55] accel/tcg: Drop signness in tracing in cputlb.c

We are already inconsistent about whether or not MO_SIGN is set in trace_mem_get_info. Dropping it entirely allows some simplification. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c| 10 +++--- accel/tcg/user-exec.c | 45 ++- 2 files cha

[PATCH v2 12/55] target/s390x: Implement do_unaligned_access for user-only

Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 28 +++- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3.

[PATCH v2 15/55] target/sparc: Remove DEBUG_UNALIGNED

The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Cc: Mark Cave-Ayland Reviewed-b

[PATCH v2 11/55] target/riscv: Implement do_unaligned_access for user-only

Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 +++ target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 8 +++- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv

[PATCH v2 14/55] target/sh4: Implement do_unaligned_access for user-only

Cc: Yoshinori Sato Signed-off-by: Richard Henderson --- linux-user/sh4/cpu_loop.c | 8 target/sh4/cpu.c | 2 +- target/sh4/op_helper.c| 3 --- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 222ed1c6

[PATCH v2 16/55] target/sparc: Split out build_sfsr

Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +-- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..5b2fda534a 100644 --- a/target/sparc/mmu_helper.c ++

[PATCH v2 13/55] target/sh4: Set fault address in superh_cpu_do_unaligned_access

We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/sh4/op_helper.c b/targ

[PATCH v2 05/55] target/hppa: Implement do_unaligned_access for user-only

Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 2 +- target/hppa/cpu.c | 9 ++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 82d8183821..5ce30fec8b 100644 --- a/linux-user/hppa/cpu_lo

[PATCH v2 10/55] target/ppc: Implement do_unaligned_access for user-only

For simplicity on the linux-user side, always use SPR_DAR. Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/linux-user/

[PATCH v2 09/55] target/ppc: Set fault address in ppc_cpu_do_unaligned_access

We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper

[PATCH v2 03/55] target/alpha: Implement do_unaligned_access for user-only

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/alpha/cpu.c| 2 +- target/alpha/mem_helper.c | 8 +++- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4871ad0c0a..cb7e5261bd 100644 --- a/target/alpha/

[PATCH v2 06/55] target/microblaze: Do not set MO_ALIGN for user-only

The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 1 file changed, 16 insertions(+) diff --git a/target/microblaze/translate.c b/ta

[PATCH v2 04/55] target/arm: Implement do_unaligned_access for user-only

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 4 linux-user/arm/cpu_loop.c | 43 +++ target/arm/cpu.c | 2 +- target/arm/cpu_tcg.c | 2 +- 4 files changed, 40 insertions(+), 11 del

[PATCH v2 07/55] target/mips: Implement do_unaligned_access for user-only

Cc: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/mips/cpu_loop.c| 20 target/mips/cpu.c | 2 +- target/mips/tcg/op_helper.c | 3 +-- target/mips/tcg/user/tlb_helper.c | 23 +++ 4 files changed, 29

[PATCH v2 08/55] target/ppc: Move SPR_DSISR setting to powerpc_excp

By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 21 +

[PATCH v2 02/55] hw/core: Make do_unaligned_access available to user-only

We shouldn't be ignoring SIGBUS for user-only. Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU. Move the wrapper, cpu_unaligned_access, to cpu-exec-common.c. Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 4 include/hw/core/tcg-cpu-ops.h | 16 ---

[PATCH v2 00/55] Unaligned access for user-only

This began with Peter wanting a cpu_ldst.h interface that can handle alignment info for Arm M-profile system mode, which will also compile for user-only without ifdefs. This is patch 32. Once I had that interface, I thought I might as well enforce the requested alignment in user-only. There are

[PATCH v2 01/55] hw/core: Make do_unaligned_access noreturn

While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 3 ++- target/alpha/cpu.h | 4 ++-- target/arm/internals.h | 3 ++- target/microblaz

Re: [PATCH] nvdimm: release the correct device list

ping Any body could help to review/queue this patch ? On 2021/6/29 22:05, Igor Mammedov wrote: On Thu, 24 Jun 2021 19:04:15 +0800 Li Zhijian wrote: Signed-off-by: Li Zhijian Reviewed-by: Igor Mammedov --- hw/acpi/nvdimm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deleti

[RFC PATCH v2 1/2] Adding i2c interface for qemu

From: padmakar The changes here includes the interface for i2c/smbus for nvme-mi protocol. We have used an address of 0x15 using which the guest VM can send and recieve the nvme-mi commands. Since the nvme-mi device uses the I2C_SLAVE as parent, we have used the send and recieve callbacks by whi

Re: [Question] qemu-img convert block alignment

ping? On 2021/4/2 11:52, Zhenyu Ye wrote: > Hi all, > > commit 8dcd3c9b91 ("qemu-img: align result of is_allocated_sectors") > introduces block alignment when doing qemu-img convert. However, the > alignment is: > > s.alignment = MAX(pow2floor(s.min_sparse), > DIV_ROU

Re: QEMU on x64

Thanks folks! I went ahead and made a feature/issue request based on Paolo's suggestion: QEMU registers support on x64 (#510) · Issues · QEMU / QEMU · GitLab Please let me know if someone has the cycles to support this. -Christopher On Mon, Aug

Re: need help with my config

Hi Cedric, Thanks for replying. I think I want to go down the PowerNV Power 9 Which I will need the OpenPower firmware. Looks like the webpage for downloading prebuild witherspoon and skiboot is down/dead. Hasn't been working for me for 24hours anyway Is that the only place to download that firmwa

RE: [PATCH v2 0/3] Add support for Fujitsu A64FX processor

> I'm afraid this isn't the way a v2 patchseries should be structured. > The idea is that a v2 series should be complete in itself, not based on > whatever v1 > was. So when you make the changes requested in review of v1, you update the > commits in your local git branch, and then you send out the

RE: [PATCH v2 1/3] target-arm: delete ARM_FEATURE_A64FX

> This is confusing because I can't see this feature flag in the mainline > branch. Have > you inadvertently based this series from an internal branch? I'm sorry for the confusion. My lack of understanding of how to handle v2 patches has led me to create a v2 patch series based on patches that

RE: [PATCH v2 1/3] target-arm: delete ARM_FEATURE_A64FX

> This feature doesn't exist in upstream QEMU, so this won't apply. > For a v2 of a patch, the patches should be based on upstream, not on top of > the v1 > series. Thank you for your comment. I understood your point. Best regards. > -Original Message- > From: Peter Maydell > Sent: Fri

RE: [PATCH v2 3/3] target-arm: Add A64FX processor support to virt machine

> Commit messages should describe what the patch is doing and why, so the reader > can understand it without having to cross-reference old mailing list threads. Thank you for your comment. I understood your point. Best regards. > -Original Message- > From: Peter Maydell > Sent: Friday,

[PATCH-for-6.1 v2 2/2] hw/sd/sdcard: Fix assertion accessing out-of-range addresses with CMD30

OSS-Fuzz found sending illegal addresses when querying the write protection bits triggers the assertion added in commit 84816fb63e5 ("hw/sd/sdcard: Assert if accessing an illegal group"): qemu-fuzz-i386-target-generic-fuzz-sdhci-v3: ../hw/sd/sd.c:824: uint32_t sd_wpbits(SDState *, uint64_t):

[PATCH-for-6.1 v2 1/2] hw/sd/sdcard: Document out-of-range addresses for SEND_WRITE_PROT

Per the 'Physical Layer Simplified Specification Version 3.01', Table 4-22: 'Block Oriented Write Protection Commands' SEND_WRITE_PROT (CMD30) If the card provides write protection features, this command asks the card to send the status of the write protection bits [1]. [1] 32 write prot

[PATCH-for-6.1 v2 0/2] hw/sd/sdcard: Fix assertion accessing out-of-range addresses with CMD30

Fix an assertion reported by OSS-Fuzz, add corresponding qtest. The change is (now) simple enough for the next rc. Since v1: - Simplified/corrected following Peter's suggestion Philippe Mathieu-Daudé (2): hw/sd/sdcard: Document out-of-range addresses for SEND_WRITE_PROT hw/sd/sdcard: Fix ass

Re: [PATCH-for-6.1 2/3] hw/sd/sdcard: Fix assertion accessing out-of-range addresses with CMD30

On 8/2/21 2:03 PM, Peter Maydell wrote: > On Wed, 28 Jul 2021 at 19:19, Philippe Mathieu-Daudé wrote: >> >> OSS-Fuzz found sending illegal addresses when querying the write >> protection bits triggers the assertion added in commit 84816fb63e5 >> ("hw/sd/sdcard: Assert if accessing an illegal group

Re: [PATCH 1/1] hw/i2c: add remote I2C device

This patch set was sent in error (duplicates and bad version names). Please ignore it. Sorry for the inconvenience, Shengtan Mao On Mon, Aug 2, 2021 at 7:03 PM Shengtan Mao wrote: > This patch adds the remote I2C device, which supports the usage of > external I2C devices. > Signed-off-by: Sheng

Re: [PATCH v2 0/1] Add remote I2C device to support external I2C device

This patch set was sent in error (duplicates and bad version names). Please ignore it. Sorry for the inconvenience, Shengtan Mao On Mon, Aug 2, 2021 at 7:03 PM Shengtan Mao wrote: > This patch implements the remote I2C device. > The remote I2C device allows an external I2C device to communicate

Re: [PATCH-for-6.2 3/5] target/mips: Convert Vr54xx MACC* opcodes to decodetree

On 8/2/21 9:50 PM, Richard Henderson wrote: > On 8/1/21 1:59 PM, Philippe Mathieu-Daudé wrote: >> Convert the following Integer Multiply-Accumulate opcodes: >> >>   * MACC Multiply, accumulate, and move LO >>   * MACCHI   Multiply, accumulate, and move HI >>   * MACCHIU  Unsigned mu

[PATCH v2 0/1] Add remote I2C device to support external I2C device

This patch implements the remote I2C device. The remote I2C device allows an external I2C device to communicate with the I2C controller in QEMU through the remote I2C protocol. Users no longer have to directly modify QEMU to add new I2C devices and can instead implement the emulated device extern

[PATCH v2 1/1] hw/i2c: add remote I2C device

This patch adds the remote I2C device, which supports the usage of external I2C devices. Signed-off-by: Shengtan Mao --- hw/arm/Kconfig| 1 + hw/i2c/Kconfig| 4 + hw/i2c/meson.build| 1 + hw/i2c/remote-i2c.c | 117 ++ tes

[PATCH 1/1] hw/i2c: add remote I2C device

This patch adds the remote I2C device, which supports the usage of external I2C devices. Signed-off-by: Shengtan Mao --- hw/arm/Kconfig| 1 + hw/i2c/Kconfig| 4 + hw/i2c/meson.build| 1 + hw/i2c/remote-i2c.c | 117 ++ tes

[PATCH v2 0/1] Add remote I2C device to support external I2C device

This patch implements the remote I2C device. The remote I2C device allows an external I2C device to communicate with the I2C controller in QEMU through the remote I2C protocol. Users no longer have to directly modify QEMU to add new I2C devices and can instead implement the emulated device extern

Re: "make check-acceptance" takes way too long

On Sat, Jul 31, 2021 at 4:33 PM Peter Maydell wrote: > > On Sat, 31 Jul 2021 at 19:43, Alex Bennée wrote: > > > > > > Peter Maydell writes: > > > > > "make check-acceptance" takes way way too long. I just did a run > > > on an arm-and-aarch64-targets-only debug build and it took over > > > half

Re: [PATCH 2/2] target/arm: Implement M-profile trapping on division by zero

On 7/30/21 5:16 AM, Peter Maydell wrote: Unlike A-profile, for M-profile the UDIV and SDIV insns can be configured to raise an exception on division by zero, using the CCR DIV_0_TRP bit. Implement support for setting this bit by making the helper functions raise the appropriate exception. Signe

[PATCH] tests/acceptance: Allow overwrite smp and memory

Removes the hard-coded values in setUp(). Class inheriting from avocado_qemu.LinuxTest can overwrite the default smp and memory instead. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/453 Signed-off-by: Ahmed Abouzied --- tests/acceptance/avocado_qemu/__init__.py | 6 -- 1 file chan

Re: [PATCH 1/2] target/arm: Re-indent sdiv and udiv helpers

On 7/30/21 5:16 AM, Peter Maydell wrote: We're about to make a code change to the sdiv and udiv helper functions, so first fix their indentation and coding style. Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) Revie

Re: [PATCH 0/2] arm: Implement M-profile trapping on division by zero

On 7/30/21 5:16 AM, Peter Maydell wrote: Unlike A-profile, for M-profile the UDIV and SDIV insns can be configured to raise an exception on division by zero, using the CCR DIV_0_TRP bit. This patchset implements that missing functionality by having the udiv and sdiv helpers raise an exception if

[PATCH-for-6.2 v6 04/10] tests: Add suffix 'tpm2' or 'tpm12' to ACPI table files

Cc: Michael S. Tsirkin Cc: Igor Mammedov Signed-off-by: Stefan Berger Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 93c9d306b5..4ccbe56158

[PATCH-for-6.2 v6 06/10] tests: tpm: Create TPM 1.2 response in TPM emulator

Signed-off-by: Stefan Berger Acked-by: Igor Mammedov --- v3: - Added TPM_VERSION_1_2 enum for when CONFIG_TPM is not defined --- tests/qtest/tpm-emu.c | 5 + tests/qtest/tpm-emu.h | 4 2 files changed, 9 insertions(+) diff --git a/tests/qtest/tpm-emu.c b/tests/qtest/tpm-emu.c index

[PATCH-for-6.2 v6 01/10] tests: Rename TestState to TPMTestState

Signed-off-by: Stefan Berger Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c| 2 +- tests/qtest/tpm-crb-test.c| 4 ++-- tests/qtest/tpm-emu.c | 6 +++--- tests/qtest/tpm-emu.h | 6 +++--- tests/qtest/tpm-tis-device-test.c | 2 +- tests/qtest/tpm-

[PATCH-for-6.2 v6 07/10] tests: acpi: prepare for new TPM 1.2 related tables

Cc: Michael S. Tsirkin Cc: Igor Mammedov Signed-off-by: Stefan Berger Acked-by: Igor Mammedov --- tests/data/acpi/q35/DSDT.tis.tpm12 | 0 tests/data/acpi/q35/TCPA.tis.tpm12 | 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 3 files changed, 2 insertions(+) create mode

[PATCH-for-6.2 v6 02/10] tests: Add tpm_version field to TPMTestState and fill it

Signed-off-by: Stefan Berger Reviewed-by: Igor Mammedov --- v3: - Added enum TPMVersion for when CONFIG_TPM is not defined --- tests/qtest/bios-tables-test.c| 5 +++-- tests/qtest/tpm-crb-test.c| 1 + tests/qtest/tpm-emu.c | 13 ++--- tests/qtest/tpm-emu.h

[PATCH-for-6.2 v6 10/10] tests: acpi: tpm1.2: Add expected TPM 1.2 ACPI blobs

The TCPA.tis.tpm12 file contains the following: [000h 4]Signature : "TCPA"[Trusted Computing Platform Alliance table] [004h 0004 4] Table Length : 0032 [008h 0008 1] Revision : 02 [009h 0009 1] Checks

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