Re: [PATCH v3 3/5] numa: Support SGX numa in the monitor and Libvirt interfaces

On 11/11/21 07:18, Yang Zhong wrote: > On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote: >> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote: >>> Add the SGXEPCSection list into SGXInfo to show the multiple >>> SGX EPC sections detailed info, not the total size like before. >>>

Re: [PATCH 0/6] RfC: try improve native hotplug for pcie root ports

Hi, > Given it's a bugfix, and given that I hear through internal channels > that QE results so far have been encouraging, I am inclined to bite the > bullet and merge this for -rc1. Fine with me. > I don't think this conflicts with Julia's patches as users can still > disable ACPI hotplug

Re: [PATCH 1/2] virtio: use virtio accessor to access packed descriptor flags

On 11/11/21 07:38, Jason Wang wrote: > We used to access packed descriptor flags via > address_space_{write|read}_cached(). When we hit the cache, memcpy() > is used which is not an atomic operation which may lead a wrong value > is read or wrote. > > So this patch switches to use

Re: [PATCH 2/2] virtio: use virtio accessor to access packed event

On 11/11/21 07:38, Jason Wang wrote: > We used to access packed descriptor event and off_wrap via > address_space_{write|read}_cached(). When we hit the cache, memcpy() > is used which is not atomic which may lead a wrong value to be read or > wrote. > > This patch fixes this by switching to use

[PULL 2/5] rcu: Introduce force_rcu notifier

From: Greg Kurz The drain_rcu_call() function can be blocked as long as an RCU reader stays in a read-side critical section. This is typically what happens when a TCG vCPU is executing a busy loop. It can deadlock the QEMU monitor as reported in https://gitlab.com/qemu-project/qemu/-/issues/650

[PULL 3/5] accel/tcg: Register a force_rcu notifier

From: Greg Kurz A TCG vCPU doing a busy loop systematicaly hangs the QEMU monitor if the user passes 'device_add' without argument. This is because drain_cpu_all() which is called from qmp_device_add() cannot return if readers don't exit read-side critical sections. That is typically what

[PULL 4/5] numa: avoid crash with SGX and "info numa"

Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case, so that enclave memory is included in the output of "info numa" instead of crashing the monitor. Fixes: a7c565a941 ("sgx-epc: Add the fill_device_info() callback support", 2021-09-30) Signed-off-by: Paolo Bonzini --- hw/core/numa.c | 7 +++ 1

Re: [PATCH v3 3/5] numa: Support SGX numa in the monitor and Libvirt interfaces

On 11/10/21 17:55, Eric Blake wrote: The QMP interface show: (QEMU) query-sgx {"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \ [{"node": 0, "size": 67108864}, {"node": 1, "size": 29360128}], "flc": true}} (QEMU) query-sgx-capabilities {"return": {"sgx": true, "sgx2": true,

[PULL 0/5] x86, RCU/TCG patches for QEMU 6.2-rc1

The following changes since commit 114f3c8cc427333dbae331dfd2ecae64676b087e: Merge remote-tracking branch 'remotes/philmd/tags/avocado-20211108' into staging (2021-11-08 18:50:09 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you

[PULL 5/5] sgx: Reset the vEPC regions during VM reboot

From: Yang Zhong For bare-metal SGX on real hardware, the hardware provides guarantees SGX state at reboot. For instance, all pages start out uninitialized. The vepc driver provides a similar guarantee today for freshly-opened vepc instances, but guests such as Windows expect all pages to be in

[PULL 1/5] target/i386: sgx: mark device not user creatable

The device is created by the machine based on the sgx-epc property. It should not be created by users. Reported-by: Thomas Huth Signed-off-by: Paolo Bonzini --- hw/i386/sgx-epc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c index

Re: [PATCH v3] s390: kvm: adjust diag318 resets to retain data

On 11/10/21 07:42, Janosch Frank wrote: > On 11/9/21 21:56, Collin Walling wrote: >> The CPNC portion of the diag 318 data is erroneously reset during an >> initial CPU reset caused by SIGP. Let's go ahead and relocate the >> diag318_info field within the CPUS390XState struct such that it is >>

[PATCH 2/2] virtio: use virtio accessor to access packed event

We used to access packed descriptor event and off_wrap via address_space_{write|read}_cached(). When we hit the cache, memcpy() is used which is not atomic which may lead a wrong value to be read or wrote. This patch fixes this by switching to use virito_{stw|lduw}_phys_cached() to make sure the

[PATCH 1/2] virtio: use virtio accessor to access packed descriptor flags

We used to access packed descriptor flags via address_space_{write|read}_cached(). When we hit the cache, memcpy() is used which is not an atomic operation which may lead a wrong value is read or wrote. So this patch switches to use virito_{stw|lduw}_phys_cached() to make sure the aceess is

Re: [PATCH v3 0/5] SGX NUMA support plus vepc reset

On Wed, Nov 10, 2021 at 05:07:40PM +0100, Paolo Bonzini wrote: > On 11/10/21 13:56, Yang Zhong wrote: > > Paolo, thanks! > > > > No other maintainers to review numa patches, so i will send the numa > > patches again? thanks! > > The patch look good, but they were sent too close to the 6.2

Re: [PATCH v3 3/5] numa: Support SGX numa in the monitor and Libvirt interfaces

On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote: > On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote: > > Add the SGXEPCSection list into SGXInfo to show the multiple > > SGX EPC sections detailed info, not the total size like before. > > This patch can enable numa support for

[PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN

When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 44 ++--- 1 file

[PATCH v3 20/20] target/riscv: Enable uxl field write

Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8f8f170768..43eaa6c710 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -553,15 +553,14 @@ static RISCVException

[PATCH v3 17/20] target/riscv: Fix check range for first fault only

Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE

Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b48c7c346c..5f35217f7d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2,

[PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f5aabd5263..41c7c88904 100644 ---

[PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 8 +--- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index

Re: [PATCH] qmp: Stabilize preconfig

Paolo Bonzini writes: >> On 11/3/21 09:02, Markus Armbruster wrote: >>> I wonder whether we really have to step through three states >>> >>> x-exit-preconfig cont >>> preconfig ---> pre run ---> run >>> >>> and not two >>> >>> cont >>> pre run ---> run > >

[PATCH v3 12/20] target/riscv: Split out the vill from vtype

We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c| 3 +-- target/riscv/csr.c | 13 - target/riscv/machine.c | 1 + target/riscv/vector_helper.c | 3 ++- 5 files

[PATCH v3 10/20] target/riscv: Calculate address according to XLEN

Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++-- target/riscv/insn_trans/trans_rvd.c.inc | 19 ++---

[PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE

Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 52ce670cbe..b48c7c346c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,7 +105,7 @@ typedef struct CPURISCVState

[PATCH v3 18/20] target/riscv: Adjust vector address with mask

The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei --- target/riscv/vector_helper.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/riscv/vector_helper.c

[PATCH v3 08/20] target/riscv: Create current pm fields in env

Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 4 target/riscv/cpu_helper.c | 43 +++ target/riscv/csr.c| 19 + target/riscv/machine.c| 10 + 5 files changed, 77

[PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/gdbstub.c | 71 +++--- 1 file changed, 52 insertions(+), 19 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..8d0f9139d7 100644 ---

[PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base

Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h| 3 ++- target/riscv/cpu_helper.c | 25 +++--

[PATCH v3 06/20] target/riscv: Relax debug check for pm write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..74c0b788fd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1445,6 +1445,9 @@ static bool

[PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN

Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/op_helper.c| 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc

[PATCH v3 04/20] target/riscv: Extend pc for runtime pc write

In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc register according to current xlen for these cases. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c| 22 +++---

[PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base]

Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei --- target/riscv/translate.c | 32 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/target/riscv/translate.c

[PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN

The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c

[PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN

When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/translate.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c

[PATCH v3 01/20] target/riscv: Don't save pc when exception return

As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++- target/riscv/op_helper.c

[PATCH v3 00/20] Support UXL filed in xstatus

In this patch set, we process the pc reigsters writes, gdb reads and writes, and address calculation under different UXLEN settings. The patch set v3 mainly address Richard comments on v2. Patch 1,2,3,5,6,16,17 have been reviewed. v3: Merge gen_pm_adjust_address into a canonical address

Re: [PATCH for 6.2 v2 3/5] bios-tables-test: Allow changes in DSDT ACPI tables

On Wed, 10 Nov 2021, Igor Mammedov wrote: > From: Julia Suvorova > > Prepare for changing the _OSC method in q35 DSDT. > > Signed-off-by: Julia Suvorova > Signed-off-by: Igor Mammedov Acked-by: Ani Sinha > --- > tests/qtest/bios-tables-test-allowed-diff.h | 16 > 1 file

Re: [PATCH for 6.2 v2 5/5] bios-tables-test: Update golden binaries

On Wed, 10 Nov 2021, Igor Mammedov wrote: > From: Julia Suvorova > > The changes are the result of > 'hw/i386/acpi-build: Deny control on PCIe Native Hot-Plug in _OSC' > and listed here: > > Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities > { >

Re: [PATCH for 6.2 v2 4/5] hw/i386/acpi-build: Deny control on PCIe Native Hot-plug in _OSC

On Wed, 10 Nov 2021, Igor Mammedov wrote: > From: Julia Suvorova > > There are two ways to enable ACPI PCI Hot-plug: > > * Disable the Hot-plug Capable bit on PCIe slots. > > This was the first approach which led to regression [1-2], as > I/O space for a port is allocated only when it

Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN

On 2021/11/10 下午10:40, Richard Henderson wrote: On 11/10/21 2:44 PM, LIU Zhiwei wrote: I suspect the extend should come before the pointer mask and not after, but this is is a weakness in the current RVJ spec that it does not specify how the extension interacts with UXL.  (The reverse

Re: [PATCH v10 00/10]vhost-vdpa: add support for configure interrupt

在 2021/11/8 下午6:53, Stefan Hajnoczi 写道: On Fri, Nov 05, 2021 at 12:48:17AM +0800, Cindy Lu wrote: these patches add the support for configure interrupt These codes are all tested in vp-vdpa (support configure interrupt) vdpa_sim (not support configure interrupt), virtio tap device test in

Re: [PATCH for 6.2 v2 1/5] pcie: rename 'native-hotplug' to 'x-native-hotplug'

On Wed, 10 Nov 2021, Igor Mammedov wrote: > Mark property as experimental/internal adding 'x-' prefix. > > Property was introduced in 6.1 and it should have provided > ability to turn on native PCIE hotplug on port even when > ACPI PCI hotplug is in use is user explicitly sets property > on

[PATCH V2] net/filter: Enable the vnet_hdr_support by default

This patch make filters and colo-compare module support vnet_hdr by default. And also support -device non-virtio-net(like e1000.). Because when enabled the support will make the vnet_hdr_len field become must-delivery part of filter transfer protocol(even 0 in use -device e1000). It fully

RE: [PATCH] net/filter: Enable the vnet_hdr_support by default

> -Original Message- > From: Jason Wang > Sent: Thursday, November 11, 2021 10:50 AM > To: Markus Armbruster > Cc: Zhang, Chen ; qemu-dev de...@nongnu.org>; Li Zhijian > Subject: Re: [PATCH] net/filter: Enable the vnet_hdr_support by default > > On Wed, Nov 10, 2021 at 4:36 PM

Re: [PATCH] net/filter: Enable the vnet_hdr_support by default

On Wed, Nov 10, 2021 at 4:36 PM Markus Armbruster wrote: > > "Zhang, Chen" writes: > > >> -Original Message- > >> From: Markus Armbruster > >> Sent: Wednesday, November 10, 2021 2:21 PM > >> To: Zhang, Chen > >> Cc: Jason Wang ; qemu-dev >> de...@nongnu.org>; Li Zhijian > >> Subject:

[PATCH v2 2/2] tests/unit/test-smp-parse: Fix a check-patch complain

Checkpatch.pl reports errors like below for commit 9e8e393bb7. Let's fix it with a simpler format. ERROR: space required after that close brace '}' +SMPTestData *data = &(SMPTestData){{ }}; Fixes: 9e8e393bb7 ("tests/unit: Add an unit test for smp parsing") Signed-off-by: Yanan Wang ---

[PATCH v2 1/2] tests/unit/test-smp-parse: Make an unified name for the tested machine

Currently, the name of the tested machine in the expected error messages is hardcoded as "(null)" which is not good, because the actual generated name of the machine maybe "(null)" or "(NULL)" which will cause an unexpected test failure in some CI platforms. So let's rename the tested machine

[PATCH v2 0/2] tests/unit/test-smp-parse: Two fixes for test-smp-parse

Hi, There are two fixes for tests/unit/test-smp-parse.c (v2). The first one makes an unified name for the tested machine, which will make the test more stable and resolve the CI failures in [1]. The second one fixes a check-patch complain for commit 9e8e393bb7. [1]

RE: [PATCH v2] Fixed a QEMU hang when guest poweroff in COLO mode

> -Original Message- > From: Rao, Lei > Sent: Thursday, November 11, 2021 10:12 AM > To: Zhang, Chen ; > zhang.zhanghaili...@huawei.com; quint...@redhat.com; > dgilb...@redhat.com > Cc: qemu-devel@nongnu.org; Rao, Lei > Subject: [PATCH v2] Fixed a QEMU hang when guest poweroff in COLO

RE: [PATCH 2/2] migration/ram.c: Remove the qemu_mutex_lock in colo_flush_ram_cache.

> -Original Message- > From: Rao, Lei > Sent: Wednesday, November 10, 2021 4:38 PM > To: Zhang, Chen ; > zhang.zhanghaili...@huawei.com; quint...@redhat.com; > dgilb...@redhat.com > Cc: qemu-devel@nongnu.org; Rao, Lei > Subject: [PATCH 2/2] migration/ram.c: Remove the qemu_mutex_lock

[PATCH v2] Fixed a QEMU hang when guest poweroff in COLO mode

From: "Rao, Lei" When the PVM guest poweroff, the COLO thread may wait a semaphore in colo_process_checkpoint().So, we should wake up the COLO thread before migration shutdown. Signed-off-by: Lei Rao --- include/migration/colo.h | 1 + migration/colo.c | 20

[RFC PATCH v2 28/30] hw/loongarch: Add LoongArch acpi support

Add a simple acpi model for LoongArch cpu More complex functions will be added later Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/acpi/Kconfig | 4 + hw/acpi/ls7a.c | 349 + hw/acpi/meson.build | 1 +

[RFC PATCH v2 27/30] hw/loongarch: Add LoongArch smbios support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 1 + hw/loongarch/ls3a5000_virt.c | 41 include/hw/loongarch/loongarch.h | 2 ++ 3 files changed, 44 insertions(+) diff --git a/hw/loongarch/Kconfig

[RFC PATCH v2 26/30] hw/loongarch: Add -kernel and -initrd options support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/ls3a5000_virt.c | 81 include/hw/loongarch/loongarch.h | 5 ++ 2 files changed, 86 insertions(+) diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c index

[RFC PATCH v2 23/30] hw/loongarch: Add some devices support for 3A5000.

1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the pci host. Non pci device use irq 0-16, pci device use 16-31. 3.Add some unimplented device to emulate guest unused memory space. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig |

[RFC PATCH v2 25/30] hw/loongarch: Add default bios startup support.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 4 +++ hw/loongarch/fw_cfg.c| 33 ++ hw/loongarch/fw_cfg.h| 15 hw/loongarch/ls3a5000_virt.c | 60 +---

[RFC PATCH v2 20/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig | 5 ++ hw/intc/loongarch_pch_msi.c | 73 + hw/intc/meson.build | 1 + hw/loongarch/Kconfig

[RFC PATCH v2 21/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig| 3 + hw/intc/loongarch_extioi.c | 570 + hw/intc/meson.build| 1 + hw/loongarch/Kconfig

[RFC PATCH v2 22/30] hw/loongarch: Add irq hierarchy for the system

This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/ls3a5000_virt.c | 64 include/hw/pci-host/ls7a.h | 4 +++ 2 files changed, 68 insertions(+) diff --git

[RFC PATCH v2 15/30] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson Platform

This is a model of the PCIe Host Bridge found on a Loongson-5000 processor. It includes a interrupt controller, some interface for pci and nonpci devices we only emulate part devices for tcg mode. It support for MSI and MSIX interrupt sources. For more detailed info about ls7a1000 you can see the

[RFC PATCH v2 30/30] hw/loongarch: Add Numa support.

1.From Loongson-3A5000 4 cpus belongs to 1 node. Now support mostly 4 nodes 16 cpus. 2.Different nodes access different address spaces. All memory access should be handle correctly even nodes not assigned memory by numa parameters in the command line. Signed-off-by: Xiaojuan Yang

[RFC PATCH v2 18/30] hw/loongarch: Add LoongArch ipi interrupt support(IPI)

This patch realize the IPI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/ipi.c | 144 +++ hw/loongarch/ls3a5000_virt.c | 1 + hw/loongarch/meson.build | 2 +- include/hw/loongarch/gipi.h

[RFC PATCH v2 13/30] target/loongarch: Add gdb support.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- configs/targets/loongarch64-softmmu.mak | 1 + gdb-xml/loongarch-base64.xml| 43 +++ gdb-xml/loongarch-fpu64.xml | 57 +++ target/loongarch/cpu.c | 9 +++

[RFC PATCH v2 29/30] hw/loongarch: Add machine->possible_cpus

Use possible_cpus for storing possible topology info Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/acpi-build.c| 16 ++-- hw/loongarch/ls3a5000_virt.c | 35 ++- 2 files changed, 44 insertions(+), 7 deletions(-) diff --git

[RFC PATCH v2 19/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

This patch realize the PCH-PIC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig | 4 + hw/intc/loongarch_pch_pic.c | 283 hw/intc/meson.build | 1 + hw/loongarch/Kconfig

[RFC PATCH v2 24/30] hw/loongarch: Add LoongArch ls7a rtc device support

This patch add ls7a rtc device support. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 1 + hw/loongarch/ls3a5000_virt.c | 3 + hw/rtc/Kconfig | 3 + hw/rtc/ls7a_rtc.c| 323 +++

[RFC PATCH v2 14/30] target/loongarch: Implement privilege instructions disassembly

Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang --- target/loongarch/disas.c | 86 1 file changed, 86 insertions(+) diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 1501462991..65aa0443bd 100644 --- a/target/loongarch/disas.c

[RFC PATCH v2 11/30] target/loongarch: Add LoongArch interrupt and exception handle

This patch Add loongarch interrupt and exception handle. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c | 279 + 1 file changed, 279 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index

[RFC PATCH v2 16/30] hw/loongarch: Add a virt LoongArch 3A5000 board support

LoongArch is a new RISC ISA, support 32bit mode or 64bit mode. Now we only add 64bit support. More detailed info you can see https://github.com/loongson/LoongArch-Documentation Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- .../devices/loongarch64-softmmu/default.mak | 3 +

[RFC PATCH v2 07/30] target/loongarch: Add MMU support for LoongArch CPU.

This patch introduces basic TLB interfaces. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu-param.h | 3 + target/loongarch/cpu.c| 36 target/loongarch/cpu.h| 57 ++ target/loongarch/internals.h | 7 + target/loongarch/machine.c

[RFC PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch.

This patch introduces all possible exceptions. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c | 13 + target/loongarch/cpu.h | 17 +++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu.c

[RFC PATCH v2 17/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)

Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76) Loongson-3A5000 and ls7a form a legacy model and extended model irq hierarchy.Tcg mode emulate a simplified extended model which has no Legacy I/O Interrupt Controller(LIOINTC) and LPC. e.g: |+-++-+

[RFC PATCH v2 12/30] target/loongarch: Add timer related instructions support.

This includes: -RDTIME{L/H}.W -RDTIME.D Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/helper.h | 1 + target/loongarch/insn_trans/trans_extra.c.inc | 32 +++ target/loongarch/op_helper.c | 4 +++

[RFC PATCH v2 10/30] target/loongarch: Add other core instructions support

This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.h | 2 + target/loongarch/helper.h| 4 + target/loongarch/insn_trans/trans_core.c.inc | 62 +++

[RFC PATCH v2 09/30] target/loongarch: Add TLB instruction support

This includes: - TLBSRCH - TLBRD - TLBWR - TLBFILL - TLBCLR - TLBFLUSH - INVTLB Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/helper.h| 8 + target/loongarch/insn_trans/trans_core.c.inc | 71 +++ target/loongarch/insns.decode|

[RFC PATCH v2 02/30] target/loongarch: Add CSR registers definition

1.Define All the CSR registers and its field. 2.Set some default csr values. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 334 + target/loongarch/cpu.c | 12 ++ target/loongarch/cpu.h | 127 ++ 3

[RFC PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions()

This patch introduces qmp_query_cpu_definitions interface. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- qapi/machine-target.json | 6 -- target/loongarch/cpu.c | 28 2 files changed, 32 insertions(+), 2

[RFC PATCH v2 08/30] target/loongarch: Add LoongArch CSR/IOCSR instruction

This includes: - CSRRD - CSRWR - CSRXCHG - IOCSR{RD/WR}.{B/H/W/D} Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/csr_helper.c| 322 ++ target/loongarch/helper.h| 11 + target/loongarch/insn_trans/trans_core.c.inc | 437

[RFC PATCH v2 01/30] target/loongarch: Update README

Mainly introduce how to run the softmmu Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/README | 20 1 file changed, 20 insertions(+) diff --git a/target/loongarch/README b/target/loongarch/README index 09f809cf80..6f64bde22f 100644 ---

[RFC PATCH v2 06/30] target/loongarch: Add stabletimer support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.h | 11 ++ target/loongarch/meson.build | 1 + target/loongarch/stabletimer.c | 70 ++ 3 files changed, 82 insertions(+) create mode 100644

[RFC PATCH v2 00/30] Add Loongarch softmmu support.

Sorry only part of the v2 patch succeed. I consulted GNU sysadmin, He said our mail server was getting temporarily banned by fail2ban. Now the ban was removed. I resend the v2 series patch. For uefi is preparing to submit to the community only uefi binary can be provided now. All of the series

[RFC PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU.

This patch introduces vmstate_loongarch_cpu Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c | 4 + target/loongarch/internals.h | 4 + target/loongarch/machine.c | 154 +++ target/loongarch/meson.build | 6 ++ 4

[PATCH v3 2/6] virtiofsd, fuse_lowlevel.c: Add capability to parse security context

Add capability to enable and parse security context as sent by client and put into fuse_req. Filesystems now can get security context from request and set it on files during creation. Signed-off-by: Vivek Goyal --- tools/virtiofsd/fuse_common.h | 5 ++ tools/virtiofsd/fuse_i.h| 7

[PATCH v3 6/6] virtiofsd: Add an option to enable/disable security label

Provide an option "-o security_label/no_security_label" to enable/disable security label functionality. By default these are turned off. If enabled, server will indicate to client that it is capable of handling one security label during file creation. Typically this is expected to be a SELinux

[PATCH v3 0/6] virtiofsd: Add support for file security context at creation

Hi, This is V3 of the patches. I posted V2 here. https://lore.kernel.org/qemu-devel/20211014153126.575173-1-vgo...@redhat.com/ Kernel patches are not upstream yet. So header files will need to be updated once kernel patches are merged. I posted V3 of kernel patches here.

[PATCH v3 1/6] fuse: Header file changes for FUSE_SECURITY_CTX

These are just header file changes which should show up in qemu if corresponding kernel changes get merged. Signed-off-by: Vivek Goyal --- include/standard-headers/linux/fuse.h | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git

[PATCH v3 5/6] virtiofsd: Create new file using O_TMPFILE and set security context

If guest and host policies can't work with each other, then guest security context (selinux label) needs to be set into an xattr. Say remap guest security.selinux xattr to trusted.virtiofs.security.selinux. That means setting "fscreate" is not going to help as that's ony useful for

[PATCH v3 3/6] virtiofsd: Move core file creation code in separate function

Move core file creation bits in a separate function. Soon this is going to get more complex as file creation need to set security context also. And there will be multiple modes of file creation in next patch. Signed-off-by: Vivek Goyal --- tools/virtiofsd/passthrough_ll.c | 36

[PATCH v3 4/6] virtiofsd: Create new file with fscreate set

This patch adds support to set /proc/thread-self/attr/fscreate before file creation. It is set to a value as sent by client. This will allow for atomic creation of security context on files w.r.t file creation. This is primarily useful when either there is no SELinux enabled on host or host and

Re: [RFC v2 6/6] *-user: move safe-syscall.* to common-user

On Wed, Nov 10, 2021 at 10:04 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 11/10/21 5:31 PM, Warner Losh wrote: > > Move linux-user/safe-syscall.S to common-user/common-safe-syscall.S and > > replace it with a #include "common-safe-syscall.S" so that bsd-user can > > also use

Re: [RFC v2 5/6] common-user/host/mips: create, though mips hosts likely don't work reliably

On Wed, Nov 10, 2021 at 10:00 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 11/10/21 5:31 PM, Warner Losh wrote: > > Signed-off-by: Warner Losh > > --- > > common-user/host/mips/safe-syscall.inc.S | 1 + > > 1 file changed, 1 insertion(+) > > create mode 100644

Re: [RFC v2 4/6] common-user: Adjust system call return on FreeBSD

On Wed, Nov 10, 2021 at 9:59 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 11/10/21 5:31 PM, Warner Losh wrote: > > All the *-users generally use the Linux style of negative return codes > > for errno. FreeBSD returns errno, not -errno. Add ifdefs for FreeBSD to > > make the

Re: [RFC v2 1/6] linux-user: Add host_signal_set_pc to set pc in mcontext

On Wed, Nov 10, 2021 at 9:42 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 11/10/21 5:31 PM, Warner Losh wrote: > > +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) > > +{ > > +#ifdef __arch64__ > > +uc->uc_mcontext.mc_gregs[MC_PC] = pc; > > +#else > > +

Re: [PATCH v3 3/3] hw/i386: expose a "smbios-entry-point-type" PC machine property

On Tue, Nov 02, 2021 at 07:25:25AM -0400, Michael S. Tsirkin wrote: > On Tue, Nov 02, 2021 at 09:51:35AM +0100, Philippe Mathieu-Daudé wrote: > > On 10/26/21 17:11, Eduardo Habkost wrote: > > > The i440fx and Q35 machine types are both hardcoded to use the > > > legacy SMBIOS 2.1 (32-bit) entry

Re: [PATCH] qmp: Stabilize preconfig

On 11/3/21 09:02, Markus Armbruster wrote: I wonder whether we really have to step through three states x-exit-preconfig cont preconfig ---> pre run ---> run and not two cont pre run ---> run Devices would be hotplugged between x-exit-preconfig and cont,

[PATCH for 6.2 v2 5/5] bios-tables-test: Update golden binaries

From: Julia Suvorova The changes are the result of 'hw/i386/acpi-build: Deny control on PCIe Native Hot-Plug in _OSC' and listed here: Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1)

[PATCH for 6.2 v2 4/5] hw/i386/acpi-build: Deny control on PCIe Native Hot-plug in _OSC

From: Julia Suvorova There are two ways to enable ACPI PCI Hot-plug: * Disable the Hot-plug Capable bit on PCIe slots. This was the first approach which led to regression [1-2], as I/O space for a port is allocated only when it is hot-pluggable, which is determined by HPC bit.

[PATCH for 6.2 v2 1/5] pcie: rename 'native-hotplug' to 'x-native-hotplug'

Mark property as experimental/internal adding 'x-' prefix. Property was introduced in 6.1 and it should have provided ability to turn on native PCIE hotplug on port even when ACPI PCI hotplug is in use is user explicitly sets property on CLI. However that never worked since slot is wired to ACPI

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