Re: [PATCH v1 28/43] target/loongarch: Add other core instructions support

On 4/15/22 02:40, Xiaojuan Yang wrote: This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 target/loongarch/helper.h | 5 +

Re: [PATCH v1 27/43] target/loongarch: Add TLB instruction support

On 4/15/22 02:40, Xiaojuan Yang wrote: This includes: - TLBSRCH - TLBRD - TLBWR - TLBFILL - TLBCLR - TLBFLUSH - INVTLB Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/disas.c | 18 + target/loongarch/helper.h | 13 +

[PATCH] target/rx: swap stack pointers on clrpsw/setpsw instruction

The control register field PSW.U determines which stack pointer register (ISP or USP) is mapped as R0. In QEMU, this is implemented by having a value copied between ISP or USP and R0 whenever PSW.U is updated or access to ISP/USP is made by an mvtc/mvic instruction. However, this update process

Re: [PATCH v10 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

On 4/15/22 19:35, Weiwei Li wrote: +target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2) +{ +return aes64_operation(rs1, rs2, true, true); +} + +target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2) +{ +return aes64_operation(rs1, rs2, true, false); +} +

Re: [PATCH v10 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

On 4/15/22 19:35, Weiwei Li wrote: +target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2, + target_ulong shamt) +{ +return aes32_operation(shamt, rs1, rs2, true, true); +} + +target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2, +

[PATCH v10 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 365bdd5fe5..973dd5ea47 100644 --- a/target/riscv/cpu.c +++

[PATCH v10 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/crypto_helper.c

[PATCH v10 12/14] target/riscv: rvk: add CSR support for Zkr

- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye

[PATCH v10 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 28 target/riscv/helper.h

[PATCH v10 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6

[PATCH v10 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- disas/riscv.c | 173 +- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c

[PATCH v10 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- crypto/meson.build | 1 + crypto/sm4.c | 49

[PATCH v10 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4

[PATCH v10 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 105

[PATCH v10 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++

[PATCH v10 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++

[PATCH v10 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++

[PATCH v10 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c

[PATCH v10 00/14] support subsets of scalar crypto extension

This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions. Partial instructions are reused from B-extension. Specification: https://github.com/riscv/riscv-crypto The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v10 To test rvk

[PATCH v10 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index faa41217d2..365bdd5fe5

Re: [PATCH v1 26/43] target/loongarch: Add LoongArch IOCSR instruction

On 4/15/22 02:40, Xiaojuan Yang wrote: +static bool trans_iocsrrd_b(DisasContext *ctx, arg_iocsrrd_b *a) +static bool trans_iocsrrd_h(DisasContext *ctx, arg_iocsrrd_h *a) +static bool trans_iocsrrd_w(DisasContext *ctx, arg_iocsrrd_w *a) +static bool trans_iocsrrd_d(DisasContext *ctx,

Re: [PATCH v1 25/43] target/loongarch: Add LoongArch CSR instruction

On 4/15/22 02:40, Xiaojuan Yang wrote: +int cpu_csr_offset(unsigned csr_num); ... +static const uint64_t csr_offsets[] = { There's no reason for this array to be uint64_t. It really should match the function. +target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val) +{ +

Re: [PATCH v1 24/43] target/loongarch: Add constant timer support

On 4/15/22 02:40, Xiaojuan Yang wrote: Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/constant_timer.c | 65 +++ target/loongarch/cpu.c| 2 + target/loongarch/cpu.h| 4 ++ target/loongarch/internals.h | 6

Re: [PATCH v1 23/43] target/loongarch: Add LoongArch interrupt and exception handle

On 4/15/22 02:40, Xiaojuan Yang wrote: +if (level) { +env->CSR_ESTAT |= 1 << irq; +} else { +env->CSR_ESTAT &= ~(1 << irq); +} This is env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); +static inline unsigned int get_vint_size(CPULoongArchState

Re: [PATCH v7 08/12] target/riscv: Add sscofpmf extension support

On Wed, Apr 13, 2022 at 12:08 AM Alistair Francis wrote: > > On Thu, Mar 31, 2022 at 10:19 AM Atish Patra wrote: > > > > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, > > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) > > extension allows the perf to

Re: [PATCH v1 20/43] target/loongarch: Add basic vmstate description of CPU.

On 4/15/22 02:40, Xiaojuan Yang wrote: +const VMStateDescription vmstate_loongarch_cpu = { +.name = "cpu", +.version_id = 0, +.minimum_version_id = 0, +.fields = (VMStateField[]) { + +VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32), +VMSTATE_UINTTL(env.pc,

Re: [PATCH v1 18/43] target/loongarch: Add system emulation introduction

On 4/15/22 02:40, Xiaojuan Yang wrote: Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 8 + docs/system/loongarch/loongson3.rst | 41 ++ target/loongarch/README | 54 + 3 files

Re: [PATCH v1 09/43] target/loongarch: Add fixed point extra instruction translation

On 4/15/22 02:40, Xiaojuan Yang wrote: @@ -45,13 +47,37 @@ target_ulong helper_bitswap(target_ulong v) void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) { if (rj > rk) { -do_raise_exception(env, EXCP_ADE, GETPC()); +do_raise_exception(env,

Re: [PATCH v1 08/43] target/loongarch: Add fixed point atomic instruction translation

On 4/15/22 02:40, Xiaojuan Yang wrote: +static bool gen_ll(DisasContext *ctx, arg_rr_i *a, + void (*func)(TCGv, TCGv, int)) +{ +TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); +TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); +TCGv t0 = tcg_temp_new(); + +

Re: [PATCH] hw/nvme: fix control flow statement

On Fri, Apr 15, 2022 at 21:42:05, Klaus Jensen wrote: > On Apr 15 13:35, Keith Busch wrote: > > On Fri, Apr 15, 2022 at 10:27:21PM +0300, Dmitry Tikhov wrote: > > > Since there is no else after nvme_dsm_cb invocation, metadata associated > > > with non-zero block range is currently zeroed. Also

[PATCH v2] hw/nvme: add missing return statement

Since there is no return after nvme_dsm_cb invocation, metadata associated with non-zero block range is currently zeroed. Also this behaviour leads to segfault since we schedule iocb->bh two times. First when entering nvme_dsm_cb with iocb->idx == iocb->nr and second because of missing return on

[PATCH] hw/nvme: fix control flow statement

Since there is no else after nvme_dsm_cb invocation, metadata associated with non-zero block range is currently zeroed. Also this behaviour leads to segfault since we schedule iocb->bh two times. First when entering nvme_dsm_cb with iocb->idx == iocb->nr and second on call stack unwinding by

Re: [PATCH] hw/nvme: fix control flow statement

On Apr 15 23:23, Dmitry Tikhov wrote: > On Fri, Apr 15, 2022 at 21:42:05, Klaus Jensen wrote: > > On Apr 15 13:35, Keith Busch wrote: > > > On Fri, Apr 15, 2022 at 10:27:21PM +0300, Dmitry Tikhov wrote: > > > > Since there is no else after nvme_dsm_cb invocation, metadata associated > > > > with

Re: [PATCH] hw/nvme: fix control flow statement

On Apr 15 13:35, Keith Busch wrote: > On Fri, Apr 15, 2022 at 10:27:21PM +0300, Dmitry Tikhov wrote: > > Since there is no else after nvme_dsm_cb invocation, metadata associated > > with non-zero block range is currently zeroed. Also this behaviour leads > > to segfault since we schedule iocb->bh

Re: [PATCH] hw/nvme: fix control flow statement

On Fri, Apr 15, 2022 at 10:27:21PM +0300, Dmitry Tikhov wrote: > Since there is no else after nvme_dsm_cb invocation, metadata associated > with non-zero block range is currently zeroed. Also this behaviour leads > to segfault since we schedule iocb->bh two times. First when entering > nvme_dsm_cb

Re: [PATCH v2 for-7.1 3/9] nbd: remove peppering of nbd_client_connected

14.04.2022 20:57, Paolo Bonzini wrote: It is unnecessary to check nbd_client_connected() because every time s->state is moved out of NBD_CLIENT_CONNECTED the socket is shut down and all coroutines are resumed. The only case where it was actually needed is when the NBD server disconnects and

Re: [PATCH v2 1/6] hw/riscv: virt: Add a machine done notifier

Hi Alistair, On Wed, Apr 6, 2022 at 10:05 PM Alistair Francis wrote: > > From: Alistair Francis > > Move the binary and device tree loading code to the machine done > notifier. This allows us to prepare for editing the device tree as part > of the notifier. > > This is based on similar code in

[PATCH 25/26] migration: add missing coroutine_fn annotations

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Reviewed-by: Juan Quintela Reviewed-by: Stefan Hajnoczi Signed-off-by: Paolo Bonzini --- migration/migration.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/migration/migration.c b/migration/migration.c index

[PATCH 23/26] raw-format: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/raw-format.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/raw-format.c b/block/raw-format.c index 69fd650eaf..45440345b6 100644 --- a/block/raw-format.c +++ b/block/raw-format.c @@ -411,7 +411,7 @@ static void

[PATCH 22/26] coroutine-lock: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- util/qemu-coroutine-lock.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/util/qemu-coroutine-lock.c b/util/qemu-coroutine-lock.c index 2669403839..ec55490b52 100644 --- a/util/qemu-coroutine-lock.c +++

[PATCH 20/26] vmdk: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/vmdk.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/block/vmdk.c b/block/vmdk.c index 37c0946066..27d3732255 100644 --- a/block/vmdk.c +++ b/block/vmdk.c @@ -1741,10 +1741,10 @@ static int coroutine_fn

[PATCH 17/26] qed: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/qed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/block/qed.c b/block/qed.c index f34d9a3ac1..208128d679 100644 --- a/block/qed.c +++ b/block/qed.c @@ -259,7 +259,7 @@ static CachedL2Table *qed_new_l2_table(BDRVQEDState *s)

[PATCH 21/26] job: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- include/qemu/job.h | 2 +- job.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/job.h b/include/qemu/job.h index c105b31076..397ac39608 100644 --- a/include/qemu/job.h +++ b/include/qemu/job.h @@ -436,7 +436,7 @@

[PATCH 16/26] curl: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/curl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/curl.c b/block/curl.c index 1e0f609579..cba4c4cac7 100644 --- a/block/curl.c +++ b/block/curl.c @@ -855,7 +855,7 @@ out_noclean: return -EINVAL; } -static void

[PATCH 15/26] copy-before-write: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/copy-before-write.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/block/copy-before-write.c b/block/copy-before-write.c index a8a06fdc09..5ad9693b13 100644 --- a/block/copy-before-write.c +++ b/block/copy-before-write.c @@

[PATCH 14/26] qcow2: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/qcow2-cluster.c | 18 +- block/qcow2-refcount.c | 2 +- block/qcow2.c | 4 ++-- block/qcow2.h | 14 +++--- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/block/qcow2-cluster.c

[PATCH 19/26] throttle: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/throttle.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/throttle.c b/block/throttle.c index 6e8d52fa24..ddd450593a 100644 --- a/block/throttle.c +++ b/block/throttle.c @@ -162,7 +162,7 @@ static int coroutine_fn

[PATCH 10/26] nbd: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/nbd.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/block/nbd.c b/block/nbd.c index 5af4deac3f..a4c8d661ad 100644 --- a/block/nbd.c +++ b/block/nbd.c @@ -974,11 +974,11 @@ static void nbd_iter_request_error(NBDReplyChunkIter

[PATCH 12/26] nvme: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/nvme.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index 01fb28aa63..6519697e40 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -1234,8 +1234,9 @@ static inline bool nvme_qiov_aligned(BlockDriverState

[PATCH 26/26] test-coroutine: add missing coroutine_fn annotations

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Message-Id: <20170704220346.29244-4-marcandre.lur...@redhat.com> Signed-off-by: Paolo Bonzini --- tests/unit/test-coroutine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/unit/test-coroutine.c

[PATCH 09/26] iscsi: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/iscsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/iscsi.c b/block/iscsi.c index d707d0b354..b33eeec794 100644 --- a/block/iscsi.c +++ b/block/iscsi.c @@ -290,7 +290,7 @@ iscsi_co_generic_cb(struct iscsi_context *iscsi, int

[PATCH 18/26] quorum: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/quorum.c | 35 ++- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/block/quorum.c b/block/quorum.c index f33f30d36b..5ff69d7443 100644 --- a/block/quorum.c +++ b/block/quorum.c @@ -161,11 +161,10 @@ static

[PATCH 11/26] nfs: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/nfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/nfs.c b/block/nfs.c index 444c40b458..596ebe98cb 100644 --- a/block/nfs.c +++ b/block/nfs.c @@ -223,7 +223,7 @@ static void nfs_process_write(void *arg)

[PATCH 24/26] 9p: add missing coroutine_fn annotations

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Acked-by: Greg Kurz Signed-off-by: Paolo Bonzini --- hw/9pfs/9p.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/9pfs/9p.h b/hw/9pfs/9p.h index 994f952600..a523ac34a9 100644 --- a/hw/9pfs/9p.h +++

[PATCH 08/26] file-posix: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/file-posix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/file-posix.c b/block/file-posix.c index bfd9b2..cf7b5531c8 100644 --- a/block/file-posix.c +++ b/block/file-posix.c @@ -2143,7 +2143,7 @@ static void

[PATCH 05/26] blkdebug: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/blkdebug.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/block/blkdebug.c b/block/blkdebug.c index bbf2948703..a93ba61487 100644 --- a/block/blkdebug.c +++ b/block/blkdebug.c @@ -587,8 +587,8 @@ out: return ret; }

[PATCH 04/26] coroutine: remove incorrect coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- include/qemu/coroutine.h | 2 +- util/qemu-coroutine.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/coroutine.h b/include/qemu/coroutine.h index 284571badb..2d9211faff 100644 --- a/include/qemu/coroutine.h +++

[PATCH 13/26] parallels: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/parallels.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 8879b7027a..bee2ff023d 100644 --- a/block/parallels.c +++ b/block/parallels.c @@ -165,8 +165,9 @@ static int64_t

[PATCH 03/26] nbd: remove incorrect coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- include/block/nbd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/block/nbd.h b/include/block/nbd.h index a98eb665da..5c3710fa52 100644 --- a/include/block/nbd.h +++ b/include/block/nbd.h @@ -423,6 +423,6 @@ QIOChannel *coroutine_fn

[PATCH 06/26] blkverify: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/blkverify.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/blkverify.c b/block/blkverify.c index e4a37af3b2..020b1ae7b6 100644 --- a/block/blkverify.c +++ b/block/blkverify.c @@ -258,7 +258,7 @@

[PATCH 07/26] block: add missing coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/block-backend.c | 18 +- block/io.c| 24 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/block/block-backend.c b/block/block-backend.c index fedf2eca83..52009b8949 100644 ---

[PATCH 02/26] qcow2: remove incorrect coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/qcow2-refcount.c | 4 ++-- block/qcow2.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c index b91499410c..b6f90b2702 100644 --- a/block/qcow2-refcount.c +++

[PATCH 01/26] block: remove incorrect coroutine_fn annotations

Signed-off-by: Paolo Bonzini --- block/block-backend.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/block/block-backend.c b/block/block-backend.c index e0e1aff4b1..fedf2eca83 100644 --- a/block/block-backend.c +++ b/block/block-backend.c @@ -1391,10 +1391,10 @@ int

[PATCH 00/19] block: fix coroutine_fn annotations

This is the initial result of reviving Marc-André's series at https://patchew.org/QEMU/20170704220346.29244-1-marcandre.lur...@redhat.com/. A lot of the patches are similar to the ones that Marc-André wrote, but due to the changes in the code it was easier to redo them. For nbd, the patch is on

Re: [PATCH v1] virtio/virtio.c: include virtio prefix in error message

Moteen Shah writes: > From: Moteen Shah > > The error message in virtio_init_region_cache() > is given a prefix virtio. It seems a shame considering we have a common virtio_error function that we couldn't do it in one place. One option would be to make virtio_error a macro that could insert

Re: [PATCH v2 for-7.1 2/9] nbd: mark more coroutine_fns

14.04.2022 20:57, Paolo Bonzini wrote: Several coroutine functions in block/nbd.c are not marked as such. This patch adds a few more markers; it is not exhaustive, but it focuses especially on: - places that wake other coroutines, because aio_co_wake() has very different semantics inside a

[PATCH v1 39/43] hw/loongarch: Add LoongArch ls7a rtc device support

This patch add ls7a rtc device support. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS| 1 + hw/loongarch/Kconfig | 1 + hw/loongarch/loongson3.c | 4 + hw/rtc/Kconfig | 3 + hw/rtc/ls7a_rtc.c | 323

[PATCH v1 32/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI)

This patch realize the IPI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 2 + hw/intc/Kconfig | 3 + hw/intc/loongarch_ipi.c | 145 +++ hw/intc/meson.build

[PATCH v1 41/43] hw/loongarch: Add LoongArch ls7a acpi device support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS| 2 + hw/acpi/Kconfig| 4 + hw/acpi/ls7a.c | 374 + hw/acpi/meson.build| 1 + hw/loongarch/Kconfig | 2 +

[PATCH v1 07/43] target/loongarch: Add fixed point load/store instruction translation

From: Song Gao This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson ---

[PATCH v1 22/43] target/loongarch: Add MMU support for LoongArch CPU.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu-param.h | 2 +- target/loongarch/cpu.c| 24 +++ target/loongarch/cpu.h| 51 ++ target/loongarch/internals.h | 9 + target/loongarch/machine.c| 17 ++

[PATCH v1 28/43] target/loongarch: Add other core instructions support

This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 target/loongarch/helper.h | 5 + .../insn_trans/trans_privileged.c.inc | 65 +

[PATCH v1 37/43] Enable common virtio pci support for LoongArch

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- softmmu/qdev-monitor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c index 12fe60c467..bb5897fc76 100644 --- a/softmmu/qdev-monitor.c

[PATCH v1 24/43] target/loongarch: Add constant timer support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/constant_timer.c | 65 +++ target/loongarch/cpu.c| 2 + target/loongarch/cpu.h| 4 ++ target/loongarch/internals.h | 6 +++ target/loongarch/meson.build |

Re: [PATCH v2 for-7.1 1/9] nbd: safeguard against waking up invalid coroutine

14.04.2022 20:57, Paolo Bonzini wrote: The .reply_possible field of s->requests is never set to false. This is not a problem as it is only a safeguard to detect protocol errors, but it's sloppy. In fact, the field is actually not necessary at all, because .coroutine is set to NULL in

[PATCH v1 21/43] target/loongarch: Implement qmp_query_cpu_definitions()

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- qapi/machine-target.json | 6 -- target/loongarch/cpu.c | 26 ++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/qapi/machine-target.json

[PATCH v1 29/43] target/loongarch: Add timer related instructions support.

This includes: -RDTIME{L/H}.W -RDTIME.D Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/disas.c | 3 ++ target/loongarch/helper.h | 2 ++ target/loongarch/insn_trans/trans_extra.c.inc | 33 +++

[PATCH v1 26/43] target/loongarch: Add LoongArch IOCSR instruction

This includes: - IOCSR{RD/WR}.{B/H/W/D} Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.h| 3 + target/loongarch/disas.c | 8 + target/loongarch/helper.h | 2 +

[PATCH v1 23/43] target/loongarch: Add LoongArch interrupt and exception handle

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c | 261 +++ target/loongarch/cpu.h | 2 + target/loongarch/internals.h | 2 + 3 files changed, 265 insertions(+) diff --git a/target/loongarch/cpu.c

[PATCH v1 15/43] target/loongarch: Add branch instruction translation

From: Song Gao This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- .../loongarch/insn_trans/trans_branch.c.inc | 83 +++ target/loongarch/insns.decode

[PATCH v1 38/43] hw/loongarch: Add some devices support for 3A5000.

1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the pci host. Non pci device use irq 0-16, pci device use 16-64. 3.Add some unimplented device to emulate guest unused memory space. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 7

[PATCH v1 35/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig| 3 + hw/intc/loongarch_extioi.c | 373 + hw/intc/meson.build| 1 + hw/intc/trace-events

[PATCH v1 34/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig | 5 ++ hw/intc/loongarch_pch_msi.c | 75 + hw/intc/meson.build | 1 + hw/intc/trace-events

[PATCH v1 18/43] target/loongarch: Add system emulation introduction

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 8 + docs/system/loongarch/loongson3.rst | 41 ++ target/loongarch/README | 54 + 3 files changed, 103 insertions(+) create mode

[PATCH v1 33/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

This patch realize the PCH-PIC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 1 + hw/intc/Kconfig | 4 + hw/intc/loongarch_pch_pic.c | 488 hw/intc/meson.build

[PATCH v1 30/43] target/loongarch: Add gdb support.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 2 + configs/targets/loongarch64-softmmu.mak | 1 + gdb-xml/loongarch-base64.xml| 44 ++ gdb-xml/loongarch-fpu64.xml | 57 +

[PATCH v1 36/43] hw/loongarch: Add irq hierarchy for the system

This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c | 106 +++ 1 file changed, 106 insertions(+) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index

[PATCH v1 25/43] target/loongarch: Add LoongArch CSR instruction

This includes: - CSRRD - CSRWR - CSRXCHG Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h| 2 + target/loongarch/csr_helper.c | 186 ++ target/loongarch/disas.c | 15 ++

[PATCH v1 20/43] target/loongarch: Add basic vmstate description of CPU.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 1 + target/loongarch/internals.h | 2 + target/loongarch/machine.c | 85 target/loongarch/meson.build | 6 +++ 4 files changed, 94

[PATCH v1 13/43] target/loongarch: Add floating point move instruction translation

From: Song Gao This includes: - FMOV.{S/D} - FSEL - MOVGR2FR.{W/D}, MOVGR2FRH.W - MOVFR2GR.{S/D}, MOVFRH2GR.S - MOVGR2FCSR, MOVFCSR2GR - MOVFR2CF, MOVCF2FR - MOVGR2CF, MOVCF2GR Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson ---

[PATCH v1 40/43] hw/loongarch: Add LoongArch boot code and load elf function.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c | 68 +++- include/hw/loongarch/loongarch.h | 8 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index

[PATCH v1 43/43] target/loongarch: 'make check-tcg' support

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Acked-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- tests/tcg/configure.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index

[PATCH v1 14/43] target/loongarch: Add floating point load/store instruction translation

From: Song Gao This includes: - FLD.{S/D}, FST.{S/D} - FLDX.{S/D}, FSTX.{S/D} - FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D} Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- .../loongarch/insn_trans/trans_fmemory.c.inc | 153 ++

[PATCH v1 16/43] target/loongarch: Add disassembler

From: Song Gao This patch adds support for disassembling via option '-d in_asm'. Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- include/disas/dis-asm.h | 2 + meson.build | 1 + target/loongarch/disas.c | 610

[PATCH v1 12/43] target/loongarch: Add floating point conversion instruction translation

From: Song Gao This includes: - FCVT.S.D, FCVT.D.S - FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D} - FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D} - FRINT.{S/D} Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- target/loongarch/fpu_helper.c| 393

[PATCH v1 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system

- We write a very minimal softmmu harness. - This is a very simple smoke test with no need to run a full Linux/kernel. - The Makefile.softmmu-target record the rule to run. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 1 +

[PATCH v1 11/43] target/loongarch: Add floating point comparison instruction translation

From: Song Gao This includes: - FCMP.cond.{S/D} Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- target/loongarch/fpu_helper.c| 60 target/loongarch/helper.h| 9 +++

[PATCH v1 17/43] target/loongarch: Add target build suport

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/loongarch/meson.build | 19 +++ target/meson.build | 1 + 2 files changed, 20 insertions(+) create mode 100644

[PATCH v1 10/43] target/loongarch: Add floating point arithmetic instruction translation

From: Song Gao This includes: - F{ADD/SUB/MUL/DIV}.{S/D} - F{MADD/MSUB/NMADD/NMSUB}.{S/D} - F{MAX/MIN}.{S/D} - F{MAXA/MINA}.{S/D} - F{ABS/NEG}.{S/D} - F{SQRT/RECIP/RSQRT}.{S/D} - F{SCALEB/LOGB/COPYSIGN}.{S/D} - FCLASS.{S/D} Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by:

[PATCH v1 19/43] target/loongarch: Add CSRs definition

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu-csr.h | 201 + target/loongarch/cpu.c | 36 +++ target/loongarch/cpu.h | 65 3 files changed, 302 insertions(+) create

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