[PULL 14/53] include/qapi: add g_autoptr support for qobject types

From: Marc-André Lureau Need wrappers for qobject_unref() calls, which is a macro. Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster Reviewed-by: Richard Henderson Message-Id: <20220323155743.1585078-10-marcandre.lur...@redhat.com> Signed-off-by: Paolo Bonzini ---

[PULL 06/53] meson: use chardev_ss dependencies

From: Marc-André Lureau chardev subsystem/library doesn't use gnutls. Use the dedicated chardev_ss.dependencies() instead. Looking at history, it was added in commit 3eacf70bb5a83e ("meson: Propagate gnutls dependency") because crypto/tlscreds.h included GnuTLS. This was cleaned-up later by

[PULL 02/53] qtest: replace gettimeofday with GTimer

From: Marc-André Lureau glib provides a convenience helper to measure elapsed time. It isn't subject to wall-clock time changes. Note that this changes the initial OPENED time, which used to print the current time. Signed-off-by: Marc-André Lureau Reviewed-by: Laurent Vivier Message-Id:

[PULL 03/53] qga: replace qemu_gettimeofday() with g_get_real_time()

From: Marc-André Lureau GLib g_get_real_time() is an alternative to gettimeofday() which allows to simplify our code. Signed-off-by: Marc-André Lureau Reviewed-by: Laurent Vivier Reviewed-by: Thomas Huth Message-Id: <20220307070401.171986-4-marcandre.lur...@redhat.com> Signed-off-by: Paolo

[PULL 01/53] qapi, target/i386/sev: Add cpu0-id to query-sev-capabilities

From: Dov Murik Add a new field 'cpu0-id' to the response of query-sev-capabilities QMP command. The value of the field is the base64-encoded unique ID of CPU0 (socket 0), which can be used to retrieve the signed CEK of the CPU from AMD's Key Distribution Service (KDS). Signed-off-by: Dov

[PULL 05/53] oslib: drop qemu_gettimeofday()

From: Marc-André Lureau No longer used after the previous patches. Signed-off-by: Marc-André Lureau Reviewed-by: Laurent Vivier Reviewed-by: Stefan Weil Reviewed-by: Richard Henderson Message-Id: <20220307070401.171986-6-marcandre.lur...@redhat.com> Signed-off-by: Paolo Bonzini ---

[PULL 04/53] Replace qemu_gettimeofday() with g_get_real_time()

From: Marc-André Lureau GLib g_get_real_time() is an alternative to gettimeofday() which allows to simplify our code. For semihosting, a few bits are lost on POSIX host, but this shouldn't be a big concern. Signed-off-by: Marc-André Lureau Reviewed-by: Laurent Vivier Message-Id:

Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis wrote: > > On Fri, Apr 15, 2022 at 7:37 PM wrote: > > > > From: Frank Chang > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > -cpu command line option. > > > > Signed-off-by: Frank Chang > > Reviewed-by: Jim Shu > >

Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Fri, Apr 15, 2022 at 7:37 PM wrote: > > From: Frank Chang > > Allow user to set core's marchid, mvendorid, mipid CSRs through > -cpu command line option. > > Signed-off-by: Frank Chang > Reviewed-by: Jim Shu > --- > target/riscv/cpu.c | 4 > target/riscv/cpu.h | 4 >

Re: [PATCH qemu v7 02/14] target/riscv: rvv: Rename ambiguous esz

On Wed, Mar 30, 2022 at 8:30 PM ~eopxd wrote: > > From: eopXD > > No functional change intended in this commit. > > Signed-off-by: eop Chen > Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/vector_helper.c | 76 ++-- > 1

Re: [PATCH v2 1/6] hw/riscv: virt: Add a machine done notifier

On Sat, Apr 16, 2022 at 1:25 AM Andrew Bresticker wrote: > > Hi Alistair, > > On Wed, Apr 6, 2022 at 10:05 PM Alistair Francis > wrote: > > > > From: Alistair Francis > > > > Move the binary and device tree loading code to the machine done > > notifier. This allows us to prepare for editing the

Re: [PATCH qemu v7 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

On Wed, Mar 30, 2022 at 8:50 PM ~eopxd wrote: > > From: eopXD > > No functional change intended in this commit. > > Signed-off-by: eop Chen > Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/vector_helper.c | 1132 +- > 1

Re: [PATCH] target/riscv/pmp: fix NAPOT range computation overflow

On Sat, Apr 9, 2022 at 2:25 AM Nicolas Pitre wrote: > > There is an overflow with the current code where a pmpaddr value of > 0x1fff is decoded as sa=0 and ea=0 whereas it should be sa=0 and > ea=0x. > > Fix that by simplifying the computation. There is in fact no need for > ctz64()

Re: [RFC 00/18] vfio: Adopt iommufd

On Sun, Apr 17, 2022 at 12:30:40PM +0200, Eric Auger wrote: > >> - More tests > > I did a quick test on my ARM64 platform, using "iommu=smmuv3" > > string. The behaviors are different between using default and > > using legacy "iommufd=off". > > > > The legacy pathway exits the VM with: > >

Re: [PATCH] chardev: avoid use-after-free when client disconnect

> Hi > > On Mon, Mar 28, 2022 at 12:22 PM Hogan Wang via wrote: > > IOWatchPoll object did not hold the @ioc and @src objects reference, > > then io_watch_poll_prepare execute in IO thread, if IOWatchPoll > > removed by mian thread, io_watch_poll_prepare may execute at last > > chance and access

Re: [PATCH] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled

On Fri, Apr 15, 2022 at 1:56 AM Niklas Cassel via wrote: > > The device tree property "mmu-type" is currently exported as either > "riscv,sv32" or "riscv,sv48". > > However, the riscv cpu device tree binding [1] has a specific value > "riscv,none" for a HART without a MMU. > > Set the device tree

[PATCH v11 12/14] target/riscv: rvk: add CSR support for Zkr

- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye

Re: XIVE VFIO kernel resample failure in INTx mode under heavy load

On 14/04/2022 22:31, Cédric Le Goater wrote: Hello Alexey, Thanks for taking over. On 4/13/22 06:56, Alexey Kardashevskiy wrote: On 3/17/22 06:16, Cédric Le Goater wrote: Timothy, On 3/16/22 17:29, Cédric Le Goater wrote: Hello, I've been struggling for some time with what is

[PATCH v11 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 365bdd5fe5..973dd5ea47 100644 --- a/target/riscv/cpu.c +++

[PATCH v11 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++

[PATCH v11 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- disas/riscv.c | 173 +- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c

Re: [PATCH v1 35/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

On 2022/4/18 下午4:57, Mark Cave-Ayland wrote: On 18/04/2022 04:48, Richard Henderson wrote: On 4/15/22 02:40, Xiaojuan Yang wrote: + memory_region_init(>mmio[cpu], OBJECT(s), +   "loongarch_extioi", EXTIOI_SIZE); + +    memory_region_init_io(>mmio_nodetype[cpu],

[PATCH v11 00/14] support subsets of scalar crypto extension

This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions. Partial instructions are reused from B-extension. Specification: https://github.com/riscv/riscv-crypto The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v11 To test rvk

[PATCH v11 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6

[PATCH v11 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 105

[PATCH v11 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index faa41217d2..365bdd5fe5

[PATCH v11 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- crypto/meson.build | 1 + crypto/sm4.c | 49

[PATCH v11 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++

[PATCH v11 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 28 target/riscv/helper.h

[PATCH v11 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4

[PATCH v11 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/crypto_helper.c

[PATCH v11 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c

[PATCH v11 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++

Re: [RFC PATCH v3 2/5] ppc64: Fix semihosting on ppc64le

On 4/18/22 12:10, Leandro Lupori wrote: +static inline uint64_t sh_swap64(CPUArchState *env, uint64_t val) +{ +return msr_le ? val : tswap64(val); +} + +static inline uint32_t sh_swap32(CPUArchState *env, uint32_t val) +{ +return msr_le ? val : tswap32(val); +} That doesn't work --

Re: [PATCH 2/2] Use io_ring_register_ring_fd() to skip fd operations

Thanks for noticing the problem. I've done that. Sam Damien Le Moal 于2022年4月19日周二 06:24写道： > On 2022/04/18 18:05, Sam Li wrote: > > fix code style issue. > > This patch must be squashed into the previous one. > > > > > Signed-off-by: Sam Li > > --- > > block/io_uring.c | 9 +++-- > > 1

[PATCH v3] Use io_uring_register_ring_fd() to skip fd operations

Linux recently added a new io_uring(7) optimization API that QEMU doesn't take advantage of yet. The liburing library that QEMU uses has added a corresponding new API calling io_uring_register_ring_fd(). When this API is called after creating the ring, the io_uring_submit() library function passes

Re: [RFC PATCH v3 1/5] ppc64: Add semihosting support

On 4/18/22 12:10, Leandro Lupori wrote: Add semihosting support for PPC64. This implementation is based on the standard for ARM semihosting version 2.0, as implemented by QEMU and documented in https://github.com/ARM-software/abi-aa/releases The PPC64 specific differences are the

Re: [PATCH 2/4] TCG support for AVX

On 4/18/22 12:45, Paul Brook wrote: Unfortunately the table driven decoding means that going from two to three operands tends to be a bit all or nothing just to get the thing to compile. Yes, gen_sse is awful. Which is why the previous attempt at AVX2 rewrote the decoder:

Re: [PATCH v7 08/12] target/riscv: Add sscofpmf extension support

On Sat, Apr 16, 2022 at 9:54 AM Atish Kumar Patra wrote: > > On Wed, Apr 13, 2022 at 12:08 AM Alistair Francis > wrote: > > > > On Thu, Mar 31, 2022 at 10:19 AM Atish Patra wrote: > > > > > > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, > > > and 'cofpmf' for Count

Re: [RFC PATCH v3 3/5] tests/tcg/ppc64: Add basic softmmu test support

On 4/18/22 17:27, Cédric Le Goater wrote: On 4/18/22 21:10, Leandro Lupori wrote: Add support to build and run the multiarch hello test, that simply prints a message and exits, through semihosting operations. The linker script was imported from https://github.com/legoater/pnv-test, that are

[PATCH v3 12/12] iotests: make qemu_io_log() check return codes by default

Just like qemu_img_log(), upgrade qemu_io_log() to enforce a return code of zero by default. Tests that use qemu_io_log(): 242 245 255 274 303 307 nbd-reconnect-on-open Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Hanna Reitz --- tests/qemu-iotests/iotests.py

[PATCH v3 03/12] iotests: Don't check qemu_io() output for specific error strings

A forthcoming commit updates qemu_io() to raise an exception on non-zero return by default, and changes its return type. In preparation, simplify some calls to qemu_io() that assert that specific error message strings do not appear in qemu-io's output. Asserting that all of these calls return a

[PATCH v3 10/12] iotests: remove qemu_io_pipe_and_status()

I know we just added it, sorry. This is done in favor of qemu_io() which *also* returns the console output and status, but with more robust error handling on failure. Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Hanna Reitz --- tests/qemu-iotests/iotests.py | 3 --- 1 file

[PATCH v3 11/12] iotests: remove qemu_io_silent() and qemu_io_silent_check().

Like qemu-img, qemu-io returning 0 should be the norm and not the exception. Remove all calls to qemu_io_silent that just assert the return code is zero (That's every last call, as it turns out), and replace them with a normal qemu_io() call. qemu_io_silent_check() appeared to have been unused

[PATCH v3 00/12] iotests: add enhanced debugging info to qemu-io failures

GitLab: https://gitlab.com/jsnow/qemu/-/commits/iotests_qemu_io_diagnostics Howdy, This series does for qemu_io() what we've done for qemu_img() and makes it a function that checks the return code by default and raises an Exception when things do not go according to plan. This series removes

[PATCH v3 06/12] iotests: create generic qemu_tool() function

reimplement qemu_img() in terms of qemu_tool() in preparation for doing the same with qemu_io(). Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Hanna Reitz --- tests/qemu-iotests/iotests.py | 32 +--- 1 file changed, 21 insertions(+), 11 deletions(-)

[PATCH v3 08/12] iotests/migration-permissions: use assertRaises() for qemu_io() negative test

Modify this test to use assertRaises for its negative testing of qemu_io. If the exception raised does not match the one we tell it to expect, we get *that* exception unhandled. If we get no exception, we get a unittest assertion failure and the provided emsg printed to screen. If we get the

[PATCH v3 05/12] iotests/040: Fix TestCommitWithFilters test

Without this change, asserting that qemu_io always returns 0 causes this test to fail in a way we happened not to be catching previously: qemu.utils.VerboseProcessError: Command '('/home/jsnow/src/qemu/bin/git/tests/qemu-iotests/../../qemu-io', '--cache', 'writeback', '--aio', 'threads',

[PATCH v3 07/12] iotests: rebase qemu_io() on top of qemu_tool()

Rework qemu_io() to be analogous to qemu_img(); a function that requires a return code of zero by default unless disabled explicitly. Tests that use qemu_io(): 030 040 041 044 055 056 093 124 129 132 136 148 149 151 152 163 165 205 209 219 236 245 248 254 255 257 260 264 280 298 300 302 304

[PATCH v3 04/12] iotests/040: Don't check image pattern on zero-length image

qemu-io fails on read/write beyond end-of-file on raw images, so skip these invocations when running the zero-length image tests. Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Hanna Reitz --- tests/qemu-iotests/040 | 14 -- 1 file changed, 12 insertions(+), 2

[PATCH v3 09/12] iotests/image-fleecing: switch to qemu_io()

This test expects failure ... but only sometimes. When? Why? It's for reads of a region not defined by a bitmap. Adjust the test to be more explicit about what it expects to fail and why. Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Hanna Reitz ---

[PATCH v3 01/12] iotests: replace calls to log(qemu_io(...)) with qemu_io_log()

This makes these callsites a little simpler, but the real motivation is a forthcoming commit will change the return type of qemu_io(), so removing users of the return value now is helpful. Signed-off-by: John Snow Reviewed-by: Eric Blake Reviewed-by: Hanna Reitz --- tests/qemu-iotests/242 | 6

[PATCH v3 02/12] iotests/163: Fix broken qemu-io invocation

The 'read' commands to qemu-io were malformed, and this invocation only worked by coincidence because the error messages were identical. Oops. There's no point in checking the patterning of the reference image, so just check the empty image by itself instead. (Note: as of this commit, nothing

Re: [RFC PATCH v3 3/5] tests/tcg/ppc64: Add basic softmmu test support

On 4/18/22 21:10, Leandro Lupori wrote: Add support to build and run the multiarch hello test, that simply prints a message and exits, through semihosting operations. The linker script was imported from https://github.com/legoater/pnv-test, that are the Microwatt tests adapted to use a PowerNV

Re: [RFC PATCH v3 1/5] ppc64: Add semihosting support

On 4/18/22 21:10, Leandro Lupori wrote: Add semihosting support for PPC64. This implementation is based on the standard for ARM semihosting version 2.0, as implemented by QEMU and documented in https://github.com/ARM-software/abi-aa/releases The PPC64 specific differences are the

Re: [PATCH 2/4] TCG support for AVX

On Mon, 18 Apr 2022 at 20:45, Paul Brook wrote: > > On Mon, 2022-04-18 at 20:33 +0100, Peter Maydell wrote: > > On Mon, 18 Apr 2022 at 18:48, Paul Brook wrote: > > > > > > Add TCG translation of guest AVX/AVX2 instructions > > > This comprises: > > > > > > > Massively too large for a single

Re: [PATCH 2/4] TCG support for AVX

On Mon, 2022-04-18 at 20:33 +0100, Peter Maydell wrote: > On Mon, 18 Apr 2022 at 18:48, Paul Brook wrote: > > > > Add TCG translation of guest AVX/AVX2 instructions > > This comprises: > > > > Massively too large for a single patch, I'm afraid. This needs > to be split, probably into at least

Re: [PATCH 2/4] TCG support for AVX

On Mon, 18 Apr 2022 at 18:48, Paul Brook wrote: > > Add TCG translation of guest AVX/AVX2 instructions > This comprises: > > * VEX encodings of most (all?) "legacy" SSE operations. > These typically add an extra source operand, and clear the unused half > of the destination register (SSE

[RFC PATCH v3 4/5] tests/tcg/ppc64: Add MMU test sources

Add MMU test sources, from https://github.com/legoater/pnv-test, based on Microwatt tests but with some adaptations. In particular, the tests that check updates to RC bits were removed, because, apparently, Microwatt never updates RC bits, but just raise an exception when they must be updated,

[RFC PATCH v3 5/5] tests/tcg/ppc64: Build PowerNV and LE tests

Each Microwatt/PowerNV test use its own head.S file and thus needs different build rules. Also add rules to build and run all tests in LE mode. Signed-off-by: Leandro Lupori --- tests/tcg/ppc64/Makefile.softmmu-rules | 34 +++ tests/tcg/ppc64/Makefile.softmmu-target | 121

[RFC PATCH v3 2/5] ppc64: Fix semihosting on ppc64le

PPC64 CPUs can change its endian dynamically, so semihosting code must check its MSR at run time to determine if byte swapping is needed. Signed-off-by: Leandro Lupori --- include/exec/softmmu-semi.h | 23 +++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git

[RFC PATCH v3 1/5] ppc64: Add semihosting support

Add semihosting support for PPC64. This implementation is based on the standard for ARM semihosting version 2.0, as implemented by QEMU and documented in https://github.com/ARM-software/abi-aa/releases The PPC64 specific differences are the following: Semihosting Trap Instruction: sc 7

[RFC PATCH v3 3/5] tests/tcg/ppc64: Add basic softmmu test support

Add support to build and run the multiarch hello test, that simply prints a message and exits, through semihosting operations. The linker script was imported from https://github.com/legoater/pnv-test, that are the Microwatt tests adapted to use a PowerNV console. Boot.S code was inspired on

[RFC PATCH v3 0/5] Port PPC64/PowerNV MMU tests to QEMU

Changes from v2: - Added semihosting support for ppc64 - Use semihosting calls to exit tests, instead of using Processor Attention instruction - Use semihosting calls for console output, instead of programming emulated serial hardware Leandro Lupori (5): ppc64: Add semihosting support ppc64:

Re: [ANNOUNCE] QEMU 7.0.0-rc4 is now available

Am 13.04.22 um 02:44 schrieb Michael Roth: A note from the maintainer: rc4 contains three fixes for late-breaking security bugs. The plan is to make the final 7.0 release in a week's time on the 19th April, with no further changes, unless we discover some last-minute catastrophic

[PATCH 3/4] Enable all x86-64 cpu features in user mode

We don't have any migration concerns for usermode emulation, so we may as well enable all available CPU features by default. Signed-off-by: Paul Brook --- linux-user/x86_64/target_elf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/x86_64/target_elf.h

[PATCH 1/4] Add AVX_EN hflag

Add a new hflag bit to determine whether AVX instructions are allowed Signed-off-by: Paul Brook --- target/i386/cpu.h| 3 +++ target/i386/helper.c | 12 target/i386/tcg/fpu_helper.c | 1 + 3 files changed, 16 insertions(+) diff --git a/target/i386/cpu.h

[PATCH 0/3] AVX guest implementation

Patch series to implement AXV/AVX2 guest support in TCG. All the system level code for this (cpid, xsave, wider registers, etc) already exists, we just need to implement the instruction translation. The majority of the new 256-bit operations operate on each 128-bit "lane" independently, so in

[PATCH for-7.1 06/10] target/ppc: Implement mffscdrn[i] instructions

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 5 + target/ppc/translate/fp-impl.c.inc | 35 ++ 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 177aa49878..e16fad2853 100644 ---

[PATCH for-7.1 09/10] target/ppc: implement cbcdtd

From: Matheus Ferst Implements the Convert Binary Coded Decimal To Declets instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to decimal32 format, from which the declets are extracted. Where the behavior

[PATCH for-7.1 10/10] target/ppc: implement cdtbcd

From: Matheus Ferst Implements the Convert Declets To Binary Coded Decimal instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero exponent is used as an intermediate value to convert the declets.

[PATCH for-7.1 02/10] target/ppc: Move mffs[.] to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 7 +++ target/ppc/translate/fp-impl.c.inc | 25 + target/ppc/translate/fp-ops.c.inc | 1 - 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/ppc/insn32.decode

[PATCH for-7.1 08/10] target/ppc: implement addg6s

From: Matheus Ferst Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 4 +++ target/ppc/translate/fixedpoint-impl.c.inc | 35 ++

[PATCH for-7.1 07/10] target/ppc: Add flag for ISA v2.06 BCDA instructions

From: Matheus Ferst Adds an insns_flags2 for the BCD assist instructions introduced in Power ISA 2.06. These instructions are not listed in the manuals for e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10 models. [1]

[PATCH for-7.1 01/10] target/ppc: Fix insn32.decode style issues

Some lines in insn32.decode have inconsistent alignment when compared to others. Fix this by changing the alignment of some lines, making it more consistent throughout the file. Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 24 1 file changed, 12

[PATCH for-7.1 05/10] target/ppc: Move mffscrn[i] to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 8 +++ target/ppc/internal.h | 3 -- target/ppc/translate/fp-impl.c.inc | 80 ++ target/ppc/translate/fp-ops.c.inc | 4 -- 4 files changed, 23 insertions(+), 72 deletions(-) diff

[PATCH for-7.1 04/10] target/ppc: Move mffsce to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 1 + target/ppc/translate/fp-impl.c.inc | 45 +++--- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 18 insertions(+), 30 deletions(-) diff --git a/target/ppc/insn32.decode

[PATCH for-7.1 03/10] target/ppc: Move mffsl to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 4 target/ppc/translate/fp-impl.c.inc | 27 --- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 12 insertions(+), 21 deletions(-) diff --git a/target/ppc/insn32.decode

[PATCH for-7.1 00/10] BCDA and mffscdrn implementations

Set of patches containing implementations for some instructions that were missing before. Also, moves some related instructions to decodetree Matheus Ferst (4): target/ppc: Add flag for ISA v2.06 BCDA instructions target/ppc: implement addg6s target/ppc: implement cbcdtd target/ppc:

Re: Question about direct block chaining

On 4/18/22 07:54, Taylor Simpson wrote: I implemented both approaches for inner loops and didn't see speedup in my benchmark. So, I have a couple of questions 1) What are the pros and cons of the two approaches (lookup_and_goto_ptr and goto_tb + exit_tb)? goto_tb can only be used within a

Re: [PATCH v1 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system

On 4/15/22 02:40, Xiaojuan Yang wrote: - We write a very minimal softmmu harness. - This is a very simple smoke test with no need to run a full Linux/kernel. - The Makefile.softmmu-target record the rule to run. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS

Re: [PATCH v1 40/43] hw/loongarch: Add LoongArch boot code and load elf function.

On 4/15/22 02:40, Xiaojuan Yang wrote: +static void ls3a5k_aui_boot(uint64_t start_addr) +{ +unsigned int ls3a5k_aui_boot_code[] = { +0x1864, /* pcaddi $r4, 0x3*/ +0x28c00084, /* ld.d$r4, $r4, 0 */ +0x4c80, /* jirl$r0, $r4, 0 */ +

Question about direct block chaining

I've been working on speeding up the Hexagon target by using direct block chaining. Due to Hexagon's VLIW packet semantics (possibly multiple branches in a packet, not processing change-of-flow until packet commit), we have historically treated all change-of-flow as indirect. I looked at the

Re: [PATCH 1/3] qapi-schema: support alternates with array type

On 3/22/22 10:48, Markus Armbruster wrote: I double-checked the generated code; it looks good to me. Thanks for implementing this, and extra thanks for the tests! Heh, the problem is having to build the infrastructure for tests. If it's already there, patches like this are actually easier

Re: [PATCH 0/3] qapi-schema: support alternates with array type

On 4/4/22 14:13, Markus Armbruster wrote: Paolo Bonzini writes: As suggested in the review of the statistics subsystem. Queued for 7.1, thanks! Thanks, I will follow up with the stats patches after these land. Paolo

Re: [PATCH v1 36/43] hw/loongarch: Add irq hierarchy for the system

On 4/15/22 02:40, Xiaojuan Yang wrote: This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c | 106 +++ 1 file changed, 106 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v1 33/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

On 4/18/22 02:14, yangxiaojuan wrote: Hi, Richard On 2022/4/18 上午11:15, Richard Henderson wrote: On 4/15/22 02:40, Xiaojuan Yang wrote: +static void pch_pic_update_irq(LoongArchPCHPIC *s, uint32_t mask, +   int level, int hi) +{ +    uint32_t val, irq; + +    if

Re: [PATCH v1 25/43] target/loongarch: Add LoongArch CSR instruction

On 4/18/22 05:38, yangxiaojuan wrote: On 2022/4/16 上午9:04, Richard Henderson wrote: +int cpu_csr_offset(unsigned csr_num); ... +static const uint64_t csr_offsets[] = { There's no reason for this array to be uint64_t. It really should match the function. Yes,  we shoud do this. If we use

Re: [RFC PATCH v7 25/25] vdpa: Add x-cvq-svq

On Thu, Apr 14, 2022 at 11:10 AM Jason Wang wrote: > > On Thu, Apr 14, 2022 at 12:33 AM Eugenio Pérez wrote: > > > > This isolates shadow cvq in its own group. > > > > Signed-off-by: Eugenio Pérez > > --- > > qapi/net.json| 8 +++- > > net/vhost-vdpa.c | 98

Re: [RFC PATCH v7 24/25] vdpa: Add asid attribute to vdpa device

On Thu, Apr 14, 2022 at 11:10 AM Jason Wang wrote: > > On Thu, Apr 14, 2022 at 12:33 AM Eugenio Pérez wrote: > > > > We can configure ASID per group, but we still use asid 0 for every vdpa > > device. Multiple asid support for cvq will be introduced in next > > patches > > > > Signed-off-by:

Re: [RFC PATCH v7 19/25] vhost: Add vhost_svq_inject

On Thu, Apr 14, 2022 at 11:10 AM Jason Wang wrote: > > On Thu, Apr 14, 2022 at 12:32 AM Eugenio Pérez wrote: > > > > This allows qemu to inject packets to the device without guest's notice. s/packets/buffers/ actually. > > Does it mean it can support guests without _F_ANNOUNCE? > Technically

[GSoC] Adding RPi4 support to qemu-system-aarch64

Hi, I would like to propose adding RPi4 to the list of supported machines for `qemu-system-aarch64` as my GSoC project, but I'm not sure if it's a suitable idea for GSoC since it might be too simple. In addition, there is already ongoing progress here

Re: [PATCH] target/rx: swap stack pointers on clrpsw/setpsw instruction

On Sat, 16 Apr 2022 12:20:09 +0900, Tomoaki Kawada wrote: > > The control register field PSW.U determines which stack pointer register > (ISP or USP) is mapped as R0. In QEMU, this is implemented by having a > value copied between ISP or USP and R0 whenever PSW.U is updated or > access to ISP/USP

Re: [PATCH] target/rx: update PC correctly in wait instruction

On Sun, 17 Apr 2022 15:02:25 +0900, Tomoaki Kawada wrote: > > `cpu_pc` at this point does not necessary point to the current > instruction (i.e., the wait instruction being translated), so it's > incorrect to calculate the new value of `cpu_pc` based on this. It must > be updated with

Re: [PATCH] target/rx: set PSW.I when executing wait instruction

On Sun, 17 Apr 2022 13:59:38 +0900, Tomoaki Kawada wrote: > > This patch fixes the implementation of the wait instruction to > implicitly update PSW.I as required by the ISA specification. > > Signed-off-by: Tomoaki Kawada > --- > target/rx/op_helper.c | 1 + > 1 file changed, 1 insertion(+) >

[PATCH 3/3] docs: parallels image format supports consistency checks

Add parallels to list of formats that support consistency checks by qemu-img check. Signed-off-by: Natalia Kuzmina --- docs/tools/qemu-img.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/tools/qemu-img.rst b/docs/tools/qemu-img.rst index 8885ea11cf..14e98df34f

[PATCH 1/3] qemu-img check: fixing duplicated clusters for parallels format

Let qemu-img check fix corruption in the image file: two guest memory areas refer to the same host memory area (duplicated offsets in BAT). Signed-off-by: Natalia Kuzmina --- block/parallels.c | 66 +-- 1 file changed, 64 insertions(+), 2 deletions(-)

[PATCH 2/3] iotests: 314 test on duplicated clusters (parallels format)

Reading from duplicated offset and from original offset returns the same data. After repairing changing either of these blocks of data does not affect another one. Signed-off-by: Natalia Kuzmina --- tests/qemu-iotests/314| 88 ++

[PATCH 0/3] Repair duplicated clusters in parallels image

Parallels image file can be corrupted this way: two guest memory areas refer to the same host memory area (duplicated offsets in BAT). qemu-img check copies data from duplicated cluster to the new cluster and writes new corresponding offset to BAT instead of duplicated one. Test 314 uses sample

Re: [PATCH v1 25/43] target/loongarch: Add LoongArch CSR instruction

On 2022/4/16 上午9:04, Richard Henderson wrote: +int cpu_csr_offset(unsigned csr_num); ... +static const uint64_t csr_offsets[] = { There's no reason for this array to be uint64_t. It really should match the function. Yes,  we shoud do this. If we use 'int', we may get a warning:

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