From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-Id: <20220317061817.3856850-2-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --gi
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time de
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to
From: Atish Patra
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and seccon
From: Atish Patra
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <2022030
From: Atish Patra
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-3-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertio
From: Niklas Cassel
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU m
From: Wilfred Mallawa
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220303045426.511588-2-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan
From: Atish Patra
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-
From: Atish Patra
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis
Signed-
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Fra
From: Alistair Francis
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or s
From: Alistair Francis
The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:
Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging
(2022-04-20 16:43:11 -0700)
are available in the Git repository at:
g...@github.com:alistair23/qem
On 4/21/22 05:07, Alexey Kardashevskiy wrote:
On 14/04/2022 22:41, Cédric Le Goater wrote:
After re-reading what I just wrote, I am leaning towards disabling use of
KVM_CAP_IRQFD_RESAMPLE as it seems last worked on POWER8 and never since :)
Did I miss something in the picture (hey Cedric)?
On 4/21/22 04:04, Nicholas Piggin wrote:
Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am:
On 4/18/22 17:22, Cédric Le Goater wrote:
On 4/18/22 21:10, Leandro Lupori wrote:
Add semihosting support for PPC64. This implementation is
based on the standard for ARM semihosting versi
+ Philippe's another email address as the redhat one is unreachable
On Thu, Apr 21, 2022 at 1:56 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the change
On 4/21/22 03:17, Bin Meng wrote:
From: Bin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events are
On Thu, Mar 17, 2022 at 8:25 AM Tomasz Jeznach wrote:
>
> The patch introduces baseline implementation of a draft proposal
> of RISC-V IOMMU specification as discussed in the RISC-V Forum [1] [2].
>
> The implementation follows a draft version of the specification published
> at [3] including all
On Thu, Mar 17, 2022 at 8:23 AM Tomasz Jeznach wrote:
>
> This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
>
> The Rivos IOMMU device implementation is based on a draft proposal of a
> RISC-V I/O Management Unit (IOMMU) [1] as published on 2022/03/10, shared and
> discuss
I think the part adding POWERPC_EXCP_SEMIHOST should be proposed in
a separate patch.
Ok, I can move it to a separate patch. That would be all changes in
target/ppc/cpu.h and target/ppc/excp_helper.c, right?
yes.
Thanks,
C.
From: Bin Meng
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
the changes were entirely useless, due to MachineState::kernel_cmdline
can't be NULL at all as the default value is given as an empty strin
From: Bin Meng
At present the adding '/chosen/stdout-path' property in device tree
is determined by whether a kernel command line is provided, which is
wrong. It should be added unconditionally.
Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
Signed-off-by: Bin Meng
On Thu, 31 Mar 2022 at 07:49, Steven Lee wrote:
>
> This add two addition test cases for accumulative mode under sg enabled.
>
> The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
> The padding length depends on algorithm, i.e. SHA512 (1024 bit),
> SHA256 (512 bit).
>
> Th
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220420
for you to fetch changes up to a61532faa5a4d5e021e35b6a4a1e180c72d4a22f:
tcg: Add tcg_constant_ptr (2022-04-20 12:12:47 -0700)
Cleanup sysemu/tcg.h usage.
Fix indirect l
On 2022/4/20 上午1:14, Richard Henderson wrote:
The emulate of PCH_PIC_CLR in qemu LoongArchPCHPIC struct member is
intirr_lo/hi(we devide 64bits reg to two 32bits reg to match the
linux kernel), it will be changed when we config clear reg or handler
irq.
static void loongarch_pch_pic_low_wr
On 14/04/2022 22:41, Cédric Le Goater wrote:
After re-reading what I just wrote, I am leaning towards disabling
use of KVM_CAP_IRQFD_RESAMPLE as it seems last worked on POWER8 and
never since :)
Did I miss something in the picture (hey Cedric)?
How about disabling it like this?
=
d
On Wed, Apr 20, 2022 at 1:52 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> This series adds support for connecting TPM devices to the RISC-V virt
> board. This is similar to how it works for the ARM virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtp
On Wed, Apr 20, 2022 at 5:57 PM wrote:
>
> From: Frank Chang
>
> Allow user to set core's marchid, mvendorid, mipid CSRs through
> -cpu command line option.
>
> The default values of marchid and mipid are built with QEMU's version
> numbers.
>
> Signed-off-by: Frank Chang
> Reviewed-by: Jim Shu
The 04/20/2022 20:53, Cédric Le Goater wrote:
> On 3/31/22 09:48, Steven Lee wrote:
> > The aspeed ast2600 accumulative mode is described in datasheet
> > ast2600v10.pdf section 25.6.4:
> > 1. Allocating and initiating accumulative hash digest write buffer
> > with initial state.
> > *
Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am:
> On 4/18/22 17:22, Cédric Le Goater wrote:
>> On 4/18/22 21:10, Leandro Lupori wrote:
>>> Add semihosting support for PPC64. This implementation is
>>> based on the standard for ARM semihosting version 2.0, as
>>> implemented by QEM
Hi, i think it is curios for a process to have so many threads.
my environment: 5.4.160-1.el7.x86_64, qemu-6.1.0
thanks
=cmd==
root 11918 0.0 0.0 112720 2280 pts/0S+ 09:30 0:00 grep
--color=auto 38032
root 38032 58.0 1.0 8705632 2823304 ? Sl
On Tue, Apr 19, 2022 at 10:03 PM Dylan Jhong wrote:
>
> The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
> address within 3GB,
> but not all platforms have dram_base within 3GB.
>
> This patch adds an exception for dram base not within 3GB,
> which will place fdt at dram_e
On Thu, Apr 21, 2022 at 10:35 AM Bin Meng wrote:
>
>
> This adds initial support for the Sdtrig extension via the Trigger Module,
> as defined in the RISC-V Debug Specification [1].
>
> Only "Address / Data Match" trigger (type 2) is implemented as of now,
> which is mainly used for hardware break
Hi Daniel,
Could you please review this series?
On 4/11/22 18:43, zhenwei pi wrote:
v3 -> v4:
- Coding style fix: Akcipher -> AkCipher, struct XXX -> XXX, Rsa -> RSA,
XXX-alg -> XXX-algo.
- Change version info in qapi/crypto.json, from 7.0 -> 7.1.
- Remove ecdsa from qapi/crypto.json, it would
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/hexagon/genptr.c | 147 +++
tests/tcg/hexagon/usr.
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/hexagon/imported/encode_pp.def
b/target/hexagon/imported/encode_pp.def
index 939c6fc55
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet commit
that uses the runtime store width.
Th
The increment used in :brev tests was causing unaligned addresses
Change the increment and the relevant expected values
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/load_unpack.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/hexagon/load_unpa
VyV operand is only used in the vshuff and vdeal instructions. These
instructions write to both VyV and VxV operands. In the case where
both operands are the same register, we need a separate location for
VyV. We use the existing vtmp field in CPUHexagonState.
Test case added in tests/tcg/hexag
From: Bin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events are not recognized if MSR[DE]
is cleared
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v4)
Changes in v4:
- move riscv_trigger_init() call to riscv_cpu_reset()
Changes in v3:
- add riscv_trigger_init(), moved from patch
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-o
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v3)
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 32
1 file changed, 32
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
target/ri
This adds initial support for the Sdtrig extension via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implement
On Thu, Apr 21, 2022 at 8:14 AM Alistair Francis wrote:
>
> On Thu, Apr 21, 2022 at 9:47 AM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
> > > >
> > > > Hi Alistair,
> > > >
On Thu, Apr 21, 2022 at 9:47 AM Bin Meng wrote:
>
> Hi Alistair,
>
> On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis wrote:
> >
> > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
> > >
> > > Hi Alistair,
> > >
> > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> > > >
> > > > On Wed, Apr 2
Hi Alistair,
On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis wrote:
>
> On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> > >
> > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis
> > > wrote:
> > > >
> > > > On Tu
https://gitlab.com/rth7680/qemu.git tags/pull-log-20220420
for you to fetch changes up to 4e51069d679348d2617512e56e28cdc7bb34c833:
util/log: Support per-thread log files (2022-04-20 10:51:11 -0700)
Clean up log locking.
Use the
On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
>
> Hi Alistair,
>
> On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> >
> > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis
> > wrote:
> > >
> > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng wrote:
> > > >
> > > > From: Bin Meng
> > > >
> > > > A
On Wed, Apr 20, 2022 at 6:09 PM wrote:
>
> From: Frank Chang
>
> This patchset makes ACLINT mtime to be writable as RISC-V privilege
> spec defines that mtime is exposed as a memory-mapped machine-mode
> read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
> accessible registe
From: Alexey Kardashevskiy
There are error paths which do not initialize propname but the trace_exit
label prints it anyway. This initializes the problem string.
Spotted by Coverity CID 1487241.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Daniel Henrique Barboza
Message-Id: <202204060450
From: Guo Zhi
There are still some files in the QEMU PPC code base that use TABs for
indentation instead of using spaces. The TABs should be replaced so
that we have a consistent coding style.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374
Signed-off-by: Guo Zhi
Reviewed-by: Danie
From: Matheus Ferst
Implements float128_to_uint128 based on parts_float_to_uint logic.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-6-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat.c | 65 +++
From: Frederic Barrat
This patch skips [de]asserting a LSI interrupt if the device doesn't
have any LSI defined. Doing so would trigger an assert in
pci_irq_handler().
The PCIE root port implementation in qemu requests a LSI (INTA), but a
subclass may want to change that behavior since it's a va
From: Fabiano Rosas
I'm moving this because next patch will add more code under the ifdef
and it will be cleaner if we keep them together.
Also switch the ifdef branches to make it more convenient to add code
under CONFIG_TCG in the next patch.
Signed-off-by: Fabiano Rosas
Reviewed-by: Nichola
From: Frederic Barrat
This patch adds tcg accessors for 2 SPRs which were missing on P10:
- the TBU40 register is used to write the upper 40 bits of the
timebase register. It is used by kvm to update the timebase when
entering/exiting the guest on P9 and above. The missing definition was
causing
From: Cédric Le Goater
All devices raising PSI interrupts are now converted to use GPIO lines
and the pnv_psi_irq_set() routines have become useless. Drop them.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-5-...@kaod.org>
Signed-off-b
From: Bernhard Beschow
Resolves the only compiler warning when building a full QEMU under Arch Linux:
Compiling C object libqemu-ppc-softmmu.fa.p/hw_ppc_ppc405_boards.c.o
In file included from /usr/include/glib-2.0/glib.h:114,
from qemu/include/glib-compat.h:32,
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to
Signed Quadword
xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to
Unsigned Quadword
Signed-off-by: Matheus Ferst
Revi
From: Cédric Le Goater
Use an anonymous output GPIO line to connect the OCC device with the
PSIHB device and raise the appropriate PSI IRQ line depending on the
processor model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-4-...@kaod.
From: Matheus Ferst
Implements float128_to_int128 based on parts_float_to_int logic.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-7-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat.c | 64 +
From: Frederic Barrat
The phb3/phb4/phb5 root ports inherit from the default PCIE root port
implementation, which requests a LSI interrupt (#INTA). On real
hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch
corrects it so that it matches the hardware.
As a consequence, the device
From: Fabiano Rosas
Before:
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hy
From: Matheus Ferst
Implement an unsigned right shift for Int128 values and add the same
tests cases of int128_rshift in the unit test.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-3-matheus.fe...@eldorado.org.br>
[danielhb: fixed long lines in t
From: Fabiano Rosas
These are the spapr virtual hypervisor implementation of the nested
KVM API. They only make sense when running with TCG.
Signed-off-by: Fabiano Rosas
Reviewed-by: Nicholas Piggin
Message-Id: <20220325221113.255834-3-faro...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barb
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
xscvsqqp: VSX Scalar Convert with round Signed Quadword to
Quad-Precision
xscvuqqp: VSX Scalar Convert with round Unsigned Quadword to
Quad-Precision format
Signed-off-by: Matheus Ferst
Reviewed-by: Rich
From: Cédric Le Goater
Create an anonymous output GPIO line to connect the LPC device with
the PSIHB device and raise the appropriate PSI IRQ line depending on
the processor model.
A temporary __pnv_psi_irq_set() routine is introduced to handle the
transition. It will be removed when all devices
From: Matheus Ferst
Based on parts_sint_to_float, implements int128_to_float128 to convert a
signed 128-bit value received through an Int128 argument.
Signed-off-by: Matheus Ferst
Message-Id: <20220330175932.6995-5-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-6-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv_psi.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/
From: Cédric Le Goater
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP int
From: Matheus Ferst
Based on parts_uint_to_float, implements uint128_to_float128 to convert
an unsigned 128-bit value received through an Int128 argument.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-4-matheus.fe...@eldorado.org.br>
Signed-off-by
s/pull-ppc-20220420-2
for you to fetch changes up to 2d94af4b16c40758eee3a8591307ae173090d4ad:
hw/ppc: change indentation to spaces from TABs (2022-04-20 18:00:30 -0300)
ppc patch queue for 2022-04-20
First batch of ppc patches fo
From: Alexey Kardashevskiy
Recently the LoPAPR spec got a new 2MB pagesize to support in Dynamic DMA
Windows API (DDW), this adds the new flag.
Linux supports it since
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38727311871
Reviewed-by: Daniel Henrique Barboza
Awesome, thanks.
Apparently I'm not properly performing a date-sorted search on the list
archives. I started here:
https://lists.gnu.org/archive/html/qemu-devel/
Then entered "slirp" and searched with chronological order, but the latest
entry is from 2020. What am I doing wrong?
Thanks,
//and
On Wed, Apr 20, 2022 at 12:43:39PM +0100, Daniel P. Berrangé wrote:
> > static void test_baddest(void)
> > {
> > MigrateStart args = {
> > @@ -2176,6 +2219,12 @@ int main(int argc, char **argv)
> >
> > qtest_add_func("/migration/postcopy/unix", test_postcopy);
> > qtest_add_func(
On Wed, Apr 20, 2022 at 12:42:15PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:56AM -0400, Peter Xu wrote:
> > It's easy to build this upon the postcopy tls test.
> >
> > Signed-off-by: Peter Xu
> > ---
> > tests/qtest/migration-test.c | 27 +--
> > 1
On 4/20/22 16:08, Anders Pitman wrote:
I noticed in the 7.0 changelog that libslirp might be removed as a submodule in
the future. Since user networking is very important for my project, I'm
wondering if this is simply an implementation detail, or if there are plans to
eventually remove sli
At the start of pc_memory_init() we usually pass a range of
0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
32G (q35). To get the real user value, we need to get pci-host
passed property for default pci_hole64_size. Thus to get that,
create the qdev prior to memory init to better make e
On Wed, Apr 20, 2022 at 12:35:21PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:54AM -0400, Peter Xu wrote:
> > This patch is based on the async preempt channel creation. It continues
> > wiring up the new channel with TLS handshake to destionation when enabled.
> >
> > Note t
Rather than hardcoding the 4G boundary everywhere, introduce a
X86MachineState property @above_4g_mem_start and use it
accordingly.
This is in preparation for relocating ram-above-4g to be
dynamically start at 1T on AMD platforms.
Signed-off-by: Joao Martins
---
hw/i386/acpi-build.c | 2 +-
hw
On 4/20/22 12:42, Peter Maydell wrote:
On Mon, 18 Apr 2022 at 20:19, Leandro Lupori
wrote:
PPC64 CPUs can change its endian dynamically, so semihosting code
must check its MSR at run time to determine if byte swapping is
needed.
Arm CPUs also change endianness dynamically, so why is this
cha
On Wed, Apr 20, 2022 at 12:13:07PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:53AM -0400, Peter Xu wrote:
> > It's useful for specifying tls credentials all in the cmdline (along with
> > the -object tls-creds-*), especially for debugging purpose.
> >
> > The trick here is we
On Wed, Apr 20, 2022 at 12:10:14PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:52AM -0400, Peter Xu wrote:
> > Add migrate_tls_enabled() to detect whether TLS is configured.
> >
> > Add migrate_channel_requires_tls() to detect whether the specific channel
> > requires TLS.
> >
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, expect for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or platform-
On Mon, 18 Apr 2022 at 20:19, Leandro Lupori
wrote:
>
> PPC64 CPUs can change its endian dynamically, so semihosting code
> must check its MSR at run time to determine if byte swapping is
> needed.
Arm CPUs also change endianness dynamically, so why is this
change PPC-specific ?
thanks
-- PMM
On Wed, Apr 20, 2022 at 12:39:07PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:55AM -0400, Peter Xu wrote:
> > We just added TLS tests for precopy but not postcopy. Add the
> > corresponding test for vanilla postcopy.
> >
> > Signed-off-by: Peter Xu
> > ---
> > tests/qtest/
v3[4] -> v4:
(changes in patch 4 and 5 only)
* Rebased to 7.1.0, hence move compat machine attribute to <= 7.0.0 versions
* Check guest vCPU vendor rather than host CPU vendor (Michael Tsirkin)
* Squash previous patch 5 into patch 4 to tie in the phys-bits check
into the relocate-4g-start logic:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesd: Vector Divide Extended Signed Doubleword
vdiveud: Vector Divide Extended Unsigned Doubleword
vdivesq: Vector Divide Extended Signed Quadword
vdiveuq: Vector Divide Extended Unsigned Quadword
Signed
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesw: Vector Divide Extended Signed Word
vdiveuw: Vector Divide Extended Unsigned Word
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc/insn32.decode| 3 ++
target/ppc/translate
The added enforcing is only relevant in the case of AMD where the
range right before the 1TB is restricted and cannot be DMA mapped
by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
or possibly other kinds of IOMMU events in the AMD IOMMU.
Although, there's a case where it may mak
From: "Lucas Mateus Castro (alqotel)"
Based on already existing QEMU implementation created a signed
256 bit by 128 bit division needed to implement the vector divide
extended signed quadword instruction from PowerISA 3.1
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henders
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vmodsq: Vector Modulo Signed Quadword
vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
target/ppc/helper.h | 2 ++
On Wed, Apr 20, 2022 at 11:41:30AM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:42AM -0400, Peter Xu wrote:
> > This variable, along with its helpers, is used to detect whether multiple
> > channel will be supported for migration. In follow up patches, there'll be
> > other cap
Use the pre-initialized pci-host qdev and fetch the
pci-hole64-size into pc_memory_init() newly added argument.
piix needs a bit of care given all the !pci_enabled()
and that the pci_hole64_size is private to i440fx.
This is in preparation to determine that host-phys-bits are
enough and for pci-ho
From: "Lucas Mateus Castro (alqotel)"
This patch series is an implementation of the vector divide, vector
divide extended and vector modulo instructions from PowerISA 3.1
The first patch are Matheus' patch, used here since the divs256 and
divu256 functions use int128_urshift.
Patches without re
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
Signed-off-by: Lucas Mateus Castro (alqotel)
---
tar
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 4/11/22 09:59, Frederic Barrat wrote:
This patch adds tcg accessors for 2 SPRs which were missing on P10:
- the TBU40 register is used to write the upper 40 bits of the
timebase register. It is used by kvm to update the tim
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