Re: [PATCH v12 00/14] support subsets of scalar crypto extension

[Alistair Francis]

On Sat, Apr 23, 2022 at 12:38 PM Weiwei Li  wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version 
> instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v12
>
> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true' or 
> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
>  to enable K-extension support. This implementation can pass the ACT tests 
> for K with our extended act support for qemu (available at 
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v12-with-act)
>
> Review status:
> patch 5 is reviewed by Philippe Mathieu-Daudé
> patch 1~14 are acked or reviewed by Alistair Francis
> patch 2~11 are reviewed by Richard Henderson (fix new comments on patch 6 and 
> 7)
>
> v12:
> * rebase on master and riscv-to-apply.next
>
> v11:
> * patch 6: add REQUIRE_32BIT to trans_* function for aes RV32 instruction
> * patch 7: add REQUIRE_64BIT to trans_* function for aes RV64 instruction
>
> v10:
> (only patch 12 is modified)
> * simplify the conditions for the check in seed function
> * add NULL check for ret_val in rmw_seed function
> * remain the change of MSECCFG_* to align with the added MSECCFG_*SEED
>
> v9:
> * check whether seed is accessed by a read-write instruction in helper_csrr.
> * fix disas for partial scalar crypto instructions
> * rebase on 
> https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00156.html
>
> v8:
> * replace large macro for trans function of sha256/512 instructions with 
> parameters to gen_sha* function in patch 8,9,10
> * fix tcg_const_tl to tcg_constant_tl
> * fix rmw_seed function
>
> v7:
> * reuse gen_unary/gen_arith to simplify trans_* functions
> * replace DEF_HELPER_* with DEF_HEPER_FLAG_*
> * move aes64 related macros from patch 6 to patch 7
> * create common helper gen_aes32_sm4 for aes32 and sm4 related instructions
> * replace bs with shamt (bs << 3)
> * optimize trans function for sha256, sha512 and sm4 instructions to be 
> generated inline
>
> v6:
> * add reviewed-by tags
> * rebase on upstream
>
> v5:
> * split the big patches
>
> v4:
> * drop "x-" in exposed properties
> * delete unrelated changes
>
> v3:
> * add extension check for SEED csr access
>
> v2:
> * optimize implementation for brev8, xperm, zip, unzip
> * use aes related sbox array from crypto/aes.h
> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>
> Weiwei Li (14):
>   target/riscv: rvk: add cfg properties for zbk* and zk*
>   target/riscv: rvk: add support for zbkb extension
>   target/riscv: rvk: add support for zbkc extension
>   target/riscv: rvk: add support for zbkx extension
>   crypto: move sm4_sbox from target/arm
>   target/riscv: rvk: add support for zknd/zkne extension in RV32
>   target/riscv: rvk: add support for zkne/zknd extension in RV64
>   target/riscv: rvk: add support for sha256 related instructions in zknh
> extension
>   target/riscv: rvk: add support for sha512 related instructions for
> RV32 in zknh extension
>   target/riscv: rvk: add support for sha512 related instructions for
> RV64 in zknh extension
>   target/riscv: rvk: add support for zksed/zksh extension
>   target/riscv: rvk: add CSR support for Zkr
>   disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>   target/riscv: rvk: expose zbk* and zk* properties

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  crypto/meson.build  |   1 +
>  crypto/sm4.c|  49 +++
>  disas/riscv.c   | 173 ++-
>  include/crypto/sm4.h|   6 +
>  target/arm/crypto_helper.c  |  36 +--
>  target/riscv/bitmanip_helper.c  |  80 +
>  target/riscv/cpu.c  |  36 +++
>  target/riscv/cpu.h  |  13 +
>  target/riscv/cpu_bits.h |   9 +
>  target/riscv/crypto_helper.c| 302 ++
>  target/riscv/csr.c  |  80 +
>  target/riscv/helper.h   |  22 ++
>  target/riscv/insn32.decode  |  97 --
>  target/riscv/insn_trans/trans_rvb.c.inc | 116 ++-
>  target/riscv/insn_trans/trans_rvk.c.inc | 391 
>  target/riscv/meson.build|   3 +-
>  target/riscv/op_helper.c|   9 +
>  target/riscv/pmp.h  |   8 +-
>  target/riscv/translate.c|   8 +
>  19 files changed, 1368 insertions(+), 71 deletions(-)
>  create mode 100644 crypto/sm4.c
>  create mode 100644 include/crypto/sm4.h
>  create mode 100644 target/riscv/crypto_helper.c
>  create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> --
> 2.17.1
>
>

Re: [PATCH v5 01/13] mm/memfd: Introduce MFD_INACCESSIBLE flag

[Vishal Annapurve]

On Thu, Mar 10, 2022 at 6:09 AM Chao Peng  wrote:
>
> From: "Kirill A. Shutemov" 
>
> Introduce a new memfd_create() flag indicating the content of the
> created memfd is inaccessible from userspace through ordinary MMU
> access (e.g., read/write/mmap). However, the file content can be
> accessed via a different mechanism (e.g. KVM MMU) indirectly.
>
> It provides semantics required for KVM guest private memory support
> that a file descriptor with this flag set is going to be used as the
> source of guest memory in confidential computing environments such
> as Intel TDX/AMD SEV but may not be accessible from host userspace.
>
> Since page migration/swapping is not yet supported for such usages
> so these pages are currently marked as UNMOVABLE and UNEVICTABLE
> which makes them behave like long-term pinned pages.
>
> The flag can not coexist with MFD_ALLOW_SEALING, future sealing is
> also impossible for a memfd created with this flag.
>
> At this time only shmem implements this flag.
>
> Signed-off-by: Kirill A. Shutemov 
> Signed-off-by: Chao Peng 
> ---
>  include/linux/shmem_fs.h   |  7 +
>  include/uapi/linux/memfd.h |  1 +
>  mm/memfd.c | 26 +++--
>  mm/shmem.c | 57 ++
>  4 files changed, 88 insertions(+), 3 deletions(-)
>
> diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
> index e65b80ed09e7..2dde843f28ef 100644
> --- a/include/linux/shmem_fs.h
> +++ b/include/linux/shmem_fs.h
> @@ -12,6 +12,9 @@
>
>  /* inode in-kernel data */
>
> +/* shmem extended flags */
> +#define SHM_F_INACCESSIBLE 0x0001  /* prevent ordinary MMU access (e.g. 
> read/write/mmap) to file content */
> +
>  struct shmem_inode_info {
> spinlock_t  lock;
> unsigned intseals;  /* shmem seals */
> @@ -24,6 +27,7 @@ struct shmem_inode_info {
> struct shared_policypolicy; /* NUMA memory alloc policy */
> struct simple_xattrsxattrs; /* list of xattrs */
> atomic_tstop_eviction;  /* hold when working on inode 
> */
> +   unsigned intxflags; /* shmem extended flags */
> struct inodevfs_inode;
>  };
>
> @@ -61,6 +65,9 @@ extern struct file *shmem_file_setup(const char *name,
> loff_t size, unsigned long flags);
>  extern struct file *shmem_kernel_file_setup(const char *name, loff_t size,
> unsigned long flags);
> +extern struct file *shmem_file_setup_xflags(const char *name, loff_t size,
> +   unsigned long flags,
> +   unsigned int xflags);
>  extern struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt,
> const char *name, loff_t size, unsigned long flags);
>  extern int shmem_zero_setup(struct vm_area_struct *);
> diff --git a/include/uapi/linux/memfd.h b/include/uapi/linux/memfd.h
> index 7a8a26751c23..48750474b904 100644
> --- a/include/uapi/linux/memfd.h
> +++ b/include/uapi/linux/memfd.h
> @@ -8,6 +8,7 @@
>  #define MFD_CLOEXEC0x0001U
>  #define MFD_ALLOW_SEALING  0x0002U
>  #define MFD_HUGETLB0x0004U
> +#define MFD_INACCESSIBLE   0x0008U
>
>  /*
>   * Huge page size encoding when MFD_HUGETLB is specified, and a huge page
> diff --git a/mm/memfd.c b/mm/memfd.c
> index 9f80f162791a..74d45a26cf5d 100644
> --- a/mm/memfd.c
> +++ b/mm/memfd.c
> @@ -245,16 +245,20 @@ long memfd_fcntl(struct file *file, unsigned int cmd, 
> unsigned long arg)
>  #define MFD_NAME_PREFIX_LEN (sizeof(MFD_NAME_PREFIX) - 1)
>  #define MFD_NAME_MAX_LEN (NAME_MAX - MFD_NAME_PREFIX_LEN)
>
> -#define MFD_ALL_FLAGS (MFD_CLOEXEC | MFD_ALLOW_SEALING | MFD_HUGETLB)
> +#define MFD_ALL_FLAGS (MFD_CLOEXEC | MFD_ALLOW_SEALING | MFD_HUGETLB | \
> +  MFD_INACCESSIBLE)
>
>  SYSCALL_DEFINE2(memfd_create,
> const char __user *, uname,
> unsigned int, flags)
>  {
> +   struct address_space *mapping;
> unsigned int *file_seals;
> +   unsigned int xflags;
> struct file *file;
> int fd, error;
> char *name;
> +   gfp_t gfp;
> long len;
>
> if (!(flags & MFD_HUGETLB)) {
> @@ -267,6 +271,10 @@ SYSCALL_DEFINE2(memfd_create,
> return -EINVAL;
> }
>
> +   /* Disallow sealing when MFD_INACCESSIBLE is set. */
> +   if (flags & MFD_INACCESSIBLE && flags & MFD_ALLOW_SEALING)
> +   return -EINVAL;
> +
> /* length includes terminating zero */
> len = strnlen_user(uname, MFD_NAME_MAX_LEN + 1);
> if (len <= 0)
> @@ -301,8 +309,11 @@ SYSCALL_DEFINE2(memfd_create,
> HUGETLB_ANONHUGE_INODE,
> (flags >> MFD_HUGE_SHIFT) &
> 

Re: [PATCH v2 2/5] 9pfs: fix qemu_mknodat(S_IFSOCK) on macOS

[Akihiko Odaki]

On 2022/04/22 23:06, Christian Schoenebeck wrote:

On Freitag, 22. April 2022 04:43:40 CEST Akihiko Odaki wrote:

On 2022/04/22 0:07, Christian Schoenebeck wrote:

mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and chmod() respectively if S_IFSOCK
was passed with mode argument.

Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by: Christian Schoenebeck 
Reviewed-by: Will Cohen 
---

   hw/9pfs/9p-util-darwin.c | 27 ++-
   1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/hw/9pfs/9p-util-darwin.c b/hw/9pfs/9p-util-darwin.c
index e24d09763a..39308f2a45 100644
--- a/hw/9pfs/9p-util-darwin.c
+++ b/hw/9pfs/9p-util-darwin.c
@@ -74,6 +74,27 @@ int fsetxattrat_nofollow(int dirfd, const char
*filename, const char *name,>
*/
   
   #if defined CONFIG_PTHREAD_FCHDIR_NP


+static int create_socket_file_at_cwd(const char *filename, mode_t mode) {
+int fd, err;
+struct sockaddr_un addr = {
+.sun_family = AF_UNIX
+};
+
+fd = socket(PF_UNIX, SOCK_DGRAM, 0);
+if (fd == -1) {
+return fd;
+}
+snprintf(addr.sun_path, sizeof(addr.sun_path), "./%s", filename);


It would result in an incorrect path if the path does not fit in
addr.sun_path. It should report an explicit error instead.


Looking at its header file, 'sun_path' is indeed defined on macOS with an
oddly small size of only 104 bytes. So yes, I should explicitly handle that
error case.

I'll post a v3.


+err = bind(fd, (struct sockaddr *) &addr, sizeof(addr));
+if (err == -1) {
+goto out;


You may close(fd) as soon as bind() returns (before checking the
returned value) and eliminate goto.


Yeah, I thought about that alternative, but found it a bit ugly, and probably
also counter-productive in case this function might get extended with more
error pathes in future. Not that I would insist on the current solution
though.


I'm happy with the explanation. Thanks.




+}
+err = chmod(addr.sun_path, mode);


I'm not sure if it is fine to have a time window between bind() and
chmod(). Do you have some rationale?


Good question. QEMU's 9p server is multi-threaded; all 9p requests come in
serialized and the 9p server controller portion (9p.c) is only running on QEMU
main thread, but the actual filesystem driver calls are then dispatched to
QEMU worker threads and therefore running concurrently at this point:

https://wiki.qemu.org/Documentation/9p#Threads_and_Coroutines

Similar situation on Linux 9p client side: it handles access to a mounted 9p
filesystem concurrently, requests are then serialized by 9p driver on Linux
and sent over wire to 9p server (host).

So yes, there might be implications by that short time windows. But could that
be exploited on macOS hosts in practice?

The socket file would have mode srwxr-xr-x for a short moment.

For security_model=mapped* this should not be a problem.

For security_model=none|passhrough, in theory, maybe? But how likely is that?
If you are using a Linux client for instance, trying to brute-force opening
the socket file, the client would send several 9p commands (Twalk, Tgetattr,
Topen, probably more). The time window of the two commands above should be
much smaller than that and I would expect one of the 9p commands to error out
in between.

What would be a viable approach to avoid this issue on macOS?


It is unlikely that a naive brute-force approach will succeed to 
exploit. The more concerning scenario is that the attacker uses the 
knowledge of the underlying implementation of macOS to cause resource 
contention to widen the window. Whether an exploitation is viable 
depends on how much time you spend digging XNU.


However, I'm also not sure if it really *has* a race condition. Looking 
at v9fs_co_mknod(), it sequentially calls s->ops->mknod() and 
s->ops->lstat(). It also results in an entity called "path name based 
fid" in the code, which inherently cannot identify a file when it is 
renamed or recreated.


If there is some rationale it is safe, it may also be applied to the 
sequence of bind() and chmod(). Can anyone explain the sequence of 
s->ops->mknod() and s->ops->lstat() or path name based fid in general?


Regards,
Akihiko Odaki




+out:
+close(fd);
+return err;
+}
+

   int qemu_mknodat(int dirfd, const char *filename, mode_t mode, dev_t
   dev)
   {
   
   int preserved_errno, err;


@@ -93,7 +114,11 @@ int qemu_mknodat(int dirfd, const char *filename,
mode_t mode, dev_t dev)>
   if (pthread_fchdir_np(dirfd) < 0) {
   
   return -1;
   
   }


-err = mknod(filename, mode, dev);
+if (S_ISSOCK(mode)) {
+err = create_socket_file_at_cwd(filename, mode);
+} else {
+err = mknod(filename, mode, dev);
+}

   preserved_errno = errno;
   /* Stop using the thread-local cwd */
   pthread_fchdir_np(-1);

[PATCH v12 11/14] target/riscv: rvk: add support for zksed/zksh extension

[Weiwei Li]

 - add sm3p0, sm3p1, sm4ed and sm4ks instructions

Co-authored-by: Ruibo Lu 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
---
 target/riscv/crypto_helper.c| 28 
 target/riscv/helper.h   |  3 ++
 target/riscv/insn32.decode  |  6 +++
 target/riscv/insn_trans/trans_rvk.c.inc | 58 +
 4 files changed, 95 insertions(+)

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index cb4783a1e9..2ef30281b1 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -271,4 +271,32 @@ target_ulong HELPER(aes64im)(target_ulong rs1)
 
 return result;
 }
+
+target_ulong HELPER(sm4ed)(target_ulong rs1, target_ulong rs2,
+   target_ulong shamt)
+{
+uint32_t sb_in = (uint8_t)(rs2 >> shamt);
+uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
+
+uint32_t x = sb_out ^ (sb_out << 8) ^ (sb_out << 2) ^ (sb_out << 18) ^
+ ((sb_out & 0x3f) << 26) ^ ((sb_out & 0xC0) << 10);
+
+uint32_t rotl = rol32(x, shamt);
+
+return sext32_xlen(rotl ^ (uint32_t)rs1);
+}
+
+target_ulong HELPER(sm4ks)(target_ulong rs1, target_ulong rs2,
+   target_ulong shamt)
+{
+uint32_t sb_in = (uint8_t)(rs2 >> shamt);
+uint32_t sb_out = sm4_sbox[sb_in];
+
+uint32_t x = sb_out ^ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
+ ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13);
+
+uint32_t rotl = rol32(x, shamt);
+
+return sext32_xlen(rotl ^ (uint32_t)rs1);
+}
 #undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 56519fcc26..4ef3b2251d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1126,3 +1126,6 @@ DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, 
tl)
 DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
+
+DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d9ebb138d1..4033565393 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -873,3 +873,9 @@ sha512sig0  00 01000 00110 . 001 . 0010011 @r2
 sha512sig1  00 01000 00111 . 001 . 0010011 @r2
 sha512sum0  00 01000 00100 . 001 . 0010011 @r2
 sha512sum1  00 01000 00101 . 001 . 0010011 @r2
+# *** RV32 Zksh Standard Extension ***
+sm3p0   00 01000 01000 . 001 . 0010011 @r2
+sm3p1   00 01000 01001 . 001 . 0010011 @r2
+# *** RV32 Zksed Standard Extension ***
+sm4ed   .. 11000 . . 000 . 0110011 @k_aes
+sm4ks   .. 11010 . . 000 . 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc 
b/target/riscv/insn_trans/trans_rvk.c.inc
index 8274b5a364..90f4eeff60 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -35,6 +35,18 @@
 }   \
 } while (0)
 
+#define REQUIRE_ZKSED(ctx) do { \
+if (!ctx->cfg_ptr->ext_zksed) { \
+return false;   \
+}   \
+} while (0)
+
+#define REQUIRE_ZKSH(ctx) do {  \
+if (!ctx->cfg_ptr->ext_zksh) {  \
+return false;   \
+}   \
+} while (0)
+
 static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
   void (*func)(TCGv, TCGv, TCGv, TCGv))
 {
@@ -331,3 +343,49 @@ static bool trans_sha512sum1(DisasContext *ctx, 
arg_sha512sum1 *a)
 REQUIRE_ZKNH(ctx);
 return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
 }
+
+/* SM3 */
+static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32_t b, int32_t c)
+{
+TCGv dest = dest_gpr(ctx, a->rd);
+TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+TCGv_i32 t0 = tcg_temp_new_i32();
+TCGv_i32 t1 = tcg_temp_new_i32();
+
+tcg_gen_trunc_tl_i32(t0, src1);
+tcg_gen_rotli_i32(t1, t0, b);
+tcg_gen_xor_i32(t1, t0, t1);
+tcg_gen_rotli_i32(t0, t0, c);
+tcg_gen_xor_i32(t1, t1, t0);
+tcg_gen_ext_i32_tl(dest, t1);
+gen_set_gpr(ctx, a->rd, dest);
+
+tcg_temp_free_i32(t0);
+tcg_temp_free_i32(t1);
+return true;
+}
+
+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
+{
+REQUIRE_ZKSH(ctx);
+return gen_sm3(ctx, a, 9, 17);
+}
+
+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
+{
+REQUIRE_ZKSH(ctx);
+return gen_sm3(ctx, a, 15, 23);
+}
+
+/* SM4 */
+static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
+{
+REQUIRE_ZKSED(ctx);
+return gen_aes32_sm4(ctx, a, gen_helper_sm4ed);
+}
+
+static bool

[PATCH v12 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

[Weiwei Li]

 - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions

Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn32.decode  |  5 +++
 target/riscv/insn_trans/trans_rvk.c.inc | 53 +
 2 files changed, 58 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 02a0c71890..d9ebb138d1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -868,3 +868,8 @@ sha512sig0l 01 01010 . . 000 . 0110011 @r
 sha512sig0h 01 01110 . . 000 . 0110011 @r
 sha512sig1l 01 01011 . . 000 . 0110011 @r
 sha512sig1h 01 0 . . 000 . 0110011 @r
+# *** RV64 Zknh Standard Extension ***
+sha512sig0  00 01000 00110 . 001 . 0010011 @r2
+sha512sig1  00 01000 00111 . 001 . 0010011 @r2
+sha512sum0  00 01000 00100 . 001 . 0010011 @r2
+sha512sum1  00 01000 00101 . 001 . 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc 
b/target/riscv/insn_trans/trans_rvk.c.inc
index 9ed057a153..8274b5a364 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -278,3 +278,56 @@ static bool trans_sha512sig1h(DisasContext *ctx, 
arg_sha512sig1h *a)
 REQUIRE_ZKNH(ctx);
 return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
 }
+
+static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+void (*func)(TCGv_i64, TCGv_i64, int64_t),
+int64_t num1, int64_t num2, int64_t num3)
+{
+TCGv dest = dest_gpr(ctx, a->rd);
+TCGv src1 = get_gpr(ctx, a->rs1, ext);
+TCGv_i64 t0 = tcg_temp_new_i64();
+TCGv_i64 t1 = tcg_temp_new_i64();
+TCGv_i64 t2 = tcg_temp_new_i64();
+
+tcg_gen_extu_tl_i64(t0, src1);
+tcg_gen_rotri_i64(t1, t0, num1);
+tcg_gen_rotri_i64(t2, t0, num2);
+tcg_gen_xor_i64(t1, t1, t2);
+func(t2, t0, num3);
+tcg_gen_xor_i64(t1, t1, t2);
+tcg_gen_trunc_i64_tl(dest, t1);
+
+gen_set_gpr(ctx, a->rd, dest);
+tcg_temp_free_i64(t0);
+tcg_temp_free_i64(t1);
+tcg_temp_free_i64(t2);
+return true;
+}
+
+static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 1, 8, 7);
+}
+
+static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 19, 61, 6);
+}
+
+static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 28, 34, 39);
+}
+
+static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
+}
-- 
2.17.1

[PATCH v12 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

[Weiwei Li]

Co-authored-by: Ruibo Lu 
Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Alistair Francis 
---
 disas/riscv.c | 173 +-
 1 file changed, 172 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..7af6afc8fa 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -156,6 +156,8 @@ typedef enum {
 rv_codec_css_swsp,
 rv_codec_css_sdsp,
 rv_codec_css_sqsp,
+rv_codec_k_bs,
+rv_codec_k_rnum,
 } rv_codec;
 
 typedef enum {
@@ -521,6 +523,43 @@ typedef enum {
 rv_op_bclr = 359,
 rv_op_binv = 360,
 rv_op_bext = 361,
+rv_op_aes32esmi = 362,
+rv_op_aes32esi = 363,
+rv_op_aes32dsmi = 364,
+rv_op_aes32dsi = 365,
+rv_op_aes64ks1i = 366,
+rv_op_aes64ks2 = 367,
+rv_op_aes64im = 368,
+rv_op_aes64esm = 369,
+rv_op_aes64es = 370,
+rv_op_aes64dsm = 371,
+rv_op_aes64ds = 372,
+rv_op_sha256sig0 = 373,
+rv_op_sha256sig1 = 374,
+rv_op_sha256sum0 = 375,
+rv_op_sha256sum1 = 376,
+rv_op_sha512sig0 = 377,
+rv_op_sha512sig1 = 378,
+rv_op_sha512sum0 = 379,
+rv_op_sha512sum1 = 380,
+rv_op_sha512sum0r = 381,
+rv_op_sha512sum1r = 382,
+rv_op_sha512sig0l = 383,
+rv_op_sha512sig0h = 384,
+rv_op_sha512sig1l = 385,
+rv_op_sha512sig1h = 386,
+rv_op_sm3p0 = 387,
+rv_op_sm3p1 = 388,
+rv_op_sm4ed = 389,
+rv_op_sm4ks = 390,
+rv_op_brev8 = 391,
+rv_op_pack = 392,
+rv_op_packh = 393,
+rv_op_packw = 394,
+rv_op_unzip = 395,
+rv_op_zip = 396,
+rv_op_xperm4 = 397,
+rv_op_xperm8 = 398,
 } rv_op;
 
 /* structures */
@@ -540,6 +579,8 @@ typedef struct {
 uint8_t   succ;
 uint8_t   aq;
 uint8_t   rl;
+uint8_t   bs;
+uint8_t   rnum;
 } rv_decode;
 
 typedef struct {
@@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
 #define rv_fmt_rd_rs2 "O\t0,2"
 #define rv_fmt_rs1_offset "O\t1,o"
 #define rv_fmt_rs2_offset "O\t2,o"
+#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
+#define rv_fmt_rd_rs1_rnum"O\t0,1,n"
 
 /* pseudo-instruction constraints */
 
@@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
 { rv_op_illegal, NULL }
 };
 
+
 static const rv_comp_data rvcp_csrrs[] = {
 { rv_op_rdcycle, rvcc_rdcycle },
 { rv_op_rdtime, rvcc_rdtime },
@@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+{ "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+{ "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+{ "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+{ "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
+{ "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+{ "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+{ "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+{ "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+{ "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+{ "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+{ "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ 

[PATCH v12 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

[Weiwei Li]

 - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions

Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn32.decode  |  5 +++
 target/riscv/insn_trans/trans_rvk.c.inc | 55 +
 2 files changed, 60 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0b800b4093..db28ecdd2b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -857,3 +857,8 @@ aes64esm00 11011 . . 000 . 0110011 @r
 # *** RV64 Zkne/zknd Standard Extension ***
 aes64ks201 1 . . 000 . 0110011 @r
 aes64ks1i   00 11000 1 . 001 . 0010011 @i_aes
+# *** RV32 Zknh Standard Extension ***
+sha256sig0  00 01000 00010 . 001 . 0010011 @r2
+sha256sig1  00 01000 00011 . 001 . 0010011 @r2
+sha256sum0  00 01000 0 . 001 . 0010011 @r2
+sha256sum1  00 01000 1 . 001 . 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc 
b/target/riscv/insn_trans/trans_rvk.c.inc
index 6336b48cb5..531e2c7cb3 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -29,6 +29,12 @@
 }   \
 } while (0)
 
+#define REQUIRE_ZKNH(ctx) do {  \
+if (!ctx->cfg_ptr->ext_zknh) {  \
+return false;   \
+}   \
+} while (0)
+
 static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
   void (*func)(TCGv, TCGv, TCGv, TCGv))
 {
@@ -123,3 +129,52 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im 
*a)
 REQUIRE_ZKND(ctx);
 return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
 }
+
+static bool gen_sha256(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+   void (*func)(TCGv_i32, TCGv_i32, int32_t),
+   int32_t num1, int32_t num2, int32_t num3)
+{
+TCGv dest = dest_gpr(ctx, a->rd);
+TCGv src1 = get_gpr(ctx, a->rs1, ext);
+TCGv_i32 t0 = tcg_temp_new_i32();
+TCGv_i32 t1 = tcg_temp_new_i32();
+TCGv_i32 t2 = tcg_temp_new_i32();
+
+tcg_gen_trunc_tl_i32(t0, src1);
+tcg_gen_rotri_i32(t1, t0, num1);
+tcg_gen_rotri_i32(t2, t0, num2);
+tcg_gen_xor_i32(t1, t1, t2);
+func(t2, t0, num3);
+tcg_gen_xor_i32(t1, t1, t2);
+tcg_gen_ext_i32_tl(dest, t1);
+
+gen_set_gpr(ctx, a->rd, dest);
+tcg_temp_free_i32(t0);
+tcg_temp_free_i32(t1);
+tcg_temp_free_i32(t2);
+return true;
+}
+
+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
+{
+REQUIRE_ZKNH(ctx);
+return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 7, 18, 3);
+}
+
+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
+{
+REQUIRE_ZKNH(ctx);
+return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 17, 19, 10);
+}
+
+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
+{
+REQUIRE_ZKNH(ctx);
+return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 2, 13, 22);
+}
+
+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+{
+REQUIRE_ZKNH(ctx);
+return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
+}
-- 
2.17.1

[PATCH v12 14/14] target/riscv: rvk: expose zbk* and zk* properties

[Weiwei Li]

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 62a47c197b..dff4606585 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -849,7 +849,20 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
 
 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
-- 
2.17.1

[PATCH v12 05/14] crypto: move sm4_sbox from target/arm

[Weiwei Li]

   - share it between target/arm and target/riscv

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Alistair Francis 
Reviewed-by: Richard Henderson 
---
 crypto/meson.build |  1 +
 crypto/sm4.c   | 49 ++
 include/crypto/sm4.h   |  6 +
 target/arm/crypto_helper.c | 36 +---
 4 files changed, 57 insertions(+), 35 deletions(-)
 create mode 100644 crypto/sm4.c
 create mode 100644 include/crypto/sm4.h

diff --git a/crypto/meson.build b/crypto/meson.build
index 19c44bea89..b47352180f 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -40,6 +40,7 @@ if have_afalg
 endif
 crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
 
+util_ss.add(files('sm4.c'))
 util_ss.add(files('aes.c'))
 util_ss.add(files('init.c'))
 if gnutls.found()
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index 00..9f0cd452c7
--- /dev/null
+++ b/crypto/sm4.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 00..9bd3ebc62e
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 4c8fd34aec..d28690321f 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -15,6 +15,7 @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "crypto/aes.h"
+#include "crypto/sm4.h"
 #include "vec_internal.h"
 
 union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
 
 #undef DO_SM3TT
 
-static uint8_t const sm4_sbox[] = {
-0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
-0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
-0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
-0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
-0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
-0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
-0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
-0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
-0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
-0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
-0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
-0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
-0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
-0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
-0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
-0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
-0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
-0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
-0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
-0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca

[PATCH v12 12/14] target/riscv: rvk: add CSR support for Zkr

[Weiwei Li]

 - add SEED CSR which must be accessed with a read-write instruction:
   A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
 - add USEED, SSEED fields for MSECCFG CSR

Co-authored-by: Ruibo Lu 
Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_bits.h  |  9 +
 target/riscv/csr.c   | 80 
 target/riscv/op_helper.c |  9 +
 target/riscv/pmp.h   |  8 ++--
 4 files changed, 103 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4a9e4f7d09..4d04b20d06 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -458,6 +458,9 @@
 #define CSR_VSPMMASK0x2c1
 #define CSR_VSPMBASE0x2c2
 
+/* Crypto Extension */
+#define CSR_SEED0x015
+
 /* mstatus CSR bits */
 #define MSTATUS_UIE 0x0001
 #define MSTATUS_SIE 0x0002
@@ -800,4 +803,10 @@ typedef enum RISCVException {
 #define HVICTL_VALID_MASK  \
 (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
 
+/* seed CSR bits */
+#define SEED_OPST(0b11 << 30)
+#define SEED_OPST_BIST   (0b00 << 30)
+#define SEED_OPST_WAIT   (0b01 << 30)
+#define SEED_OPST_ES16   (0b10 << 30)
+#define SEED_OPST_DEAD   (0b11 << 30)
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1c2d3f7193..3500e07f92 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -24,6 +24,8 @@
 #include "qemu/main-loop.h"
 #include "exec/exec-all.h"
 #include "sysemu/cpu-timers.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
 
 /* CSR function table public API */
 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -301,6 +303,46 @@ static RISCVException debug(CPURISCVState *env, int csrno)
 }
 #endif
 
+static RISCVException seed(CPURISCVState *env, int csrno)
+{
+RISCVCPU *cpu = env_archcpu(env);
+
+if (!cpu->cfg.ext_zkr) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+#if !defined(CONFIG_USER_ONLY)
+/*
+ * With a CSR read-write instruction:
+ * 1) The seed CSR is always available in machine mode as normal.
+ * 2) Attempted access to seed from virtual modes VS and VU always raises
+ * an exception(virtual instruction exception only if mseccfg.sseed=1).
+ * 3) Without the corresponding access control bit set to 1, any attempted
+ * access to seed from U, S or HS modes will raise an illegal instruction
+ * exception.
+ */
+if (env->priv == PRV_M) {
+return RISCV_EXCP_NONE;
+} else if (riscv_cpu_virt_enabled(env)) {
+if (env->mseccfg & MSECCFG_SSEED) {
+return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+} else {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+} else {
+if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
+return RISCV_EXCP_NONE;
+} else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
+return RISCV_EXCP_NONE;
+} else {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+}
+#else
+return RISCV_EXCP_NONE;
+#endif
+}
+
 /* User Floating-Point CSRs */
 static RISCVException read_fflags(CPURISCVState *env, int csrno,
   target_ulong *val)
@@ -3044,6 +3086,41 @@ static RISCVException write_upmbase(CPURISCVState *env, 
int csrno,
 
 #endif
 
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+   target_ulong *ret_value,
+   target_ulong new_value,
+   target_ulong write_mask)
+{
+uint16_t random_v;
+Error *random_e = NULL;
+int random_r;
+target_ulong rval;
+
+random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
+if (unlikely(random_r < 0)) {
+/*
+ * Failed, for unknown reasons in the crypto subsystem.
+ * The best we can do is log the reason and return a
+ * failure indication to the guest.  There is no reason
+ * we know to expect the failure to be transitory, so
+ * indicate DEAD to avoid having the guest spin on WAIT.
+ */
+qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
+  __func__, error_get_pretty(random_e));
+error_free(random_e);
+rval = SEED_OPST_DEAD;
+} else {
+rval = random_v | SEED_OPST_ES16;
+}
+
+if (ret_value) {
+*ret_value = rval;
+}
+
+return RISCV_EXCP_NONE;
+}
+
 /*
  * riscv_csrrw - read and/or update control and status register
  *
@@ -3282,6 +3359,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 [CSR_TIME]  = { "time",  ctr,   read_time  },
 [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
 
+/* Crypto Exte

[PATCH v12 03/14] target/riscv: rvk: add support for zbkc extension

[Weiwei Li]

 - reuse partial instructions of zbc extension, update extension check for them

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Alistair Francis 
Reviewed-by: Richard Henderson 
---
 target/riscv/insn32.decode  | 3 ++-
 target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fdceaf621a..3a49acab37 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -770,9 +770,10 @@ clzw   011 0 . 001 . 0011011 @r2
 ctzw   011 1 . 001 . 0011011 @r2
 cpopw  011 00010 . 001 . 0011011 @r2
 
-# *** RV32 Zbc Standard Extension ***
+# *** RV32 Zbc/Zbkc Standard Extension ***
 clmul  101 .. 001 . 0110011 @r
 clmulh 101 .. 011 . 0110011 @r
+# *** RV32 extra Zbc Standard Extension ***
 clmulr 101 .. 010 . 0110011 @r
 
 # *** RV32 Zbs Standard Extension ***
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index f36577579d..5a5751557d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -489,7 +489,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
 
 static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
 {
-REQUIRE_ZBC(ctx);
+REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
 return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
 }
 
@@ -501,7 +501,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
 
 static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
 {
-REQUIRE_ZBC(ctx);
+REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
 return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
 }
 
-- 
2.17.1

[PATCH v12 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

[Weiwei Li]

 - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i 
instructions

Co-authored-by: Ruibo Lu 
Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Acked-by: Alistair Francis 
---
 target/riscv/crypto_helper.c| 169 
 target/riscv/helper.h   |   8 ++
 target/riscv/insn32.decode  |  12 ++
 target/riscv/insn_trans/trans_rvk.c.inc |  54 
 4 files changed, 243 insertions(+)

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 220d51c742..cb4783a1e9 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -102,4 +102,173 @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, 
target_ulong rs2,
 {
 return aes32_operation(shamt, rs1, rs2, false, false);
 }
+
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+(((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+(((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+(((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+(((RS1 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
+(((RS2 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+(((RS1 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+(((RS1 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+(((RS2 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
+BY(COL, B3) ^ BY(COL, B2) ^ AES_GFMUL(BY(COL, B1), 3) ^ \
+AES_GFMUL(BY(COL, B0), 2))
+
+#define AES_MIXCOLUMN(COL) ( \
+AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | AES_MIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
+AES_GFMUL(BY(COL, B3), 0x9) ^ AES_GFMUL(BY(COL, B2), 0xd) ^ \
+AES_GFMUL(BY(COL, B1), 0xb) ^ AES_GFMUL(BY(COL, B0), 0xe))
+
+#define AES_INVMIXCOLUMN(COL) ( \
+AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+   bool enc, bool mix)
+{
+uint64_t RS1 = rs1;
+uint64_t RS2 = rs2;
+uint64_t result;
+uint64_t temp;
+uint32_t col_0;
+uint32_t col_1;
+
+if (enc) {
+temp = AES_SHIFROWS_LO(RS1, RS2);
+temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
+if (mix) {
+col_0 = temp & 0x;
+col_1 = temp >> 32;
+
+col_0 = AES_MIXCOLUMN(col_0);
+col_1 = AES_MIXCOLUMN(col_1);
+
+result = ((uint64_t)col_1 << 32) | col_0;
+} else {
+result = temp;
+}
+} else {
+temp = AES_INVSHIFROWS_LO(RS1, RS2);
+temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
+if (mix) {
+col_0 = temp & 0x;
+col_1 = temp >> 32;
+
+col_0 = AES_INVMIXCOLUMN(col_0);
+col_1 = AES_INVMIXCOLUMN(col_1);
+
+result = ((uint64_t)col_1 << 32) | col_0;
+} else {
+result = temp;
+}
+}
+
+return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+uint64_t RS1 = rs1;
+uint64_t RS2 = rs

[PATCH v12 02/14] target/riscv: rvk: add support for zbkb extension

[Weiwei Li]

 - reuse partial instructions of zbb extension, update extension check for them
 - add brev8, pack, packh, packw, unzip, zip instructions

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
---
 target/riscv/bitmanip_helper.c  | 53 ++
 target/riscv/helper.h   |  3 +
 target/riscv/insn32.decode  | 45 +++-
 target/riscv/insn_trans/trans_rvb.c.inc | 94 +
 target/riscv/translate.c|  7 ++
 5 files changed, 174 insertions(+), 28 deletions(-)

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index f1b5e5549f..e003e8b25b 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -49,3 +49,56 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong 
rs2)
 
 return result;
 }
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+target_ulong HELPER(brev8)(target_ulong rs1)
+{
+target_ulong x = rs1;
+
+x = do_swap(x, 0xull, 1);
+x = do_swap(x, 0xull, 2);
+x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
+return x;
+}
+
+static const uint64_t shuf_masks[] = {
+dup_const(MO_8, 0x44),
+dup_const(MO_8, 0x30),
+dup_const(MO_16, 0x0f00),
+dup_const(MO_32, 0xff)
+};
+
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
+ uint64_t maskR, int shift)
+{
+target_ulong x = src & ~(maskL | maskR);
+
+x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
+return x;
+}
+
+target_ulong HELPER(unzip)(target_ulong rs1)
+{
+target_ulong x = rs1;
+
+x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+return x;
+}
+
+target_ulong HELPER(zip)(target_ulong rs1)
+{
+target_ulong x = rs1;
+
+x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+return x;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a669d0187b..8a3a7615f2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,9 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 /* Bitmanip */
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
 
 /* Floating Point - Half Precision */
 DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1d3ff1efe1..fdceaf621a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -717,8 +717,22 @@ sh2add_uw  001 .. 100 . 0111011 @r
 sh3add_uw  001 .. 110 . 0111011 @r
 slli_uw1  001 . 0011011 @sh
 
-# *** RV32 Zbb Standard Extension ***
+# *** RV32 Zbb/Zbkb Standard Extension ***
 andn   010 .. 111 . 0110011 @r
+rol011 .. 001 . 0110011 @r
+ror011 .. 101 . 0110011 @r
+rori   01100  101 . 0010011 @sh
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32011010 011000 . 101 . 0010011 @r2
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+  zext_h_32  100 0 . 100 . 0110011 @r2
+  pack   100 . . 100 . 0110011 @r
+}
+xnor   010 .. 100 . 0110011 @r
+# *** RV32 extra Zbb Standard Extension ***
 clz011000 00 . 001 . 0010011 @r2
 cpop   011000 10 . 001 . 0010011 @r2
 ctz011000 01 . 001 . 0010011 @r2
@@ -728,23 +742,15 @@ min101 .. 100 . 0110011 @r
 minu   101 .. 101 . 0110011 @r
 orc_b  001010 000111 . 101 . 0010011 @r2
 orn010 .. 110 . 0110011 @r
-# The encoding for rev8 differs between RV32 and RV64.
-# rev8_32 denotes the RV32 variant.
-rev8_32011010 011000 . 101 . 0010011 @r2
-rol011 .. 001 . 0110011 @r
-ror011 .. 101 . 0110011 @r
-rori   01100  101 . 0010011 @sh
 sext_b 011000 000100 . 001 . 0010011 @r2
 sext_h 011000 000101 . 001 . 0010011 @r2
-xnor   010 ..

[PATCH v12 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

[Weiwei Li]

 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions

Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
---
 target/riscv/crypto_helper.c| 105 
 target/riscv/helper.h   |   6 ++
 target/riscv/insn32.decode  |  11 +++
 target/riscv/insn_trans/trans_rvk.c.inc |  71 
 target/riscv/meson.build|   3 +-
 target/riscv/translate.c|   1 +
 6 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/crypto_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
new file mode 100644
index 00..220d51c742
--- /dev/null
+++ b/target/riscv/crypto_helper.c
@@ -0,0 +1,105 @@
+/*
+ * RISC-V Crypto Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2...@163.com
+ * Copyright (c) 2021 Zewen Ye, lust...@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "crypto/aes.h"
+#include "crypto/sm4.h"
+
+#define AES_XTIME(a) \
+((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a, b) (( \
+(((b) & 0x1) ? (a) : 0) ^ \
+(((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+(((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+(((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+{
+uint32_t u;
+
+if (fwd) {
+u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
+(AES_GFMUL(x, 2) << 0);
+} else {
+u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
+(AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
+}
+return u;
+}
+
+#define sext32_xlen(x) (target_ulong)(int32_t)(x)
+
+static inline target_ulong aes32_operation(target_ulong shamt,
+   target_ulong rs1, target_ulong rs2,
+   bool enc, bool mix)
+{
+uint8_t si = rs2 >> shamt;
+uint8_t so;
+uint32_t mixed;
+target_ulong res;
+
+if (enc) {
+so = AES_sbox[si];
+if (mix) {
+mixed = aes_mixcolumn_byte(so, true);
+} else {
+mixed = so;
+}
+} else {
+so = AES_isbox[si];
+if (mix) {
+mixed = aes_mixcolumn_byte(so, false);
+} else {
+mixed = so;
+}
+}
+mixed = rol32(mixed, shamt);
+res = rs1 ^ mixed;
+
+return sext32_xlen(res);
+}
+
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
+   target_ulong shamt)
+{
+return aes32_operation(shamt, rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
+  target_ulong shamt)
+{
+return aes32_operation(shamt, rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
+   target_ulong shamt)
+{
+return aes32_operation(shamt, rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
+  target_ulong shamt)
+{
+return aes32_operation(shamt, rs1, rs2, false, false);
+}
+#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index cfead7abfc..3c4e7e6113 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1112,3 +1112,9 @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
 DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
 DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
 DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
+
+/* Crypto functions */
+DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 75ffac9c81..0f2e661583 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,6 +35,7 @@
 %imm_b31:s1 7:1 25:6 8:4 !function=ex_shift_1
 %imm_j31:s1

[PATCH v12 00/14] support subsets of scalar crypto extension

[Weiwei Li]

This patchset implements RISC-V scalar crypto extension v1.0.0 version 
instructions.
Partial instructions are reused from B-extension.

Specification:
https://github.com/riscv/riscv-crypto

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v12

To test rvk implementation, specify cpu argument with 'zks=true,zkn=true' or 
"zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
 to enable K-extension support. This implementation can pass the ACT tests for 
K with our extended act support for qemu (available at 
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v12-with-act)

Review status:
patch 5 is reviewed by Philippe Mathieu-Daudé
patch 1~14 are acked or reviewed by Alistair Francis
patch 2~11 are reviewed by Richard Henderson (fix new comments on patch 6 and 7)

v12:
* rebase on master and riscv-to-apply.next

v11:
* patch 6: add REQUIRE_32BIT to trans_* function for aes RV32 instruction
* patch 7: add REQUIRE_64BIT to trans_* function for aes RV64 instruction

v10:
(only patch 12 is modified)
* simplify the conditions for the check in seed function
* add NULL check for ret_val in rmw_seed function
* remain the change of MSECCFG_* to align with the added MSECCFG_*SEED

v9:
* check whether seed is accessed by a read-write instruction in helper_csrr.
* fix disas for partial scalar crypto instructions
* rebase on 
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00156.html

v8:
* replace large macro for trans function of sha256/512 instructions with 
parameters to gen_sha* function in patch 8,9,10
* fix tcg_const_tl to tcg_constant_tl
* fix rmw_seed function

v7:
* reuse gen_unary/gen_arith to simplify trans_* functions
* replace DEF_HELPER_* with DEF_HEPER_FLAG_*
* move aes64 related macros from patch 6 to patch 7
* create common helper gen_aes32_sm4 for aes32 and sm4 related instructions
* replace bs with shamt (bs << 3)
* optimize trans function for sha256, sha512 and sm4 instructions to be 
generated inline

v6:
* add reviewed-by tags
* rebase on upstream

v5:
* split the big patches

v4:
* drop "x-" in exposed properties
* delete unrelated changes

v3:
* add extension check for SEED csr access

v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm

Weiwei Li (14):
  target/riscv: rvk: add cfg properties for zbk* and zk*
  target/riscv: rvk: add support for zbkb extension
  target/riscv: rvk: add support for zbkc extension
  target/riscv: rvk: add support for zbkx extension
  crypto: move sm4_sbox from target/arm
  target/riscv: rvk: add support for zknd/zkne extension in RV32
  target/riscv: rvk: add support for zkne/zknd extension in RV64
  target/riscv: rvk: add support for sha256 related instructions in zknh
extension
  target/riscv: rvk: add support for sha512 related instructions for
RV32 in zknh extension
  target/riscv: rvk: add support for sha512 related instructions for
RV64 in zknh extension
  target/riscv: rvk: add support for zksed/zksh extension
  target/riscv: rvk: add CSR support for Zkr
  disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
  target/riscv: rvk: expose zbk* and zk* properties

 crypto/meson.build  |   1 +
 crypto/sm4.c|  49 +++
 disas/riscv.c   | 173 ++-
 include/crypto/sm4.h|   6 +
 target/arm/crypto_helper.c  |  36 +--
 target/riscv/bitmanip_helper.c  |  80 +
 target/riscv/cpu.c  |  36 +++
 target/riscv/cpu.h  |  13 +
 target/riscv/cpu_bits.h |   9 +
 target/riscv/crypto_helper.c| 302 ++
 target/riscv/csr.c  |  80 +
 target/riscv/helper.h   |  22 ++
 target/riscv/insn32.decode  |  97 --
 target/riscv/insn_trans/trans_rvb.c.inc | 116 ++-
 target/riscv/insn_trans/trans_rvk.c.inc | 391 
 target/riscv/meson.build|   3 +-
 target/riscv/op_helper.c|   9 +
 target/riscv/pmp.h  |   8 +-
 target/riscv/translate.c|   8 +
 19 files changed, 1368 insertions(+), 71 deletions(-)
 create mode 100644 crypto/sm4.c
 create mode 100644 include/crypto/sm4.h
 create mode 100644 target/riscv/crypto_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc

-- 
2.17.1

[PATCH v12 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

[Weiwei Li]

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Acked-by: Alistair Francis 
---
 target/riscv/cpu.c | 23 +++
 target/riscv/cpu.h | 13 +
 2 files changed, 36 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ace68ed855..62a47c197b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -612,6 +612,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 cpu->cfg.ext_zfinx = true;
 }
 
+if (cpu->cfg.ext_zk) {
+cpu->cfg.ext_zkn = true;
+cpu->cfg.ext_zkr = true;
+cpu->cfg.ext_zkt = true;
+}
+
+if (cpu->cfg.ext_zkn) {
+cpu->cfg.ext_zbkb = true;
+cpu->cfg.ext_zbkc = true;
+cpu->cfg.ext_zbkx = true;
+cpu->cfg.ext_zkne = true;
+cpu->cfg.ext_zknd = true;
+cpu->cfg.ext_zknh = true;
+}
+
+if (cpu->cfg.ext_zks) {
+cpu->cfg.ext_zbkb = true;
+cpu->cfg.ext_zbkc = true;
+cpu->cfg.ext_zbkx = true;
+cpu->cfg.ext_zksed = true;
+cpu->cfg.ext_zksh = true;
+}
+
 /* Set the ISA extensions, checks should have happened above */
 if (cpu->cfg.ext_i) {
 ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 46c66fbf8e..fe6c9a2c92 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -377,7 +377,20 @@ struct RISCVCPUConfig {
 bool ext_zba;
 bool ext_zbb;
 bool ext_zbc;
+bool ext_zbkb;
+bool ext_zbkc;
+bool ext_zbkx;
 bool ext_zbs;
+bool ext_zk;
+bool ext_zkn;
+bool ext_zknd;
+bool ext_zkne;
+bool ext_zknh;
+bool ext_zkr;
+bool ext_zks;
+bool ext_zksed;
+bool ext_zksh;
+bool ext_zkt;
 bool ext_counters;
 bool ext_ifencei;
 bool ext_icsr;
-- 
2.17.1

[PATCH v12 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

[Weiwei Li]

 - add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and 
sha512sig1h instructions

Co-authored-by: Zewen Ye 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn32.decode  |   6 ++
 target/riscv/insn_trans/trans_rvk.c.inc | 100 
 2 files changed, 106 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index db28ecdd2b..02a0c71890 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -862,3 +862,9 @@ sha256sig0  00 01000 00010 . 001 . 0010011 @r2
 sha256sig1  00 01000 00011 . 001 . 0010011 @r2
 sha256sum0  00 01000 0 . 001 . 0010011 @r2
 sha256sum1  00 01000 1 . 001 . 0010011 @r2
+sha512sum0r 01 01000 . . 000 . 0110011 @r
+sha512sum1r 01 01001 . . 000 . 0110011 @r
+sha512sig0l 01 01010 . . 000 . 0110011 @r
+sha512sig0h 01 01110 . . 000 . 0110011 @r
+sha512sig1l 01 01011 . . 000 . 0110011 @r
+sha512sig1h 01 0 . . 000 . 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc 
b/target/riscv/insn_trans/trans_rvk.c.inc
index 531e2c7cb3..9ed057a153 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -178,3 +178,103 @@ static bool trans_sha256sum1(DisasContext *ctx, 
arg_sha256sum1 *a)
 REQUIRE_ZKNH(ctx);
 return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
 }
+
+static bool gen_sha512_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
+void (*func1)(TCGv_i64, TCGv_i64, int64_t),
+void (*func2)(TCGv_i64, TCGv_i64, int64_t),
+int64_t num1, int64_t num2, int64_t num3)
+{
+TCGv dest = dest_gpr(ctx, a->rd);
+TCGv src1 = get_gpr(ctx, a->rs1, ext);
+TCGv src2 = get_gpr(ctx, a->rs2, ext);
+TCGv_i64 t0 = tcg_temp_new_i64();
+TCGv_i64 t1 = tcg_temp_new_i64();
+TCGv_i64 t2 = tcg_temp_new_i64();
+
+tcg_gen_concat_tl_i64(t0, src1, src2);
+func1(t1, t0, num1);
+func2(t2, t0, num2);
+tcg_gen_xor_i64(t1, t1, t2);
+tcg_gen_rotri_i64(t2, t0, num3);
+tcg_gen_xor_i64(t1, t1, t2);
+tcg_gen_trunc_i64_tl(dest, t1);
+
+gen_set_gpr(ctx, a->rd, dest);
+tcg_temp_free_i64(t0);
+tcg_temp_free_i64(t1);
+tcg_temp_free_i64(t2);
+return true;
+}
+
+static bool trans_sha512sum0r(DisasContext *ctx, arg_sha512sum0r *a)
+{
+REQUIRE_32BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+   tcg_gen_rotli_i64, 25, 30, 28);
+}
+
+static bool trans_sha512sum1r(DisasContext *ctx, arg_sha512sum1r *a)
+{
+REQUIRE_32BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+   tcg_gen_rotri_i64, 23, 14, 18);
+}
+
+static bool trans_sha512sig0l(DisasContext *ctx, arg_sha512sig0l *a)
+{
+REQUIRE_32BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64,
+   tcg_gen_rotri_i64, 1, 7, 8);
+}
+
+static bool trans_sha512sig1l(DisasContext *ctx, arg_sha512sig1l *a)
+{
+REQUIRE_32BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+   tcg_gen_rotri_i64, 3, 6, 19);
+}
+
+static bool gen_sha512h_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*func)(TCGv_i64, TCGv_i64, int64_t),
+ int64_t num1, int64_t num2, int64_t num3)
+{
+TCGv dest = dest_gpr(ctx, a->rd);
+TCGv src1 = get_gpr(ctx, a->rs1, ext);
+TCGv src2 = get_gpr(ctx, a->rs2, ext);
+TCGv_i64 t0 = tcg_temp_new_i64();
+TCGv_i64 t1 = tcg_temp_new_i64();
+TCGv_i64 t2 = tcg_temp_new_i64();
+
+tcg_gen_concat_tl_i64(t0, src1, src2);
+func(t1, t0, num1);
+tcg_gen_ext32u_i64(t2, t0);
+tcg_gen_shri_i64(t2, t2, num2);
+tcg_gen_xor_i64(t1, t1, t2);
+tcg_gen_rotri_i64(t2, t0, num3);
+tcg_gen_xor_i64(t1, t1, t2);
+tcg_gen_trunc_i64_tl(dest, t1);
+
+gen_set_gpr(ctx, a->rd, dest);
+tcg_temp_free_i64(t0);
+tcg_temp_free_i64(t1);
+tcg_temp_free_i64(t2);
+return true;
+}
+
+static bool trans_sha512sig0h(DisasContext *ctx, arg_sha512sig0h *a)
+{
+REQUIRE_32BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 1, 7, 8);
+}
+
+static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
+{
+REQUIRE_32BIT(ctx);
+REQUIRE_ZKNH(ctx);
+return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
+}
-- 
2.17.1

[PATCH v12 04/14] target/riscv: rvk: add support for zbkx extension

[Weiwei Li]

 - add xperm4 and xperm8 instructions

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Richard Henderson 
Acked-by: Alistair Francis 
---
 target/riscv/bitmanip_helper.c  | 27 +
 target/riscv/helper.h   |  2 ++
 target/riscv/insn32.decode  |  4 
 target/riscv/insn_trans/trans_rvb.c.inc | 18 +
 4 files changed, 51 insertions(+)

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e003e8b25b..b99c4a39a1 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -102,3 +102,30 @@ target_ulong HELPER(zip)(target_ulong rs1)
 x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
 return x;
 }
+
+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
+uint32_t sz_log2)
+{
+target_ulong r = 0;
+target_ulong sz = 1LL << sz_log2;
+target_ulong mask = (1LL << sz) - 1;
+target_ulong pos;
+
+for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
+pos = ((rs2 >> i) & mask) << sz_log2;
+if (pos < sizeof(target_ulong) * 8) {
+r |= ((rs1 >> pos) & mask) << i;
+}
+}
+return r;
+}
+
+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
+{
+return do_xperm(rs1, rs2, 2);
+}
+
+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
+{
+return do_xperm(rs1, rs2, 3);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8a3a7615f2..cfead7abfc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -69,6 +69,8 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Floating Point - Half Precision */
 DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3a49acab37..75ffac9c81 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -776,6 +776,10 @@ clmulh 101 .. 011 . 0110011 @r
 # *** RV32 extra Zbc Standard Extension ***
 clmulr 101 .. 010 . 0110011 @r
 
+# *** RV32 Zbkx Standard Extension ***
+xperm4 0010100 .. 010 . 0110011 @r
+xperm8 0010100 .. 100 . 0110011 @r
+
 # *** RV32 Zbs Standard Extension ***
 bclr   0100100 .. 001 . 0110011 @r
 bclri  01001. ... 001 . 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 5a5751557d..e2b8329f1e 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -48,6 +48,12 @@
 }\
 } while (0)
 
+#define REQUIRE_ZBKX(ctx) do {   \
+if (!ctx->cfg_ptr->ext_zbkx) {   \
+return false;\
+}\
+} while (0)
+
 static void gen_clz(TCGv ret, TCGv arg1)
 {
 tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -574,3 +580,15 @@ static bool trans_zip(DisasContext *ctx, arg_zip *a)
 REQUIRE_ZBKB(ctx);
 return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
 }
+
+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
+{
+REQUIRE_ZBKX(ctx);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
+}
+
+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
+{
+REQUIRE_ZBKX(ctx);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
+}
-- 
2.17.1

RE: Backtrace stopped: previous frame identical to this frame (corrupt stack?) , even with fresh qemu and linux build

[Chan Kim]

Hi, Mulyadi

Thank you for replying.

I found CONFIG_DEBUG_FRAME_POINTER, CONFIG_DEBUG_INFO are already set by 
default.

And I tried adding CONFIG_DEBUG_KERNEL, CONFIG_KGDB, CONFIG_GDB_SCRIPTS, 
CONFIG_STACKTRACE all to no avail.

Regards,

Chan

 

From: Mulyadi Santosa  
Sent: Friday, April 22, 2022 11:53 PM
To: Chan Kim 
Cc: qemu-devel ; kernelnewbies 

Subject: Re: Backtrace stopped: previous frame identical to this frame (corrupt 
stack?) , even with fresh qemu and linux build

 

 

 

On Fri, Apr 22, 2022 at 7:30 PM Chan Kim mailto:c...@etri.re.kr> > wrote:

Hello all,

Really strange thing happening here.. I can't see the full stack trace with
'bt' command in gdb.
So I tried with fresh linux-5.10.122 source and qemu-6.2.0 source and it's
happening too!
(it's happening when I do combinations with linux 5.10.0 and qemu-5.1.0. But
it's not happening with linux-5.4.21)

I would be grateful if somebody could check if this happens to other people
or just me.

1. download linux-5.1.122 tarball from https://www.kernel.org/ 
2. uncompress it and set env variable ARCH=arm64,
CROSS_COMPILE=aarch64-none-elf- , do "make defconfig" and "make -j`nproc`
Image"
3. download qemu-6.2.0 from https://www.qemu.org/
4. uncompress it and do "mkdir build" "cd build" "../configure
--target-list=aarch64-softmmu --enable-debug"
5. run qemu and wait for debugger to attach.
qemu-6.2.0/build/aarch64-softmmu/qemu-system-aarch64 -machine
virt,gic-version=max,secure=off,virtualization=true -cpu max -kernel
linux-5.10.112/arch/arm64/boot/Image -m 2G -nographic -netdev
user,id=vnet,hostfwd=:127.0.0.1:0-:22,tftp=/srv/tftp -device
virtio-net-pci,netdev=vnet -machine iommu=smmuv3 --append "root=/dev/ram
init=/init nokaslr earlycon ip=dhcp hugepages=16" -s -S
6. run debugger, do "aarch64-none-elf-gdb linux-6.10.112/vmlinux -x\

 

It has been long time since I compiled linux kernel but I guess, either you 
need to compile kernel with enabled frame pointer, and/or you need to enable 
debug symbol embedded into final kernel image. cmiiw

 

gdb_script"
(gdb_script content : 
target remote :1234
layout src
b start_kernel
b __driver_attach
)

Now, in gdb, when you press 'c' twice, it'll stop at the first
__driver_attach. (first one stops at start_kernel).
When you are at __attach_driver, type 'bt'. See if you see the full function
stack trace.
This is what I see. 
(gdb) bt
#0  __driver_attach (dev=0x02582810, data=0x800011dc2358
)
at drivers/base/dd.c:1060
#1  0x8000107a3ed0 in bus_for_each_dev (bus=,
start=,
data=0x800011dc2358 ,
fn=0x8000107a6f60 <__driver_attach>)
at drivers/base/bus.c:305
#2  0xd6d78000107a5c58 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)

I used to see more thatn 20 stacks trace but strangely I see only two. 
I can still see many stacks for linux-5.4.21 that I was working with in the
past. 
Could anyone check if this happens to anyone?
I think if I add BLK_DEV_RAM and set initramfs.cpio.gz in the linux build,
the kernel will boot ok to the shell prompt.
Only the gdb can't show the stack levels.

My OS : ubuntu-20.04  5.13.0-35-generic

$ aarch64-none-elf-gdb --version
GNU gdb (GNU Toolchain for the A-profile Architecture 10.2-2020.11
(arm-10.16)) 10.1.90.20201028-git
Copyright (C) 2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later

This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.

Thank you.
Chan Kim





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-- 

regards,

Mulyadi Santosa
Freelance Linux trainer and consultant

blog: the-hydra.blogspot.com  
training: mulyaditraining.blogspot.com  

Re: [EXT] Re: [PATCH v2] target/riscv: Fix incorrect PTE merge in walk_pte

[Alistair Francis]

On Fri, Apr 22, 2022 at 10:10 PM Ralf Ramsauer
 wrote:
>
>
>
> On 22/04/2022 04:54, Bin Meng wrote:
> > On Fri, Apr 22, 2022 at 10:53 AM Bin Meng  wrote:
> >>
> >> On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
> >>  wrote:
> >>>
> >>> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> >>> case, walk_pte will erroneously merge them.
> >>>
> >>> Enforce the split up, by tracking the virtual base address.
> >>>
> >>> Let's say we have the mapping:
> >>> 0x8120 -> 0x89623000 (4K)
> >>> 0x8120f000 -> 0x89624000 (4K)
> >>>
> >>> Before, walk_pte would have shown:
> >>>
> >>> vaddrpaddrsize attr
> >>>    ---
> >>> 8120 89623000 2000 rwxu-ad
> >>>
> >>> as it only checks for subsequent paddrs. With this patch, it becomes:
> >>>
> >>> vaddrpaddrsize attr
> >>>    ---
> >>> 8120 89623000 1000 rwxu-ad
> >>> 8120f000 89624000 1000 rwxu-ad
> >>>
> >>> Signed-off-by: Ralf Ramsauer 
> >>> ---
> >>>   target/riscv/monitor.c | 5 -
> >>>   1 file changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> >>> index 7efb4b62c1..9dc4cb1156 100644
> >>> --- a/target/riscv/monitor.c
> >>> +++ b/target/riscv/monitor.c
> >>> @@ -84,6 +84,7 @@ static void walk_pte(Monitor *mon, hwaddr base, 
> >>> target_ulong start,
> >>>   {
> >>>   hwaddr pte_addr;
> >>>   hwaddr paddr;
> >>> +target_ulong last_start = -1;
> >>>   target_ulong pgsize;
> >>>   target_ulong pte;
> >>>   int ptshift;
> >>> @@ -116,7 +117,8 @@ static void walk_pte(Monitor *mon, hwaddr base, 
> >>> target_ulong start,
> >>>* contiguous mapped block details.
> >>>*/
> >>
> >> Please also update the comments above to mention the new case you added 
> >> here.
>
> Shall I provide a v3? No problem, if that makes your life easier.
> Otherwise, you could also squash attached comment on integration.

Yes, please submit a v3

Alistair

>
> Thanks
>Ralf
>
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index 02512ed48f..1cb0932e03 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -143,9 +143,9 @@ static void walk_pte(Monitor *mon, hwaddr base,
> target_ulong start,
>* A leaf PTE has been found
>*
>* If current PTE's permission bits differ from the
> last one,
> - * or current PTE's ppn does not make a contiguous physical
> - * address block together with the last one, print out
> the last
> - * contiguous mapped block details.
> +* or the current PTE breaks up a contiguous virtual or
> +* physical mapping, address block together with the
> last one,
> +* print out the last contiguous mapped block details.
>*/
>   if ((*last_attr != attr) ||
>   (*last_paddr + *last_size != paddr) ||
>

Re: [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

[Alistair Francis]

On Fri, Apr 22, 2022 at 2:05 PM  wrote:
>
> From: Frank Chang 
>
> Allow user to set core's marchid, mvendorid, mipid CSRs through
> -cpu command line option.
>
> The default values of marchid and mipid are built with QEMU's version
> numbers.
>
> Signed-off-by: Frank Chang 
> Reviewed-by: Jim Shu 
> Reviewed-by: Alistair Francis 
> Reviewed-by: Bin Meng 

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu.c |  9 +
>  target/riscv/cpu.h |  4 
>  target/riscv/csr.c | 38 ++
>  3 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0c774056c5..ace68ed855 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
>  /* RISC-V CPU definitions */
>
> +#define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
> + (QEMU_VERSION_MINOR << 8)  | \
> + (QEMU_VERSION_MICRO))
> +#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
> +
>  static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
>
>  struct isa_ext_data {
> @@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
>  DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> +DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> +DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> +DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
> +
>  DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>  DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>  DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 34c22d5d3b..46c66fbf8e 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -393,6 +393,10 @@ struct RISCVCPUConfig {
>  bool ext_zve32f;
>  bool ext_zve64f;
>
> +uint32_t mvendorid;
> +uint64_t marchid;
> +uint64_t mipid;
> +
>  /* Vendor-specific custom extensions */
>  bool ext_XVentanaCondOps;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6ba85e7b5d..1c2d3f7193 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, 
> int csrno,
>  return RISCV_EXCP_NONE;
>  }
>
> +static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +*val = cpu->cfg.mvendorid;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_marchid(CPURISCVState *env, int csrno,
> +   target_ulong *val)
> +{
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +*val = cpu->cfg.marchid;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_mipid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +*val = cpu->cfg.mipid;
> +return RISCV_EXCP_NONE;
> +}
> +
>  static RISCVException read_mhartid(CPURISCVState *env, int csrno,
> target_ulong *val)
>  {
> @@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>  [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
>
>  /* Machine Information Registers */
> -[CSR_MVENDORID] = { "mvendorid", any,   read_zero},
> -[CSR_MARCHID]   = { "marchid",   any,   read_zero},
> -[CSR_MIMPID]= { "mimpid",any,   read_zero},
> -[CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> +[CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
> +[CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
> +[CSR_MIMPID]= { "mimpid",any,   read_mipid },
> +[CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
>
>  [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
>  .min_priv_ver = PRIV_VERSION_1_12_0 
> },
> --
> 2.35.1
>
>

Re: [PATCH 2/2] hw/riscv: Don't add empty bootargs to device tree

[Alistair Francis]

On Thu, Apr 21, 2022 at 3:58 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the changes were entirely useless, due to MachineState::kernel_cmdline
> can't be NULL at all as the default value is given as an empty string.
> (see hw/core/machine.c::machine_initfn()).
>
> Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
> a segfault had already been observed by dereferencing the NULL pointer.
> It should be worded as *empty" bootargs.
>
> Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> Signed-off-by: Bin Meng 

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>
>  hw/riscv/microchip_pfsoc.c | 2 +-
>  hw/riscv/sifive_u.c| 2 +-
>  hw/riscv/spike.c   | 2 +-
>  hw/riscv/virt.c| 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index cafd1fc9ae..10a5d0e501 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -571,7 +571,7 @@ static void 
> microchip_icicle_kit_machine_init(MachineState *machine)
>"linux,initrd-end", end);
>  }
>
> -if (machine->kernel_cmdline) {
> +if (machine->kernel_cmdline && *machine->kernel_cmdline) {
>  qemu_fdt_setprop_string(machine->fdt, "/chosen",
>  "bootargs", machine->kernel_cmdline);
>  }
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7fbc7dea42..cc8c7637cb 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -511,7 +511,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry 
> *memmap,
>  g_free(nodename);
>
>  update_bootargs:
> -if (cmdline) {
> +if (cmdline && *cmdline) {
>  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
>  }
>  }
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 1562b000bb..068ba3493e 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -177,7 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry 
> *memmap,
>  qemu_fdt_add_subnode(fdt, "/chosen");
>  qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
>
> -if (cmdline) {
> +if (cmdline && *cmdline) {
>  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
>  }
>  }
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index da50cbed43..a628a3abdf 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -998,7 +998,7 @@ static void create_fdt(RISCVVirtState *s, const 
> MemMapEntry *memmap,
>  create_fdt_flash(s, memmap);
>
>  update_bootargs:
> -if (cmdline) {
> +if (cmdline && *cmdline) {
>  qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
>  }
>  }
> --
> 2.25.1
>
>

Re: [PATCH v11 00/14] support subsets of scalar crypto extension

[Alistair Francis]

On Tue, Apr 19, 2022 at 11:58 AM Weiwei Li  wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version 
> instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v11
>
> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true' or 
> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
>  to enable K-extension support. This implementation can pass the ACT tests 
> for K with our extended act support for qemu (available at 
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v11-with-act)
>
> Review status:
> patch 5 is reviewed by Philippe Mathieu-Daudé
> patch 1~11 and 13-14 are acked or reviewed by Alistair Francis
> patch 2~11 are reviewed by Richard Henderson (fix new comments on patch 6 and 
> 7)
>
> v11:
> * patch 6: add REQUIRE_32BIT to trans_* function for aes RV32 instruction
> * patch 7: add REQUIRE_64BIT to trans_* function for aes RV64 instruction
>
> v10:
> (only patch 12 is modified)
> * simplify the conditions for the check in seed function
> * add NULL check for ret_val in rmw_seed function
> * remain the change of MSECCFG_* to align with the added MSECCFG_*SEED
>
> v9:
> * check whether seed is accessed by a read-write instruction in helper_csrr.
> * fix disas for partial scalar crypto instructions
> * rebase on 
> https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00156.html
>
> v8:
> * replace large macro for trans function of sha256/512 instructions with 
> parameters to gen_sha* function in patch 8,9,10
> * fix tcg_const_tl to tcg_constant_tl
> * fix rmw_seed function
>
> v7:
> * reuse gen_unary/gen_arith to simplify trans_* functions
> * replace DEF_HELPER_* with DEF_HEPER_FLAG_*
> * move aes64 related macros from patch 6 to patch 7
> * create common helper gen_aes32_sm4 for aes32 and sm4 related instructions
> * replace bs with shamt (bs << 3)
> * optimize trans function for sha256, sha512 and sm4 instructions to be 
> generated inline
>
> v6:
> * add reviewed-by tags
> * rebase on upstream
>
> v5:
> * split the big patches
>
> v4:
> * drop "x-" in exposed properties
> * delete unrelated changes
>
> v3:
> * add extension check for SEED csr access
>
> v2:
> * optimize implementation for brev8, xperm, zip, unzip
> * use aes related sbox array from crypto/aes.h
> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>
> Weiwei Li (14):
>   target/riscv: rvk: add cfg properties for zbk* and zk*
>   target/riscv: rvk: add support for zbkb extension
>   target/riscv: rvk: add support for zbkc extension
>   target/riscv: rvk: add support for zbkx extension
>   crypto: move sm4_sbox from target/arm
>   target/riscv: rvk: add support for zknd/zkne extension in RV32
>   target/riscv: rvk: add support for zkne/zknd extension in RV64
>   target/riscv: rvk: add support for sha256 related instructions in zknh
> extension
>   target/riscv: rvk: add support for sha512 related instructions for
> RV32 in zknh extension
>   target/riscv: rvk: add support for sha512 related instructions for
> RV64 in zknh extension
>   target/riscv: rvk: add support for zksed/zksh extension
>   target/riscv: rvk: add CSR support for Zkr
>   disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>   target/riscv: rvk: expose zbk* and zk* properties

Do you mind rebasing this on the latest master? Then I can merge it

Alistair

>
>  crypto/meson.build  |   1 +
>  crypto/sm4.c|  49 +++
>  disas/riscv.c   | 173 ++-
>  include/crypto/sm4.h|   6 +
>  target/arm/crypto_helper.c  |  36 +--
>  target/riscv/bitmanip_helper.c  |  80 +
>  target/riscv/cpu.c  |  36 +++
>  target/riscv/cpu.h  |  13 +
>  target/riscv/cpu_bits.h |   9 +
>  target/riscv/crypto_helper.c| 302 ++
>  target/riscv/csr.c  |  80 +
>  target/riscv/helper.h   |  22 ++
>  target/riscv/insn32.decode  |  97 --
>  target/riscv/insn_trans/trans_rvb.c.inc | 116 ++-
>  target/riscv/insn_trans/trans_rvk.c.inc | 391 
>  target/riscv/meson.build|   3 +-
>  target/riscv/op_helper.c|   9 +
>  target/riscv/pmp.h  |   8 +-
>  target/riscv/translate.c|   8 +
>  19 files changed, 1368 insertions(+), 71 deletions(-)
>  create mode 100644 crypto/sm4.c
>  create mode 100644 include/crypto/sm4.h
>  create mode 100644 target/riscv/crypto_helper.c
>  create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> --
> 2.17.1
>
>

Re: [RFC 00/18] vfio: Adopt iommufd

[Alex Williamson]

[Cc +libvirt folks]

On Thu, 14 Apr 2022 03:46:52 -0700
Yi Liu  wrote:

> With the introduction of iommufd[1], the linux kernel provides a generic
> interface for userspace drivers to propagate their DMA mappings to kernel
> for assigned devices. This series does the porting of the VFIO devices
> onto the /dev/iommu uapi and let it coexist with the legacy implementation.
> Other devices like vpda, vfio mdev and etc. are not considered yet.
> 
> For vfio devices, the new interface is tied with device fd and iommufd
> as the iommufd solution is device-centric. This is different from legacy
> vfio which is group-centric. To support both interfaces in QEMU, this
> series introduces the iommu backend concept in the form of different
> container classes. The existing vfio container is named legacy container
> (equivalent with legacy iommu backend in this series), while the new
> iommufd based container is named as iommufd container (may also be mentioned
> as iommufd backend in this series). The two backend types have their own
> way to setup secure context and dma management interface. Below diagram
> shows how it looks like with both BEs.
> 
> VFIO   AddressSpace/Memory
> +---+  +--+  +-+  +-+
> |  pci  |  | platform |  |  ap |  | ccw |
> +---+---+  ++-+  +--+--+  +--+--+ +--+
> |   |   |||   AddressSpace   |
> |   |   ||++-+
> +---V---V---VV+   /
> |   VFIOAddressSpace  | <+
> |  |  |  MemoryListener
> |  VFIOContainer list |
> +---+++
> ||
> ||
> +---V--++V--+
> |   iommufd||vfio legacy|
> |  container   || container |
> +---+--+++--+
> ||
> | /dev/iommu | /dev/vfio/vfio
> | /dev/vfio/devices/vfioX| /dev/vfio/$group_id
>  Userspace  ||
>  ===++
>  Kernel |  device fd |
> +---+| group/container fd
> | (BIND_IOMMUFD || (SET_CONTAINER/SET_IOMMU)
> |  ATTACH_IOAS) || device fd
> |   ||
> |   +---VV-+
> iommufd |   |vfio  |
> (map/unmap  |   +-++---+
>  ioas_copy) | || map/unmap
> | ||
>  +--V--++-V--+  +--V+
>  | iommfd core ||  device|  |  vfio iommu   |
>  +-+++  +---+
> 
> [Secure Context setup]
> - iommufd BE: uses device fd and iommufd to setup secure context
>   (bind_iommufd, attach_ioas)
> - vfio legacy BE: uses group fd and container fd to setup secure context
>   (set_container, set_iommu)
> [Device access]
> - iommufd BE: device fd is opened through /dev/vfio/devices/vfioX
> - vfio legacy BE: device fd is retrieved from group fd ioctl
> [DMA Mapping flow]
> - VFIOAddressSpace receives MemoryRegion add/del via MemoryListener
> - VFIO populates DMA map/unmap via the container BEs
>   *) iommufd BE: uses iommufd
>   *) vfio legacy BE: uses container fd
> 
> This series qomifies the VFIOContainer object which acts as a base class
> for a container. This base class is derived into the legacy VFIO container
> and the new iommufd based container. The base class implements generic code
> such as code related to memory_listener and address space management whereas
> the derived class implements callbacks that depend on the kernel user space
> being used.
> 
> The selection of the backend is made on a device basis using the new
> iommufd option (on/off/auto). By default the iommufd backend is selected
> if supported by the host and by QEMU (iommufd KConfig). This option is
> currently available only for the vfio-pci device. For other types of
> devices, it does not yet exist and the legacy BE is chosen by default.

I've discussed this a bit with Eric, but let me propose a different
command line interface.  Libvirt generally likes to pass file
descriptors to QEMU rather than grant it access to those files
directly.  This was problematic with vfio-pci because libvirt can't
easily know when QEMU will want to grab another /dev/vfio/vfio
container.  Therefore we abandoned 

Re: [PATCH] iotests/108: Fix when missing user_allow_other

[Eric Blake]

On Thu, Apr 21, 2022 at 04:24:35PM +0200, Hanna Reitz wrote:
> FUSE exports' allow-other option defaults to "auto", which means that it
> will try passing allow_other as a mount option, and fall back to not
> using it when an error occurs.  We make no effort to hide fusermount's
> error message (because it would be difficult, and because users might
> want to know about the fallback occurring), and so when allow_other does
> not work (primarily when /etc/fuse.conf does not contain
> user_allow_other), this error message will appear and break the
> reference output.
> 
> We do not need allow_other here, though, so we can just pass
> allow-other=off to fix that.
> 
> Reported-by: Markus Armbruster 
> Signed-off-by: Hanna Reitz 
> ---
>  tests/qemu-iotests/108 | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I hit this today as well, and your fix works.

Tested-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [RFC 15/18] vfio/iommufd: Implement iommufd backend

[Alex Williamson]

On Fri, 22 Apr 2022 11:58:15 -0300
Jason Gunthorpe  wrote:
> 
> I don't see IOMMU_IOAS_IOVA_RANGES called at all, that seems like a
> problem..

Not as much as you might think.  Note that you also won't find QEMU
testing VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE in the QEMU vfio-pci
driver either.  The vfio-nvme driver does because it has control of the
address space it chooses to use, but for vfio-pci the address space is
dictated by the VM and there's not a lot of difference between knowing
in advance that a mapping conflicts with a reserved range or just
trying add the mapping and taking appropriate action if it fails.
Thanks,

Alex

Re: [PATCH v2 for-7.1 0/9] nbd: actually make s->state thread-safe

[Eric Blake]

On Sat, Apr 16, 2022 at 07:03:57PM +, Lukas Straub wrote:
> On Thu, 14 Apr 2022 19:57:47 +0200
> Paolo Bonzini  wrote:
> 
> > The main point of this series is patch 7, which removes the dubious and
> > probably wrong use of atomics in block/nbd.c.  This in turn is enabled
> > mostly by the cleanups in patches 3-5.  Together, they introduce a
> > QemuMutex that synchronizes the NBD client coroutines, the reconnect_delay
> > timer and nbd_cancel_in_flight() as well.
> > 
> > The fixes happen to remove an incorrect use of qemu_co_queue_restart_all
> > and qemu_co_enter_next on the s->free_sema CoQueue, which was not guarded
> > by s->send_mutex.
> > 
> > The rest is bugfixes, simplifying the code a bit, and extra documentation.

> For the whole series:
> 
> Reviewed-by: Lukas Straub 

I've queued the series through my NBD tree for a pull request in the next week.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [PATCH v2 1/3] hw/audio/ac97: Coding style fixes to avoid checkpatch errors

[Víctor Colombo]

On 22/04/2022 12:14, BALATON Zoltan wrote:

Signed-off-by: BALATON Zoltan 
---
  hw/audio/ac97.c | 727 
  1 file changed, 357 insertions(+), 370 deletions(-)

diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c
index 3cb8131060..0b1d8ce9c6 100644
--- a/hw/audio/ac97.c
+++ b/hw/audio/ac97.c
@@ -87,39 +87,39 @@ enum {
  #define GC_CR2  /* rw */
  #define GC_VALID_MASK ((1 << 6) - 1)
  
-#define GS_MD3   (1<<17)/* rw */

-#define GS_AD3   (1<<16)/* rw */
-#define GS_RCS   (1<<15)/* rwc */
-#define GS_B3S12 (1<<14)/* ro */
-#define GS_B2S12 (1<<13)/* ro */
-#define GS_B1S12 (1<<12)/* ro */
-#define GS_S1R1  (1<<11)/* rwc */
-#define GS_S0R1  (1<<10)/* rwc */
-#define GS_S1CR  (1<<9) /* ro */
-#define GS_S0CR  (1<<8) /* ro */
-#define GS_MINT  (1<<7) /* ro */
-#define GS_POINT (1<<6) /* ro */
-#define GS_PIINT (1<<5) /* ro */
-#define GS_RSRVD ((1<<4)|(1<<3))
-#define GS_MOINT (1<<2) /* ro */
-#define GS_MIINT (1<<1) /* ro */
+#define GS_MD3   (1 << 17)/* rw */
+#define GS_AD3   (1 << 16)/* rw */
+#define GS_RCS   (1 << 15)/* rwc */
+#define GS_B3S12 (1 << 14)/* ro */
+#define GS_B2S12 (1 << 13)/* ro */
+#define GS_B1S12 (1 << 12)/* ro */
+#define GS_S1R1  (1 << 11)/* rwc */
+#define GS_S0R1  (1 << 10)/* rwc */
+#define GS_S1CR  (1 << 9) /* ro */
+#define GS_S0CR  (1 << 8) /* ro */
+#define GS_MINT  (1 << 7) /* ro */
+#define GS_POINT (1 << 6) /* ro */
+#define GS_PIINT (1 << 5) /* ro */
+#define GS_RSRVD ((1 << 4) | (1 << 3))
+#define GS_MOINT (1 << 2) /* ro */
+#define GS_MIINT (1 << 1) /* ro */
  #define GS_GSCI  1  /* rwc */


What do you think about aligning the `/*` in the lines above?
It was aligned before.

...


-mixer_store (s, AC97_Reset   , 0x); /* 6940 */
-mixer_store (s, AC97_Headphone_Volume_Mute   , 0x);
-mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x);
-mixer_store (s, AC97_Master_Tone_RL,   0x);
-mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x);
-mixer_store (s, AC97_Phone_Volume_Mute   , 0x);
-mixer_store (s, AC97_Mic_Volume_Mute , 0x);
-mixer_store (s, AC97_Line_In_Volume_Mute , 0x);
-mixer_store (s, AC97_CD_Volume_Mute  , 0x);
-mixer_store (s, AC97_Video_Volume_Mute   , 0x);
-mixer_store (s, AC97_Aux_Volume_Mute , 0x);
-mixer_store (s, AC97_Record_Gain_Mic_Mute, 0x);
-mixer_store (s, AC97_General_Purpose , 0x);
-mixer_store (s, AC97_3D_Control  , 0x);
-mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
+dolog("mixer_reset\n");
+memset(s->mixer_data, 0, sizeof(s->mixer_data));
+memset(active, 0, sizeof(active));
+mixer_store(s, AC97_Reset   , 0x); /* 6940 */
+mixer_store(s, AC97_Headphone_Volume_Mute   , 0x);
+mixer_store(s, AC97_Master_Volume_Mono_Mute , 0x);
+mixer_store(s, AC97_Master_Tone_RL,   0x);


It was already like this before, but I think this might be a good
oportunity to fix this spaces before comma inconsistency here.

Personally I think the best approach would be to make all of them
like `AC97_Master_Tone_RL,` instead of something like
`AC97_Master_Tone_RL ,`


+mixer_store(s, AC97_PC_BEEP_Volume_Mute , 0x);
+mixer_store(s, AC97_Phone_Volume_Mute   , 0x);
+mixer_store(s, AC97_Mic_Volume_Mute , 0x);
+mixer_store(s, AC97_Line_In_Volume_Mute , 0x);
+mixer_store(s, AC97_CD_Volume_Mute  , 0x);
+mixer_store(s, AC97_Video_Volume_Mute   , 0x);
+mixer_store(s, AC97_Aux_Volume_Mute , 0x);
+mixer_store(s, AC97_Record_Gain_Mic_Mute, 0x);
+mixer_store(s, AC97_General_Purpose , 0x);
+mixer_store(s, AC97_3D_Control  , 0x);
+mixer_store(s, AC97_Powerdown_Ctrl_Stat , 0x000f);
  
  /*

   * Sigmatel 9700 (STAC9700)
   */
-mixer_store (s, AC97_Vendor_ID1  , 0x8384);
-mixer_store (s, AC97_Vendor_ID2  , 0x7600); /* 7608 */
-
-mixer_store (s, AC97_Extended_Audio_ID   , 0x0809);
-mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
-mixer_store (s, AC97_PCM_Front_DAC_Rate  , 0xbb80);
-mixer_store (s, AC97_PCM_Surround_DAC_Rate   , 0xbb80);
-mixer_store (s, AC97_PCM_LFE_DAC_Rate, 0xbb80);
-mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
-mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
-
-record_select (s, 0);
-set_volume (s, AC97_Master_Volume_Mute, 0x8000);
-set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808);
-set_volume (s, AC97_Record_Gain_Mute, 0

Re: [PATCH v2] Only advertise aio=io_uring if support is actually available

[Eric Blake]

On Thu, Apr 21, 2022 at 02:27:55PM -0500, Eric Blake wrote:
> On Thu, Apr 21, 2022 at 06:50:48PM +0200, Dirk Müller wrote:
> > Change --help output for aio option to only list the aio backend options 
> > that
> > are actually available. io_uring is an optional, linux only backend
> > option so hide it for cases where it isn't there.
> 
> As pointed out by Dan, this commit message is not quite accurate.  It
> hides only one of the two conditional options, but 'native' is also a
> Linux-only optional backend (CONFIG_LINUX_AIO).

Stepping back a bit - we already said that making --help
machine-parseable is a non-goal, and so the intent of this patch is
for human readers.  But adding an #ifdef ladder to show all 4 possible
combinations gets hairy; adding another option turns it into 8
combinations.  Is there a better way?

What if we just document ALL strings possible in at least one build
(no #ifdef ladder in the help text), but add --aio=help as a way to do
a runtime list of which aio modes are understood by THIS build?  It
would match how we have --device=help for qemu proper, and may even be
able to reuse some of that framework code (for parsing out when help
is requested).

Yes, that would be a bigger patch, but it may also be easier to
maintain down the road.  And even though there is an #ifdef ladder at
runtime, it only has O(n) growth rather than O(n^2) for each possible
combination of which options are enabled, and would appear only once
in the runtime rather than duplicated across each place which
documents similar help text across multiple utilities.

> 
> > 
> > Reviewed-by: Eric Blake 
> > Signed-off-by: Dirk Müller 
> > ---
> >  block/file-posix.c | 4 
> >  qemu-nbd.c | 4 
> >  qemu-options.hx| 6 +-
> >  3 files changed, 13 insertions(+), 1 deletion(-)
> > 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [PATCH v3 0/3] nbd: MULTI_CONN for shared writable exports

[Eric Blake]

Ping. Now that 7.1 is open, I'd like to include this series in my next
NBD pull request.

On Mon, Mar 14, 2022 at 03:38:15PM -0500, Eric Blake wrote:
> v2 was here:
> https://lists.gnu.org/archive/html/qemu-devel/2022-02/msg03314.html
> 
> Since then:
> - expose the knob through 'qemu-nbd -m on|off|auto'
> - reuse QAPI OnOffAuto type instead of rolling my own
> - rewrite the iotest from bash into python (thanks: Nir, Vladimir)
> - split out easy preliminary fixes (patches 1 and 2 are new)
> 
> Given that this is a new feature, it probably needs to be 7.1 material.
> 
> Eric Blake (3):
>   docs: Consistent typography for options of qemu-nbd
>   qemu-nbd: Pass max connections to blockdev layer
>   nbd/server: Allow MULTI_CONN for shared writable exports
> 
>  docs/interop/nbd.txt   |   1 +
>  docs/tools/qemu-nbd.rst|  26 ++--
>  qapi/block-export.json |  19 ++-
>  include/block/nbd.h|   5 +-
>  blockdev-nbd.c |  13 +-
>  nbd/server.c   |  27 +++-
>  qemu-nbd.c |  22 ++-
>  MAINTAINERS|   1 +
>  tests/qemu-iotests/tests/nbd-multiconn | 157 +
>  tests/qemu-iotests/tests/nbd-multiconn.out |   5 +
>  10 files changed, 252 insertions(+), 24 deletions(-)
>  create mode 100755 tests/qemu-iotests/tests/nbd-multiconn
>  create mode 100644 tests/qemu-iotests/tests/nbd-multiconn.out
> 
> -- 
> 2.35.1
> 
> 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [PATCH v2 for-7.1 0/3] qapi: nbd-export: select bitmap by node/name pair

[Eric Blake]

On Tue, Mar 15, 2022 at 12:45:04AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 15.03.2022 00:32, Vladimir Sementsov-Ogievskiy wrote:
> > From: Vladimir Sementsov-Ogievskiy 
> > 
> > Hi all!
> > 
> > Here is small improvement for bitmap exporting interface.
> > 
> > v2: Sorry for the noise, me trying to find a email service, that don't
> > consider sending patch series by git-send-email as as spam :/
> 
> Aha, and @mail.ru works a lot better. So, that's a candidate for v2 of my 
> "[PATCH] MAINTAINERS: change Vladimir's email address".
> 
> This series itself is OK for reviewing, but email in s-o-b mark may change in 
> v3.

Vladimir, do I have your permission to alter your S-o-b marks from
@ya.ru to @mail.ru (since we have established that you have sent mail
from both addresses, but selected @mail.ru in MAINTAINERS)?  That's
the only thing that's preventing me from queuing this series as-is.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [PATCH v2 2/3] qapi: nbd-export: allow select bitmaps by node/name pair

[Eric Blake]

On Fri, Apr 08, 2022 at 11:27:42PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 17.03.2022 00:28, Eric Blake wrote:
> > > +++ b/qapi/block-export.json
> > > @@ -6,6 +6,7 @@
> > >   ##
> > >   { 'include': 'sockets.json' }
> > > +{ 'include': 'block-core.json' }
> > Hmm.  Does this extra inclusion negatively impact qemu-storage-daemon,
> > since that is why we created block-export.json in the first place (to
> > minimize the stuff that qsd pulled in without needing all of
> > block-core.json)?  In other words, would it be better to move
> > BlockDirtyBitmapOrStr to this file?
> 
> Actually, looking at storage-daemon/qapi/qapi-schema.json I see 
> block-cores.json.
> 
> That's block.json which is not mentioned in 
> storage-daemon/qapi/qapi-schema.json.
> 
> So, I think it's OK to keep simple include for now.

We're early enough in the 7.1 cycle that if someone proposes a reason
why this would need to change, then we can adjust it.

So for now, I'm adding

Reviewed-by: Eric Blake 

and queuing this series through my NBD tree.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [RFC PATCH] 9p: case-insensitive host filesystems

[Dominique Martinet]

Christian Schoenebeck wrote on Fri, Apr 22, 2022 at 08:02:46PM +0200:
> So maybe it's better to handle case-insensitivity entirely on client side? 
> I've read that some generic "case fold" code has landed in the Linux kernel 
> recently that might do the trick?

I haven't tried, but settings S_CASEFOLD on every inodes i_flags might do
what you want client-side.
That's easy enough to test and could be a mount option

Even with that it's possible to do a direct open without readdir first
if one knows the path and I that would only be case-insensitive if the
backing server is case insensitive though, so just setting the option
and expecting it to work all the time might be a little bit
optimistic... I believe guess that should be an optimization at best.

Ideally the server should tell the client they are casefolded somehow,
but 9p doesn't have any capability/mount time negotiation besides msize
so that's difficult with the current protocol.

-- 
Dominique | Asmadeus

[PATCH] target/xtensa: add clock input to xtensa CPU

[Max Filippov]

Create clock input for the xtensa CPU device and initialize its
frequency to the default core frequency specified in the config.

Signed-off-by: Max Filippov 
---
 target/xtensa/cpu.c   | 15 +++
 target/xtensa/cpu.h   |  5 +
 target/xtensa/op_helper.c |  7 ---
 3 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 224f72323693..fd553fdfb5e6 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -34,6 +34,7 @@
 #include "fpu/softfloat.h"
 #include "qemu/module.h"
 #include "migration/vmstate.h"
+#include "hw/qdev-clock.h"
 
 
 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
@@ -172,9 +173,23 @@ static void xtensa_cpu_initfn(Object *obj)
 memory_region_init_io(env->system_er, obj, NULL, env, "er",
   UINT64_C(0x1));
 address_space_init(env->address_space_er, env->system_er, "ER");
+
+cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
+clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
 #endif
 }
 
+XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock 
*cpu_refclk)
+{
+DeviceState *cpu;
+
+cpu = DEVICE(object_new(cpu_type));
+qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
+qdev_realize(cpu, NULL, &error_abort);
+
+return XTENSA_CPU(cpu);
+}
+
 #ifndef CONFIG_USER_ONLY
 static const VMStateDescription vmstate_xtensa_cpu = {
 .name = "cpu",
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 4515f682aa26..6f773e681384 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -30,6 +30,7 @@
 
 #include "cpu-qom.h"
 #include "exec/cpu-defs.h"
+#include "hw/clock.h"
 #include "xtensa-isa.h"
 
 /* Xtensa processors have a weak memory model */
@@ -558,6 +559,7 @@ struct ArchCPU {
 CPUState parent_obj;
 /*< public >*/
 
+Clock *clock;
 CPUNegativeOffsetState neg;
 CPUXtensaState env;
 };
@@ -792,4 +794,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState 
*env, target_ulong *pc,
 }
 }
 
+XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
+Clock *cpu_refclk);
+
 #endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index d85d3516d6a5..1af7becc54b1 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -38,12 +38,12 @@
 
 void HELPER(update_ccount)(CPUXtensaState *env)
 {
+XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 
 env->ccount_time = now;
 env->sregs[CCOUNT] = env->ccount_base +
-(uint32_t)((now - env->time_base) *
-   env->config->clock_freq_khz / 100);
+(uint32_t)clock_ns_to_ticks(cpu->clock, now - env->time_base);
 }
 
 void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
@@ -59,6 +59,7 @@ void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
 
 void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
 {
+XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
 uint64_t dcc;
 
 qatomic_and(&env->sregs[INTSET],
@@ -66,7 +67,7 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
 HELPER(update_ccount)(env);
 dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
 timer_mod(env->ccompare[i].timer,
-  env->ccount_time + (dcc * 100) / 
env->config->clock_freq_khz);
+  env->ccount_time + clock_ticks_to_ns(cpu->clock, dcc));
 env->yield_needed = 1;
 }
 
-- 
2.30.2

[PATCH 20/20] target/ppc: Add unused M_MSR_* macros

[Víctor Colombo]

Add M_MSR_* macros for msr bits that had an unused msr_* before.

Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 24 
 1 file changed, 24 insertions(+)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3cbecc96d8..dda289a121 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,9 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_SF (1ull << MSR_SF)
+#define M_MSR_TAG (1ull << MSR_TAG)
+#define M_MSR_ISF (1ull << MSR_ISF)
 #if defined(TARGET_PPC64)
 #define M_MSR_HV (1ull << MSR_HV)
 #else
@@ -360,10 +363,20 @@ typedef enum {
 #endif
 #define M_MSR_TS0 (1ull << MSR_TS0)
 #define M_MSR_TS1 (1ull << MSR_TS1)
+#define M_MSR_TM (1ull << MSR_TM)
 #define M_MSR_TS (M_MSR_TS0 | M_MSR_TS1)
 #define M_MSR_CM (1ull << MSR_CM)
+#define M_MSR_ICM (1ull << MSR_ICM)
 #define M_MSR_GS (1ull << MSR_GS)
+#define M_MSR_UCLE (1ull << MSR_UCLE)
+#define M_MSR_VR (1ull << MSR_VR)
+#define M_MSR_SPE (1ull << MSR_SPE)
+#define M_MSR_VSX (1ull << MSR_VSX)
+#define M_MSR_S (1ull << MSR_S)
+#define M_MSR_KEY (1ull << MSR_KEY)
 #define M_MSR_POW (1ull << MSR_POW)
+#define M_MSR_WE (1ull << MSR_WE)
+#define M_MSR_TGPR (1ull << MSR_TGPR)
 #define M_MSR_CE (1ull << MSR_CE)
 #define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_EE (1ull << MSR_EE)
@@ -373,10 +386,21 @@ typedef enum {
 #define M_MSR_FE0 (1ull << MSR_FE0)
 #define M_MSR_FE1 (1ull << MSR_FE1)
 #define M_MSR_FE (M_MSR_FE0 | M_MSR_FE1)
+#define M_MSR_SE (1ull << MSR_SE)
+#define M_MSR_DWE (1ull << MSR_DWE)
+#define M_MSR_UBLE (1ull << MSR_UBLE)
+#define M_MSR_BE (1ull << MSR_BE)
+#define M_MSR_DE (1ull << MSR_DE)
+#define M_MSR_AL (1ull << MSR_AL)
 #define M_MSR_EP (1ull << MSR_EP)
 #define M_MSR_IR (1ull << MSR_IR)
 #define M_MSR_DR (1ull << MSR_DR)
+#define M_MSR_IS (1ull << MSR_IS)
 #define M_MSR_DS (1ull << MSR_DS)
+#define M_MSR_PE (1ull << MSR_PE)
+#define M_MSR_PX (1ull << MSR_PX)
+#define M_MSR_PMM (1ull << MSR_PMM)
+#define M_MSR_RI (1ull << MSR_RI)
 #define M_MSR_LE (1ull << MSR_LE)
 
 /* PMU bits */
-- 
2.25.1

[PATCH 19/20] target/ppc: Substitute msr_hv macro with new M_MSR_HV macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 11 +--
 target/ppc/cpu_init.c|  4 ++--
 target/ppc/excp_helper.c |  9 +
 target/ppc/mem_helper.c  |  5 +++--
 target/ppc/misc_helper.c |  2 +-
 target/ppc/mmu-radix64.c |  6 +++---
 6 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ee00b27818..3cbecc96d8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,11 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#if defined(TARGET_PPC64)
+#define M_MSR_HV (1ull << MSR_HV)
+#else
+#define M_MSR_HV 0
+#endif
 #define M_MSR_TS0 (1ull << MSR_TS0)
 #define M_MSR_TS1 (1ull << MSR_TS1)
 #define M_MSR_TS (M_MSR_TS0 | M_MSR_TS1)
@@ -484,12 +489,6 @@ typedef enum {
 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
 #define HFSCR_IC_MSGP  0xA
 
-#if defined(TARGET_PPC64)
-#define msr_hv   ((env->msr >> MSR_HV)   & 1)
-#else
-#define msr_hv   (0)
-#endif
-
 #define DBCR0_ICMP (1 << 27)
 #define DBCR0_BRT (1 << 26)
 #define DBSR_ICMP (1 << 27)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 4d949ab1f1..d2a7911a86 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6305,7 +6305,7 @@ static bool cpu_has_work_POWER9(CPUState *cs)
 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
 (env->spr[SPR_LPCR] & LPCR_EEE)) {
 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
-if (!heic || !msr_hv || (env->msr & M_MSR_PR)) {
+if (!heic || !(env->msr & M_MSR_HV) || (env->msr & M_MSR_PR)) {
 return true;
 }
 }
@@ -6520,7 +6520,7 @@ static bool cpu_has_work_POWER10(CPUState *cs)
 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
 (env->spr[SPR_LPCR] & LPCR_EEE)) {
 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
-if (!heic || !msr_hv || (env->msr & M_MSR_PR)) {
+if (!heic || !(env->msr & M_MSR_HV) || (env->msr & M_MSR_PR)) {
 return true;
 }
 }
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 88e5eb91f1..06bee7689b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1715,7 +1715,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
 /* LPCR will be clear when not supported so this will work */
 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
-if ((async_deliver || msr_hv == 0) && hdice) {
+if ((async_deliver || !(env->msr & M_MSR_HV)) && hdice) {
 /* HDEC clears on delivery */
 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 powerpc_excp(cpu, POWERPC_EXCP_HDECR);
@@ -1727,7 +1727,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
 /* LPCR will be clear when not supported so this will work */
 bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
-if ((async_deliver || msr_hv == 0) && hvice) {
+if ((async_deliver || !(env->msr & M_MSR_HV)) && hvice) {
 powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
 return;
 }
@@ -1738,8 +1738,9 @@ static void ppc_hw_interrupt(CPUPPCState *env)
 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
 /* HEIC blocks delivery to the hypervisor */
-if ((async_deliver && !(heic && msr_hv && !(env->msr & M_MSR_PR))) ||
-(env->has_hv_mode && msr_hv == 0 && !lpes0)) {
+if ((async_deliver && !(heic && (env->msr & M_MSR_HV) &&
+!(env->msr & M_MSR_PR))) ||
+(env->has_hv_mode && !(env->msr & M_MSR_HV) && !lpes0)) {
 if (books_vhyp_promotes_external_to_hvirt(cpu)) {
 powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
 } else {
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 8ff99a6568..d3964a7eb0 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -612,11 +612,12 @@ void helper_tbegin(CPUPPCState *env)
 env->spr[SPR_TEXASR] =
 (1ULL << TEXASR_FAILURE_PERSISTENT) |
 (1ULL << TEXASR_NESTING_OVERFLOW) |
-(msr_hv << TEXASR_PRIVILEGE_HV) |
+(!!(env->msr & M_MSR_HV) << TEXASR_PRIVILEGE_HV) |
 (!!(env->msr & M_MSR_PR) << TEXASR_PRIVILEGE_PR) |
 (1ULL << TEXASR_FAILURE_SUMMARY) |
 (1ULL << TEXASR_TFIAR_EXACT);
-env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | !!(env->msr & M_MSR_PR);
+env->spr[SPR_TFIAR] = env->nip | (!!(env->msr & M_MSR_HV) << 1) |
+  !!(env->msr & M_MSR_PR);
 env->spr[SPR_TFHAR] = env->nip + 4;
 env->crf[0]

[PATCH 18/20] target/ppc: Substitute msr_ts macro with new M_MSR_TS macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 4 +++-
 target/ppc/kvm.c | 4 ++--
 target/ppc/machine.c | 2 +-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b957fc95e0..ee00b27818 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,9 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_TS0 (1ull << MSR_TS0)
+#define M_MSR_TS1 (1ull << MSR_TS1)
+#define M_MSR_TS (M_MSR_TS0 | M_MSR_TS1)
 #define M_MSR_CM (1ull << MSR_CM)
 #define M_MSR_GS (1ull << MSR_GS)
 #define M_MSR_POW (1ull << MSR_POW)
@@ -486,7 +489,6 @@ typedef enum {
 #else
 #define msr_hv   (0)
 #endif
-#define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
 #define DBCR0_BRT (1 << 26)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 1ca18f21b2..3cccac41fd 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -973,7 +973,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
 }
 
 #ifdef TARGET_PPC64
-if (msr_ts) {
+if (env->msr & M_MSR_TS) {
 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
 }
@@ -1281,7 +1281,7 @@ int kvm_arch_get_registers(CPUState *cs)
 }
 
 #ifdef TARGET_PPC64
-if (msr_ts) {
+if (env->msr & M_MSR_TS) {
 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
 }
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index e673944597..51832c4bde 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -417,7 +417,7 @@ static bool tm_needed(void *opaque)
 {
 PowerPCCPU *cpu = opaque;
 CPUPPCState *env = &cpu->env;
-return msr_ts;
+return env->msr & M_MSR_TS;
 }
 
 static const VMStateDescription vmstate_tm = {
-- 
2.25.1

[PATCH 15/20] target/ppc: Substitute msr_dr macro with new M_MSR_DR macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 2 +-
 target/ppc/helper_regs.c | 2 +-
 target/ppc/mmu_common.c  | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cc0b5d72de..3a5218a2cd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,7 @@ typedef enum {
 #define M_MSR_FP (1ull << MSR_FP)
 #define M_MSR_ME (1ull << MSR_ME)
 #define M_MSR_IR (1ull << MSR_IR)
+#define M_MSR_DR (1ull << MSR_DR)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
 
@@ -484,7 +485,6 @@ typedef enum {
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
-#define msr_dr   ((env->msr >> MSR_DR)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index fa8f213cd5..1c67fbf7c1 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -228,7 +228,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, 
int alter_hv)
 value |= env->msr & MSR_HVB;
 }
 if (!(value & env->msr & M_MSR_IR) ||
-((value >> MSR_DR) & 1) != msr_dr) {
+!(value & env->msr & M_MSR_DR)) {
 cpu_interrupt_exittb(cs);
 }
 if ((env->mmu_model == POWERPC_MMU_BOOKE ||
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 918c15f78d..dbb657d9bc 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -388,7 +388,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t 
*ctx,
   " nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
   " ir=%d dr=%d pr=%d %d t=%d\n",
   eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
-  !!(env->msr & M_MSR_IR), (int)msr_dr, pr ? 1 : 0,
+  !!(env->msr & M_MSR_IR), !!(env->msr & M_MSR_DR), pr ? 1 : 0,
   access_type == MMU_DATA_STORE, type);
 pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
 hash = vsid ^ pgidx;
@@ -627,7 +627,7 @@ found_tlb:
 
 /* Check the address space */
 if ((access_type == MMU_INST_FETCH ?
-!!(env->msr & M_MSR_IR) : msr_dr) != (tlb->attr & 1)) {
+!!(env->msr & M_MSR_IR) : !!(env->msr & M_MSR_DR)) != (tlb->attr & 1)) 
{
 qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
 return -1;
 }
@@ -1171,7 +1171,7 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t 
*ctx,
 {
 int ret = -1;
 bool real_mode = (type == ACCESS_CODE && !(env->msr & M_MSR_IR))
-|| (type != ACCESS_CODE && msr_dr == 0);
+|| (type != ACCESS_CODE && !(env->msr & M_MSR_DR));
 
 switch (env->mmu_model) {
 case POWERPC_MMU_SOFT_6xx:
-- 
2.25.1

[PATCH 08/20] target/ppc: Substitute msr_ce macro with new M_MSR_CE macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 2 +-
 target/ppc/excp_helper.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bfde66ed66..3f10c1f5b2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,7 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_CE (1ull << MSR_CE)
 #define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_EE (1ull << MSR_EE)
 #define M_MSR_PR (1ull << MSR_PR)
@@ -477,7 +478,6 @@ typedef enum {
 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
-#define msr_ce   ((env->msr >> MSR_CE)   & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 39d1c2a543..6dcaa79516 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1748,7 +1748,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
 return;
 }
 }
-if (msr_ce != 0) {
+if (env->msr & M_MSR_CE) {
 /* External critical interrupt */
 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
 powerpc_excp(cpu, POWERPC_EXCP_CRITICAL);
-- 
2.25.1

[PATCH 17/20] target/ppc: Substitute msr_fe macro with new M_MSR_FE macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h |  5 +++--
 target/ppc/excp_helper.c | 12 ++--
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1767a3a430..b957fc95e0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -362,6 +362,9 @@ typedef enum {
 #define M_MSR_PR (1ull << MSR_PR)
 #define M_MSR_FP (1ull << MSR_FP)
 #define M_MSR_ME (1ull << MSR_ME)
+#define M_MSR_FE0 (1ull << MSR_FE0)
+#define M_MSR_FE1 (1ull << MSR_FE1)
+#define M_MSR_FE (M_MSR_FE0 | M_MSR_FE1)
 #define M_MSR_EP (1ull << MSR_EP)
 #define M_MSR_IR (1ull << MSR_IR)
 #define M_MSR_DR (1ull << MSR_DR)
@@ -483,8 +486,6 @@ typedef enum {
 #else
 #define msr_hv   (0)
 #endif
-#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
-#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 3e52061cd6..88e5eb91f1 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -478,7 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
+if (!(env->msr & M_MSR_FE) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -615,7 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
+if (!(env->msr & M_MSR_FE) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -788,7 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
+if (!(env->msr & M_MSR_FE) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -973,7 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
+if (!(env->msr & M_MSR_FE) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -1171,7 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
+if (!(env->msr & M_MSR_FE) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -1434,7 +1434,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
+if (!(env->msr & M_MSR_FE) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
-- 
2.25.1

[PATCH 14/20] target/ppc: Substitute msr_ir macro with new M_MSR_IR macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h |  2 +-
 target/ppc/helper_regs.c |  2 +-
 target/ppc/mmu_common.c  | 11 ++-
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e26530fa09..cc0b5d72de 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -362,6 +362,7 @@ typedef enum {
 #define M_MSR_PR (1ull << MSR_PR)
 #define M_MSR_FP (1ull << MSR_FP)
 #define M_MSR_ME (1ull << MSR_ME)
+#define M_MSR_IR (1ull << MSR_IR)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
 
@@ -483,7 +484,6 @@ typedef enum {
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
-#define msr_ir   ((env->msr >> MSR_IR)   & 1)
 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 2742938abf..fa8f213cd5 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -227,7 +227,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, 
int alter_hv)
 value &= ~MSR_HVB;
 value |= env->msr & MSR_HVB;
 }
-if (((value >> MSR_IR) & 1) != msr_ir ||
+if (!(value & env->msr & M_MSR_IR) ||
 ((value >> MSR_DR) & 1) != msr_dr) {
 cpu_interrupt_exittb(cs);
 }
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index a82649f2ff..918c15f78d 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -388,7 +388,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t 
*ctx,
   " nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
   " ir=%d dr=%d pr=%d %d t=%d\n",
   eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
-  (int)msr_ir, (int)msr_dr, pr ? 1 : 0,
+  !!(env->msr & M_MSR_IR), (int)msr_dr, pr ? 1 : 0,
   access_type == MMU_DATA_STORE, type);
 pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
 hash = vsid ^ pgidx;
@@ -626,7 +626,8 @@ found_tlb:
 }
 
 /* Check the address space */
-if ((access_type == MMU_INST_FETCH ? msr_ir : msr_dr) != (tlb->attr & 1)) {
+if ((access_type == MMU_INST_FETCH ?
+!!(env->msr & M_MSR_IR) : msr_dr) != (tlb->attr & 1)) {
 qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
 return -1;
 }
@@ -839,7 +840,7 @@ found_tlb:
 if (access_type == MMU_INST_FETCH) {
 /* There is no way to fetch code using epid load */
 assert(!use_epid);
-as = msr_ir;
+as = env->msr & M_MSR_IR;
 }
 
 if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
@@ -1169,7 +1170,7 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t 
*ctx,
  int mmu_idx)
 {
 int ret = -1;
-bool real_mode = (type == ACCESS_CODE && msr_ir == 0)
+bool real_mode = (type == ACCESS_CODE && !(env->msr & M_MSR_IR))
 || (type != ACCESS_CODE && msr_dr == 0);
 
 switch (env->mmu_model) {
@@ -1231,7 +1232,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState 
*env, target_ulong address,
 bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
 
 if (access_type == MMU_INST_FETCH) {
-as = msr_ir;
+as = env->msr & M_MSR_IR;
 }
 env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
 env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
-- 
2.25.1

[PATCH 07/20] target/ppc: Substitute msr_ee macro with new M_MSR_EE macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h |  2 +-
 target/ppc/cpu_init.c| 15 ++-
 target/ppc/excp_helper.c |  2 +-
 target/ppc/kvm.c |  3 ++-
 4 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 95c28c3c1b..bfde66ed66 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
 #define M_MSR_ILE (1ull << MSR_ILE)
+#define M_MSR_EE (1ull << MSR_EE)
 #define M_MSR_PR (1ull << MSR_PR)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
@@ -477,7 +478,6 @@ typedef enum {
 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
-#define msr_ee   ((env->msr >> MSR_EE)   & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9dddc0e8f6..4d949ab1f1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5949,7 +5949,8 @@ static bool cpu_has_work_POWER7(CPUState *cs)
 }
 return false;
 } else {
-return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+return (env->msr & M_MSR_EE) &&
+   (cs->interrupt_request & CPU_INTERRUPT_HARD);
 }
 }
 
@@ -6120,7 +6121,8 @@ static bool cpu_has_work_POWER8(CPUState *cs)
 }
 return false;
 } else {
-return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+return (env->msr & M_MSR_EE) &&
+   (cs->interrupt_request & CPU_INTERRUPT_HARD);
 }
 }
 
@@ -6337,7 +6339,8 @@ static bool cpu_has_work_POWER9(CPUState *cs)
 }
 return false;
 } else {
-return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+return (env->msr & M_MSR_EE) &&
+   (cs->interrupt_request & CPU_INTERRUPT_HARD);
 }
 }
 
@@ -6551,7 +6554,8 @@ static bool cpu_has_work_POWER10(CPUState *cs)
 }
 return false;
 } else {
-return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+return (env->msr & M_MSR_EE) &&
+   (cs->interrupt_request & CPU_INTERRUPT_HARD);
 }
 }
 
@@ -7119,7 +7123,8 @@ static bool ppc_cpu_has_work(CPUState *cs)
 PowerPCCPU *cpu = POWERPC_CPU(cs);
 CPUPPCState *env = &cpu->env;
 
-return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+return (env->msr & M_MSR_EE) &&
+   (cs->interrupt_request & CPU_INTERRUPT_HARD);
 }
 
 static void ppc_cpu_reset(DeviceState *dev)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 10cd381be2..39d1c2a543 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1709,7 +1709,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
  * clear when coming out of some power management states (in order
  * for them to become a 0x100).
  */
-async_deliver = (msr_ee != 0) || env->resume_as_sreset;
+async_deliver = (env->msr & M_MSR_EE) || env->resume_as_sreset;
 
 /* Hypervisor decrementer exception */
 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index a3c31b4e48..1ca18f21b2 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1351,7 +1351,8 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu)
 CPUState *cs = CPU(cpu);
 CPUPPCState *env = &cpu->env;
 
-if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
+if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+(env->msr & M_MSR_EE)) {
 cs->halted = 1;
 cs->exception_index = EXCP_HLT;
 }
-- 
2.25.1

[PATCH 04/20] target/ppc: Substitute msr_le macro with new M_MSR_LE macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h|  2 +-
 target/ppc/cpu_init.c   |  2 +-
 target/ppc/gdbstub.c|  2 +-
 target/ppc/mem_helper.c | 16 
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2ad023e981..d25a778b7c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
 #define M_MSR_PR (1ull << MSR_PR)
+#define M_MSR_LE (1ull << MSR_LE)
 
 /* PMU bits */
 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters  */
@@ -484,7 +485,6 @@ typedef enum {
 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
-#define msr_le   ((env->msr >> MSR_LE)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6e2b23a859..9dddc0e8f6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7210,7 +7210,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
 
 cpu_synchronize_state(cs);
 
-return !msr_le;
+return !(env->msr & M_MSR_LE);
 }
 
 #ifdef CONFIG_TCG
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 1252429a2a..df1dcd90f0 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -95,7 +95,7 @@ static int ppc_gdb_register_len(int n)
 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
 {
 #ifndef CONFIG_USER_ONLY
-if (!msr_le) {
+if (!(env->msr & M_MSR_LE)) {
 /* do nothing */
 } else if (len == 4) {
 bswap32s((uint32_t *)mem_buf);
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index bd219e9c9c..8ff99a6568 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -33,9 +33,9 @@
 static inline bool needs_byteswap(const CPUPPCState *env)
 {
 #if TARGET_BIG_ENDIAN
-  return msr_le;
+  return env->msr & M_MSR_LE;
 #else
-  return !msr_le;
+  return !(env->msr & M_MSR_LE);
 #endif
 }
 
@@ -470,8 +470,8 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, 
target_ulong addr,
 #endif
 
 /*
- * We use msr_le to determine index ordering in a vector.  However,
- * byteswapping is not simply controlled by msr_le.  We also need to
+ * We use MSR_LE to determine index ordering in a vector.  However,
+ * byteswapping is not simply controlled by MSR_LE.  We also need to
  * take into account endianness of the target.  This is done for the
  * little-endian PPC64 user-mode target.
  */
@@ -484,7 +484,7 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, 
target_ulong addr,
 int adjust = HI_IDX * (n_elems - 1);\
 int sh = sizeof(r->element[0]) >> 1;\
 int index = (addr & 0xf) >> sh; \
-if (msr_le) {   \
+if (env->msr & M_MSR_LE) {  \
 index = n_elems - index - 1;\
 }   \
 \
@@ -511,7 +511,7 @@ LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
 int adjust = HI_IDX * (n_elems - 1);\
 int sh = sizeof(r->element[0]) >> 1;\
 int index = (addr & 0xf) >> sh; \
-if (msr_le) {   \
+if (env->msr & M_MSR_LE) {  \
 index = n_elems - index - 1;\
 }   \
 \
@@ -545,7 +545,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, 
\
 t.s128 = int128_zero(); \
 if (nb) {   \
 nb = (nb >= 16) ? 16 : nb;  \
-if (msr_le && !lj) {\
+if ((env->msr & M_MSR_LE) && !lj) { \
 for (i = 16; i > 16 - nb; i--) {\
 t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC());   \
 addr = addr_add(env, addr, 1);  \
@@ -576,7 +576,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, 
  \
 } \
   \
 nb = (nb >= 16) ? 16 : nb;\
-if (msr_le && !lj) { 

[PATCH 16/20] target/ppc: Substitute msr_ep macro with new M_MSR_EP macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 2 +-
 target/ppc/helper_regs.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3a5218a2cd..1767a3a430 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -362,6 +362,7 @@ typedef enum {
 #define M_MSR_PR (1ull << MSR_PR)
 #define M_MSR_FP (1ull << MSR_FP)
 #define M_MSR_ME (1ull << MSR_ME)
+#define M_MSR_EP (1ull << MSR_EP)
 #define M_MSR_IR (1ull << MSR_IR)
 #define M_MSR_DR (1ull << MSR_DR)
 #define M_MSR_DS (1ull << MSR_DS)
@@ -484,7 +485,6 @@ typedef enum {
 #endif
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
-#define msr_ep   ((env->msr >> MSR_EP)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 1c67fbf7c1..f9d2e123cf 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -241,8 +241,8 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, 
int alter_hv)
 /* Swap temporary saved registers with GPRs */
 hreg_swap_gpr_tgpr(env);
 }
-if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
-env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF0;
+if (unlikely(!(value & env->msr & M_MSR_EP))) {
+env->excp_prefix = !!(value & M_MSR_EP) * 0xFFF0;
 }
 /*
  * If PR=1 then EE, IR and DR must be 1
-- 
2.25.1

[PATCH 13/20] target/ppc: Substitute msr_cm macro with new M_MSR_CM macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h| 2 +-
 target/ppc/mmu_common.c | 2 +-
 target/ppc/mmu_helper.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 634c05a9d2..e26530fa09 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,7 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_CM (1ull << MSR_CM)
 #define M_MSR_GS (1ull << MSR_GS)
 #define M_MSR_POW (1ull << MSR_POW)
 #define M_MSR_CE (1ull << MSR_CE)
@@ -479,7 +480,6 @@ typedef enum {
 #else
 #define msr_hv   (0)
 #endif
-#define msr_cm   ((env->msr >> MSR_CM)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index b7865d24b2..a82649f2ff 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -692,7 +692,7 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
 hwaddr mask;
 uint32_t tlb_pid;
 
-if (!msr_cm) {
+if (!(env->msr & M_MSR_CM)) {
 /* In 32bit mode we can only address 32bit EAs */
 address = (uint32_t)address;
 }
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 9044b7b036..6c49920d0a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1003,7 +1003,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
 /* Add a mask for page attributes */
 mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
 
-if (!msr_cm) {
+if (!(env->msr & M_MSR_CM)) {
 /*
  * Executing a tlbwe instruction in 32-bit mode will set bits
  * 0:31 of the TLB EPN field to zero.
-- 
2.25.1

[PATCH 06/20] target/ppc: Substitute msr_ile macro with new M_MSR_ILE macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e81f1f2d68..95c28c3c1b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,7 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_PR (1ull << MSR_PR)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
@@ -476,7 +477,6 @@ typedef enum {
 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
-#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_me   ((env->msr >> MSR_ME)   & 1)
@@ -2677,7 +2677,7 @@ static inline bool 
ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
 } else if (pcc->lpcr_mask & LPCR_ILE) {
 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
 } else {
-ile = !!(msr_ile);
+ile = !!(env->msr & M_MSR_ILE);
 }
 
 return ile;
-- 
2.25.1

[PATCH 01/20] target/ppc: Remove fpscr_* macros from cpu.h

[Víctor Colombo]

fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.c|  2 +-
 target/ppc/cpu.h| 29 -
 target/ppc/fpu_helper.c | 28 ++--
 3 files changed, 15 insertions(+), 44 deletions(-)

diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index d7b42bae52..401b6f9e63 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -88,7 +88,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)
 int rnd_type;
 
 /* Set rounding mode */
-switch (fpscr_rn) {
+switch (env->fpscr & FP_RN) {
 case 0:
 /* Best approximation (round to nearest) */
 rnd_type = float_round_nearest_even;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c2b6c987c0..ad31e51d69 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -713,41 +713,12 @@ enum {
 #define FPSCR_NI 2  /* Floating-point non-IEEE mode  */
 #define FPSCR_RN11
 #define FPSCR_RN00  /* Floating-point rounding control   */
-#define fpscr_drn(((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
-#define fpscr_fex(((env->fpscr) >> FPSCR_FEX)& 0x1)
-#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
-#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
-#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
-#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
-#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
-#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
-#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
-#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
-#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
-#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
-#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
-#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
-#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
-#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
-#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
-#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
-#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
-#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
-#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
-#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
-#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
-#define fpscr_rn (((env->fpscr) >> FPSCR_RN0)& 0x3)
 /* Invalid operation exception summary */
 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
   (1 << FPSCR_VXCVI))
-/* exception summary */
-#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
-/* enabled exception summary */
-#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
-   0x1F)
 
 #define FP_DRN2 (1ull << FPSCR_DRN2)
 #define FP_DRN1 (1ull << FPSCR_DRN1)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 99281cc37a..f6c8318a71 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -202,7 +202,7 @@ static void finish_invalid_op_excp(CPUPPCState *env, int 
op, uintptr_t retaddr)
 env->fpscr |= FP_VX;
 /* Update the floating-point exception summary */
 env->fpscr |= FP_FX;
-if (fpscr_ve != 0) {
+if (env->fpscr & FP_VE) {
 /* Update the floating-point enabled exception summary */
 env->fpscr |= FP_FEX;
 if (fp_exceptions_enabled(env)) {
@@ -216,7 +216,7 @@ static void finish_invalid_op_arith(CPUPPCState *env, int 
op,
 bool set_fpcc, uintptr_t retaddr)
 {
 env->fpscr &= ~(FP_FR | FP_FI);
-if (fpscr_ve == 0) {
+if (!(env->fpscr & FP_VE)) {
 if (set_fpcc) {
 env->fpscr &= ~FP_FPCC;
 env->fpscr |= (FP_C | FP_FU);
@@ -286,7 +286,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool 
set_fpcc,
 /* Update the floating-point exception summary */
 env->fpscr |= FP_FX;
 /* We must update the target FPR before raising the exception */
-if (fpscr_ve != 0) {
+if (env->fpscr & FP_VE) {
 CPUState *cs = env_cpu(env);
 
 cs->exception_index = POWERPC_EXCP_PROGRAM;
@@ -303,7 +303,7 @@ static void float_invalid_op_vxcvi(CPUPPCState *env, bool 
set_fpcc,
 {
 env->fpscr |= FP_VXCVI;
 env->fpscr &= ~(FP_FR | FP_FI);
-if (fpscr_ve == 0) {
+if (!(env->fpscr & FP_VE)) {
 if (set_fpcc) {
 env->fpscr &= ~FP_FPCC;
 env->fpscr |= (FP_C | FP_FU);
@@ -318,7 +318,7 

[PATCH 12/20] target/ppc: Substitute msr_fp macro with new M_MSR_FP macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h |  2 +-
 target/ppc/excp_helper.c | 12 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 15f5d059a3..634c05a9d2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -359,6 +359,7 @@ typedef enum {
 #define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_EE (1ull << MSR_EE)
 #define M_MSR_PR (1ull << MSR_PR)
+#define M_MSR_FP (1ull << MSR_FP)
 #define M_MSR_ME (1ull << MSR_ME)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
@@ -479,7 +480,6 @@ typedef enum {
 #define msr_hv   (0)
 #endif
 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
-#define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0548b493a7..3e52061cd6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -478,7 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -615,7 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -788,7 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -973,7 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -1171,7 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
@@ -1434,7 +1434,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_PROGRAM:   /* Program exception*/
 switch (env->error_code & ~0xF) {
 case POWERPC_EXCP_FP:
-if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+if ((msr_fe0 == 0 && msr_fe1 == 0) || !(env->msr & M_MSR_FP)) {
 trace_ppc_excp_fp_ignore();
 powerpc_reset_excp_state(cpu);
 return;
-- 
2.25.1

[PATCH 02/20] target/ppc: Remove unused msr_* macros

[Víctor Colombo]

Some msr_* macros are not used anywhere. Remove them as part of
the work to remove all hidden usage of *env.

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 21 -
 1 file changed, 21 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ad31e51d69..106b555b86 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -463,23 +463,14 @@ typedef enum {
 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
 #define HFSCR_IC_MSGP  0xA
 
-#define msr_sf   ((env->msr >> MSR_SF)   & 1)
-#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 #if defined(TARGET_PPC64)
 #define msr_hv   ((env->msr >> MSR_HV)   & 1)
 #else
 #define msr_hv   (0)
 #endif
 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
-#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
-#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
-#define msr_vr   ((env->msr >> MSR_VR)   & 1)
-#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
-#define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
-#define msr_key  ((env->msr >> MSR_KEY)  & 1)
 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
-#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
@@ -487,25 +478,13 @@ typedef enum {
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
-#define msr_se   ((env->msr >> MSR_SE)   & 1)
-#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
-#define msr_uble ((env->msr >> MSR_UBLE) & 1)
-#define msr_be   ((env->msr >> MSR_BE)   & 1)
-#define msr_de   ((env->msr >> MSR_DE)   & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
-#define msr_al   ((env->msr >> MSR_AL)   & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
-#define msr_is   ((env->msr >> MSR_IS)   & 1)
 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
-#define msr_pe   ((env->msr >> MSR_PE)   & 1)
-#define msr_px   ((env->msr >> MSR_PX)   & 1)
-#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
-#define msr_ri   ((env->msr >> MSR_RI)   & 1)
 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
-#define msr_tm   ((env->msr >> MSR_TM)   & 1)
 
 #define DBCR0_ICMP (1 << 27)
 #define DBCR0_BRT (1 << 26)
-- 
2.25.1

[PATCH 11/20] target/ppc: Substitute msr_gs macro with new M_MSR_GS macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h | 2 +-
 target/ppc/helper_regs.c | 2 +-
 target/ppc/mmu_helper.c  | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index aa20a604ab..15f5d059a3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,7 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_GS (1ull << MSR_GS)
 #define M_MSR_POW (1ull << MSR_POW)
 #define M_MSR_CE (1ull << MSR_CE)
 #define M_MSR_ILE (1ull << MSR_ILE)
@@ -478,7 +479,6 @@ typedef enum {
 #define msr_hv   (0)
 #endif
 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
-#define msr_gs   ((env->msr >> MSR_GS)   & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index a9bedfce50..2742938abf 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -233,7 +233,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, 
int alter_hv)
 }
 if ((env->mmu_model == POWERPC_MMU_BOOKE ||
  env->mmu_model == POWERPC_MMU_BOOKE206) &&
-((value >> MSR_GS) & 1) != msr_gs) {
+!(value & env->msr & M_MSR_GS)) {
 cpu_interrupt_exittb(cs);
 }
 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 142a717255..9044b7b036 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -935,7 +935,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
 }
 
 if (((env->spr[SPR_BOOKE_MAS0] & MAS0_ATSEL) == MAS0_ATSEL_LRAT) &&
-!msr_gs) {
+!(env->msr & M_MSR_GS)) {
 /* XXX we don't support direct LRAT setting yet */
 fprintf(stderr, "cpu: don't support LRAT setting yet\n");
 return;
@@ -962,7 +962,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
POWERPC_EXCP_INVAL_INVAL, GETPC());
 }
 
-if (msr_gs) {
+if (env->msr & M_MSR_GS) {
 cpu_abort(env_cpu(env), "missing HV implementation\n");
 }
 
-- 
2.25.1

[PATCH 00/20] target/ppc: Remove hidden usages of *env

[Víctor Colombo]

By running the grep command `git grep -nr 'define \(fpscr\|msr\)_[a-z0-9]\+\>'`
we can find multiple macros that use `env->fpscr` and `env->msr` but doesn't 
take *env as a parameter.

Richard Henderson said [1] that these macros hiding the usage of *env "are 
evil".
This patch series remove them and substitute with an explicit usage of *env by
adding macros in the same style of FP_* ones (e.g. FP_FI defined in cpu.h).

Patch 20 (target/ppc: Add unused M_MSR_* macros) implements unused macros, the
same that were removed in patch 02 (target/ppc: Remove unused msr_* macros). I
did that to keep the changes consistent with what was already present before.

[1]: https://lists.gnu.org/archive/html/qemu-ppc/2021-11/msg00280.html

Víctor Colombo (20):
  target/ppc: Remove fpscr_* macros from cpu.h
  target/ppc: Remove unused msr_* macros
  target/ppc: Substitute msr_pr macro with new M_MSR_PR macro
  target/ppc: Substitute msr_le macro with new M_MSR_LE macro
  target/ppc: Substitute msr_ds macro with new M_MSR_DS macro
  target/ppc: Substitute msr_ile macro with new M_MSR_ILE macro
  target/ppc: Substitute msr_ee macro with new M_MSR_EE macro
  target/ppc: Substitute msr_ce macro with new M_MSR_CE macro
  target/ppc: Substitute msr_pow macro with new M_MSR_POW macro
  target/ppc: Substitute msr_me macro with new M_MSR_ME macro
  target/ppc: Substitute msr_gs macro with new M_MSR_GS macro
  target/ppc: Substitute msr_fp macro with new M_MSR_FP macro
  target/ppc: Substitute msr_cm macro with new M_MSR_CM macro
  target/ppc: Substitute msr_ir macro with new M_MSR_IR macro
  target/ppc: Substitute msr_dr macro with new M_MSR_DR macro
  target/ppc: Substitute msr_ep macro with new M_MSR_EP macro
  target/ppc: Substitute msr_fe macro with new M_MSR_FE macro
  target/ppc: Substitute msr_ts macro with new M_MSR_TS macro
  target/ppc: Substitute msr_hv macro with new M_MSR_HV macro
  target/ppc: Add unused M_MSR_* macros

 hw/ppc/pegasos2.c|   2 +-
 hw/ppc/spapr.c   |   2 +-
 target/ppc/cpu.c |   2 +-
 target/ppc/cpu.h | 125 ---
 target/ppc/cpu_init.c|  21 ---
 target/ppc/excp_helper.c |  53 +
 target/ppc/fpu_helper.c  |  28 -
 target/ppc/gdbstub.c |   2 +-
 target/ppc/helper_regs.c |  12 ++--
 target/ppc/kvm.c |   7 ++-
 target/ppc/machine.c |   2 +-
 target/ppc/mem_helper.c  |  23 +++
 target/ppc/misc_helper.c |   2 +-
 target/ppc/mmu-radix64.c |  10 ++--
 target/ppc/mmu_common.c  |  38 ++--
 target/ppc/mmu_helper.c  |   6 +-
 16 files changed, 161 insertions(+), 174 deletions(-)

-- 
2.25.1

[PATCH 10/20] target/ppc: Substitute msr_me macro with new M_MSR_ME macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h |  2 +-
 target/ppc/excp_helper.c | 12 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b79c00dd65..aa20a604ab 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -358,6 +358,7 @@ typedef enum {
 #define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_EE (1ull << MSR_EE)
 #define M_MSR_PR (1ull << MSR_PR)
+#define M_MSR_ME (1ull << MSR_ME)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
 
@@ -479,7 +480,6 @@ typedef enum {
 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
-#define msr_me   ((env->msr >> MSR_ME)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 91af089d2e..0548b493a7 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -444,7 +444,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
 srr1 = SPR_40x_SRR3;
 break;
 case POWERPC_EXCP_MCHECK:/* Machine check exception  */
-if (msr_me == 0) {
+if (!(env->msr & M_MSR_ME)) {
 /*
  * Machine check exception is not enabled.  Enter
  * checkstop state.
@@ -575,7 +575,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_CRITICAL:/* Critical input */
 break;
 case POWERPC_EXCP_MCHECK:/* Machine check exception  */
-if (msr_me == 0) {
+if (!(env->msr & M_MSR_ME)) {
 /*
  * Machine check exception is not enabled.  Enter
  * checkstop state.
@@ -748,7 +748,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
 
 switch (excp) {
 case POWERPC_EXCP_MCHECK:/* Machine check exception  */
-if (msr_me == 0) {
+if (!(env->msr & M_MSR_ME)) {
 /*
  * Machine check exception is not enabled.  Enter
  * checkstop state.
@@ -933,7 +933,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
 
 switch (excp) {
 case POWERPC_EXCP_MCHECK:/* Machine check exception  */
-if (msr_me == 0) {
+if (!(env->msr & M_MSR_ME)) {
 /*
  * Machine check exception is not enabled.  Enter
  * checkstop state.
@@ -1128,7 +1128,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
 srr1 = SPR_BOOKE_CSRR1;
 break;
 case POWERPC_EXCP_MCHECK:/* Machine check exception  */
-if (msr_me == 0) {
+if (!(env->msr & M_MSR_ME)) {
 /*
  * Machine check exception is not enabled.  Enter
  * checkstop state.
@@ -1366,7 +1366,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
 
 switch (excp) {
 case POWERPC_EXCP_MCHECK:/* Machine check exception  */
-if (msr_me == 0) {
+if (!(env->msr & M_MSR_ME)) {
 /*
  * Machine check exception is not enabled.  Enter
  * checkstop state.
-- 
2.25.1

[PATCH 09/20] target/ppc: Substitute msr_pow macro with new M_MSR_POW macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h |  2 +-
 target/ppc/excp_helper.c | 12 ++--
 target/ppc/helper_regs.c |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3f10c1f5b2..b79c00dd65 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,7 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_POW (1ull << MSR_POW)
 #define M_MSR_CE (1ull << MSR_CE)
 #define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_EE (1ull << MSR_EE)
@@ -477,7 +478,6 @@ typedef enum {
 #endif
 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
-#define msr_pow  ((env->msr >> MSR_POW)  & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6dcaa79516..91af089d2e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -661,7 +661,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_ITLB:  /* Instruction TLB error*/
 break;
 case POWERPC_EXCP_RESET: /* System reset exception   */
-if (msr_pow) {
+if (env->msr & M_MSR_POW) {
 cpu_abort(cs, "Trying to deliver power-saving system reset "
   "exception %d with no HV support\n", excp);
 }
@@ -853,7 +853,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_DECR:  /* Decrementer exception*/
 break;
 case POWERPC_EXCP_RESET: /* System reset exception   */
-if (msr_pow) {
+if (env->msr & M_MSR_POW) {
 cpu_abort(cs, "Trying to deliver power-saving system reset "
   "exception %d with no HV support\n", excp);
 }
@@ -1038,7 +1038,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
 case POWERPC_EXCP_DECR:  /* Decrementer exception*/
 break;
 case POWERPC_EXCP_RESET: /* System reset exception   */
-if (msr_pow) {
+if (env->msr & M_MSR_POW) {
 cpu_abort(cs, "Trying to deliver power-saving system reset "
   "exception %d with no HV support\n", excp);
 }
@@ -1248,7 +1248,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 break;
 case POWERPC_EXCP_RESET: /* System reset exception   */
-if (msr_pow) {
+if (env->msr & M_MSR_POW) {
 cpu_abort(cs, "Trying to deliver power-saving system reset "
   "exception %d with no HV support\n", excp);
 }
@@ -1507,7 +1507,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
 break;
 case POWERPC_EXCP_RESET: /* System reset exception   */
 /* A power-saving exception sets ME, otherwise it is unchanged */
-if (msr_pow) {
+if (env->msr & M_MSR_POW) {
 /* indicate that we resumed from power save mode */
 msr |= 0x1;
 new_msr |= ((target_ulong)1 << MSR_ME);
@@ -1519,7 +1519,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
  */
 new_msr |= (target_ulong)MSR_HVB;
 } else {
-if (msr_pow) {
+if (env->msr & M_MSR_POW) {
 cpu_abort(cs, "Trying to deliver power-saving system reset "
   "exception %d with no HV support\n", excp);
 }
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 9a691d6833..a9bedfce50 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -261,7 +261,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, 
int alter_hv)
 env->msr = value;
 hreg_compute_hflags(env);
 #if !defined(CONFIG_USER_ONLY)
-if (unlikely(msr_pow == 1)) {
+if (unlikely(env->msr & M_MSR_POW)) {
 if (!env->pending_interrupts && (*env->check_pow)(env)) {
 cs->halted = 1;
 excp = EXCP_HALTED;
-- 
2.25.1

[qemu.qmp PATCH 05/12] add a couple new trove classifiers

[John Snow]

Signed-off-by: John Snow 
Reviewed-by: Beraldo Leal 
---
 setup.cfg | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/setup.cfg b/setup.cfg
index 0a1c215..000f00a 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -12,6 +12,7 @@ long_description = file:PACKAGE.rst
 long_description_content_type = text/x-rst
 classifiers =
 Development Status :: 3 - Alpha
+Intended Audience :: Developers
 License :: OSI Approved :: GNU General Public License v2 (GPLv2)
 Natural Language :: English
 Operating System :: OS Independent
@@ -21,6 +22,7 @@ classifiers =
 Programming Language :: Python :: 3.8
 Programming Language :: Python :: 3.9
 Programming Language :: Python :: 3.10
+Topic :: System :: Emulators
 Typing :: Typed
 
 [options]
-- 
2.34.1

[qemu.qmp PATCH 09/12] add LGPLv2+ and GPLv2 LICENSE files

[John Snow]

This clarifies that the majority of this package is LGPLv2+. Copyright
blurbs that pointed to QEMU's "COPYING" file are amended to point to
this repository's "LICENSE" file instead.

The only file that is not already licensed as LGPLv2+ is legacy.py,
which is GPLv2 only. Amend the copyright blurb there to point to
LICENSE_GPL2, which is a copy of qemu.git's COPYING file.

legacy.py is scheduled for removal, at which point the license of this
library will become exclusively LGPLv2+. As the package currently
contains a mixture of LGPLv2+ and GPLv2 code, the trove classifiers will
reflect this mixture until such time as the remaining GPLv2 code is
removed.

Signed-off-by: John Snow 
---
 FILES.rst |   3 +
 LICENSE   | 481 ++
 LICENSE_GPL2  | 339 +
 qemu/qmp/__init__.py  |   2 +-
 qemu/qmp/legacy.py|   2 +-
 qemu/qmp/qmp_shell.py |   2 +-
 qemu/qmp/qmp_tui.py   |   2 +-
 setup.cfg |   1 +
 8 files changed, 828 insertions(+), 4 deletions(-)
 create mode 100644 LICENSE
 create mode 100644 LICENSE_GPL2

diff --git a/FILES.rst b/FILES.rst
index 0c29a88..f70e8de 100644
--- a/FILES.rst
+++ b/FILES.rst
@@ -50,6 +50,9 @@ Files in this directory
 - ``avocado.cfg`` Configuration for the Avocado test-runner.
   Used by ``make check`` et al.
 - ``FILES.rst`` you are here!
+- ``LICENSE`` This project is licensed as LGPLv2+; except for
+  ``legacy.py``.
+- ``LICENSE_GPL2`` This is the license for ``legacy.py``.
 - ``Makefile`` provides some common testing/installation invocations.
   Try ``make help`` to see available targets.
 - ``MANIFEST.in`` is read by python setuptools, it specifies additional files
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 000..12735e6
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,481 @@
+  GNU LIBRARY GENERAL PUBLIC LICENSE
+   Version 2, June 1991
+
+ Copyright (C) 1991 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the library GPL.  It is
+ numbered 2 because it goes with version 2 of the ordinary GPL.]
+
+Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+  This license, the Library General Public License, applies to some
+specially designated Free Software Foundation software, and to any
+other libraries whose authors decide to use it.  You can use it for
+your libraries, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if
+you distribute copies of the library, or if you modify it.
+
+  For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you.  You must make sure that they, too, receive or can get the source
+code.  If you link a program with the library, you must provide
+complete object files to the recipients so that they can relink them
+with the library, after making changes to the library and recompiling
+it.  And you must show them these terms so they know their rights.
+
+  Our method of protecting your rights has two steps: (1) copyright
+the library, and (2) offer you this license which gives you legal
+permission to copy, distribute and/or modify the library.
+
+  Also, for each distributor's protection, we want to make certain
+that everyone understands that there is no warranty for this free
+library.  If the library is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original
+version, so that any problems introduced by others will not reflect on
+the original authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that companies distributing free
+software will individually obtain patent licenses, thus in effect
+transforming the program into proprietary software.  To prevent this,
+we have made it clear that any patent must be licensed for everyone's
+free use or no

[PATCH 05/20] target/ppc: Substitute msr_ds macro with new M_MSR_DS macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 target/ppc/cpu.h| 2 +-
 target/ppc/mmu_common.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d25a778b7c..e81f1f2d68 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
 #define M_MSR_PR (1ull << MSR_PR)
+#define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
 
 /* PMU bits */
@@ -484,7 +485,6 @@ typedef enum {
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
-#define msr_ds   ((env->msr >> MSR_DS)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index fef2b11733..b7865d24b2 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -768,7 +768,7 @@ static bool mmubooke206_get_as(CPUPPCState *env,
 *pr_out = !!(epidr & EPID_EPR);
 return true;
 } else {
-*as_out = msr_ds;
+*as_out = env->msr & M_MSR_DS;
 *pr_out = env->msr & M_MSR_PR;
 return false;
 }
-- 
2.25.1

[PATCH 03/20] target/ppc: Substitute msr_pr macro with new M_MSR_PR macro

[Víctor Colombo]

Suggested-by: Richard Henderson 
Signed-off-by: Víctor Colombo 
---
 hw/ppc/pegasos2.c|  2 +-
 hw/ppc/spapr.c   |  2 +-
 target/ppc/cpu.h |  3 ++-
 target/ppc/cpu_init.c|  4 ++--
 target/ppc/excp_helper.c |  6 +++---
 target/ppc/mem_helper.c  |  4 ++--
 target/ppc/mmu-radix64.c |  4 ++--
 target/ppc/mmu_common.c  | 23 ---
 8 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 56bf203dfd..27ed54a71d 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -461,7 +461,7 @@ static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, 
PowerPCCPU *cpu)
 /* The TCG path should also be holding the BQL at this point */
 g_assert(qemu_mutex_iothread_locked());
 
-if (msr_pr) {
+if (env->msr & M_MSR_PR) {
 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
 env->gpr[3] = H_PRIVILEGE;
 } else if (env->gpr[3] == KVMPPC_H_RTAS) {
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 22569305d2..c947494099 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1269,7 +1269,7 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor 
*vhyp,
 
 g_assert(!vhyp_cpu_in_nested(cpu));
 
-if (msr_pr) {
+if (env->msr & M_MSR_PR) {
 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
 env->gpr[3] = H_PRIVILEGE;
 } else {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 106b555b86..2ad023e981 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,8 @@ typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt1*/
 #define MSR_LE   0  /* Little-endian mode   1 hflags */
 
+#define M_MSR_PR (1ull << MSR_PR)
+
 /* PMU bits */
 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters  */
 #define MMCR0_PMAO   PPC_BIT(56) /* Perf Monitor Alert Ocurred */
@@ -474,7 +476,6 @@ typedef enum {
 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
-#define msr_pr   ((env->msr >> MSR_PR)   & 1)
 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d42e2ba8e0..6e2b23a859 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6303,7 +6303,7 @@ static bool cpu_has_work_POWER9(CPUState *cs)
 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
 (env->spr[SPR_LPCR] & LPCR_EEE)) {
 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
-if (heic == 0 || !msr_hv || msr_pr) {
+if (!heic || !msr_hv || (env->msr & M_MSR_PR)) {
 return true;
 }
 }
@@ -6517,7 +6517,7 @@ static bool cpu_has_work_POWER10(CPUState *cs)
 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
 (env->spr[SPR_LPCR] & LPCR_EEE)) {
 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
-if (heic == 0 || !msr_hv || msr_pr) {
+if (!heic || !msr_hv || (env->msr & M_MSR_PR)) {
 return true;
 }
 }
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d3e2cfcd71..10cd381be2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1738,7 +1738,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
 /* HEIC blocks delivery to the hypervisor */
-if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
+if ((async_deliver && !(heic && msr_hv && !(env->msr & M_MSR_PR))) ||
 (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
 if (books_vhyp_promotes_external_to_hvirt(cpu)) {
 powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
@@ -1818,7 +1818,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
  * EBB exception must be taken in problem state and
  * with BESCR_GE set.
  */
-if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
+if ((env->msr & M_MSR_PR) && (env->spr[SPR_BESCR] & BESCR_GE)) {
 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
 
 if (env->spr[SPR_BESCR] & BESCR_PMEO) {
@@ -2094,7 +2094,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp)
 env->spr[SPR_BESCR] |= BESCR_EEO;
 }
 
-if (msr_pr == 1) {
+if (env->msr & M_MSR_PR) {
 powerpc_excp(cpu, ebb_excp);
 } else {
 env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index c4ff8fd632..bd219e9c9c 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -613,10 +613,10 @@ void helper_tbegin(CPUPPCState *env)
 (1ULL << TEXASR_FAILURE_P

[qemu.qmp PATCH 11/12] remove sub-dependency pins from Pipfile

[John Snow]

Now that we've got a Pipfile.lock generated that works, we can remove
the static pins from the Pipfile to allow various dependencies to be
added or removed as necessary when updating our direct dependencies in
the future.

So long as --keep-outdated is always passed to Pipenv, items that aren't
absolutely necessary to update will not be, which will help keep our
requirements more at the very oldest possible versions that still work.

Signed-off-by: John Snow 
---
 Pipfile | 33 -
 1 file changed, 33 deletions(-)

diff --git a/Pipfile b/Pipfile
index 595b83f..f44fd1e 100644
--- a/Pipfile
+++ b/Pipfile
@@ -4,42 +4,9 @@ url = "https://pypi.org/simple";
 verify_ssl = true
 
 [dev-packages]
-avocado-framework = "==90.0"
-isort = "==5.1.2"
-tox = "==3.18.0"
-toml = "==0.10.0"
-six = "==1.14.0"
-filelock = "==3.0.0"
-virtualenv = "==16.0.0"
-py = "==1.4.17"
-pluggy = "==0.12.0"
-pyparsing = "==2.0.2"
-"backports.entry-points-selectable" = "==1.0.4"
-platformdirs = "==2.0.0"
-distlib = "==0.3.1"
-importlib-metadata = "==0.12"
-zipp = "==0.5"
-pylint = "==2.8.0"
-astroid = "==2.5.4"
-mccabe = "==0.6"
-lazy-object-proxy = "==1.4.0"
-wrapt = "==1.11"
-flake8 = "==3.6.0"
-pycodestyle = "==2.4.0"
-pyflakes = "==2.0.0"
-mypy = "==0.780"
-typed-ast = "==1.4.0"
-typing-extensions = "==3.7.4"
-mypy-extensions = "==0.4.3"
-urwid = "==2.1.2"
-urwid-readline = "==0.13"
-Pygments = "==2.9.0"
 "qemu.qmp" = {editable = true, extras = ["devel"], path = "."}
 
 [packages]
-urwid = "==2.1.2"
-urwid-readline = "==0.13"
-Pygments = "==2.9.0"
 "qemu.qmp" = {editable = true, extras = ["tui"], path = "."}
 
 [requires]
-- 
2.34.1

[qemu.qmp PATCH 12/12] update VERSION to 0.0.0a1

[John Snow]

qemu.qmp will be independently versioned, without regard to QEMU
version. While the repo is being established here, set the version to
something impossibly low.

Later, I intend to introduce automatic versioning based on git
tags. While the repo is being established it's going to be
easier to have a static version while we get bootstrapped.

(Note: PyPI already has a 0.0.0a0 version which I uploaded without prior
review to aid in developing and testing this series. This version, and
all 0.0.0 pre-release versions, will be buried after the first "real"
release, expected to be 0.0.1.)

Signed-off-by: John Snow 
---
 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index c19f3b8..7741e1a 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-0.6.1.0a1
+0.0.0a1
-- 
2.34.1

[qemu.qmp PATCH 02/12] update maintainer metadata

[John Snow]

Modify "QEMU Developer Team" to "QEMU Project", as this matches the
spelling we use for the collective on gitlab.com/qemu-project.

Add myself as the principal maintainer contact.

Signed-off-by: John Snow 
---
 setup.cfg | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/setup.cfg b/setup.cfg
index 4ffab73..f06f944 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -1,8 +1,10 @@
 [metadata]
 name = qemu.qmp
 version = file:VERSION
-maintainer = QEMU Developer Team
-maintainer_email = qemu-devel@nongnu.org
+author = QEMU Project
+author_email = qemu-devel@nongnu.org
+maintainer = John Snow
+maintainer_email = js...@redhat.com
 url = https://www.qemu.org/
 download_url = https://www.qemu.org/download/
 description = QEMU Python Build, Debug and SDK tooling.
-- 
2.34.1

[qemu.qmp PATCH 08/12] docs: add versioning policy to README

[John Snow]

The package is in an alpha state, but there's a method to the madness.

Signed-off-by: John Snow 
Reviewed-by: Damien Hedde 
---
 README.rst | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/README.rst b/README.rst
index 20f513e..cea1400 100644
--- a/README.rst
+++ b/README.rst
@@ -157,6 +157,28 @@ fail. These checks use their own `virtual environments
 working space.
 
 
+Stability and Versioning
+
+
+This package uses a major.minor.micro `SemVer versioning
+`_, with the following additional semantics during
+the alpha/beta period (Major version 0):
+
+This package treats 0.0.z versions as "alpha" versions. Each micro
+version update may change the API incompatibly. Early users are advised
+to pin against explicit versions, but check for updates often.
+
+A planned 0.1.z version will introduce the first "beta", whereafter each
+micro update will be backwards compatible, but each minor update will
+not be. The first beta version will be released after legacy.py is
+removed, and the API is tentatively "stable".
+
+Thereafter, normal `SemVer `_ / `PEP440
+`_ rules will apply; micro updates
+will always be bugfixes, and minor updates will be reserved for
+backwards compatible feature changes.
+
+
 Changelog
 -
 
-- 
2.34.1

[qemu.qmp PATCH 10/12] update Pipfile

[John Snow]

The name of the package has changed and the dependencies are different,
so the Pipfile needs to be updated.

This is a little annoying, but Python doesn't offer any tool (to my
knowledge) that behaves in a manner that gives you the *oldest*, but
still adequate, versions of dependencies. So testing minimum version
requirements is actually kind of challenging.

So, do it manually: pin every version at the minimum that still allows
the tests to succeed. This is the best way to experimentally determine
what precisely our development minimum criteria actually are.

Most of these follow from just observing the minimum stated requirements
for each package, manually, recursively. However, I observed that toml's
stated dependency of >= 0.9.4 in pylint actually needs to be >= 0.10.0.

(If you're new to pipenv, it's a tool separate from packaging metadata
that is used to provide a precise specification for a virtual
environment. In this repository, I am using it to pin a testing
environment against the very oldest packages we support in order to test
that we do not break compatibility with older versions of python,
pylint, mypy, etc.)

Signed-off-by: John Snow 
---
 Pipfile  |  37 ++-
 Pipfile.lock | 288 ---
 2 files changed, 195 insertions(+), 130 deletions(-)

diff --git a/Pipfile b/Pipfile
index e7acb8c..595b83f 100644
--- a/Pipfile
+++ b/Pipfile
@@ -4,10 +4,43 @@ url = "https://pypi.org/simple";
 verify_ssl = true
 
 [dev-packages]
-qemu = {editable = true, extras = ["devel"], path = "."}
+avocado-framework = "==90.0"
+isort = "==5.1.2"
+tox = "==3.18.0"
+toml = "==0.10.0"
+six = "==1.14.0"
+filelock = "==3.0.0"
+virtualenv = "==16.0.0"
+py = "==1.4.17"
+pluggy = "==0.12.0"
+pyparsing = "==2.0.2"
+"backports.entry-points-selectable" = "==1.0.4"
+platformdirs = "==2.0.0"
+distlib = "==0.3.1"
+importlib-metadata = "==0.12"
+zipp = "==0.5"
+pylint = "==2.8.0"
+astroid = "==2.5.4"
+mccabe = "==0.6"
+lazy-object-proxy = "==1.4.0"
+wrapt = "==1.11"
+flake8 = "==3.6.0"
+pycodestyle = "==2.4.0"
+pyflakes = "==2.0.0"
+mypy = "==0.780"
+typed-ast = "==1.4.0"
+typing-extensions = "==3.7.4"
+mypy-extensions = "==0.4.3"
+urwid = "==2.1.2"
+urwid-readline = "==0.13"
+Pygments = "==2.9.0"
+"qemu.qmp" = {editable = true, extras = ["devel"], path = "."}
 
 [packages]
-qemu = {editable = true,path = "."}
+urwid = "==2.1.2"
+urwid-readline = "==0.13"
+Pygments = "==2.9.0"
+"qemu.qmp" = {editable = true, extras = ["tui"], path = "."}
 
 [requires]
 python_version = "3.6"
diff --git a/Pipfile.lock b/Pipfile.lock
index ce46404..f771fb6 100644
--- a/Pipfile.lock
+++ b/Pipfile.lock
@@ -1,7 +1,7 @@
 {
 "_meta": {
 "hash": {
-"sha256": 
"f1a25654d884a5b450e38d78b1f2e3ebb9073e421cc4358d4bbb83ac251a5670"
+"sha256": 
"b9067d0e558c07da0a02abceee8495da37c3eb7246d555e7061709521cdf3777"
 },
 "pipfile-spec": 6,
 "requires": {
@@ -16,26 +16,51 @@
 ]
 },
 "default": {
-"qemu": {
+"pygments": {
+"hashes": [
+
"sha256:a18f47b506a429f6f4b9df81bb02beab9ca21d0a5fee38ed15aef65f0545519f",
+
"sha256:d66e804411278594d764fc69ec36ec13d9ae9147193a1740cd34d272ca383b8e"
+],
+"index": "pypi",
+"version": "==2.9.0"
+},
+"qemu-qmp": {
 "editable": true,
+"extras": [
+"tui"
+],
 "path": "."
+},
+"qemu.qmp": {
+"editable": true,
+"extras": [
+"tui"
+],
+"path": "."
+},
+"urwid": {
+"hashes": [
+
"sha256:588bee9c1cb208d0906a9f73c613d2bd32c3ed3702012f51efe318a3f2127eae"
+],
+"index": "pypi",
+"version": "==2.1.2"
+},
+"urwid-readline": {
+"hashes": [
+
"sha256:018020cbc864bb5ed87be17dc26b069eae2755cb29f3a9c569aac3bded1efaf4"
+],
+"index": "pypi",
+"version": "==0.13"
 }
 },
 "develop": {
-"appdirs": {
-"hashes": [
-
"sha256:7d5d0167b2b1ba821647616af46a749d1c653740dd0d2415100fe26e27afdf41",
-
"sha256:a841dacd6b99318a741b166adb07e19ee71a274450e68237b4650ca1055ab128"
-],
-"version": "==1.4.4"
-},
 "astroid": {
 "hashes": [
-
"sha256:09bdb456e02564731f8b5957cdd0c98a7f01d2db5e90eb1d794c353c28bfd705",
-
"sha256:6a8a51f64dae307f6e0c9db752b66a7951e282389d8362cc1d39a56f3feeb31d"
+
"sha256:f040fe9c4a2a7699a8ec30c9ed10fb59067c97f64c36577f476c0953ba29847c",
+
"sha256:f9f472d4002d55199b1c151ef0570cf71d42aaa34aaa3d29c3e41c75f6f47564"
 ],
 "index": "pypi",
-"version": "==2.6.0"
+"version": "==2.5.4"
 },
   

[qemu.qmp PATCH 06/12] move README.rst to FILES.rst and update

[John Snow]

The intent is to use README.rst as the new package-level readme that
will be bundled with the source and be displayed on the GitLab landing
page; so move the old "git level readme" over to FILES.rst instead, and
update it accordingly.

This is primarily here to just document and explain what all the little
bits and pieces of files in the root are and what they do. I find this
stuff helpful when I wander over into other projects, so I'd like to
extend the same courtesy.

Signed-off-by: John Snow 
---
 README.rst => FILES.rst | 49 +++--
 MANIFEST.in |  1 -
 2 files changed, 13 insertions(+), 37 deletions(-)
 rename README.rst => FILES.rst (64%)

diff --git a/README.rst b/FILES.rst
similarity index 64%
rename from README.rst
rename to FILES.rst
index 9c1fcea..68892c3 100644
--- a/README.rst
+++ b/FILES.rst
@@ -1,9 +1,14 @@
-QEMU Python Tooling
+qemu.qmp File Index
 ===
 
-This directory houses Python tooling used by the QEMU project to build,
-configure, and test QEMU. It is organized by namespace (``qemu``), and
-then by package (e.g. ``qemu/machine``, ``qemu/qmp``, etc).
+This file is here to explain the purpose of all the little bits and
+pieces of project files in the root directory and how they are
+used. It's useful info for those contributing to this project, but not
+so much for those who just want to use the library.
+
+
+Much ado about packaging
+
 
 ``setup.py`` is used by ``pip`` to install this tooling to the current
 environment. ``setup.cfg`` provides the packaging configuration used by
@@ -20,7 +25,7 @@ environment. ``setup.cfg`` provides the packaging 
configuration used by
 
 If you append the ``--editable`` or ``-e`` argument to either invocation
 above, pip will install in "editable" mode. This installs the package as
-a forwarder ("qemu.egg-link") that points to the source tree. In so
+a forwarder ("qemu.qmp.egg-link") that points to the source tree. In so
 doing, the installed package always reflects the latest version in your
 source tree.
 
@@ -37,34 +42,6 @@ See `Installing packages using pip and virtual environments
 for more information.
 
 
-Using these packages without installing them
-
-
-These packages may be used without installing them first, by using one
-of two tricks:
-
-1. Set your PYTHONPATH environment variable to include this source
-   directory, e.g. ``~/src/qemu/python``. See
-   https://docs.python.org/3/using/cmdline.html#envvar-PYTHONPATH
-
-2. Inside a Python script, use ``sys.path`` to forcibly include a search
-   path prior to importing the ``qemu`` namespace. See
-   https://docs.python.org/3/library/sys.html#sys.path
-
-A strong downside to both approaches is that they generally interfere
-with static analysis tools being able to locate and analyze the code
-being imported.
-
-Package installation also normally provides executable console scripts,
-so that tools like ``qmp-shell`` are always available via $PATH. To
-invoke them without installation, you can invoke e.g.:
-
-``> PYTHONPATH=~/src/qemu/python python3 -m qemu.qmp.qmp_shell``
-
-The mappings between console script name and python module path can be
-found in ``setup.cfg``.
-
-
 Files in this directory
 ---
 
@@ -72,6 +49,7 @@ Files in this directory
 - ``tests/`` Python package tests directory.
 - ``avocado.cfg`` Configuration for the Avocado test-runner.
   Used by ``make check`` et al.
+- ``FILES.rst`` you are here!
 - ``Makefile`` provides some common testing/installation invocations.
   Try ``make help`` to see available targets.
 - ``MANIFEST.in`` is read by python setuptools, it specifies additional files
@@ -80,8 +58,7 @@ Files in this directory
 - ``Pipfile`` is used by Pipenv to generate ``Pipfile.lock``.
 - ``Pipfile.lock`` is a set of pinned package dependencies that this package
   is tested under in our CI suite. It is used by ``make check-pipenv``.
-- ``README.rst`` you are here!
-- ``VERSION`` contains the PEP-440 compliant version used to describe
-  this package; it is referenced by ``setup.cfg``.
 - ``setup.cfg`` houses setuptools package configuration.
 - ``setup.py`` is the setuptools installer used by pip; See above.
+- ``VERSION`` contains the PEP-440 compliant version used to describe
+  this package; it is referenced by ``setup.cfg``.
diff --git a/MANIFEST.in b/MANIFEST.in
index 7059ad2..639caae 100644
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,3 +1,2 @@
 include VERSION
 include PACKAGE.rst
-exclude README.rst
-- 
2.34.1

[qemu.qmp PATCH 01/12] fork qemu.qmp from qemu.git

[John Snow]

Split python/ from qemu.git, using these commands:

> git subtree split -P python/ -b python-split-v3
> mkdir ~/src/tmp
> cd ~/src/tmp
> git clone --no-local --branch python-split-v3 --single-branch ~/src/qemu
> cd qemu
> git filter-repo --path qemu/machine/   \
  --path qemu/utils/ \
  --path tests/iotests-mypy.sh   \
  --path tests/iotests-pylint.sh \
  --invert-paths

This commit, however, only performs some minimum cleanup to reflect the
deletion of the other subpackages. It is not intended to be exhaustive,
and further edits are made in forthcoming commits.

These fixes are broken apart into micro-changes to facilitate mailing
list review subject-by-subject. They *could* be squashed into a single
larger commit on merge if desired, but due to the nature of the fork,
bisectability across the fork boundary is going to be challenging
anyway. It may be better value to just leave these initial commits
as-is.

Signed-off-by: John Snow 
Reviewed-by: Kashyap Chamarthy 
---
 .gitignore |  2 +-
 Makefile   | 16 
 setup.cfg  | 24 +---
 setup.py   |  2 +-
 4 files changed, 11 insertions(+), 33 deletions(-)

diff --git a/.gitignore b/.gitignore
index 904f324..b071f02 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,7 +5,7 @@
 # python packaging
 build/
 dist/
-qemu.egg-info/
+qemu.qmp.egg-info/
 
 # editor config
 .idea/
diff --git a/Makefile b/Makefile
index 3334311..a2d2f2c 100644
--- a/Makefile
+++ b/Makefile
@@ -30,7 +30,7 @@ help:
@echo ""
@echo "make develop:"
@echo "Install deps needed for for 'make check',"
-   @echo "and install the qemu package in editable mode."
+   @echo "and install the qemu.qmp package in editable mode."
@echo "(Can be used in or outside of a venv.)"
@echo ""
@echo "make pipenv"
@@ -43,7 +43,7 @@ help:
@echo "Remove package build output."
@echo ""
@echo "make distclean:"
-   @echo "remove pipenv/venv files, qemu package forwarder,"
+   @echo "remove pipenv/venv files, qemu.qmp package forwarder,"
@echo "built distribution files, and everything from 'make clean'."
@echo ""
@echo -e "Have a nice day ^_^\n"
@@ -64,11 +64,11 @@ dev-venv: $(QEMU_VENV_DIR) $(QEMU_VENV_DIR)/bin/activate
 $(QEMU_VENV_DIR) $(QEMU_VENV_DIR)/bin/activate: setup.cfg
@echo "VENV $(QEMU_VENV_DIR)"
@python3 -m venv $(QEMU_VENV_DIR)
-   @(  \
-   echo "ACTIVATE $(QEMU_VENV_DIR)";   \
-   . $(QEMU_VENV_DIR)/bin/activate;\
-   echo "INSTALL qemu[devel] $(QEMU_VENV_DIR)";\
-   make develop 1>/dev/null;   \
+   @(  \
+   echo "ACTIVATE $(QEMU_VENV_DIR)";   \
+   . $(QEMU_VENV_DIR)/bin/activate;\
+   echo "INSTALL qemu.qmp[devel] $(QEMU_VENV_DIR)";\
+   make develop 1>/dev/null;   \
)
@touch $(QEMU_VENV_DIR)
 
@@ -106,6 +106,6 @@ clean:
 
 .PHONY: distclean
 distclean: clean
-   rm -rf qemu.egg-info/ .venv/ .tox/ $(QEMU_VENV_DIR) dist/
+   rm -rf qemu.qmp.egg-info/ .venv/ .tox/ $(QEMU_VENV_DIR) dist/
rm -f .coverage .coverage.*
rm -rf htmlcov/
diff --git a/setup.cfg b/setup.cfg
index e877ea5..4ffab73 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -1,5 +1,5 @@
 [metadata]
-name = qemu
+name = qemu.qmp
 version = file:VERSION
 maintainer = QEMU Developer Team
 maintainer_email = qemu-devel@nongnu.org
@@ -25,8 +25,6 @@ classifiers =
 python_requires = >= 3.6
 packages =
 qemu.qmp
-qemu.machine
-qemu.utils
 
 [options.package_data]
 * = py.typed
@@ -38,7 +36,6 @@ packages =
 devel =
 avocado-framework >= 90.0
 flake8 >= 3.6.0
-fusepy >= 2.0.4
 isort >= 5.1.2
 mypy >= 0.780
 pylint >= 2.8.0
@@ -47,10 +44,6 @@ devel =
 urwid-readline >= 0.13
 Pygments >= 2.9.0
 
-# Provides qom-fuse functionality
-fuse =
-fusepy >= 2.0.4
-
 # QMP TUI dependencies
 tui =
 urwid >= 2.1.2
@@ -59,13 +52,6 @@ tui =
 
 [options.entry_points]
 console_scripts =
-qom = qemu.utils.qom:main
-qom-set = qemu.utils.qom:QOMSet.entry_point
-qom-get = qemu.utils.qom:QOMGet.entry_point
-qom-list = qemu.utils.qom:QOMList.entry_point
-qom-tree = qemu.utils.qom:QOMTree.entry_point
-qom-fuse = qemu.utils.qom_fuse:QOMFuse.entry_point [fuse]
-qemu-ga-client = qemu.utils.qemu_ga_client:main
 qmp-shell = qemu.qmp.qmp_shell:main
 qmp-shell-wrap = qemu.qmp.qmp_shell:main_wrap
 qmp-tui = qemu.qmp.qmp_tui:main [tui]
@@ -80,19 +66,12 @@ python_version = 3.6
 warn_unused_configs = True
 namespace_packages = True
 
-[mypy-qemu.utils.qom_

[qemu.qmp PATCH 03/12] update project description

[John Snow]

Signed-off-by: John Snow 
Reviewed-by: Beraldo Leal 
---
 setup.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/setup.cfg b/setup.cfg
index f06f944..c21f2ce 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -7,7 +7,7 @@ maintainer = John Snow
 maintainer_email = js...@redhat.com
 url = https://www.qemu.org/
 download_url = https://www.qemu.org/download/
-description = QEMU Python Build, Debug and SDK tooling.
+description = QEMU Monitor Protocol library
 long_description = file:PACKAGE.rst
 long_description_content_type = text/x-rst
 classifiers =
-- 
2.34.1

[qemu.qmp PATCH 00/12] python: fork qemu.qmp python lib into independent repo

[John Snow]

GitLab: https://gitlab.com/jsnow/qemu.qmp/-/commits/initial-checkin

Hi, this series is part of an effort to publish the qemu.qmp package on
PyPI. It is part of the second of three phases to complete this work:

(1) Switch the new Async QMP library in to python/qemu/qmp [merged!]
(2) Fork python/qemu/qmp out into its own repository.
-->(2a) Do the bare minimum to be consistent.
   (2b) Add most GitLab CI/CD targets.
   (2c) Add Sphinx doc builds, update docs, and publish to GitLab pages.
   (2d) Add dynamic git versioning and GitLab package builds.
(3) Update qemu.git to install qemu.qmp from PyPI,
and then delete python/qemu/qmp.

This series is not meant to apply to qemu.git, rather -- it's the series
that performs the split and applies to the brand new repository.

If there are no objections, I intend to push the content of this branch
to https://gitlab.com/qemu-project/python-qemu-qmp within a week or so.

Most URLs in this series have been updated to point to the new repo URL,
except one link to https://jsnow.gitlab.io/qemu.qmp/ which will be
updated when step (2c) above is handled.

John Snow (12):
  fork qemu.qmp from qemu.git
  update maintainer metadata
  update project description
  update project URLs
  add a couple new trove classifiers
  move README.rst to FILES.rst and update
  move PACKAGE.rst to README.rst and update
  docs: add versioning policy to README
  add LGPLv2+ and GPLv2 LICENSE files
  update Pipfile
  remove sub-dependency pins from Pipfile
  update VERSION to 0.0.0a1

 .gitignore|   2 +-
 FILES.rst |  67 ++
 LICENSE   | 481 ++
 LICENSE_GPL2  | 339 +
 MANIFEST.in   |   3 +-
 Makefile  |  16 +-
 PACKAGE.rst   |  43 
 Pipfile   |   4 +-
 Pipfile.lock  | 288 ++---
 README.rst| 272 
 VERSION   |   2 +-
 qemu/qmp/__init__.py  |   2 +-
 qemu/qmp/legacy.py|   2 +-
 qemu/qmp/qmp_shell.py |   2 +-
 qemu/qmp/qmp_tui.py   |   2 +-
 setup.cfg |  41 ++--
 setup.py  |   2 +-
 17 files changed, 1262 insertions(+), 306 deletions(-)
 create mode 100644 FILES.rst
 create mode 100644 LICENSE
 create mode 100644 LICENSE_GPL2
 delete mode 100644 PACKAGE.rst

-- 
2.34.1

[qemu.qmp PATCH 04/12] update project URLs

[John Snow]

Point to this library's URLs instead of the entire project's.

Signed-off-by: John Snow 
---
 setup.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/setup.cfg b/setup.cfg
index c21f2ce..0a1c215 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -5,8 +5,8 @@ author = QEMU Project
 author_email = qemu-devel@nongnu.org
 maintainer = John Snow
 maintainer_email = js...@redhat.com
-url = https://www.qemu.org/
-download_url = https://www.qemu.org/download/
+url = https://gitlab.com/qemu-project/python-qemu-qmp
+download_url = https://gitlab.com/qemu-project/python-qemu-qmp/-/packages
 description = QEMU Monitor Protocol library
 long_description = file:PACKAGE.rst
 long_description_content_type = text/x-rst
-- 
2.34.1

[qemu.qmp PATCH 07/12] move PACKAGE.rst to README.rst and update

[John Snow]

The README here will reflect both what is shown on GitLab and on the
PyPI landing page. Update it accordingly, and freshen it up.

The documentation URL still points to my mirror, as the patches to
establish sphinx as part of the build process aren't checked in yet,
this will be updated later.

Signed-off-by: John Snow 
Reviewed-by: Kashyap Chamarthy 
---
 FILES.rst   |   2 +-
 MANIFEST.in |   2 +-
 PACKAGE.rst |  43 --
 README.rst  | 163 
 setup.cfg   |   2 +-
 5 files changed, 166 insertions(+), 46 deletions(-)
 delete mode 100644 PACKAGE.rst
 create mode 100644 README.rst

diff --git a/FILES.rst b/FILES.rst
index 68892c3..0c29a88 100644
--- a/FILES.rst
+++ b/FILES.rst
@@ -54,10 +54,10 @@ Files in this directory
   Try ``make help`` to see available targets.
 - ``MANIFEST.in`` is read by python setuptools, it specifies additional files
   that should be included by a source distribution.
-- ``PACKAGE.rst`` is used as the README file that is visible on PyPI.org.
 - ``Pipfile`` is used by Pipenv to generate ``Pipfile.lock``.
 - ``Pipfile.lock`` is a set of pinned package dependencies that this package
   is tested under in our CI suite. It is used by ``make check-pipenv``.
+- ``README.rst`` is used as the README file that is visible on PyPI.org.
 - ``setup.cfg`` houses setuptools package configuration.
 - ``setup.py`` is the setuptools installer used by pip; See above.
 - ``VERSION`` contains the PEP-440 compliant version used to describe
diff --git a/MANIFEST.in b/MANIFEST.in
index 639caae..2a3fc58 100644
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,2 +1,2 @@
 include VERSION
-include PACKAGE.rst
+include README.rst
diff --git a/PACKAGE.rst b/PACKAGE.rst
deleted file mode 100644
index b0b86cc..000
--- a/PACKAGE.rst
+++ /dev/null
@@ -1,43 +0,0 @@
-QEMU Python Tooling
-===
-
-This package provides QEMU tooling used by the QEMU project to build,
-configure, and test QEMU. It is not a fully-fledged SDK and it is subject
-to change at any time.
-
-Usage
--
-
-The ``qemu.qmp`` subpackage provides a library for communicating with
-QMP servers. The ``qemu.machine`` subpackage offers rudimentary
-facilities for launching and managing QEMU processes. Refer to each
-package's documentation
-(``>>> help(qemu.qmp)``, ``>>> help(qemu.machine)``)
-for more information.
-
-Contributing
-
-
-This package is maintained by John Snow  as part of
-the QEMU source tree. Contributions are welcome and follow the `QEMU
-patch submission process
-`_, which involves
-sending patches to the QEMU development mailing list.
-
-John maintains a `GitLab staging branch
-`_, and there is an
-official `GitLab mirror `_.
-
-Please report bugs on the `QEMU issue tracker
-`_ and tag ``@jsnow`` in
-the report.
-
-Optional packages necessary for running code quality analysis for this
-package can be installed with the optional dependency group "devel":
-``pip install qemu[devel]``.
-
-``make develop`` can be used to install this package in editable mode
-(to the current environment) *and* bring in testing dependencies in one
-command.
-
-``make check`` can be used to run the available tests.
diff --git a/README.rst b/README.rst
new file mode 100644
index 000..20f513e
--- /dev/null
+++ b/README.rst
@@ -0,0 +1,163 @@
+qemu.qmp: QEMU Monitor Protocol Library
+===
+
+Welcome! ``qemu.qmp`` is a `QEMU Monitor Protocol
+`_
+(“QMP”) library written in Python, using `asyncio
+`_. It is used to send
+QMP messages to running `QEMU `_ emulators. It
+requires Python 3.6+ and has no mandatory dependencies.
+
+This library can be used to communicate with QEMU emulators, the `QEMU
+Guest Agent
+`_ (QGA),
+the `QEMU Storage Daemon
+`_
+(QSD), or any other utility or application that `speaks QMP
+`_.
+
+This library makes as few assumptions as possible about the actual
+version or what type of endpoint it will be communicating with;
+i.e. this library does not contain command definitions and does not seek
+to be an SDK or a replacement for tools like `libvirt
+`_ or `virsh
+`_. It is "simply" the protocol
+(QMP) and not the vocabulary (`QAPI
+`_). It is up
+to the library user (you!) to know which commands and arguments you want
+to send.
+
+
+Who is this library for?
+--

Re: [PULL v2 00/61] target-arm queue

[Richard Henderson]

On 4/22/22 06:47, Peter Maydell wrote:

This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's
cleanup patchset (3) one patch fixing an smmuv3 bug...

v2 changes: fix build failure on aarch64 hosts by moving the
gicv3_add_its() and gicv3_foreach_its() functions to
arm_gicv3_its_common.h.

thanks
-- PMM


The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f:

   Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into 
staging (2022-04-21 18:48:18 -0700)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20220422-1

for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce:

   hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
smmuv3_translate() (2022-04-22 14:44:55 +0100)


target-arm queue:
  * Implement GICv4 emulation
  * Some cleanup patches in target/arm
  * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
smmuv3_translate()


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as 
appropriate.


r~






Peter Maydell (41):
   hw/intc/arm_gicv3_its: Add missing blank line
   hw/intc/arm_gicv3: Sanity-check num-cpu property
   hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count
   hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers
   target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
   hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"
   hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4
   hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI
   hw/intc/arm_gicv3_its: Implement VMAPP
   hw/intc/arm_gicv3_its: Distinguish success and error cases of 
CMD_CONTINUE
   hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"
   hw/intc/arm_gicv3_its: Factor out CTE lookup sequence
   hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt 
code
   hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()
   hw/intc/arm_gicv3: Keep pointers to every connected ITS
   hw/intc/arm_gicv3_its: Implement VMOVP
   hw/intc/arm_gicv3_its: Implement VSYNC
   hw/intc/arm_gicv3_its: Implement INV command properly
   hw/intc/arm_gicv3_its: Implement INV for virtual interrupts
   hw/intc/arm_gicv3_its: Implement VMOVI
   hw/intc/arm_gicv3_its: Implement VINVALL
   hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
   hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
   hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from 
gicv3_cpuif_virt_update()
   hw/intc/arm_gicv3_cpuif: Support vLPIs
   hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily
   hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic
   hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic
   hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes
   hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code
   hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()
   hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()
   hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling
   hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()
   hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()
   hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()
   hw/intc/arm_gicv3: Update ID and feature registers for GICv4
   hw/intc/arm_gicv3: Allow 'revision' property to be set to 4
   hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()
   hw/arm/virt: Abstract out calculation of redistributor region capacity
   hw/arm/virt: Support TCG GICv4

Richard Henderson (19):
   target/arm: Update ISAR fields for ARMv8.8
   target/arm: Update SCR_EL3 bits to ARMv8.8
   target/arm: Update SCTLR bits to ARMv9.2
   target/arm: Change DisasContext.aarch64 to bool
   target/arm: Change CPUArchState.aarch64 to bool
   target/arm: Extend store_cpu_offset to take field size
   target/arm: Change DisasContext.thumb to bool
   target/arm: Change CPUArchState.thumb to bool
   target/arm: Remove fpexc32_access
   target/arm: Split out set_btype_raw
   target/arm: Split out gen_rebuild_hflags
   target/arm: Simplify GEN_SHIFT in translate.c
   target/arm: Simplify gen_sar
   target/arm: Simplify aa32 DISAS_WFI
   target/arm: Use tcg_constant in translate-m-nocp.c
   target/arm: Use tcg_constant in translate-neon.c
   target/arm: Use smin/smax for do_sat_addsub_32
   target/arm: Use tcg_constant in transl

Re: [PATCH] qapi: Fix malformed "Since:" section tags

[Andrea Bolognani]

On Fri, Apr 22, 2022 at 03:28:07PM +0200, Markus Armbruster wrote:
> "Since X.Y" is not recognized as a tagged section, and therefore not
> formatted as such in generated documentation.  Fix by adding the
> required colon.
>
> Signed-off-by: Markus Armbruster 
> ---
>  qapi/crypto.json | 3 +--
>  qapi/machine.json| 2 +-
>  qapi/misc.json   | 2 +-
>  qga/qapi-schema.json | 2 +-
>  4 files changed, 4 insertions(+), 5 deletions(-)

Reviewed-by: Andrea Bolognani 

-- 
Andrea Bolognani / Red Hat / Virtualization

[RFC PATCH] 9p: case-insensitive host filesystems

[Christian Schoenebeck]

Now that 9p support for macOS hosts just landed in QEMU 7.0 and with support 
for Windows hosts on the horizon [1], the question is how to deal with case-
insensitive host filesystems, which are very common on those two systems?

I made some tests, e.g. trying to setup a 9p root fs Linux installation on a 
macOS host as described in the QEMU HOWTO [2], which at a certain point causes 
the debootstrap script to fail when trying to unpack the 'libpam-runtime' 
package. That's because it would try to create this symlink:

  /usr/share/man/man7/PAM.7.gz -> /usr/share/man/man7/pam.7.gz

which fails with EEXIST on a case-insensitive APFS. Unfortunately you can't 
easily switch an existing APFS partition to case-sensitivity. It requires to 
reformat the entire partition, loosing all your data, etc.

So I did a quick test with QEMU as outlined below, trying to simply let 9p 
server "eat" EEXIST errors in such cases, but then I realized that most of the 
time it would not even come that far, as Linux client would first send a 
'Twalk' request to check whether target symlink entry already exists, and as 
it gets a positive response from 9p server (again, due to case-insensitivity) 
client would stop right there without even trying to send a 'Tsymlink' 
request.

So maybe it's better to handle case-insensitivity entirely on client side? 
I've read that some generic "case fold" code has landed in the Linux kernel 
recently that might do the trick?

Should 9p server give a hint to 9p client that it's a case-insensitive fs? And 
if yes, once per entire exported fs or rather for each directory (as there 
might be submounts on host)?

[1] https://lore.kernel.org/all/20220408171013.912436-1-bmeng...@gmail.com/
[2] https://wiki.qemu.org/Documentation/9p_root_fs

---
 hw/9pfs/9p-local.c | 54 ++
 1 file changed, 54 insertions(+)

diff --git a/hw/9pfs/9p-local.c b/hw/9pfs/9p-local.c
index d42ce6d8b8..d6cb45c758 100644
--- a/hw/9pfs/9p-local.c
+++ b/hw/9pfs/9p-local.c
@@ -39,6 +39,10 @@
 #endif
 #endif
 #include 
+#ifdef CONFIG_DARWIN
+#include 
+#include 
+#endif
 
 #ifndef XFS_SUPER_MAGIC
 #define XFS_SUPER_MAGIC  0x58465342
@@ -57,6 +61,18 @@ typedef struct {
 int mountfd;
 } LocalData;
 
+#ifdef CONFIG_DARWIN
+
+/* Compare strings case-insensitive (assuming UTF-8 encoding). */
+static int p9_stricmp(const char *a, const char *b)
+{
+g_autofree gchar *cia = g_utf8_casefold(a, -1);
+g_autofree gchar *cib = g_utf8_casefold(b, -1);
+return g_utf8_collate(cia, cib);
+}
+
+#endif
+
 int local_open_nofollow(FsContext *fs_ctx, const char *path, int flags,
 mode_t mode)
 {
@@ -931,6 +947,25 @@ static int local_symlink(FsContext *fs_ctx, const char 
*oldpath,
fs_ctx->export_flags & V9FS_SM_NONE) {
 err = symlinkat(oldpath, dirfd, name);
 if (err) {
+#if CONFIG_DARWIN
+if (errno == EEXIST) {
+printf("  -> symlinkat(oldpath='%s', dirfd=%d, name='%s') = 
EEXIST\n", oldpath, dirfd, name);
+}
+if (errno == EEXIST &&
+strcmp(oldpath, name) && !p9_stricmp(oldpath, name))
+{
+struct stat st1, st2;
+const int cur_errno = errno;
+if (!fstatat(dirfd, oldpath, &st1, AT_SYMLINK_NOFOLLOW) &&
+!fstatat(dirfd, name, &st2, AT_SYMLINK_NOFOLLOW) &&
+st1.st_dev == st2.st_dev && st1.st_ino == st2.st_ino)
+{
+printf("  -> iCASE SAME\n");
+err = 0;
+}
+errno = cur_errno;
+}
+#endif
 goto out;
 }
 err = fchownat(dirfd, name, credp->fc_uid, credp->fc_gid,
@@ -983,6 +1018,25 @@ static int local_link(FsContext *ctx, V9fsPath *oldpath,
 
 ret = linkat(odirfd, oname, ndirfd, name, 0);
 if (ret < 0) {
+#if CONFIG_DARWIN
+if (errno == EEXIST) {
+printf("  -> linkat(odirfd=%d, oname='%s', ndirfd=%d, name='%s') 
= EEXIST\n", odirfd, oname, ndirfd, name);
+}
+if (errno == EEXIST &&
+strcmp(oname, name) && !p9_stricmp(oname, name))
+{
+struct stat st1, st2;
+const int cur_errno = errno;
+if (!fstatat(odirfd, oname, &st1, AT_SYMLINK_NOFOLLOW) &&
+!fstatat(ndirfd, name, &st2, AT_SYMLINK_NOFOLLOW) &&
+st1.st_dev == st2.st_dev && st1.st_ino == st2.st_ino)
+{
+printf("  -> iCASE SAME\n");
+ret = 0;
+}
+errno = cur_errno;
+}
+#endif
 goto out_close;
 }
 
-- 
2.32.0 (Apple Git-132)

[PATCH v9 09/12] target/hexagon: import lexer for idef-parser

[Anton Johansson via]

From: Paolo Montesel 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/idef-parser.h   | 253 +++
 target/hexagon/idef-parser/idef-parser.lex | 471 +
 target/hexagon/meson.build |   4 +
 3 files changed, 728 insertions(+)
 create mode 100644 target/hexagon/idef-parser/idef-parser.h
 create mode 100644 target/hexagon/idef-parser/idef-parser.lex

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
new file mode 100644
index 00..5c49d4da3e
--- /dev/null
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -0,0 +1,253 @@
+/*
+ *  Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+
+#ifndef IDEF_PARSER_H
+#define IDEF_PARSER_H
+
+#include 
+#include 
+#include 
+#include 
+
+#define TCGV_NAME_SIZE 7
+#define MAX_WRITTEN_REGS 32
+#define OFFSET_STR_LEN 32
+#define ALLOC_LIST_LEN 32
+#define ALLOC_NAME_SIZE 32
+#define INIT_LIST_LEN 32
+#define OUT_BUF_LEN (1024 * 1024)
+#define SIGNATURE_BUF_LEN (128 * 1024)
+#define HEADER_BUF_LEN (128 * 1024)
+
+/* Variadic macros to wrap the buffer printing functions */
+#define EMIT(c, ...)   
\
+do {   
\
+g_string_append_printf((c)->out_str, __VA_ARGS__); 
\
+} while (0)
+
+#define EMIT_SIG(c, ...)   
\
+do {   
\
+g_string_append_printf((c)->signature_str, __VA_ARGS__);   
\
+} while (0)
+
+#define EMIT_HEAD(c, ...)  
\
+do {   
\
+g_string_append_printf((c)->header_str, __VA_ARGS__);  
\
+} while (0)
+
+/**
+ * Type of register, assigned to the HexReg.type field
+ */
+typedef enum { GENERAL_PURPOSE, CONTROL, MODIFIER, DOTNEW } HexRegType;
+
+typedef enum { UNKNOWN_SIGNEDNESS, SIGNED, UNSIGNED } HexSignedness;
+
+/**
+ * Semantic record of the REG tokens, identifying registers
+ */
+typedef struct HexReg {
+uint8_t id; /**< Identifier of the register   
*/
+HexRegType type;/**< Type of the register 
*/
+unsigned bit_width; /**< Bit width of the reg, 32 or 64 bits  
*/
+} HexReg;
+
+/**
+ * Data structure, identifying a TCGv temporary value
+ */
+typedef struct HexTmp {
+unsigned index; /**< Index of the TCGv temporary value
*/
+} HexTmp;
+
+/**
+ * Enum of the possible immediated, an immediate is a value which is known
+ * at tinycode generation time, e.g. an integer value, not a TCGv
+ */
+enum ImmUnionTag {
+I,
+VARIABLE,
+VALUE,
+QEMU_TMP,
+IMM_PC,
+IMM_NPC,
+IMM_CONSTEXT,
+};
+
+/**
+ * Semantic record of the IMM token, identifying an immediate constant
+ */
+typedef struct HexImm {
+union {
+char id;/**< Identifier, used when type is VARIABLE   
*/
+uint64_t value; /**< Immediate value, used when type is VALUE 
*/
+uint64_t index; /**< Index, used when type is QEMU_TMP
*/
+};
+enum ImmUnionTag type;  /**< Type of the immediate
*/
+} HexImm;
+
+/**
+ * Semantic record of the PRED token, identifying a predicate
+ */
+typedef struct HexPred {
+char id;/**< Identifier of the predicate  
*/
+} HexPred;
+
+/**
+ * Semantic record of the SAT token, identifying the saturate operator
+ * Note: All saturates are assumed to implicitly set overflow.
+ */
+typedef struct HexSat {
+HexSignedness signedness;   /**< Signedness of the sat. op.   
*/
+} HexSat;
+
+/**
+ * Semantic record of the CAST token, identifying the cast operator
+ */
+typedef struct HexCast {
+unsigned bit_width; /**< Bit width of the cast operator   
*/
+HexSignedness signedness;   /**< Unsigned flag for the cast operator  
*/
+} HexCast;
+
+/**
+ * Semantic record of th

[PATCH v9 07/12] target/hexagon: prepare input for the idef-parser

[Anton Johansson via]

From: Alessandro Di Federico 

Introduce infrastructure necessary to produce a file suitable for being
parsed by the idef-parser.

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/gen_idef_parser_funcs.py | 128 ++
 target/hexagon/idef-parser/macros.inc   | 140 
 target/hexagon/idef-parser/prepare  |  24 
 target/hexagon/meson.build  |  17 +++
 4 files changed, 309 insertions(+)
 create mode 100644 target/hexagon/gen_idef_parser_funcs.py
 create mode 100644 target/hexagon/idef-parser/macros.inc
 create mode 100755 target/hexagon/idef-parser/prepare

diff --git a/target/hexagon/gen_idef_parser_funcs.py 
b/target/hexagon/gen_idef_parser_funcs.py
new file mode 100644
index 00..178648b287
--- /dev/null
+++ b/target/hexagon/gen_idef_parser_funcs.py
@@ -0,0 +1,128 @@
+#!/usr/bin/env python3
+
+##
+##  Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
+##
+##  This program is free software; you can redistribute it and/or modify
+##  it under the terms of the GNU General Public License as published by
+##  the Free Software Foundation; either version 2 of the License, or
+##  (at your option) any later version.
+##
+##  This program is distributed in the hope that it will be useful,
+##  but WITHOUT ANY WARRANTY; without even the implied warranty of
+##  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+##  GNU General Public License for more details.
+##
+##  You should have received a copy of the GNU General Public License
+##  along with this program; if not, see .
+##
+
+import sys
+import re
+import string
+from io import StringIO
+
+import hex_common
+
+##
+## Generate code to be fed to the idef_parser
+##
+## Consider A2_add:
+##
+## Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
+##
+## We produce:
+##
+## A2_add(RdV, in RsV, in RtV) {
+##   { RdV=RsV+RtV;}
+## }
+##
+## A2_add represents the instruction tag. Then we have a list of TCGv
+## that the code generated by the parser can expect in input. Some of
+## them are inputs ("in" prefix), while some others are outputs.
+##
+def main():
+hex_common.read_semantics_file(sys.argv[1])
+hex_common.read_attribs_file(sys.argv[2])
+hex_common.calculate_attribs()
+tagregs = hex_common.get_tagregs()
+tagimms = hex_common.get_tagimms()
+
+with open(sys.argv[3], 'w') as f:
+f.write('#include "macros.inc"\n\n')
+
+for tag in hex_common.tags:
+## Skip the priv instructions
+if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+continue
+## Skip the guest instructions
+if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+continue
+## Skip instructions that saturate in a ternary expression
+if ( tag in {'S2_asr_r_r_sat', 'S2_asl_r_r_sat'} ) :
+continue
+## Skip instructions using switch
+if ( tag in {'S4_vrcrotate_acc', 'S4_vrcrotate'} ) :
+continue
+## Skip trap instructions
+if ( tag in {'J2_trap0', 'J2_trap1'} ) :
+continue
+## Skip 128-bit instructions
+if ( tag in {'A7_croundd_ri', 'A7_croundd_rr'} ) :
+continue
+if ( tag in {'M7_wcmpyrw', 'M7_wcmpyrwc',
+ 'M7_wcmpyiw', 'M7_wcmpyiwc',
+ 'M7_wcmpyrw_rnd', 'M7_wcmpyrwc_rnd',
+ 'M7_wcmpyiw_rnd', 'M7_wcmpyiwc_rnd'} ) :
+continue
+## Skip interleave/deinterleave instructions
+if ( tag in {'S2_interleave', 'S2_deinterleave'} ) :
+continue
+## Skip instructions using bit reverse
+if ( tag in {'S2_brev', 'S2_brevp', 'S2_ct0', 'S2_ct1',
+ 'S2_ct0p', 'S2_ct1p', 'A4_tlbmatch'} ) :
+continue
+## Skip other unsupported instructions
+if ( tag == 'S2_cabacdecbin' or tag == 'A5_ACS' ) :
+continue
+if ( tag.startswith('Y') ) :
+continue
+if ( tag.startswith('V6_') ) :
+continue
+if ( tag.startswith('F') ) :
+continue
+if ( tag.endswith('_locked') ) :
+continue
+
+regs = tagregs[tag]
+imms = tagimms[tag]
+
+arguments = []
+for regtype,regid,toss,numregs in regs:
+prefix = "in " if hex_common.is_read(regid) else ""
+
+is_pair = hex_common.is_pair(regid)
+is_single_old = (hex_common.is_single(regid)
+ and hex_common.is_old_val(regtype, regid, 
tag))
+is_single_new = (hex_common.is_single(regid)
+ and hex_common.is_new_val(regtype, regid, 
tag))
+
+ 

target/i386/kvm/kvm.c:2996: kvm_buf_set_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed

[Michael Tokarev]

Hi!

Apparently there's an assertion failure like in $subj in qemu-7.0.0
(it didn't happen with qemu-6.2), even after the commit:

commit e910a53fb4f20aa012e46371ffb4c32c8da259b4
Author: Maxim Levitsky 
Date:   Wed Feb 23 13:56:49 2022 +0200

KVM: x86: nSVM: disallow userspace setting of MSR_AMD64_TSC_RATIO to non 
default value when tsc scaling disabled

is included in the kernel build.

The original debian bugreport: https://bugs.debian.org/1010026

The logs from libvirt with 2 kernels which have the said commit
included: (based on 5.16.18 and 5.17.3 - unfortunately the kernel
release reported there is difficult):
 https://bugs.debian.org/1010026#42

Both ends up with

qemu-system-x86_64: error: failed to set MSR 0xc104 to 0x1
qemu-system-x86_64: ../../target/i386/kvm/kvm.c:2996: kvm_buf_set_msrs:
 Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed.

I wonder if there's something else needs to be fixed..

BTW, commit e910a53fb4f20aa012e46 included a bugfix for qemu 6.2, -
maybe we should not accumulate fixes for other software bugs in
kernel?  That's just a thought, nothing more..

Thanks!

/mjt

[PATCH v9 10/12] target/hexagon: import parser for idef-parser

[Anton Johansson via]

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/idef-parser.y|  961 
 target/hexagon/idef-parser/parser-helpers.c | 2346 +++
 target/hexagon/idef-parser/parser-helpers.h |  372 +++
 target/hexagon/meson.build  |   25 +
 4 files changed, 3704 insertions(+)
 create mode 100644 target/hexagon/idef-parser/idef-parser.y
 create mode 100644 target/hexagon/idef-parser/parser-helpers.c
 create mode 100644 target/hexagon/idef-parser/parser-helpers.h

diff --git a/target/hexagon/idef-parser/idef-parser.y 
b/target/hexagon/idef-parser/idef-parser.y
new file mode 100644
index 00..096cca2d17
--- /dev/null
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -0,0 +1,961 @@
+%{
+/*
+ *  Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+
+#include "idef-parser.h"
+#include "parser-helpers.h"
+#include "idef-parser.tab.h"
+#include "idef-parser.yy.h"
+
+/* Uncomment this to disable yyasserts */
+/* #define NDEBUG */
+
+#define ERR_LINE_CONTEXT 40
+
+%}
+
+%lex-param {void *scanner}
+%parse-param {void *scanner}
+%parse-param {Context *c}
+
+%define parse.error verbose
+%define parse.lac full
+%define api.pure full
+
+%locations
+
+%union {
+GString *string;
+HexValue rvalue;
+HexSat sat;
+HexCast cast;
+HexExtract extract;
+HexMpy mpy;
+HexSignedness signedness;
+int index;
+}
+
+/* Tokens */
+%start input
+
+%expect 1
+
+%token IN INAME VAR
+%token ABS CROUND ROUND CIRCADD COUNTONES INC DEC ANDA ORA XORA PLUSPLUS ASL
+%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK SXT
+%token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC NPC LPCFG
+%token CANCEL IDENTITY PART1 ROTL INSBITS SETBITS EXTRANGE
+%token CAST4_8U FAIL CARRY_FROM_ADD ADDSAT64 LSBNEW
+%token TYPE_SIZE_T TYPE_INT TYPE_SIGNED TYPE_UNSIGNED TYPE_LONG
+
+%token  REG IMM PRED
+%token  ELSE
+%token  MPY
+%token  SAT
+%token  CAST DEPOSIT SETHALF
+%token  EXTRACT
+%type  INAME
+%type  rvalue lvalue VAR assign_statement var var_decl var_type
+%type  FAIL
+%type  TYPE_SIGNED TYPE_UNSIGNED TYPE_INT TYPE_LONG TYPE_SIZE_T
+%type  if_stmt IF
+%type  SIGN
+
+/* Operator Precedences */
+%left MIN MAX
+%left '('
+%left ','
+%left '='
+%right CIRCADD
+%right INC DEC ANDA ORA XORA
+%left '?' ':'
+%left ANDL
+%left '|'
+%left '^' ANDOR
+%left '&'
+%left EQ NEQ
+%left '<' '>' LTE GTE
+%left ASL ASR LSR
+%right ABS
+%left '-' '+'
+%left '*' '/' '%' MPY
+%right '~' '!'
+%left '['
+%right CAST
+%right LOCNT BREV
+
+/* Bison Grammar */
+%%
+
+/* Input file containing the description of each hexagon instruction */
+input : instructions
+  {
+  YYACCEPT;
+  }
+  ;
+
+instructions : instruction instructions
+ | %empty
+ ;
+
+instruction : INAME
+  {
+  gen_inst(c, $1);
+  }
+  arguments
+  {
+  EMIT_SIG(c, ")");
+  EMIT_HEAD(c, "{\n");
+  }
+  code
+  {
+  gen_inst_code(c, &@1);
+  }
+| error /* Recover gracefully after instruction compilation error 
*/
+  {
+  free_instruction(c);
+  }
+;
+
+arguments : '(' ')'
+  | '(' argument_list ')';
+
+argument_list : argument_decl ',' argument_list
+  | argument_decl
+  ;
+
+var : VAR
+  {
+  track_string(c, $1.var.name);
+  $$ = $1;
+  }
+;
+
+/*
+ * Here the integer types are defined from valid combinations of
+ * `signed`, `unsigned`, `int`, and `long` tokens. The `signed`
+ * and `unsigned` tokens are here assumed to always be placed
+ * first in the type declaration, which is not the case in
+ * normal C. Similarly, `int` is assumed to always be placed
+ * last in the type.
+ */
+type_int : TYPE_INT
+ | TYPE_SIGNED
+ | TYPE_SIGNED TYPE_INT;
+type_uint : TYPE_UNSIGNED
+  | TYPE_UNSIGNED TYPE_INT;
+type_ulonglong : TYPE_UNSIGNED TYPE_LONG TYPE_LONG
+   | TYPE_UNSIGNED TYPE_LONG TYPE_LONG TYPE_INT;
+
+/*
+ * Here the various valid int types defined above specify
+ * their `signedness` and `bit_width`. The LP64 convention
+ * is assumed where longs are 64-bit, long longs are then
+ * assumed to also be 64-bit.
+ */
+var_type : TYPE_SIZE_T
+   {
+  yyassert(c, &@1, $1.bit_width <= 64,
+   "Variables with size > 64-bit are not

[PATCH v9 04/12] target/hexagon: make helper functions non-static

[Anton Johansson via]

From: Paolo Montesel 

Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.

This commit also makes some op_helper.c non-static in order to avoid
having them marked as unused when using the idef-parser generated code.

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Reviewed-by: Richard Henderson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/genptr.c| 59 +-
 target/hexagon/genptr.h| 30 +++
 target/hexagon/op_helper.c | 29 +--
 target/hexagon/op_helper.h | 37 
 4 files changed, 113 insertions(+), 42 deletions(-)
 create mode 100644 target/hexagon/op_helper.h

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index df126de55b..8d1b3f6e2e 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -29,6 +29,13 @@
 #undef QEMU_GENERATE
 #include "gen_tcg.h"
 #include "gen_tcg_hvx.h"
+#include "genptr.h"
+
+TCGv gen_read_preg(TCGv pred, uint8_t num)
+{
+tcg_gen_mov_tl(pred, hex_pred[num]);
+return pred;
+}
 
 static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
 uint32_t slot)
@@ -54,7 +61,7 @@ static inline void gen_log_predicated_reg_write(int rnum, 
TCGv val,
 tcg_temp_free(slot_mask);
 }
 
-static inline void gen_log_reg_write(int rnum, TCGv val)
+void gen_log_reg_write(int rnum, TCGv val)
 {
 tcg_gen_mov_tl(hex_new_value[rnum], val);
 if (HEX_DEBUG) {
@@ -116,7 +123,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
 }
 }
 
-static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
+void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
 {
 TCGv base_val = tcg_temp_new();
 
@@ -274,7 +281,7 @@ static inline void gen_write_ctrl_reg_pair(DisasContext 
*ctx, int reg_num,
 }
 }
 
-static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
+TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
 {
 if (sign) {
 tcg_gen_sextract_tl(result, src, N * 8, 8);
@@ -284,7 +291,7 @@ static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool 
sign)
 return result;
 }
 
-static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
+TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
 {
 TCGv_i64 res64 = tcg_temp_new_i64();
 if (sign) {
@@ -298,7 +305,7 @@ static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 
src, bool sign)
 return result;
 }
 
-static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
+TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
 {
 if (sign) {
 tcg_gen_sextract_tl(result, src, N * 16, 16);
@@ -308,12 +315,12 @@ static inline TCGv gen_get_half(TCGv result, int N, TCGv 
src, bool sign)
 return result;
 }
 
-static inline void gen_set_half(int N, TCGv result, TCGv src)
+void gen_set_half(int N, TCGv result, TCGv src)
 {
 tcg_gen_deposit_tl(result, result, src, N * 16, 16);
 }
 
-static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
+void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
 {
 TCGv_i64 src64 = tcg_temp_new_i64();
 tcg_gen_extu_i32_i64(src64, src);
@@ -321,7 +328,7 @@ static inline void gen_set_half_i64(int N, TCGv_i64 result, 
TCGv src)
 tcg_temp_free_i64(src64);
 }
 
-static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
+void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
 {
 TCGv_i64 src64 = tcg_temp_new_i64();
 tcg_gen_extu_i32_i64(src64, src);
@@ -396,57 +403,57 @@ static inline void gen_store_conditional8(DisasContext 
*ctx,
 tcg_gen_movi_tl(hex_llsc_addr, ~0);
 }
 
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
 {
 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 tcg_gen_movi_tl(hex_store_width[slot], width);
 tcg_gen_mov_tl(hex_store_val32[slot], src);
 }
 
-static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, uint32_t slot)
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+uint32_t slot)
 {
 gen_store32(vaddr, src, 1, slot);
 ctx->store_width[slot] = 1;
 }
 
-static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, uint32_t slot)
+void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot)
 {
 TCGv tmp = tcg_constant_tl(src);
 gen_store1(cpu_env, vaddr, tmp, ctx, slot);
 }
 
-static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, uint32_t slot)
+void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+  

[PATCH v9 08/12] target/hexagon: import flex/bison to docker files

[Anton Johansson via]

This patch points `tests/lcitool/libvirt-ci` to an upstreamed commit of
`libvirt-ci` which includes flex and bison. The `lcitool/refresh` script
was then ran to update the the generated docker/cirrus files.

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Signed-off-by: Anton Johansson 
---
 .gitlab-ci.d/cirrus/freebsd-12.vars   |  2 +-
 .gitlab-ci.d/cirrus/freebsd-13.vars   |  2 +-
 .gitlab-ci.d/cirrus/macos-11.vars |  2 +-
 .gitlab-ci.d/windows.yml  |  2 ++
 tests/docker/dockerfiles/alpine.docker|  6 --
 tests/docker/dockerfiles/centos8.docker   |  7 ---
 tests/docker/dockerfiles/debian-amd64.docker  |  2 ++
 .../dockerfiles/debian-arm64-cross.docker |  6 --
 tests/docker/dockerfiles/debian-native.docker |  3 +++
 .../dockerfiles/debian-riscv64-cross.docker   |  3 +++
 .../dockerfiles/debian-s390x-cross.docker |  6 --
 .../dockerfiles/debian-tricore-cross.docker   |  1 +
 tests/docker/dockerfiles/debian10.docker  |  3 +++
 .../dockerfiles/fedora-i386-cross.docker  |  3 +++
 .../dockerfiles/fedora-win32-cross.docker |  3 +++
 .../dockerfiles/fedora-win64-cross.docker |  3 +++
 tests/docker/dockerfiles/fedora.docker|  5 +++--
 tests/docker/dockerfiles/opensuse-leap.docker |  5 +++--
 tests/docker/dockerfiles/ubuntu1804.docker|  4 +++-
 tests/docker/dockerfiles/ubuntu2004.docker|  5 +++--
 tests/lcitool/libvirt-ci  |  2 +-
 tests/lcitool/projects/qemu.yml   | 20 ++-
 22 files changed, 66 insertions(+), 29 deletions(-)

diff --git a/.gitlab-ci.d/cirrus/freebsd-12.vars 
b/.gitlab-ci.d/cirrus/freebsd-12.vars
index b4842271b2..0cfe18c67c 100644
--- a/.gitlab-ci.d/cirrus/freebsd-12.vars
+++ b/.gitlab-ci.d/cirrus/freebsd-12.vars
@@ -11,6 +11,6 @@ MAKE='/usr/local/bin/gmake'
 NINJA='/usr/local/bin/ninja'
 PACKAGING_COMMAND='pkg'
 PIP3='/usr/local/bin/pip-3.8'
-PKGS='alsa-lib bash bzip2 ca_root_nss capstone4 ccache cdrkit-genisoimage 
ctags curl cyrus-sasl dbus diffutils dtc fusefs-libs3 gettext git glib gmake 
gnutls gsed gtk3 libepoxy libffi libgcrypt libjpeg-turbo libnfs libspice-server 
libssh libtasn1 llvm lzo2 meson ncurses nettle ninja opencv perl5 pixman 
pkgconf png py38-numpy py38-pillow py38-pip py38-sphinx py38-sphinx_rtd_theme 
py38-virtualenv py38-yaml python3 rpm2cpio sdl2 sdl2_image snappy 
spice-protocol tesseract texinfo usbredir virglrenderer vte3 zstd'
+PKGS='alsa-lib bash bison bzip2 ca_root_nss capstone4 ccache 
cdrkit-genisoimage ctags curl cyrus-sasl dbus diffutils dtc flex gettext git 
glib gmake gnutls gsed gtk3 libepoxy libffi libgcrypt libjpeg-turbo libnfs 
libspice-server libssh libtasn1 libxml2 llvm lzo2 meson ncurses nettle ninja 
opencv perl5 pixman pkgconf png py38-numpy py38-pillow py38-pip py38-sphinx 
py38-sphinx_rtd_theme py38-virtualenv py38-yaml python3 rpm2cpio sdl2 
sdl2_image snappy spice-protocol tesseract texinfo usbredir virglrenderer vte3 
zstd'
 PYPI_PKGS=''
 PYTHON='/usr/local/bin/python3'
diff --git a/.gitlab-ci.d/cirrus/freebsd-13.vars 
b/.gitlab-ci.d/cirrus/freebsd-13.vars
index 546a82dd75..33c8856fd4 100644
--- a/.gitlab-ci.d/cirrus/freebsd-13.vars
+++ b/.gitlab-ci.d/cirrus/freebsd-13.vars
@@ -11,6 +11,6 @@ MAKE='/usr/local/bin/gmake'
 NINJA='/usr/local/bin/ninja'
 PACKAGING_COMMAND='pkg'
 PIP3='/usr/local/bin/pip-3.8'
-PKGS='alsa-lib bash bzip2 ca_root_nss capstone4 ccache cdrkit-genisoimage 
ctags curl cyrus-sasl dbus diffutils dtc fusefs-libs3 gettext git glib gmake 
gnutls gsed gtk3 libepoxy libffi libgcrypt libjpeg-turbo libnfs libspice-server 
libssh libtasn1 llvm lzo2 meson ncurses nettle ninja opencv perl5 pixman 
pkgconf png py38-numpy py38-pillow py38-pip py38-sphinx py38-sphinx_rtd_theme 
py38-virtualenv py38-yaml python3 rpm2cpio sdl2 sdl2_image snappy 
spice-protocol tesseract texinfo usbredir virglrenderer vte3 zstd'
+PKGS='alsa-lib bash bison bzip2 ca_root_nss capstone4 ccache 
cdrkit-genisoimage ctags curl cyrus-sasl dbus diffutils dtc flex gettext git 
glib gmake gnutls gsed gtk3 libepoxy libffi libgcrypt libjpeg-turbo libnfs 
libspice-server libssh libtasn1 libxml2 llvm lzo2 meson ncurses nettle ninja 
opencv perl5 pixman pkgconf png py38-numpy py38-pillow py38-pip py38-sphinx 
py38-sphinx_rtd_theme py38-virtualenv py38-yaml python3 rpm2cpio sdl2 
sdl2_image snappy spice-protocol tesseract texinfo usbredir virglrenderer vte3 
zstd'
 PYPI_PKGS=''
 PYTHON='/usr/local/bin/python3'
diff --git a/.gitlab-ci.d/cirrus/macos-11.vars 
b/.gitlab-ci.d/cirrus/macos-11.vars
index cfe9181fd4..1c7366c810 100644
--- a/.gitlab-ci.d/cirrus/macos-11.vars
+++ b/.gitlab-ci.d/cirrus/macos-11.vars
@@ -11,6 +11,6 @@ MAKE='/usr/local/bin/gmake'
 NINJA='/usr/local/bin/ninja'
 PACKAGING_COMMAND='brew'
 PIP3='/usr/local/bin/pip3'
-PKGS='bash bc bzip2 capstone ccache ctags curl dbus diffutils dtc gcovr 
gettext git glib gnu-sed gnutls gtk+3 jemalloc jpeg-turbo libepoxy libffi 
libgcrypt libisc

[PATCH v9 12/12] target/hexagon: import additional tests

[Anton Johansson via]

From: Niccolò Izzo 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Niccolò Izzo 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 tests/tcg/hexagon/Makefile.target  | 28 -
 tests/tcg/hexagon/crt.S| 14 +++
 tests/tcg/hexagon/test_abs.S   | 17 
 tests/tcg/hexagon/test_bitcnt.S| 40 +++
 tests/tcg/hexagon/test_bitsplit.S  | 22 ++
 tests/tcg/hexagon/test_call.S  | 64 ++
 tests/tcg/hexagon/test_clobber.S   | 29 ++
 tests/tcg/hexagon/test_cmp.S   | 31 +++
 tests/tcg/hexagon/test_dotnew.S| 38 ++
 tests/tcg/hexagon/test_ext.S   | 13 ++
 tests/tcg/hexagon/test_fibonacci.S | 30 ++
 tests/tcg/hexagon/test_hl.S| 16 
 tests/tcg/hexagon/test_hwloops.S   | 19 +
 tests/tcg/hexagon/test_jmp.S   | 22 ++
 tests/tcg/hexagon/test_lsr.S   | 36 +
 tests/tcg/hexagon/test_mpyi.S  | 17 
 tests/tcg/hexagon/test_packet.S| 29 ++
 tests/tcg/hexagon/test_reorder.S   | 33 +++
 tests/tcg/hexagon/test_round.S | 29 ++
 tests/tcg/hexagon/test_vavgw.S | 31 +++
 tests/tcg/hexagon/test_vcmpb.S | 30 ++
 tests/tcg/hexagon/test_vcmpw.S | 30 ++
 tests/tcg/hexagon/test_vlsrw.S | 20 ++
 tests/tcg/hexagon/test_vmaxh.S | 35 
 tests/tcg/hexagon/test_vminh.S | 35 
 tests/tcg/hexagon/test_vpmpyh.S| 28 +
 tests/tcg/hexagon/test_vspliceb.S  | 31 +++
 27 files changed, 766 insertions(+), 1 deletion(-)
 create mode 100644 tests/tcg/hexagon/crt.S
 create mode 100644 tests/tcg/hexagon/test_abs.S
 create mode 100644 tests/tcg/hexagon/test_bitcnt.S
 create mode 100644 tests/tcg/hexagon/test_bitsplit.S
 create mode 100644 tests/tcg/hexagon/test_call.S
 create mode 100644 tests/tcg/hexagon/test_clobber.S
 create mode 100644 tests/tcg/hexagon/test_cmp.S
 create mode 100644 tests/tcg/hexagon/test_dotnew.S
 create mode 100644 tests/tcg/hexagon/test_ext.S
 create mode 100644 tests/tcg/hexagon/test_fibonacci.S
 create mode 100644 tests/tcg/hexagon/test_hl.S
 create mode 100644 tests/tcg/hexagon/test_hwloops.S
 create mode 100644 tests/tcg/hexagon/test_jmp.S
 create mode 100644 tests/tcg/hexagon/test_lsr.S
 create mode 100644 tests/tcg/hexagon/test_mpyi.S
 create mode 100644 tests/tcg/hexagon/test_packet.S
 create mode 100644 tests/tcg/hexagon/test_reorder.S
 create mode 100644 tests/tcg/hexagon/test_round.S
 create mode 100644 tests/tcg/hexagon/test_vavgw.S
 create mode 100644 tests/tcg/hexagon/test_vcmpb.S
 create mode 100644 tests/tcg/hexagon/test_vcmpw.S
 create mode 100644 tests/tcg/hexagon/test_vlsrw.S
 create mode 100644 tests/tcg/hexagon/test_vmaxh.S
 create mode 100644 tests/tcg/hexagon/test_vminh.S
 create mode 100644 tests/tcg/hexagon/test_vpmpyh.S
 create mode 100644 tests/tcg/hexagon/test_vspliceb.S

diff --git a/tests/tcg/hexagon/Makefile.target 
b/tests/tcg/hexagon/Makefile.target
index 23b9870534..44ffa1337d 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -24,7 +24,7 @@ CFLAGS += -fno-unroll-loops
 HEX_SRC=$(SRC_PATH)/tests/tcg/hexagon
 VPATH += $(HEX_SRC)
 
-first: $(HEX_SRC)/first.S
+%: $(HEX_SRC)/%.S $(HEX_SRC)/crt.S
$(CC) -static -mv67 -nostdlib $^ -o $@
 
 HEX_TESTS = first
@@ -43,6 +43,32 @@ HEX_TESTS += atomics
 HEX_TESTS += fpstuff
 HEX_TESTS += overflow
 
+HEX_TESTS += test_abs
+HEX_TESTS += test_bitcnt
+HEX_TESTS += test_bitsplit
+HEX_TESTS += test_call
+HEX_TESTS += test_clobber
+HEX_TESTS += test_cmp
+HEX_TESTS += test_dotnew
+HEX_TESTS += test_ext
+HEX_TESTS += test_fibonacci
+HEX_TESTS += test_hl
+HEX_TESTS += test_hwloops
+HEX_TESTS += test_jmp
+HEX_TESTS += test_lsr
+HEX_TESTS += test_mpyi
+HEX_TESTS += test_packet
+HEX_TESTS += test_reorder
+HEX_TESTS += test_round
+HEX_TESTS += test_vavgw
+HEX_TESTS += test_vcmpb
+HEX_TESTS += test_vcmpw
+HEX_TESTS += test_vlsrw
+HEX_TESTS += test_vmaxh
+HEX_TESTS += test_vminh
+HEX_TESTS += test_vpmpyh
+HEX_TESTS += test_vspliceb
+
 TESTS += $(HEX_TESTS)
 
 # This test has to be compiled for the -mv67t target
diff --git a/tests/tcg/hexagon/crt.S b/tests/tcg/hexagon/crt.S
new file mode 100644
index 00..f9e6bc80f7
--- /dev/null
+++ b/tests/tcg/hexagon/crt.S
@@ -0,0 +1,14 @@
+#define SYS_exit_group 94
+
+.text
+.globl pass
+pass:
+r0 = #0
+r6 = #SYS_exit_group
+trap0(#1)
+
+.globl fail
+fail:
+r0 = #1
+r6 = #SYS_exit_group
+trap0(#1)
diff --git a/tests/tcg/hexagon/test_abs.S b/tests/tcg/hexagon/test_abs.S
new file mode 100644
index 00..d68aea6f64
--- /dev/null
+++ b/tests/tcg/hexagon/test_abs.S
@@ -0,0 +1,17 @@
+/* Purpose: test example, verify the soundness of the abs operation */
+
+.text
+.globl _start
+
+_start:
+{
+r1 = #-2
+r2 = #2
+}
+{
+  

[PATCH v9 06/12] target/hexagon: expose next PC in DisasContext

[Anton Johansson via]

From: Paolo Montesel 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Reviewed-by: Richard Henderson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/translate.c | 3 ++-
 target/hexagon/translate.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index d4fc92f7e9..e3e250fd4f 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -741,11 +741,12 @@ static void decode_and_translate_packet(CPUHexagonState 
*env, DisasContext *ctx)
 if (decode_packet(nwords, words, &pkt, false) > 0) {
 HEX_DEBUG_PRINT_PKT(&pkt);
 gen_start_packet(ctx, &pkt);
+ctx->npc = ctx->base.pc_next + pkt.encod_pkt_size_in_bytes;
 for (i = 0; i < pkt.num_insns; i++) {
 gen_insn(env, ctx, &pkt.insn[i], &pkt);
 }
 gen_commit_packet(env, ctx, &pkt);
-ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
+ctx->base.pc_next = ctx->npc;
 } else {
 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
 }
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index a245172827..494471548e 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -53,6 +53,7 @@ typedef struct DisasContext {
 bool qreg_is_predicated[NUM_QREGS];
 int qreg_log_idx;
 bool pre_commit;
+uint32_t npc;
 } DisasContext;
 
 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
-- 
2.35.1

[PATCH v9 03/12] target/hexagon: make slot number an unsigned

[Anton Johansson via]

From: Paolo Montesel 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Acked-by: Richard Henderson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/genptr.c | 24 +---
 target/hexagon/macros.h |  2 +-
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index cd6af4bceb..df126de55b 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -30,7 +30,8 @@
 #include "gen_tcg.h"
 #include "gen_tcg_hvx.h"
 
-static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
+static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
+uint32_t slot)
 {
 TCGv zero = tcg_constant_tl(0);
 TCGv slot_mask = tcg_temp_new();
@@ -62,7 +63,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
 }
 }
 
-static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
+static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
+  uint32_t slot)
 {
 TCGv val32 = tcg_temp_new();
 TCGv zero = tcg_constant_tl(0);
@@ -394,7 +396,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,
 tcg_gen_movi_tl(hex_llsc_addr, ~0);
 }
 
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
+static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
 {
 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 tcg_gen_movi_tl(hex_store_width[slot], width);
@@ -402,49 +404,49 @@ static inline void gen_store32(TCGv vaddr, TCGv src, int 
width, int slot)
 }
 
 static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 gen_store32(vaddr, src, 1, slot);
 ctx->store_width[slot] = 1;
 }
 
 static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv tmp = tcg_constant_tl(src);
 gen_store1(cpu_env, vaddr, tmp, ctx, slot);
 }
 
 static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 gen_store32(vaddr, src, 2, slot);
 ctx->store_width[slot] = 2;
 }
 
 static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv tmp = tcg_constant_tl(src);
 gen_store2(cpu_env, vaddr, tmp, ctx, slot);
 }
 
 static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 gen_store32(vaddr, src, 4, slot);
 ctx->store_width[slot] = 4;
 }
 
 static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv tmp = tcg_constant_tl(src);
 gen_store4(cpu_env, vaddr, tmp, ctx, slot);
 }
 
 static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 tcg_gen_movi_tl(hex_store_width[slot], 8);
@@ -453,7 +455,7 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, 
TCGv_i64 src,
 }
 
 static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv_i64 tmp = tcg_constant_i64(src);
 gen_store8(cpu_env, vaddr, tmp, ctx, slot);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index a78e84faa4..5ea2d54ebe 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -185,7 +185,7 @@
 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 
 #ifdef QEMU_GENERATE
-static inline void gen_pred_cancel(TCGv pred, int slot_num)
+static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
  {
 TCGv slot_mask = tcg_temp_new();
 TCGv tmp = tcg_temp_new();
-- 
2.35.1

[PATCH v9 00/12] target/hexagon: introduce idef-parser

[Anton Johansson via]

This patchset introduces the idef-parser for target/hexagon.

It's the ninth iteration of the patchset and includes fixes suggested in
previous iterations.

`idef-parser` is a build-time tool built using flex and bison. Its aim
is to generate a large part of the tiny code generator frontend for
Hexagon. The prototype of idef-parser has been presented at KVM Forum
2019 ("QEMU-Hexagon: Automatic Translation of the ISA Manual Pseudocode
to Tiny Code Instructions"):

https://www.youtube.com/watch?v=3EpnTYBOXCI

`target/hexagon/idef-parser/README.rst` provides an overview of the
parser and its inner working.

A couple of notes:

* These commits build successfully on the CI (including using clang),
  with one notable exception. Presently, the `build-user-hexagon` job
  fails due to not being able to find `flex`/`bison`. This is due to
  the `debian-hexagon-cross` container not being built by the CI.

  As such the `debian-hexagon-cross` container will have to be manually
  rebuilt before merging.

* `checkpatch.pl` complains about the `_Generic` macro `OUT_IMPL` in
  `idef-parser/parser-helpers.h` which we believe to be correctly
  formatted. The complaints concern the `:` in the type "labels" of the
  macro, and also the `default:` label.

* The eight patch, which introduces `flex`/`bison` as new build pre-
  requisites using `libvirt-ci`, will update `tests/lcitool/libvirt-ci`
  to a new upstream commit which includes these package mappings.

Alessandro Di Federico (4):
  target/hexagon: update MAINTAINERS for idef-parser
  target/hexagon: import README for idef-parser
  target/hexagon: prepare input for the idef-parser
  target/hexagon: call idef-parser functions

Anton Johansson (2):
  target/hexagon: import flex/bison to docker files
  target/hexagon: import parser for idef-parser

Niccolò Izzo (2):
  target/hexagon: introduce new helper functions
  target/hexagon: import additional tests

Paolo Montesel (4):
  target/hexagon: make slot number an unsigned
  target/hexagon: make helper functions non-static
  target/hexagon: expose next PC in DisasContext
  target/hexagon: import lexer for idef-parser

 .gitlab-ci.d/cirrus/freebsd-12.vars   |2 +-
 .gitlab-ci.d/cirrus/freebsd-13.vars   |2 +-
 .gitlab-ci.d/cirrus/macos-11.vars |2 +-
 .gitlab-ci.d/windows.yml  |2 +
 MAINTAINERS   |9 +
 meson_options.txt |3 +
 target/hexagon/README |5 +
 target/hexagon/gen_helper_funcs.py|   17 +-
 target/hexagon/gen_helper_protos.py   |   17 +-
 target/hexagon/gen_idef_parser_funcs.py   |  128 +
 target/hexagon/gen_tcg_funcs.py   |   41 +-
 target/hexagon/genptr.c   |  241 +-
 target/hexagon/genptr.h   |   45 +
 target/hexagon/hex_common.py  |   10 +
 target/hexagon/idef-parser/README.rst |  722 +
 target/hexagon/idef-parser/idef-parser.h  |  253 ++
 target/hexagon/idef-parser/idef-parser.lex|  471 
 target/hexagon/idef-parser/idef-parser.y  |  961 +++
 target/hexagon/idef-parser/macros.inc |  140 +
 target/hexagon/idef-parser/parser-helpers.c   | 2346 +
 target/hexagon/idef-parser/parser-helpers.h   |  372 +++
 target/hexagon/idef-parser/prepare|   24 +
 target/hexagon/macros.h   |   11 +-
 target/hexagon/meson.build|  138 +-
 target/hexagon/op_helper.c|   29 +-
 target/hexagon/op_helper.h|   37 +
 target/hexagon/translate.c|3 +-
 target/hexagon/translate.h|1 +
 tests/docker/dockerfiles/alpine.docker|6 +-
 tests/docker/dockerfiles/centos8.docker   |7 +-
 tests/docker/dockerfiles/debian-amd64.docker  |2 +
 .../dockerfiles/debian-arm64-cross.docker |6 +-
 tests/docker/dockerfiles/debian-native.docker |3 +
 .../dockerfiles/debian-riscv64-cross.docker   |3 +
 .../dockerfiles/debian-s390x-cross.docker |6 +-
 .../dockerfiles/debian-tricore-cross.docker   |1 +
 tests/docker/dockerfiles/debian10.docker  |3 +
 .../dockerfiles/fedora-i386-cross.docker  |3 +
 .../dockerfiles/fedora-win32-cross.docker |3 +
 .../dockerfiles/fedora-win64-cross.docker |3 +
 tests/docker/dockerfiles/fedora.docker|5 +-
 tests/docker/dockerfiles/opensuse-leap.docker |5 +-
 tests/docker/dockerfiles/ubuntu1804.docker|4 +-
 tests/docker/dockerfiles/ubuntu2004.docker|5 +-
 tests/lcitool/libvirt-ci  |2 +-
 tests/lcitool/projects/qemu.yml   |   20 +-
 tests/tcg/hexagon/Makefile.target |   28 +-
 tests/tcg/hexagon/crt.S   |   14 +
 tests/tcg/hexagon/test_abs.S  |   17 +
 tests/tcg/hexagon/test_bitcnt.S   |   40 +
 tes

[PATCH v9 01/12] target/hexagon: update MAINTAINERS for idef-parser

[Anton Johansson via]

From: Alessandro Di Federico 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Anton Johansson 
Reviewed-by: Richard Henderson 
Reviewed-by: Taylor Simpson 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 294c88ace9..d6b62ff319 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -200,6 +200,8 @@ Hexagon TCG CPUs
 M: Taylor Simpson 
 S: Supported
 F: target/hexagon/
+X: target/hexagon/idef-parser/
+X: target/hexagon/gen_idef_parser_funcs.py
 F: linux-user/hexagon/
 F: tests/tcg/hexagon/
 F: disas/hexagon.c
@@ -207,6 +209,13 @@ F: configs/targets/hexagon-linux-user/default.mak
 F: docker/dockerfiles/debian-hexagon-cross.docker
 F: docker/dockerfiles/debian-hexagon-cross.docker.d/build-toolchain.sh
 
+Hexagon idef-parser
+M: Alessandro Di Federico 
+M: Anton Johansson 
+S: Supported
+F: target/hexagon/idef-parser/
+F: target/hexagon/gen_idef_parser_funcs.py
+
 HPPA (PA-RISC) TCG CPUs
 M: Richard Henderson 
 S: Maintained
-- 
2.35.1

[PATCH v9 05/12] target/hexagon: introduce new helper functions

[Anton Johansson via]

From: Niccolò Izzo 

These helpers will be employed by the idef-parser generated code, to
correctly implement instruction semantics. "Helper" functions, in the
context of this patch, refers to functions which provide a manual TCG
implementation of certain features.

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Niccolò Izzo 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/genptr.c | 178 ++--
 target/hexagon/genptr.h |  17 +++-
 target/hexagon/macros.h |   9 ++
 3 files changed, 196 insertions(+), 8 deletions(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 8d1b3f6e2e..036d0cef2e 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -31,6 +31,12 @@
 #include "gen_tcg_hvx.h"
 #include "genptr.h"
 
+TCGv gen_read_reg(TCGv result, int num)
+{
+tcg_gen_mov_tl(result, hex_gpr[num]);
+return result;
+}
+
 TCGv gen_read_preg(TCGv pred, uint8_t num)
 {
 tcg_gen_mov_tl(pred, hex_pred[num]);
@@ -403,18 +409,19 @@ static inline void gen_store_conditional8(DisasContext 
*ctx,
 tcg_gen_movi_tl(hex_llsc_addr, ~0);
 }
 
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long 
width,
+ uint32_t slot)
 {
 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 tcg_gen_movi_tl(hex_store_width[slot], width);
 tcg_gen_mov_tl(hex_store_val32[slot], src);
+ctx->store_width[slot] = width;
 }
 
 void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
 uint32_t slot)
 {
-gen_store32(vaddr, src, 1, slot);
-ctx->store_width[slot] = 1;
+gen_store32(ctx, vaddr, src, 1, slot);
 }
 
 void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -427,8 +434,7 @@ void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, 
DisasContext *ctx,
 void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
 uint32_t slot)
 {
-gen_store32(vaddr, src, 2, slot);
-ctx->store_width[slot] = 2;
+gen_store32(ctx, vaddr, src, 2, slot);
 }
 
 void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -441,8 +447,7 @@ void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, 
DisasContext *ctx,
 void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
 uint32_t slot)
 {
-gen_store32(vaddr, src, 4, slot);
-ctx->store_width[slot] = 4;
+gen_store32(ctx, vaddr, src, 4, slot);
 }
 
 void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -647,5 +652,164 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, 
intptr_t srcoff)
 tcg_temp_free_i64(mask);
 }
 
+void gen_set_usr_field(int field, TCGv val)
+{
+tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
+   val,
+   reg_field_info[field].offset,
+   reg_field_info[field].width);
+}
+
+void gen_set_usr_fieldi(int field, int x)
+{
+TCGv val = tcg_constant_tl(x);
+gen_set_usr_field(field, val);
+}
+
+/*
+ * Note: Since this function might branch, `val` is
+ * required to be a `tcg_temp_local`.
+ */
+void gen_set_usr_field_if(int field, TCGv val)
+{
+/* Sets the USR field if `val` is non-zero */
+if (reg_field_info[field].width == 1) {
+TCGv tmp = tcg_temp_new();
+tcg_gen_extract_tl(tmp, val, 0, reg_field_info[field].width);
+tcg_gen_shli_tl(tmp, tmp, reg_field_info[field].offset);
+tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
+  hex_new_value[HEX_REG_USR],
+  tmp);
+tcg_temp_free(tmp);
+} else {
+TCGLabel *skip_label = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
+gen_set_usr_field(field, val);
+gen_set_label(skip_label);
+}
+}
+
+void gen_write_new_pc(TCGv addr)
+{
+/* If there are multiple branches in a packet, ignore the second one */
+TCGv zero = tcg_constant_tl(0);
+tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero,
+   hex_next_PC, addr);
+tcg_gen_movi_tl(hex_branch_taken, 1);
+}
+
+void gen_sat_i32(TCGv dest, TCGv source, int width)
+{
+TCGv max_val = tcg_constant_tl((1 << (width - 1)) - 1);
+TCGv min_val = tcg_constant_tl(-(1 << (width - 1)));
+tcg_gen_smin_tl(dest, source, max_val);
+tcg_gen_smax_tl(dest, dest, min_val);
+}
+
+void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+gen_sat_i32(dest, source, width);
+tcg_gen_setcond_tl(TCG_COND_NE, ovfl, source, dest);
+}
+
+void gen_satu_i32(TCGv dest, TCGv source, int width)
+{
+TCGv max_val = tcg_constant_tl((1 << width) - 1);
+TCGv zero = tcg_constant_tl(0);
+tcg_gen_movcond_tl(TCG_COND_GTU, dest, source, max_val, max_val, source);
+tcg_gen_movcond_tl(TCG_C

[PATCH v8 63/68] hw/intc: Vectored Interrupt Controller (VIC)

[Richard Henderson]

From: Amir Gonnen 

Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
nios2 cpu and set by the board that connects VIC.

Reviewed-by: Peter Maydell 
Signed-off-by: Amir Gonnen 
Message-Id: <20220303153906.2024748-5-amir.gon...@neuroblade.ai>
[rth: Split out nios2_vic.h]
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-60-richard.hender...@linaro.org>
---
 include/hw/intc/nios2_vic.h |  64 
 hw/intc/nios2_vic.c | 313 
 hw/intc/Kconfig |   3 +
 hw/intc/meson.build |   1 +
 4 files changed, 381 insertions(+)
 create mode 100644 include/hw/intc/nios2_vic.h
 create mode 100644 hw/intc/nios2_vic.c

diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h
new file mode 100644
index 00..af1517a967
--- /dev/null
+++ b/include/hw/intc/nios2_vic.h
@@ -0,0 +1,64 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ * See: 
https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_INTC_NIOS2_VIC
+#define HW_INTC_NIOS2_VIC
+
+#define TYPE_NIOS2_VIC "nios2-vic"
+OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC)
+
+#define NIOS2_VIC_MAX_IRQ 32
+
+struct Nios2VIC {
+/*< private >*/
+SysBusDevice parent_obj;
+
+/*< public >*/
+qemu_irq output_int;
+
+/* properties */
+CPUState *cpu;
+MemoryRegion csr;
+
+uint32_t int_config[NIOS2_VIC_MAX_IRQ];
+uint32_t vic_config;
+uint32_t int_raw_status;
+uint32_t int_enable;
+uint32_t sw_int;
+uint32_t vic_status;
+uint32_t vec_tbl_base;
+uint32_t vec_tbl_addr;
+};
+
+#endif /* HW_INTC_NIOS2_VIC */
diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c
new file mode 100644
index 00..cf63212a88
--- /dev/null
+++ b/hw/intc/nios2_vic.c
@@ -0,0 +1,313 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ * See: 
https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMA

[PATCH v9 02/12] target/hexagon: import README for idef-parser

[Anton Johansson via]

From: Alessandro Di Federico 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/README |   5 +
 target/hexagon/idef-parser/README.rst | 722 ++
 2 files changed, 727 insertions(+)
 create mode 100644 target/hexagon/idef-parser/README.rst

diff --git a/target/hexagon/README b/target/hexagon/README
index 372e24747c..6cb5affddb 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -27,6 +27,10 @@ Hexagon-specific code are
 encode*.def Encoding patterns for each instruction
 iclass.def  Instruction class definitions used to determine
 legal VLIW slots for each instruction
+qemu/target/hexagon/idef-parser
+Parser that, given the high-level definitions of an instruction,
+produces a C function generating equivalent tiny code instructions.
+See README.rst.
 qemu/linux-user/hexagon
 Helpers for loading the ELF file and making Linux system calls,
 signals, etc
@@ -47,6 +51,7 @@ header files in /target/hexagon
 gen_tcg_funcs.py-> tcg_funcs_generated.c.inc
 gen_tcg_func_table.py   -> tcg_func_table_generated.c.inc
 gen_helper_funcs.py -> helper_funcs_generated.c.inc
+gen_idef_parser_funcs.py-> idef_parser_input.h
 
 Qemu helper functions have 3 parts
 DEF_HELPER declaration indicates the signature of the helper
diff --git a/target/hexagon/idef-parser/README.rst 
b/target/hexagon/idef-parser/README.rst
new file mode 100644
index 00..65e6bf4ee5
--- /dev/null
+++ b/target/hexagon/idef-parser/README.rst
@@ -0,0 +1,722 @@
+Hexagon ISA instruction definitions to tinycode generator compiler
+--
+
+idef-parser is a small compiler able to translate the Hexagon ISA description
+language into tinycode generator code, that can be easily integrated into QEMU.
+
+Compilation Example
+---
+
+To better understand the scope of the idef-parser, we'll explore an applicative
+example. Let's start by one of the simplest Hexagon instruction: the ``add``.
+
+The ISA description language represents the ``add`` instruction as
+follows:
+
+.. code:: c
+
+   A2_add(RdV, in RsV, in RtV) {
+   { RdV=RsV+RtV;}
+   }
+
+idef-parser will compile the above code into the following code:
+
+.. code:: c
+
+   /* A2_add */
+   void emit_A2_add(DisasContext *ctx, Insn *insn, Packet *pkt, TCGv_i32 RdV,
+TCGv_i32 RsV, TCGv_i32 RtV)
+   /*  { RdV=RsV+RtV;} */
+   {
+   TCGv_i32 tmp_0 = tcg_temp_new_i32();
+   tcg_gen_add_i32(tmp_0, RsV, RtV);
+   tcg_gen_mov_i32(RdV, tmp_0);
+   tcg_temp_free_i32(tmp_0);
+   }
+
+The output of the compilation process will be a function, containing the
+tinycode generator code, implementing the correct semantics. That function will
+not access any global variable, because all the accessed data structures will 
be
+passed explicitly as function parameters. Among the passed parameters we will
+have TCGv (tinycode variables) representing the input and output registers of
+the architecture, integers representing the immediates that come from the code,
+and other data structures which hold information about the disassemblation
+context (``DisasContext`` struct).
+
+Let's begin by describing the input code. The ``add`` instruction is associated
+with a unique identifier, in this case ``A2_add``, which allows to distinguish
+variants of the same instruction, and expresses the class to which the
+instruction belongs, in this case ``A2`` corresponds to the Hexagon
+``ALU32/ALU`` instruction subclass.
+
+After the instruction identifier, we have a series of parameters that 
represents
+TCG variables that will be passed to the generated function. Parameters marked
+with ``in`` are already initialized, while the others are output parameters.
+
+We will leverage this information to infer several information:
+
+-  Fill in the output function signature with the correct TCGv registers
+-  Fill in the output function signature with the immediate integers
+-  Keep track of which registers, among the declared one, have been
+   initialized
+
+Let's now observe the actual instruction description code, in this case:
+
+.. code:: c
+
+   { RdV=RsV+RtV;}
+
+This code is composed by a subset of the C syntax, and is the result of the
+application of some macro definitions contained in the ``macros.h`` file.
+
+This file is used to reduce the complexity of the input language where complex
+variants of similar constructs can be mapped to a unique primitive, so that the
+idef-parser has to handle a lower number of computation primitives.
+
+As you may notice, the description code modifies the registers which have been
+declared by the declaration statements. In this case all the three registers
+will be declar

Re: [PATCH] qga/vss-win32: enable qga-vss.tlb generation with widl

[Helge Konetzka]

Hello,

a few moments ago I sent a PR to Msys2 to make widl work as expected.

I've prepared a rather simple patch to activate the generation of 
qga-vss.tlb by widl in targets all and qemu-ga, which I will post later on.


Thank you for your patience and your help!

Regards, Helge.


Am 20.04.22 um 14:27 schrieb Marc-André Lureau:

Hi

On Wed, Apr 20, 2022 at 3:17 PM Konstantin Kostiuk > wrote:


Hi Helge,

I checked what happened in MSYS2 and this looks like a bug in the
widl tool.

I looked into the widl source code and think that it detects the
default include path incorrectly.

During build of widl tool the corresponding variable receive
incorrect value:
`BIN_TO_INCLUDEDIR = ../x86_64-w64-mingw32/include` but should be
`BIN_TO_INCLUDEDIR = ../include`. Looks like a package mismatch,
because the `/ming64/x86_64-w64-mingw32` directory exist
but contains only few libs and no any include files.

So I agreed with Marc-André. I think this bug should be fixed in MSYS2.
I think you can report this issue there
https://github.com/msys2/MINGW-packages/issues



Thanks for the investigation and your comment on the msys2 issue: 
https://github.com/msys2/MINGW-packages/issues/11520 



When I checked the build using cross-compilation from Linux,
the widl tool uses proper BIN_TO_INCLUDEDIR.

We should add the rule that qga_vss depends on gen_tlb to get this
error more visible.

Marc-André, what do you think?


yes, that's what I suggested earlier

thanks

Best Regards,
Konstantin Kostiuk.


On Mon, Apr 18, 2022 at 11:15 AM Marc-André Lureau
mailto:marcandre.lur...@gmail.com>> wrote:

Hi Helge

On Sun, Apr 17, 2022 at 6:51 PM Helge Konetzka mailto:h...@zapateado.de>> wrote:

Generation with widl needs to be triggered explicitly and
requires
library and include directories containing referenced *.idl
and *.tlb
as parameters.


Ok, that's different issues, it would help to split the patch.


Signed-off-by: Helge Konetzka mailto:h...@zapateado.de>>
---

For tested Msys2 build all referenced resources reside in
//include.
Msys2 provides its flavours in different / bases.

This patch derives the missing include directory path from
widl path.
Assuming the given widl path is //bin/widl, it
determines /
as base and appends //include as include and library
directories
to widl command. This way the directory is correct for any Msys2
flavour.
It makes sure, only existing directories are appended as
parameter.


I would file a bug to msys2 instead for widl to use the default
include directory. Otherwise, every widl user out there needs to
be adjusted.
(I think it would need a special --with-widl-includedir=DIR,
given how msys2 remaps directory)


---
   qga/vss-win32/meson.build | 11 +--
   1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/qga/vss-win32/meson.build
b/qga/vss-win32/meson.build
index 71c50d0866..51539a582c 100644
--- a/qga/vss-win32/meson.build
+++ b/qga/vss-win32/meson.build
@@ -30,9 +30,16 @@ if midl.found()
                             input: 'qga-vss.idl',
                             output: 'qga-vss.tlb',
                             command: [midl, '@INPUT@',
'/tlb', '@OUTPUT@'])
-else
+elif widl.found()
+  widl_cmd = [widl, '-t', '@INPUT@', '-o', '@OUTPUT@']
+  usr_include =
fs.parent(fs.parent(widl.full_path()))/'include'
+  if fs.is_dir(usr_include)
+    widl_cmd += ['-L', usr_include]
+    widl_cmd += ['-I', usr_include]
+  endif
     gen_tlb = custom_target('gen-tlb',
                             input: 'qga-vss.idl',
                             output: 'qga-vss.tlb',
-                          command: [widl, '-t', '@INPUT@',
'-o',
'@OUTPUT@'])
+                          build_by_default: true,


I would make qga_vss depend on gen_tlb instead (so the tlb is
always built with the dll)

thanks

-- 
Marc-André Lureau




--
Marc-André Lureau

[PATCH v8 58/68] target/nios2: Implement rdprs, wrprs

[Richard Henderson]

Implement these out of line, so that tcg global temps
(aka the architectural registers) are synced back to
tcg storage as required.  This makes sure that we get
the proper results when status.PRS == status.CRS.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-55-richard.hender...@linaro.org>
---
 target/nios2/cpu.h   |  1 +
 target/nios2/helper.h|  2 ++
 target/nios2/op_helper.c | 16 +++
 target/nios2/translate.c | 57 ++--
 4 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index f6efaa79b3..cca821cf80 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -220,6 +220,7 @@ struct ArchCPU {
 
 bool diverr_present;
 bool mmu_present;
+bool eic_present;
 
 uint32_t pid_num_bits;
 uint32_t tlb_num_ways;
diff --git a/target/nios2/helper.h b/target/nios2/helper.h
index 6f5ec60b0d..1648d76ade 100644
--- a/target/nios2/helper.h
+++ b/target/nios2/helper.h
@@ -24,6 +24,8 @@ DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
 
 #if !defined(CONFIG_USER_ONLY)
 DEF_HELPER_3(eret, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_2(rdprs, TCG_CALL_NO_WG, i32, env, i32)
+DEF_HELPER_3(wrprs, void, env, i32, i32)
 DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
 DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
 DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 38a71a1f2d..a3164f5356 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -83,4 +83,20 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, 
uint32_t new_pc)
 env->pc = new_pc;
 cpu_loop_exit(cs);
 }
+
+/*
+ * RDPRS and WRPRS are implemented out of line so that if PRS == CRS,
+ * all of the tcg global temporaries are synced back to ENV.
+ */
+uint32_t helper_rdprs(CPUNios2State *env, uint32_t regno)
+{
+unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS);
+return env->shadow_regs[prs][regno];
+}
+
+void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val)
+{
+unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS);
+env->shadow_regs[prs][regno] = val;
+}
 #endif /* !CONFIG_USER_ONLY */
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 363f2ea3ca..e566175db5 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -130,6 +130,7 @@ typedef struct DisasContext {
 uint32_t  tb_flags;
 TCGv  sink;
 const ControlRegState *cr_state;
+bool  eic_present;
 } DisasContext;
 
 static TCGv cpu_R[NUM_GP_REGS];
@@ -387,6 +388,27 @@ gen_i_math_logic(andhi, andi, 0, imm_shifted)
 gen_i_math_logic(orhi , ori,  1, imm_shifted)
 gen_i_math_logic(xorhi, xori, 1, imm_shifted)
 
+/* rB <- prs.rA + sigma(IMM16) */
+static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags)
+{
+if (!dc->eic_present) {
+t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
+return;
+}
+if (!gen_check_supervisor(dc)) {
+return;
+}
+
+#ifdef CONFIG_USER_ONLY
+g_assert_not_reached();
+#else
+I_TYPE(instr, code);
+TCGv dest = dest_gpr(dc, instr.b);
+gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a));
+tcg_gen_addi_tl(dest, dest, instr.imm16.s);
+#endif
+}
+
 /* Prototype only, defined below */
 static void handle_r_type_instr(DisasContext *dc, uint32_t code,
 uint32_t flags);
@@ -448,7 +470,7 @@ static const Nios2Instruction i_type_instructions[] = {
 INSTRUCTION_FLG(gen_stx, MO_SL),  /* stwio */
 INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU),   /* bltu */
 INSTRUCTION_FLG(gen_ldx, MO_UL),  /* ldwio */
-INSTRUCTION_UNIMPLEMENTED(),  /* rdprs */
+INSTRUCTION(rdprs),   /* rdprs */
 INSTRUCTION_ILLEGAL(),
 INSTRUCTION_FLG(handle_r_type_instr, 0),  /* R-Type */
 INSTRUCTION_NOP(),/* flushd */
@@ -648,6 +670,36 @@ static void wrctl(DisasContext *dc, uint32_t code, 
uint32_t flags)
 #endif
 }
 
+/* prs.rC <- rA */
+static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags)
+{
+if (!dc->eic_present) {
+t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
+return;
+}
+if (!gen_check_supervisor(dc)) {
+return;
+}
+
+#ifdef CONFIG_USER_ONLY
+g_assert_not_reached();
+#else
+R_TYPE(instr, code);
+gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c),
+ load_gpr(dc, instr.a));
+/*
+ * The expected write to PRS[r0] is 0, from CRS[r0].
+ * If not, and CRS == PRS (which we cannot tell from here),
+ * we may now have a non-zero value in our current r0.
+ * By ending the TB, we re-evaluate tb_flags and find out.
+ */
+if (instr.c == 0
+&& (instr.a != 0 || !FIELD_EX3

[PATCH v8 52/68] target/nios2: Create gen_jumpr

[Richard Henderson]

Split out a function to perform an indirect branch.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-49-richard.hender...@linaro.org>
---
 target/nios2/translate.c | 27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index e2742a8556..8616813365 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -36,7 +36,6 @@
 #include "semihosting/semihost.h"
 
 /* is_jmp field values */
-#define DISAS_JUMPDISAS_TARGET_0 /* only pc was modified dynamically */
 #define DISAS_UPDATE  DISAS_TARGET_1 /* cpu state was modified dynamically */
 
 #define INSTRUCTION_FLG(func, flags) { (func), (flags) }
@@ -195,6 +194,16 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t 
dest)
 }
 }
 
+static void gen_jumpr(DisasContext *dc, int regno, bool is_call)
+{
+tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno));
+if (is_call) {
+tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
+}
+tcg_gen_exit_tb(NULL, 0);
+dc->base.is_jmp = DISAS_NORETURN;
+}
+
 static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags)
 {
 t_gen_helper_raise_exception(dc, flags);
@@ -437,8 +446,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t 
flags)
 /* PC <- ra */
 static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
 {
-tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA));
-dc->base.is_jmp = DISAS_JUMP;
+gen_jumpr(dc, R_RA, false);
 }
 
 /*
@@ -468,8 +476,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t 
flags)
 {
 R_TYPE(instr, code);
 
-tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
-dc->base.is_jmp = DISAS_JUMP;
+gen_jumpr(dc, instr.a, false);
 }
 
 /* rC <- PC + 4 */
@@ -488,10 +495,7 @@ static void callr(DisasContext *dc, uint32_t code, 
uint32_t flags)
 {
 R_TYPE(instr, code);
 
-tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
-tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
-
-dc->base.is_jmp = DISAS_JUMP;
+gen_jumpr(dc, instr.a, true);
 }
 
 /* rC <- ctlN */
@@ -909,11 +913,6 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, 
CPUState *cs)
 tcg_gen_exit_tb(NULL, 0);
 break;
 
-case DISAS_JUMP:
-/* The jump will already have updated the PC register */
-tcg_gen_exit_tb(NULL, 0);
-break;
-
 case DISAS_NORETURN:
 /* nothing more to generate */
 break;
-- 
2.34.1

[PATCH v8 66/68] hw/nios2: Machine with a Vectored Interrupt Controller

[Richard Henderson]

From: Amir Gonnen 

Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine property to attach a VIC.

When VIC is present, let the CPU know that it should use the
External Interrupt Interface instead of the Internal Interrupt Interface.
The devices on the machine are attached to the VIC and not directly to cpu.
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.

[rth: Put a property on the 10m50-ghrd machine, rather than
  create a new machine class.]

Reviewed-by: Mark Cave-Ayland 
Signed-off-by: Amir Gonnen 
Message-Id: <20220303153906.2024748-6-amir.gon...@neuroblade.ai>
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-63-richard.hender...@linaro.org>
---
 hw/nios2/10m50_devboard.c | 61 +--
 hw/nios2/Kconfig  |  1 +
 2 files changed, 53 insertions(+), 9 deletions(-)

diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index dda4ab2bf5..91383fb097 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -27,6 +27,7 @@
 
 #include "hw/sysbus.h"
 #include "hw/char/serial.h"
+#include "hw/intc/nios2_vic.h"
 #include "hw/qdev-properties.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
@@ -43,6 +44,8 @@ struct Nios2MachineState {
 MemoryRegion phys_tcm_alias;
 MemoryRegion phys_ram;
 MemoryRegion phys_ram_alias;
+
+bool vic;
 };
 
 #define TYPE_NIOS2_MACHINE  MACHINE_TYPE_NAME("10m50-ghrd")
@@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
 memory_region_add_subregion(address_space_mem, 0xc000 + ram_base,
 &nms->phys_ram_alias);
 
-/* Create CPU -- FIXME */
-cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
-for (i = 0; i < 32; i++) {
-irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+/* Create CPU.  We need to set eic_present between init and realize. */
+cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
+
+/* Enable the External Interrupt Controller within the CPU. */
+cpu->eic_present = nms->vic;
+
+/* Configure new exception vectors. */
+cpu->reset_addr = 0xd400;
+cpu->exception_addr = 0xc8000120;
+cpu->fast_tlb_miss_addr = 0xc100;
+
+qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
+
+if (nms->vic) {
+DeviceState *dev = qdev_new(TYPE_NIOS2_VIC);
+MemoryRegion *dev_mr;
+qemu_irq cpu_irq;
+
+object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), 
&error_fatal);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0);
+sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
+for (int i = 0; i < 32; i++) {
+irq[i] = qdev_get_gpio_in(dev, i);
+}
+
+dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
+} else {
+for (i = 0; i < 32; i++) {
+irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+}
 }
 
 /* Register: Altera 16550 UART */
@@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe880);
 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
 
-/* Configure new exception vectors and reset CPU for it to take effect. */
-cpu->reset_addr = 0xd400;
-cpu->exception_addr = 0xc8000120;
-cpu->fast_tlb_miss_addr = 0xc100;
-
 nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
   BINARY_DEVICE_TREE_FILE, NULL);
 }
 
+static bool get_vic(Object *obj, Error **errp)
+{
+Nios2MachineState *nms = NIOS2_MACHINE(obj);
+return nms->vic;
+}
+
+static void set_vic(Object *obj, bool value, Error **errp)
+{
+Nios2MachineState *nms = NIOS2_MACHINE(obj);
+nms->vic = value;
+}
+
 static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
 {
 MachineClass *mc = MACHINE_CLASS(oc);
@@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *oc, 
void *data)
 mc->desc = "Altera 10M50 GHRD Nios II design";
 mc->init = nios2_10m50_ghrd_init;
 mc->is_default = true;
+
+object_class_property_add_bool(oc, "vic", get_vic, set_vic);
+object_class_property_set_description(oc, "vic",
+"Set on/off to enable/disable the Vectored Interrupt Controller");
 }
 
 static const TypeInfo nios2_10m50_ghrd_type_info = {
diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig
index b10ea640da..4748ae27b6 100644
--- a/hw/nios2/Kconfig
+++ b/hw/nios2/Kconfig
@@ -3,6 +3,7 @@ config NIOS2_10M50
 select NIOS2
 select SERIAL
 select ALTERA_TIMER
+select NIOS2_VIC
 
 config NIOS2_GENERIC_NOMMU
 bool
-- 
2.34.1

[PATCH v9 11/12] target/hexagon: call idef-parser functions

[Anton Johansson via]

From: Alessandro Di Federico 

Extend gen_tcg_funcs.py in order to emit calls to the functions emitted
by the idef-parser, if available. An option is also added to fully
disable the output of the idef-parser, which is useful for debugging
purposes.

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 meson_options.txt   |  3 +
 target/hexagon/gen_helper_funcs.py  | 17 +-
 target/hexagon/gen_helper_protos.py | 17 +-
 target/hexagon/gen_tcg_funcs.py | 41 -
 target/hexagon/hex_common.py| 10 
 target/hexagon/meson.build  | 92 +++--
 6 files changed, 146 insertions(+), 34 deletions(-)

diff --git a/meson_options.txt b/meson_options.txt
index 52b11cead4..ae8f53b1fd 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -270,3 +270,6 @@ option('profiler', type: 'boolean', value: false,
description: 'profiler support')
 option('slirp_smbd', type : 'feature', value : 'auto',
description: 'use smbd (at path --smbd=*) in slirp networking')
+
+option('hexagon_idef_parser_enabled', type : 'boolean', value : true,
+   description: 'Whether idef-parser should be used to automatically 
generate TCG code for the Hexagon frontend')
diff --git a/target/hexagon/gen_helper_funcs.py 
b/target/hexagon/gen_helper_funcs.py
index a446c45384..71d611283a 100755
--- a/target/hexagon/gen_helper_funcs.py
+++ b/target/hexagon/gen_helper_funcs.py
@@ -287,11 +287,24 @@ def main():
 hex_common.read_attribs_file(sys.argv[2])
 hex_common.read_overrides_file(sys.argv[3])
 hex_common.read_overrides_file(sys.argv[4])
+## Whether or not idef-parser is enabled is
+## determined by the number of arguments to
+## this script:
+##
+##   5 args. -> not enabled,
+##   6 args. -> idef-parser enabled.
+##
+## The 6:th arg. then holds a list of the successfully
+## parsed instructions.
+is_idef_parser_enabled = len(sys.argv) > 6
+if is_idef_parser_enabled:
+hex_common.read_idef_parser_enabled_file(sys.argv[5])
 hex_common.calculate_attribs()
 tagregs = hex_common.get_tagregs()
 tagimms = hex_common.get_tagimms()
 
-with open(sys.argv[5], 'w') as f:
+output_file = sys.argv[-1]
+with open(output_file, 'w') as f:
 for tag in hex_common.tags:
 ## Skip the priv instructions
 if ( "A_PRIV" in hex_common.attribdict[tag] ) :
@@ -308,6 +321,8 @@ def main():
 continue
 if ( hex_common.skip_qemu_helper(tag) ):
 continue
+if ( hex_common.is_idef_parser_enabled(tag) ):
+continue
 
 gen_helper_function(f, tag, tagregs, tagimms)
 
diff --git a/target/hexagon/gen_helper_protos.py 
b/target/hexagon/gen_helper_protos.py
index 3b4e993fd1..74eff457a6 100755
--- a/target/hexagon/gen_helper_protos.py
+++ b/target/hexagon/gen_helper_protos.py
@@ -136,11 +136,24 @@ def main():
 hex_common.read_attribs_file(sys.argv[2])
 hex_common.read_overrides_file(sys.argv[3])
 hex_common.read_overrides_file(sys.argv[4])
+## Whether or not idef-parser is enabled is
+## determined by the number of arguments to
+## this script:
+##
+##   5 args. -> not enabled,
+##   6 args. -> idef-parser enabled.
+##
+## The 6:th arg. then holds a list of the successfully
+## parsed instructions.
+is_idef_parser_enabled = len(sys.argv) > 6
+if is_idef_parser_enabled:
+hex_common.read_idef_parser_enabled_file(sys.argv[5])
 hex_common.calculate_attribs()
 tagregs = hex_common.get_tagregs()
 tagimms = hex_common.get_tagimms()
 
-with open(sys.argv[5], 'w') as f:
+output_file = sys.argv[-1]
+with open(output_file, 'w') as f:
 for tag in hex_common.tags:
 ## Skip the priv instructions
 if ( "A_PRIV" in hex_common.attribdict[tag] ) :
@@ -158,6 +171,8 @@ def main():
 
 if ( hex_common.skip_qemu_helper(tag) ):
 continue
+if ( hex_common.is_idef_parser_enabled(tag) ):
+continue
 
 gen_helper_prototype(f, tag, tagregs, tagimms)
 
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 1fd9de95d5..4d12e192a7 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -610,7 +610,29 @@ def gen_tcg_func(f, tag, regs, imms):
 if (hex_common.is_read(regid)):
 genptr_src_read_opn(f,regtype,regid,tag)
 
-if ( hex_common.skip_qemu_helper(tag) ):
+if hex_common.is_idef_parser_enabled(tag):
+declared = []
+## Handle registers
+for regtype,regid,toss,numregs in regs:
+if (hex_common.is_pair(regid)
+or (hex_common.is_single(regid)
+and hex_common.is_old_val(regtype, regid, tag))):
+declared.append("%s%sV" % (regtype, regi

[PATCH v8 51/68] target/nios2: Enable unaligned traps for system mode

[Richard Henderson]

Unaligned traps are optional, but required with an mmu.
Turn them on always, because the fallback behaviour undefined.

Enable alignment checks in the config file.
Unwind the guest pc properly from do_unaligned_access.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-48-richard.hender...@linaro.org>
---
 target/nios2/helper.c | 4 ++--
 configs/targets/nios2-softmmu.mak | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index c5a2dd65b1..2e9fea4a01 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -241,8 +241,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 CPUNios2State *env = &cpu->env;
 
 env->ctrl[CR_BADADDR] = addr;
-env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN);
-helper_raise_exception(env, EXCP_UNALIGN);
+cs->exception_index = EXCP_UNALIGN;
+cpu_loop_exit_restore(cs, retaddr);
 }
 
 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/configs/targets/nios2-softmmu.mak 
b/configs/targets/nios2-softmmu.mak
index 9a372f0717..1e93b54cd1 100644
--- a/configs/targets/nios2-softmmu.mak
+++ b/configs/targets/nios2-softmmu.mak
@@ -1 +1,2 @@
 TARGET_ARCH=nios2
+TARGET_ALIGNED_ONLY=y
-- 
2.34.1

[PATCH v8 68/68] tests/tcg/nios2: Add test-shadow-1

[Richard Henderson]

Add a regression test for tcg indirect global lowering.

This appeared with nios2, with cps != 0, so that we use
indirection into the shadow register set.  An indirect
call verifies alignment of rA.  The use of rA was live
across the brcond leading to a tcg_debug_assert failure.

Cc: Alex Bennée 
Signed-off-by: Richard Henderson 
Reviewed-by: Peter Maydell 
Message-Id: <20220421151735.31996-65-richard.hender...@linaro.org>
---
 tests/tcg/nios2/Makefile.softmmu-target |  1 +
 tests/tcg/nios2/test-shadow-1.S | 40 +
 2 files changed, 41 insertions(+)
 create mode 100644 tests/tcg/nios2/test-shadow-1.S

diff --git a/tests/tcg/nios2/Makefile.softmmu-target 
b/tests/tcg/nios2/Makefile.softmmu-target
index cea27472a6..c3d0594a39 100644
--- a/tests/tcg/nios2/Makefile.softmmu-target
+++ b/tests/tcg/nios2/Makefile.softmmu-target
@@ -30,3 +30,4 @@ QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel
 
 memory: CFLAGS+=-DCHECK_UNALIGNED=0
 TESTS += $(MULTIARCH_TESTS)
+TESTS += test-shadow-1
diff --git a/tests/tcg/nios2/test-shadow-1.S b/tests/tcg/nios2/test-shadow-1.S
new file mode 100644
index 00..79ef69db12
--- /dev/null
+++ b/tests/tcg/nios2/test-shadow-1.S
@@ -0,0 +1,40 @@
+/*
+ * Regression test for TCG indirect global lowering.
+ *
+ * Copyright Linaro Ltd 2022
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "semicall.h"
+
+   .text
+   .set noat
+   .align  2
+   .globl  main
+   .type   main, @function
+
+main:
+   /* Initialize r0 in shadow register set 1. */
+   movhi   at, 1   /* PRS=1, CRS=0, RSIE=0, PIE=0 */
+   wrctl   status, at
+   wrprs   zero, zero
+
+   /* Change current register set to 1. */
+   moviat, 1 << 10 /* PRS=0, CRS=1, RSIE=0, PIE=0 */
+   wrctl   estatus, at
+   movia   ea, 1f
+   eret
+
+   /* Load address for callr, then end TB. */
+1: movia   at, 3f
+   br  2f
+
+   /* Test case! TCG abort on indirect lowering across brcond. */
+2: callr   at
+
+   /* exit(0) */
+3: movir4, HOSTED_EXIT
+   movir5, 0
+   semihosting_call
+
+   .size   main, . - main
-- 
2.34.1

[PATCH v8 64/68] hw/nios2: Introduce Nios2MachineState

[Richard Henderson]

We want to move data from the heap into Nios2MachineState,
which is not possible with DEFINE_MACHINE.

Reviewed-by: Mark Cave-Ayland 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-61-richard.hender...@linaro.org>
---
 hw/nios2/10m50_devboard.c | 24 ++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index 3d1205b8bd..bdc3ffd50d 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -36,6 +36,13 @@
 
 #include "boot.h"
 
+struct Nios2MachineState {
+MachineState parent_obj;
+};
+
+#define TYPE_NIOS2_MACHINE  MACHINE_TYPE_NAME("10m50-ghrd")
+OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE)
+
 #define BINARY_DEVICE_TREE_FILE"10m50-devboard.dtb"
 
 static void nios2_10m50_ghrd_init(MachineState *machine)
@@ -105,11 +112,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
   BINARY_DEVICE_TREE_FILE, NULL);
 }
 
-static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc)
+static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
 {
+MachineClass *mc = MACHINE_CLASS(oc);
+
 mc->desc = "Altera 10M50 GHRD Nios II design";
 mc->init = nios2_10m50_ghrd_init;
 mc->is_default = true;
 }
 
-DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);
+static const TypeInfo nios2_10m50_ghrd_type_info = {
+.name  = TYPE_NIOS2_MACHINE,
+.parent= TYPE_MACHINE,
+.instance_size = sizeof(Nios2MachineState),
+.class_init= nios2_10m50_ghrd_class_init,
+};
+
+static void nios2_10m50_ghrd_type_init(void)
+{
+type_register_static(&nios2_10m50_ghrd_type_info);
+}
+type_init(nios2_10m50_ghrd_type_init);
-- 
2.34.1

[PATCH v8 65/68] hw/nios2: Move memory regions into Nios2Machine

[Richard Henderson]

Convert to contiguous allocation, as much as possible so far.
The two timer objects are not exposed for subobject allocation.

Reviewed-by: Mark Cave-Ayland 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-62-richard.hender...@linaro.org>
---
 hw/nios2/10m50_devboard.c | 30 --
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index bdc3ffd50d..dda4ab2bf5 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -38,6 +38,11 @@
 
 struct Nios2MachineState {
 MachineState parent_obj;
+
+MemoryRegion phys_tcm;
+MemoryRegion phys_tcm_alias;
+MemoryRegion phys_ram;
+MemoryRegion phys_ram_alias;
 };
 
 #define TYPE_NIOS2_MACHINE  MACHINE_TYPE_NAME("10m50-ghrd")
@@ -47,13 +52,10 @@ OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, 
NIOS2_MACHINE)
 
 static void nios2_10m50_ghrd_init(MachineState *machine)
 {
+Nios2MachineState *nms = NIOS2_MACHINE(machine);
 Nios2CPU *cpu;
 DeviceState *dev;
 MemoryRegion *address_space_mem = get_system_memory();
-MemoryRegion *phys_tcm = g_new(MemoryRegion, 1);
-MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1);
-MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
-MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1);
 ram_addr_t tcm_base = 0x0;
 ram_addr_t tcm_size = 0x1000;/* 1 kiB, but QEMU limit is 4 kiB */
 ram_addr_t ram_base = 0x0800;
@@ -62,22 +64,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
 int i;
 
 /* Physical TCM (tb_ram_1k) with alias at 0xc000 */
-memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size,
+memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size,
&error_abort);
-memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias",
- phys_tcm, 0, tcm_size);
-memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm);
+memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias",
+ &nms->phys_tcm, 0, tcm_size);
+memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tcm);
 memory_region_add_subregion(address_space_mem, 0xc000 + tcm_base,
-phys_tcm_alias);
+&nms->phys_tcm_alias);
 
 /* Physical DRAM with alias at 0xc000 */
-memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size,
+memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size,
&error_abort);
-memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias",
- phys_ram, 0, ram_size);
-memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
+memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias",
+ &nms->phys_ram, 0, ram_size);
+memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ram);
 memory_region_add_subregion(address_space_mem, 0xc000 + ram_base,
-phys_ram_alias);
+&nms->phys_ram_alias);
 
 /* Create CPU -- FIXME */
 cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
-- 
2.34.1

[PATCH v8 50/68] target/nios2: Drop CR_STATUS_EH from tb->flags

[Richard Henderson]

There's nothing about EH that affects translation,
so there's no need to include it in tb->flags.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-47-richard.hender...@linaro.org>
---
 target/nios2/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 4d63006ffe..477a661f17 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -272,7 +272,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, 
target_ulong *pc,
 {
 *pc = env->pc;
 *cs_base = 0;
-*flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U);
+*flags = env->ctrl[CR_STATUS] & CR_STATUS_U;
 }
 
 #endif /* NIOS2_CPU_H */
-- 
2.34.1

[PATCH v8 60/68] target/nios2: Implement EIC interrupt processing

[Richard Henderson]

This is the cpu side of the operation.  Register one irq line,
called EIC.  Split out the rather different processing to a
separate function.

Delay initialization of gpio irqs until realize.  We need to
provide a window after init in which the board can set eic_present.

Signed-off-by: Richard Henderson 
Reviewed-by: Peter Maydell 
Message-Id: <20220421151735.31996-57-richard.hender...@linaro.org>
---
 target/nios2/cpu.h|  8 
 target/nios2/cpu.c| 92 +--
 target/nios2/helper.c | 51 +++-
 3 files changed, 129 insertions(+), 22 deletions(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index eb171a33e6..5474b1c404 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -114,6 +114,7 @@ FIELD(CR_STATUS, CRS, 10, 6)
 FIELD(CR_STATUS, PRS, 16, 6)
 FIELD(CR_STATUS, NMI, 22, 1)
 FIELD(CR_STATUS, RSIE, 23, 1)
+FIELD(CR_STATUS, SRS, 31, 1)  /* only in sstatus */
 
 #define CR_STATUS_PIER_CR_STATUS_PIE_MASK
 #define CR_STATUS_U  R_CR_STATUS_U_MASK
@@ -121,6 +122,7 @@ FIELD(CR_STATUS, RSIE, 23, 1)
 #define CR_STATUS_IH R_CR_STATUS_IH_MASK
 #define CR_STATUS_NMIR_CR_STATUS_NMI_MASK
 #define CR_STATUS_RSIE   R_CR_STATUS_RSIE_MASK
+#define CR_STATUS_SRSR_CR_STATUS_SRS_MASK
 
 FIELD(CR_EXCEPTION, CAUSE, 2, 5)
 FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
@@ -234,6 +236,12 @@ struct ArchCPU {
 
 /* Bits within each control register which are reserved or readonly. */
 ControlRegState cr_state[NUM_CR_REGS];
+
+/* External Interrupt Controller Interface */
+uint32_t rha; /* Requested handler address */
+uint32_t ril; /* Requested interrupt level */
+uint32_t rrs; /* Requested register set */
+bool rnmi;/* Requested nonmaskable interrupt */
 };
 
 
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index d043c02fcd..19b2409974 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -63,7 +63,19 @@ static void nios2_cpu_reset(DeviceState *dev)
 }
 
 #ifndef CONFIG_USER_ONLY
-static void nios2_cpu_set_irq(void *opaque, int irq, int level)
+static void eic_set_irq(void *opaque, int irq, int level)
+{
+Nios2CPU *cpu = opaque;
+CPUState *cs = CPU(cpu);
+
+if (level) {
+cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+}
+}
+
+static void iic_set_irq(void *opaque, int irq, int level)
 {
 Nios2CPU *cpu = opaque;
 CPUNios2State *env = &cpu->env;
@@ -87,15 +99,6 @@ static void nios2_cpu_initfn(Object *obj)
 
 #if !defined(CONFIG_USER_ONLY)
 mmu_init(&cpu->env);
-
-/*
- * These interrupt lines model the IIC (internal interrupt
- * controller). QEMU does not currently support the EIC
- * (external interrupt controller) -- if we did it would be
- * a separate device in hw/intc with a custom interface to
- * the CPU, and boards using it would not wire up these IRQ lines.
- */
-qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
 #endif
 }
 
@@ -128,10 +131,18 @@ static void realize_cr_status(CPUState *cs)
 RO_REG(CR_EXCEPTION);
 WR_REG(CR_BADADDR);
 
-/* TODO: These control registers are not present with the EIC. */
-RO_FIELD(CR_STATUS, RSIE);
-WR_REG(CR_IENABLE);
-RO_REG(CR_IPENDING);
+if (cpu->eic_present) {
+WR_FIELD(CR_STATUS, RSIE);
+RO_FIELD(CR_STATUS, NMI);
+WR_FIELD(CR_STATUS, PRS);
+RO_FIELD(CR_STATUS, CRS);
+WR_FIELD(CR_STATUS, IL);
+WR_FIELD(CR_STATUS, IH);
+} else {
+RO_FIELD(CR_STATUS, RSIE);
+WR_REG(CR_IENABLE);
+RO_REG(CR_IPENDING);
+}
 
 if (cpu->mmu_present) {
 WR_FIELD(CR_STATUS, U);
@@ -170,6 +181,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error 
**errp)
 Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
 Error *local_err = NULL;
 
+#ifndef CONFIG_USER_ONLY
+if (cpu->eic_present) {
+qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
+} else {
+qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
+}
+#endif
+
 cpu_exec_realizefn(cs, &local_err);
 if (local_err != NULL) {
 error_propagate(errp, local_err);
@@ -187,17 +206,48 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error 
**errp)
 }
 
 #ifndef CONFIG_USER_ONLY
+static bool eic_take_interrupt(Nios2CPU *cpu)
+{
+CPUNios2State *env = &cpu->env;
+const uint32_t status = env->ctrl[CR_STATUS];
+
+if (cpu->rnmi) {
+return !(status & CR_STATUS_NMI);
+}
+if (!(status & CR_STATUS_PIE)) {
+return false;
+}
+if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) {
+return false;
+}
+if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) {
+return true;
+}
+return status & CR_STATUS_RSIE;
+}
+
+static bool iic_take_interrupt(Nios2CPU *cpu)
+{
+CPUNios2State *env = &cpu->env;
+
+if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) {
+  

[PATCH v8 67/68] tests/tcg/nios2: Add semihosting multiarch tests

[Richard Henderson]

Add runtime supporting the nios2-semi.c interface.
Execute the hello and memory multiarch tests.

Cc: Alex Bennée 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-64-richard.hender...@linaro.org>
---
 tests/tcg/nios2/semicall.h  |  28 +++
 tests/tcg/nios2/10m50-ghrd.ld   |  66 +++
 tests/tcg/nios2/Makefile.softmmu-target |  32 
 tests/tcg/nios2/boot.S  | 218 
 tests/tcg/nios2/intr.S  |  31 
 5 files changed, 375 insertions(+)
 create mode 100644 tests/tcg/nios2/semicall.h
 create mode 100644 tests/tcg/nios2/10m50-ghrd.ld
 create mode 100644 tests/tcg/nios2/Makefile.softmmu-target
 create mode 100644 tests/tcg/nios2/boot.S
 create mode 100644 tests/tcg/nios2/intr.S

diff --git a/tests/tcg/nios2/semicall.h b/tests/tcg/nios2/semicall.h
new file mode 100644
index 00..6ad4978099
--- /dev/null
+++ b/tests/tcg/nios2/semicall.h
@@ -0,0 +1,28 @@
+/*
+ * Nios2 semihosting interface.
+ *
+ * Copyright Linaro Ltd 2022
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef SEMICALL_H
+#define SEMICALL_H
+
+#define HOSTED_EXIT  0
+#define HOSTED_INIT_SIM  1
+#define HOSTED_OPEN  2
+#define HOSTED_CLOSE 3
+#define HOSTED_READ  4
+#define HOSTED_WRITE 5
+#define HOSTED_LSEEK 6
+#define HOSTED_RENAME7
+#define HOSTED_UNLINK8
+#define HOSTED_STAT  9
+#define HOSTED_FSTAT 10
+#define HOSTED_GETTIMEOFDAY  11
+#define HOSTED_ISATTY12
+#define HOSTED_SYSTEM13
+
+#define semihosting_call break 1
+
+#endif /* SEMICALL_H */
diff --git a/tests/tcg/nios2/10m50-ghrd.ld b/tests/tcg/nios2/10m50-ghrd.ld
new file mode 100644
index 00..7db0d59ad7
--- /dev/null
+++ b/tests/tcg/nios2/10m50-ghrd.ld
@@ -0,0 +1,66 @@
+/*
+ * Link script for the Nios2 10m50-ghrd board.
+ *
+ * Copyright Linaro Ltd 2022
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+MEMORY
+{
+  tpf (rx)  : ORIGIN = 0xc000, LENGTH = 1K
+  ram (rwx) : ORIGIN = 0xc800, LENGTH = 128M
+}
+
+PHDRS
+{
+  RAM PT_LOAD;
+}
+
+ENTRY(_start)
+EXTERN(_start)
+EXTERN(_interrupt)
+EXTERN(_fast_tlb_miss)
+
+SECTIONS
+{
+/* Begin at the (hardcoded) _interrupt entry point. */
+.text 0xc8000120 : {
+*(.text.intr)
+*(.text .text.* .gnu.linkonce.t.*)
+} >ram :RAM
+
+.rodata : ALIGN(4) {
+*(.rodata .rodata.* .gnu.linkonce.r.*)
+} > ram :RAM
+
+.eh_frame_hdr : ALIGN (4) {
+KEEP (*(.eh_frame_hdr))
+*(.eh_frame_entry .eh_frame_entry.*)
+} >ram :RAM
+.eh_frame : ALIGN (4) {
+KEEP (*(.eh_frame)) *(.eh_frame.*)
+} >ram :RAM
+
+.data : ALIGN(4) {
+*(.shdata)
+*(.data .data.* .gnu.linkonce.d.*)
+. = ALIGN(4);
+_gp = ABSOLUTE(. + 0x8000);
+*(.got.plt) *(.got)
+*(.lit8)
+*(.lit4)
+*(.sdata .sdata.* .gnu.linkonce.s.*)
+} >ram :RAM
+
+.bss : ALIGN(4) {
+ __bss_start = ABSOLUTE(.);
+*(.sbss .sbss.* .gnu.linkonce.sb.*)
+*(.scommon)
+*(.bss .bss.* .gnu.linkonce.b.*)
+*(COMMON)
+. = ALIGN(4);
+__bss_end = ABSOLUTE(.);
+} >ram :RAM
+
+__stack = ORIGIN(ram) + LENGTH(ram);
+}
diff --git a/tests/tcg/nios2/Makefile.softmmu-target 
b/tests/tcg/nios2/Makefile.softmmu-target
new file mode 100644
index 00..cea27472a6
--- /dev/null
+++ b/tests/tcg/nios2/Makefile.softmmu-target
@@ -0,0 +1,32 @@
+#
+# Nios2 system tests
+#
+# Copyright Linaro Ltd 2022
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+NIOS2_SYSTEM_SRC = $(SRC_PATH)/tests/tcg/nios2
+VPATH += $(NIOS2_SYSTEM_SRC)
+
+# These objects provide the basic boot code and helper functions for all tests
+CRT_OBJS = boot.o intr.o $(MINILIB_OBJS)
+LINK_SCRIPT = $(NIOS2_SYSTEM_SRC)/10m50-ghrd.ld
+
+CFLAGS  += -nostdlib -g -O0 $(MINILIB_INC)
+LDFLAGS += -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(CRT_OBJS) -lgcc
+
+%.o: %.S
+   $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x 
assembler-with-cpp -c $< -o $@, AS, $@)
+
+%.o: %.c
+   $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@, CC, 
$@)
+
+# Build and link the tests
+%: %.o $(LINK_SCRIPT) $(CRT_OBJS)
+   $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ 
$(LDFLAGS), LD, $@)
+
+# FIXME: nios2 semihosting writes to stdout, not a chardev
+QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel
+
+memory: CFLAGS+=-DCHECK_UNALIGNED=0
+TESTS += $(MULTIARCH_TESTS)
diff --git a/tests/tcg/nios2/boot.S b/tests/tcg/nios2/boot.S
new file mode 100644
index 00..f6771cbc81
--- /dev/null
+++ b/tests/tcg/nios2/boot.S
@@ -0,0 +1,218 @@
+/*
+ * Minimal Nios2 system boot code.
+ *
+ * Copyright Linaro Ltd 2022
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "semicall.h"
+
+.text
+   .setnoat
+
+_start:
+   /* Linker script defines stack at end of ram. */
+   movia   sp, __

[PATCH v8 61/68] target/nios2: Advance pc when raising exceptions

[Richard Henderson]

The exception return address for nios2 is the instruction
after the one that was executing at the time of the exception.

We have so far implemented this by advancing the pc during the
process of raising the exception.  It is perhaps a little less
confusing to do this advance in the translator (and helpers)
when raising the exception in the first place, so that we may
more closely match kernel sources.

Signed-off-by: Richard Henderson 
Reviewed-by: Peter Maydell 
Message-Id: <20220421151735.31996-58-richard.hender...@linaro.org>
---
 target/nios2/cpu.h  |  2 ++
 linux-user/nios2/cpu_loop.c |  8 ++--
 target/nios2/helper.c   | 13 +++--
 target/nios2/op_helper.c| 18 --
 target/nios2/translate.c|  6 +++---
 5 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 5474b1c404..f85581ee56 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -266,6 +266,8 @@ hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr 
addr);
 G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
   MMUAccessType access_type, int 
mmu_idx,
   uintptr_t retaddr);
+G_NORETURN void nios2_cpu_loop_exit_advance(CPUNios2State *env,
+uintptr_t retaddr);
 
 void do_nios2_semihosting(CPUNios2State *env);
 
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 30a27f252b..a5e86990e2 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -39,6 +39,8 @@ void cpu_loop(CPUNios2State *env)
 break;
 
 case EXCP_DIV:
+/* Match kernel's handle_diverror_c(). */
+env->pc -= 4;
 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
 break;
 
@@ -49,12 +51,6 @@ void cpu_loop(CPUNios2State *env)
 break;
 
 case EXCP_TRAP:
-/*
- * TODO: This advance should be done in the translator, as
- * hardware produces an advanced pc as part of all exceptions.
- */
-env->pc += 4;
-
 switch (env->error_code) {
 case 0:
 qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index e256d1528e..bb3b09e5a7 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -49,7 +49,7 @@ static void do_exception(Nios2CPU *cpu, uint32_t 
exception_addr,
 cr_es = CR_BSTATUS;
 }
 env->ctrl[cr_es] = old_status;
-env->regs[r_ea] = env->pc + 4;
+env->regs[r_ea] = env->pc;
 
 if (cpu->mmu_present) {
 new_status |= CR_STATUS_EH;
@@ -113,7 +113,7 @@ static void do_eic_irq(Nios2CPU *cpu)
 }
 env->shadow_regs[new_rs][R_SSTATUS] = old_status;
 }
-env->shadow_regs[new_rs][R_EA] = env->pc + 4;
+env->shadow_regs[new_rs][R_EA] = env->pc;
 }
 
 env->ctrl[CR_STATUS] = new_status;
@@ -187,6 +187,8 @@ void nios2_cpu_do_interrupt(CPUState *cs)
 
 switch (cs->exception_index) {
 case EXCP_IRQ:
+/* Note that PC is advanced for interrupts as well. */
+env->pc += 4;
 if (cpu->eic_present) {
 do_eic_irq(cpu);
 } else {
@@ -249,7 +251,6 @@ void nios2_cpu_do_interrupt(CPUState *cs)
 break;
 
 case EXCP_SEMIHOST:
-env->pc += 4;
 do_nios2_semihosting(env);
 break;
 
@@ -291,7 +292,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 
 env->ctrl[CR_BADADDR] = addr;
 cs->exception_index = EXCP_UNALIGN;
-cpu_loop_exit_restore(cs, retaddr);
+nios2_cpu_loop_exit_advance(env, retaddr);
 }
 
 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -330,7 +331,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 cs->exception_index = (access_type == MMU_INST_FETCH
? EXCP_SUPERA_X : EXCP_SUPERA_D);
 env->ctrl[CR_BADADDR] = address;
-cpu_loop_exit_restore(cs, retaddr);
+nios2_cpu_loop_exit_advance(env, retaddr);
 }
 }
 
@@ -367,5 +368,5 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 
 cs->exception_index = excp;
 env->ctrl[CR_BADADDR] = address;
-cpu_loop_exit_restore(cs, retaddr);
+nios2_cpu_loop_exit_advance(env, retaddr);
 }
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 94040102f4..2e30d0a908 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -31,6 +31,20 @@ void helper_raise_exception(CPUNios2State *env, uint32_t 
index)
 cpu_loop_exit(cs);
 }
 
+void nios2_cpu_loop_exit_advance(CPUNios2State *env, uintptr_t retaddr)
+{
+CPUState *cs = env_cpu(env);
+
+/*
+ * Note that PC is advanced for all hardware exceptions.
+ * D

[PATCH v8 49/68] target/nios2: Introduce dest_gpr

[Richard Henderson]

Constrain all references to cpu_R[] to load_gpr and dest_gpr.
This will be required for supporting shadow register sets.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-46-richard.hender...@linaro.org>
---
 target/nios2/translate.c | 144 +--
 1 file changed, 49 insertions(+), 95 deletions(-)

diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index f2dcaa3fbb..e2742a8556 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -128,6 +128,7 @@ typedef struct DisasContext {
 DisasContextBase  base;
 target_ulong  pc;
 int   mem_idx;
+TCGv  sink;
 const ControlRegState *cr_state;
 } DisasContext;
 
@@ -160,6 +161,18 @@ static TCGv load_gpr(DisasContext *dc, unsigned reg)
 return cpu_R[reg];
 }
 
+static TCGv dest_gpr(DisasContext *dc, unsigned reg)
+{
+assert(reg < NUM_GP_REGS);
+if (unlikely(reg == R_ZERO)) {
+if (dc->sink == NULL) {
+dc->sink = tcg_temp_new();
+}
+return dc->sink;
+}
+return cpu_R[reg];
+}
+
 static void t_gen_helper_raise_exception(DisasContext *dc,
  uint32_t index)
 {
@@ -218,7 +231,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t 
flags)
 
 static void call(DisasContext *dc, uint32_t code, uint32_t flags)
 {
-tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
+tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
 jmpi(dc, code, flags);
 }
 
@@ -231,27 +244,10 @@ static void gen_ldx(DisasContext *dc, uint32_t code, 
uint32_t flags)
 I_TYPE(instr, code);
 
 TCGv addr = tcg_temp_new();
-TCGv data;
-
-/*
- * WARNING: Loads into R_ZERO are ignored, but we must generate the
- *  memory access itself to emulate the CPU precisely. Load
- *  from a protected page to R_ZERO will cause SIGSEGV on
- *  the Nios2 CPU.
- */
-if (likely(instr.b != R_ZERO)) {
-data = cpu_R[instr.b];
-} else {
-data = tcg_temp_new();
-}
+TCGv data = dest_gpr(dc, instr.b);
 
 tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
 tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
-
-if (unlikely(instr.b == R_ZERO)) {
-tcg_temp_free(data);
-}
-
 tcg_temp_free(addr);
 }
 
@@ -281,7 +277,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, 
uint32_t flags)
 I_TYPE(instr, code);
 
 TCGLabel *l1 = gen_new_label();
-tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1);
+tcg_gen_brcond_tl(flags, load_gpr(dc, instr.a), load_gpr(dc, instr.b), l1);
 gen_goto_tb(dc, 0, dc->base.pc_next);
 gen_set_label(l1);
 gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4));
@@ -293,11 +289,8 @@ static void do_i_cmpxx(DisasContext *dc, uint32_t insn,
TCGCond cond, ImmFromIType *imm)
 {
 I_TYPE(instr, insn);
-
-if (likely(instr.b != R_ZERO)) {
-tcg_gen_setcondi_tl(cond, cpu_R[instr.b],
-load_gpr(dc, instr.a), imm(&instr));
-}
+tcg_gen_setcondi_tl(cond, dest_gpr(dc, instr.b),
+load_gpr(dc, instr.a), imm(&instr));
 }
 
 #define gen_i_cmpxx(fname, imm) \
@@ -324,9 +317,9 @@ static void do_i_math_logic(DisasContext *dc, uint32_t insn,
 
 if (instr.a == R_ZERO) {
 /* This catches the canonical expansions of movi and movhi. */
-tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0);
+tcg_gen_movi_tl(dest_gpr(dc, instr.b), x_op_0_eq_x ? val : 0);
 } else {
-fn(cpu_R[instr.b], cpu_R[instr.a], val);
+fn(dest_gpr(dc, instr.b), load_gpr(dc, instr.a), val);
 }
 }
 
@@ -434,7 +427,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t 
flags)
 #else
 TCGv tmp = tcg_temp_new();
 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
-gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
+gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
 tcg_temp_free(tmp);
 
 dc->base.is_jmp = DISAS_NORETURN;
@@ -444,8 +437,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t 
flags)
 /* PC <- ra */
 static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
 {
-tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]);
-
+tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA));
 dc->base.is_jmp = DISAS_JUMP;
 }
 
@@ -464,7 +456,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t 
flags)
 #else
 TCGv tmp = tcg_temp_new();
 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
-gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
+gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA));
 tcg_temp_free(tmp);
 
 dc->base.is_jmp = DISAS_NORETURN;
@@ -477,7 +469,6 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t 
flags)
 R_TYPE(instr, code);
 

[PATCH v8 62/68] linux-user/nios2: Handle various SIGILL exceptions

[Richard Henderson]

We missed out on a couple of exception types that may
legitimately be raised by a userland program.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
Message-Id: <20220421151735.31996-59-richard.hender...@linaro.org>
---
 linux-user/nios2/cpu_loop.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index a5e86990e2..da77ede76b 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -50,6 +50,18 @@ void cpu_loop(CPUNios2State *env)
 env->ctrl[CR_BADADDR]);
 break;
 
+case EXCP_ILLEGAL:
+case EXCP_UNIMPL:
+/* Match kernel's handle_illegal_c(). */
+env->pc -= 4;
+force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc);
+break;
+case EXCP_SUPERI:
+/* Match kernel's handle_supervisor_instr(). */
+env->pc -= 4;
+force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc);
+break;
+
 case EXCP_TRAP:
 switch (env->error_code) {
 case 0:
-- 
2.34.1