On May 6 08:36, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Pass the right constant to nvme_smart_event(). The NVME_AER* values hold
> the bit position in the SMART byte, not the shifted value that we expect
> it to be in nvme_smart_event().
>
> Fixes: c62720f137df ("hw/block/nvme: trigger
在 2022/5/11 16:55, Jason Wang 写道:
On Wed, May 11, 2022 at 2:10 PM Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
在 2022/5/11 10:56, Jason Wang 写道:
On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
From: Longpeng
Supports vdpa-dev.
Signed-off-by: Longpeng
Hello Iris,
[ Fixing Thomas email ]
On 5/12/22 02:54, Iris Chen via wrote:
The write_enable latch property is not currently exposed.
This commit makes it a modifiable property using get/set methods.
Signed-off-by: Iris Chen
---
Ran ./scripts/checkpatch.pl on the patch and added a
On Tue, May 10, 2022 at 3:02 AM Atish Patra wrote:
>
> Historically, The mtimer/mtimecmp has been part of the CPU because
s/mtimer/mtime
> they are per hart entities. However, they actually belong to aclint
> which is a MMIO device.
>
> Move them to the ACLINT device. This also emulates the
On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote:
>
> vstimecmp CSR allows the guest OS or to program the next guest timer
> interrupt directly. Thus, hypervisor no longer need to inject the
> timer interrupt to the guest if vstimecmp is used. This was ratified
> as a part of the Sstc extension.
On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote:
>
> stimecmp allows the supervisor mode to update stimecmp CSR directly
> to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra
> ---
> target/riscv/cpu.c
On Thu, May 12, 2022 at 3:44 AM Eugenio Perez Martin
wrote:
>
> This is a proposal to restore the state of the vhost-vdpa device at
> the destination after a live migration. It uses as many available
> features both from the device and from qemu as possible so we keep the
> communication simple
Add docs/system/i386/tdx.rst for TDX support, and add tdx in
confidential-guest-support.rst
Signed-off-by: Xiaoyao Li
---
docs/system/confidential-guest-support.rst | 1 +
docs/system/i386/tdx.rst | 103 +
docs/system/target-i386.rst| 1
KVM doesn't allow wirting to MSR_IA32_APICBASE for TDs.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 9c5bf075b542..4d520d0e34bd 100644
--- a/target/i386/kvm/kvm.c
+++
TDX CPU state is protected and thus vcpu state cann't be reset by VMM.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index c51125ab200f..9a1e1dab938f 100644
---
For TDs, only MSR_IA32_UCODE_REV in kvm_init_msrs() can be configured
by VMM, while the features enumerated/controlled by other MSRs except
MSR_IA32_UCODE_REV in kvm_init_msrs() are not under control of VMM.
Only configure MSR_IA32_UCODE_REV for TDs.
Signed-off-by: Xiaoyao Li
---
From: Isaku Yamahata
TSC of TDs is not accessible and KVM doesn't allow access of
MSR_IA32_TSC for TDs. To avoid the assert() in kvm_get_tsc, make
kvm_synchronize_all_tsc() noop for TDs,
Signed-off-by: Isaku Yamahata
Reviewed-by: Connor Kuehl
Signed-off-by: Xiaoyao Li
---
Legacy PIC (8259) cannot be supported for TDX VMs since TDX module
doesn't allow directly interrupt injection. Using posted interrupts
for the PIC is not a viable option as the guest BIOS/kernel will not
do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
Hence disable PIC for TDX VMs and
From: Isaku Yamahata
TDVF firmware (CODE and VARS) needs to be added/copied to TD's private
memory via KVM_TDX_INIT_MEM_REGION, as well as TD HOB and TEMP memory.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 24
1 file changed,
From: Isaku Yamahata
When level trigger isn't supported on x86 platform,
forcibly report edge trigger in acpi tables.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
hw/i386/acpi-build.c | 99 ---
hw/i386/acpi-common.c | 50
The TD HOB list is used to pass the information from VMM to TDVF. The TD
HOB must include PHIT HOB and Resource Descriptor HOB. More details can
be found in TDVF specification and PI specification.
Build the TD HOB in TDX's machine_init_done callback.
Co-developed-by: Isaku Yamahata
From: Sean Christopherson
Don't get/put state of TDX VMs since accessing/mutating guest state of
production TDs is not supported.
Note, it will be allowed for a debug TD. Corresponding support will be
introduced when debug TD support is implemented in the future.
Signed-off-by: Sean
Add a new bool member, eoi_intercept_unsupported, to X86MachineState
with default value false. Set true for TDX VM.
Inability to intercept eoi causes impossibility to emulate level
triggered interrupt to be re-injected when level is still kept active.
which affects interrupt controller emulation.
For each TDVF sections, QEMU needs to copy the content to guest
private memory via KVM API (KVM_TDX_INIT_MEM_REGION).
Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory
pointer of each TDVF sections. So that QEMU can add/copy them to guest
private memory later.
TDVF sections can
Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index
The RAM of TDX VM can be classified into two types:
- TDX_RAM_UNACCEPTED: default type of TDX memory, which needs to be
accepted by TDX guest before it can be used and will be all-zeros
after being accepted.
- TDX_RAM_ADDED: the RAM that is ADD'ed to TD guest before running, and
can
TDX doesn't support SMM and VMM cannot emulate SMM for TDX VMs because
VMM cannot manipulate TDX VM's memory.
Disable SMM for TDX VMs and error out if user requests to enable SMM.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 8
1 file changed, 8 insertions(+)
diff --git
Validate TD attributes with tdx_caps that fixed-0 bits must be zero and
fixed-1 bits must be set.
Besides, sanity check the attribute bits that have not been supported by
QEMU yet. e.g., debug bit, it will be allowed in the future when debug
TD support lands in QEMU.
Signed-off-by: Xiaoyao Li
TDX cannot support pflash device since it doesn't support read-only
memslot and doesn't support emulation. Load TDVF(OVMF) with -bios option
for TDs.
When boot a TD, besides load TDVF to the address below 4G, it needs
parse TDVF metadata.
Signed-off-by: Xiaoyao Li
---
hw/i386/pc_sysfw.c
Before a TD can run, it needs to
- setup/configure TD HOB list;
- initialize TDVF into TD's private memory;
- initialize TD vcpu state;
Register a machine_init_done callback to all those stuff.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 12
1 file changed, 12
TDX vcpu needs to be initialized by SEAMCALL(TDH.VP.INIT) and KVM
provides vcpu level IOCTL KVM_TDX_INIT_VCPU for it.
KVM_TDX_INIT_VCPU needs the address of the HOB as input. Invoke it for
each vcpu after HOB list is created.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 18
Invoke KVM_TDX_INIT in kvm_arch_pre_create_vcpu() that KVM_TDX_INIT
configures global TD state, e.g. the canonical CPUID config, and must
be executed prior to creating vCPUs.
Use kvm_x86_arch_cpuid() to setup the CPUID settings for TDX VM and
tie x86cpu->enable_pmu with TD's attributes.
Note,
TDX guest cannot go to real mode, so just skip the setup of isa-bios.
Signed-off-by: Xiaoyao Li
---
hw/i386/x86.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index fdf6af2f6add..17f2252296c5 100644
---
From: Isaku Yamahata
TDX VM needs to boot with its specialized firmware, Trusted Domain
Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD
guest memory prior to running the TDX VM.
A TDVF Metadata in TDVF image describes the structure of firmware.
QEMU refers to it to setup
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c | 12
include/sysemu/kvm.h | 1 +
2 files changed, 13
For TDX, the allowable CPUID configuration differs from what KVM
reports for KVM scope via KVM_GET_SUPPORTED_CPUID.
- Some CPUID bits are not supported for TDX VM while KVM reports the
support. Mask them off for TDX VM. e.g., CPUID_EXT_VMX, some PV
features.
- The supported XCR0 and XSS bits
Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and pass it
to KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by TDX module).
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 8
target/i386/kvm/tdx.c
TDX only supports readonly for shared memory but not for private memory.
In the view of QEMU, it has no idea whether a memslot is used as shared
memory of private. Thus just mark kvm_readonly_mem_enabled to false to
TDX VM for simplicity.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 9
Introduce tdx_kvm_init() and invoke it in kvm_confidential_guest_init()
if it's a TDX VM. More initialization will be added later.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 15 ++-
target/i386/kvm/meson.build | 2 +-
target/i386/kvm/tdx-stub.c | 9 +
For QEMU VMs, PKS is configured via CPUID_7_0_ECX_PKS and PMU is
configured by x86cpu->enable_pmu. Reuse the existing configuration
interface for TDX VMs.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 14 ++
1 file changed, 14 insertions(+)
diff --git
KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's setting later.
Besides, introduce the interfaces to invoke TDX "ioctls" at different
scope (KVM, VM and VCPU)
TDX VM requires VM type KVM_X86_TDX_VM to be passed to
kvm_ioctl(KVM_CREATE_VM). Hence implement mc->kvm_type() for i386
architecture.
If tdx-guest object is specified to confidential-guest-support, like,
qemu -machine ...,confidential-guest-support=tdx0 \
-object tdx-guest,id=tdx0,...
From: Sean Christopherson
Move the architectural (for lack of a better term) CPUID leaf generation
to a separate helper so that the generation code can be reused by TDX,
which needs to generate a canonical VM-scoped configuration.
Signed-off-by: Sean Christopherson
Signed-off-by: Xiaoyao Li
For TDX, the address below 1MB are entirely general RAM. No need to
initialize pc.rom memory region for TDs.
Signed-off-by: Xiaoyao Li
---
hw/i386/pc.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index
Introduce a separate function kvm_confidential_guest_init() for SEV (and
future TDX).
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 11 ++-
target/i386/sev.c | 1 -
target/i386/sev.h | 2 ++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git
Pull in recent TDX updates, which are not backwards compatible.
It's just to make this series runnable. It will be updated by script
scripts/update-linux-headers.sh
once TDX support is upstreamed in linux kernel.
Signed-off-by: Xiaoyao Li
Co-developed-by: Sean Christopherson
This is the v4 RFC, I would like to get feedback on whether the design
in this series is the good direction to enable TDX on QEMU.
This patch series aims to enable TDX support to allow creating and booting a
TD (TDX VM) with QEMU. It needs to work with corresponding v6 KVM patch
for TDX [1]. You
It will need special handling for TDX VMs all around the QEMU.
Introduce is_tdx_vm() helper to query if it's a TDX VM.
Cache tdx_guest object thus no need to cast from ms->cgs every time.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 13 +
target/i386/kvm/tdx.h | 10
Introduce tdx-guest object which implements the interface of
CONFIDENTIAL_GUEST_SUPPORT, and will be used to create TDX VMs (TDs) by
qemu -machine ...,confidential-guest-support=tdx0 \
-object tdx-guset,id=tdx0
It has only one property 'attributes' with fixed value 0 and not
On 5/12/22 06:42, Daniel Henrique Barboza wrote:
On 5/6/22 02:51, Alexey Kardashevskiy wrote:
The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.
Signed-off-by: Alexey Kardashevskiy
---
docs/system/ppc/pseries.rst | 28
在 2022/3/7 下午3:10, ~eopxd 写道:
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last
On 5/11/22 15:34, Stafford Horne wrote:
In this case I don't see how the tb->flag would be updated, ooh, I guess it
would have been set earlier when the TB was generated. Maybe that is what I am
missing.
Correct, it should be unchanged (and correct) from generation.
r~
在 2022/5/11 22:14, Richard Henderson 写道:
> On 5/11/22 02:54, yangxiaojuan wrote:
>>
>> On 2022/5/10 上午1:56, Richard Henderson wrote:
>>>
>> + case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
>> + index = (offset - EXTIOI_IPMAP_START) >> 2;
>> + s->ipmap[index] =
> On May 11, 2022, at 6:38 PM, Peter Delevoryas wrote:
>
>
>
>> On May 11, 2022, at 5:54 PM, Iris Chen wrote:
>>
>> The write_enable latch property is not currently exposed.
>> This commit makes it a modifiable property using get/set methods.
>>
>> Signed-off-by: Iris Chen
>> ---
>> Ran
> On May 11, 2022, at 5:54 PM, Iris Chen wrote:
>
> The write_enable latch property is not currently exposed.
> This commit makes it a modifiable property using get/set methods.
>
> Signed-off-by: Iris Chen
> ---
> Ran ./scripts/checkpatch.pl on the patch and added a description. Fixed
>
Add a new 'guest-get-diskstats' command for report disk io statistics
for Linux guests. This can be usefull for getting io flow or handling
IO fault, no need to enter guests.
Signed-off-by: luzhipeng
---
qga/commands-posix.c | 94
The write_enable latch property is not currently exposed.
This commit makes it a modifiable property using get/set methods.
Signed-off-by: Iris Chen
---
Ran ./scripts/checkpatch.pl on the patch and added a description. Fixed
comments regarding DEFINE_PROP_BOOL.
hw/block/m25p80.c |
According to the NBD spec, a server that advertises
NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
not see any cache inconsistencies: when properly separated by a single
flush, actions performed by one client will be visible to another
client, regardless of which client did
The next patch wants to adjust whether the NBD server code advertises
MULTI_CONN based on whether it is known if the server limits to
exactly one client. For a server started by QMP, this information is
obtained through nbd_server_start (which can support more than one
export); but for qemu-nbd
v3 was here:
https://lists.gnu.org/archive/html/qemu-devel/2022-03/msg03701.html
with additional review here:
https://lists.gnu.org/archive/html/qemu-devel/2022-05/msg00166.html
Since then:
- patch 1 of v3 applied independently
- patch 3 simplified with beefed up commit message (now
Convert the variable names of some registers to human-readable and
understandable names.
Signed-off-by: Helge Deller
---
hw/display/artist.c | 72 ++---
1 file changed, 49 insertions(+), 23 deletions(-)
diff --git a/hw/display/artist.c
The misc_video and misc_ctrl registers control the visibility of the
screen. Start with the screen turned on, and hide or show the screen
based on the control registers.
Signed-off-by: Helge Deller
---
hw/display/artist.c | 30 ++
1 file changed, 30 insertions(+)
Drop the hard-coded value of 1146 lines which seems to work with HP-UX
11, but not with HP-UX 10. Instead encode the screen height in byte 0 of
active_lines_low and byte 3 of misc_video as it's expected by the Xorg
X11 graphics driver.
This potentially allows for higher vertical screen
This series adds additional HP fonts to the SeaBIOS-hppa firmware.
And in the qemu artist graphics driver it:
- fixes the vertical postioning of the X11 cursor with HP-UX
- allows X11 to blank the screen (e.g. screensaver)
- allows the X11 driver to turn the X11 cursor on/off
Signed-off-by:
Bit 0x80 in the cursor_cntrl register specifies if the cursor
should be visible. Prevent rendering the cursor if it's invisible.
Signed-off-by: Helge Deller
---
hw/display/artist.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/display/artist.c b/hw/display/artist.c
Add the constant NGLE_MAX_SPRITE_SIZE which defines the currently
maximum supported cursor size.
Signed-off-by: Helge Deller
---
hw/display/artist.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/display/artist.c b/hw/display/artist.c
index
On Wed, May 11, 2022 at 02:56:37PM -0700, Richard Henderson wrote:
> On 5/11/22 14:43, Stafford Horne wrote:
> > At this point how would tb->flags have the right value? Would it always be
> > set
> > correctly by `cpu_get_tb_cpu_state` in the `lookup_tb_ptr`call?
>
> Well, it would be set by
Hi Stefan, Nicolas,
On Mon, May 9, 2022 at 3:14 PM Stefan Hajnoczi wrote:
>
> The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
>
> Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
> staging (2022-05-08 17:03:26 -0500)
>
> are available in
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
From: Atish Patra
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension.
From: Atish Patra
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Atish Patra
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h |
From: Atish Patra
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair
From: Atish Patra
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 90 ++
1 file changed, 60 insertions(+), 30 deletions(-)
diff --git a/target/riscv/csr.c
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Reviewed-by: Bin Meng
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode
On 5/11/22 14:43, Stafford Horne wrote:
At this point how would tb->flags have the right value? Would it always be set
correctly by `cpu_get_tb_cpu_state` in the `lookup_tb_ptr`call?
Well, it would be set by cpu_get_tb_cpu_state in cpu_exec, which is then passed to
tb_gen_code. If we go
On Wed, May 11, 2022 at 07:32:58AM -0700, Richard Henderson wrote:
> On 5/11/22 05:05, Stafford Horne wrote:
> > +static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
> > + const TranslationBlock *tb)
> > +{
> > +OpenRISCCPU *cpu =
On 5/11/22 07:59, Markus Armbruster wrote:
The following changes since commit 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2022-05-09 11:07:04 -0700)
are available in the Git repository at:
From: Marcin Nowakowski
bit 31 (M) of WatchHiN register is a read-only register indicating
whether the next WatchHi register is present. It must not be reset
during user writes to the register.
Signed-off-by: Marcin Nowakowski
Reviewed-by: David Daney
Signed-off-by: Philippe Mathieu-Daudé
On Wed, May 11, 2022 at 04:59:21PM +0200, Markus Armbruster wrote:
> We commonly define the header guard symbol without an explicit value.
> Normalize the exceptions.
>
> Done with scripts/clean-header-guards.pl.
>
> Signed-off-by: Markus Armbruster
> Message-Id:
Hello Iris,
You need to add a description to the patch, may be use what you wrote
in the cover letter to start with, and a Signed-off-by tag.
Before sending, please run :
$ ./scripts/checkpatch.pl
and
$ ./scripts/get_maintainer.pl
to know who to send to.
The long story is here :
On 5/6/22 02:51, Alexey Kardashevskiy wrote:
The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.
Signed-off-by: Alexey Kardashevskiy
---
docs/system/ppc/pseries.rst | 28
1 file changed, 28
> On May 11, 2022, at 11:45 AM, Iris Chen via wrote:
>
> ---
> hw/block/m25p80.c | 30 ++
> tests/qtest/aspeed_smc-test.c | 20
> 2 files changed, 50 insertions(+)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index
Hey everyone,
My patch adds the get/set property for the write_enable latch. Currently, it is
not an exposed property but this change adds QOM visibility and makes this
property modifiable.
Acceptance tests have also been added to verify the value in the status
register (after the value is
---
hw/block/m25p80.c | 30 ++
tests/qtest/aspeed_smc-test.c | 20
2 files changed, 50 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 430d1298a8..fb72704e5a 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
---
hw/block/m25p80.c | 30 ++
tests/qtest/aspeed_smc-test.c | 20
2 files changed, 50 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 430d1298a8..fb72704e5a 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
Hey everyone,
My patch adds the get/set property for the write_enable latch. Currently, it is
not an exposed property but this change adds QOM visibility and makes this
property modifiable.
Acceptance tests have also been added to verify the value in the status
register (after the value is
This is a proposal to restore the state of the vhost-vdpa device at
the destination after a live migration. It uses as many available
features both from the device and from qemu as possible so we keep the
communication simple and speed up the merging process.
# Initializing a vhost-vdpa device.
Paolo Bonzini writes:
> Signed-off-by: Paolo Bonzini
> ---
> softmmu/vl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/softmmu/vl.c b/softmmu/vl.c
> index c2919579fd..fbef0f5c5f 100644
> --- a/softmmu/vl.c
> +++ b/softmmu/vl.c
> @@ -3723,7 +3723,7 @@ void
On 5/10/22 04:57, Mark Cave-Ayland wrote:
On 09/05/2022 23:30, Daniel Henrique Barboza wrote:
On 5/9/22 18:17, Mark Cave-Ayland wrote:
On 07/05/2022 20:06, Daniel Henrique Barboza wrote:
Hi,
Since the 7.0.0 release cycle we have a desire to use the powernv
emulation with libvirt. To do
Hello!
Thanks everyone for your kind reviews
On 11/05/2022 07:12, Rashmica Gupta wrote:
Hello,
cc'ing Paul and Nick for clarification on the behaviour of xsrsp (see below)
On Tue, 2022-05-10 at 17:46 -0300, Víctor Colombo wrote:
The FI bit in FPSCR is said to be a non-sticky bit on Power
On 5/7/22 02:48, Paolo Bonzini wrote:
-machine graphics=off is the usual way to tell the firmware or the OS that the
user wants a serial console. The pseries machine however does not support
this, and never adds the stdout-path node to the device tree if a VGA device
is provided. This is in
The "-display sdl" option still uses a hand-crafted parser for its
parameters since some of them used underscores which is forbidden
in QAPI. Now that the problematic parameters have been removed, we can
switch to use the QAPI parser instead.
This introduces the new "DisplaySDL" QAPI struct that
The "-display sdl" option still uses a hand-crafted parser for its
parameters since some of them used underscores which is forbidden
in QAPI. Now that they've been deprecated and the deprecation period
is over, we can remove the problematic parameters and switch to use
the QAPI parser instead.
We have "-sdl" and "-curses", but no "-gtk" and no "-cocoa" ...
these old-style options are rather confusing than helpful nowadays.
Now that the deprecation period is over, let's remove them, so we
get a cleaner interface (where "-display" is the only way to select
the user interface).
Signed-off-by: Paolo Bonzini
---
softmmu/vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/softmmu/vl.c b/softmmu/vl.c
index c2919579fd..fbef0f5c5f 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -3723,7 +3723,7 @@ void qemu_init(int argc, char **argv, char **envp)
These parameters are in the way for further refactoring (since they
use an underscore in the name which is forbidden in QAPI), so let's
remove these now that their deprecation period is over.
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 16 -
Alexey Kardashevskiy writes:
> On 06/05/2022 01:50, Fabiano Rosas wrote:
>> Alexey Kardashevskiy writes:
>>
>>> On 5/5/22 05:16, Fabiano Rosas wrote:
Alexey Kardashevskiy writes:
> tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on.
>
> QEMU loads the
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 18 ++
1 file changed, 18 insertions(+)
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