[PATCH v2 4/5] target/riscv: FP extension requirements

QEMU allowed inconsistent configurations that made floating point arithmetic effectively unusable. This commit adds certain checks for consistent FP arithmetic: - F requires Zicsr - Zfinx requires Zicsr - Zfh/Zfhmin require F - D requires F - V requires D Because F/D/Zicsr are enabled

[PATCH v2 3/5] target/riscv: Change "G" expansion

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to be (virtually) enabled as well, it should be safe to change its expansion. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 7 +-- 1 file

[PATCH v2 2/5] target/riscv: Disable "G" by default

Because "G" virtual extension expands to "IMAFD", we cannot separately disable extensions like "F" or "D" without disabling "G". Because all "IMAFD" are enabled by default, it's harmless to disable "G" by default. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 2 +- 1 file changed, 1

[PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks

We should separate "check" and "configure" steps as possible. This commit separates both steps except vector/Zfinx-related checks. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 31 --- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git

[PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion

Because ext_? members are boolean variables, operator `&&' should be used instead of `&'. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..00bf26ec8b 100644 ---

[PATCH v2 0/5] target/riscv: Enhanced ISA extension checks

c.f. I was obviously drunk when finalizing PATCH v1. [BUGS in PATCH v1 (fixed in v2)] PATCH 1: My English was (or, "is"?) broken (commit subject and message is rewritten) PATCH 4: Zfinx requirement test were in the

[PULL 4/4] target/openrisc: Do not reset delay slot flag on early tb exit

This was found when running linux crypto algorithm selftests used by wireguard. We found that randomly the tests would fail. We found through investigation that a combination of a tick timer interrupt, raised when executing a delay slot instruction at a page boundary caused the issue. This was

[PULL 2/4] hw/openrisc: support 4 serial ports in or1ksim

From: "Jason A. Donenfeld" The 8250 serial controller supports 4 serial ports, so wire them all up, so that we can have more than one basic I/O channel. Cc: Stafford Horne Signed-off-by: Jason A. Donenfeld [smh:Fixup indentation and lines over 80 chars] Signed-off-by: Stafford Horne ---

[PULL 3/4] hw/openrisc: use right OMPIC size variable

From: "Jason A. Donenfeld" This appears to be a copy and paste error. The UART size was used instead of the much smaller OMPIC size. But actually that smaller OMPIC size is wrong too and doesn't allow the IPI to work in Linux. So set it to the old value. Signed-off-by: Jason A. Donenfeld

[PULL 1/4] hw/openrisc: page-align FDT address

From: "Jason A. Donenfeld" The QEMU-provided FDT was only being recognized by the kernel when it was used in conjunction with -initrd. Without it, the magic bytes wouldn't be there and the kernel couldn't load it. This patch fixes the issue by page aligning the provided FDT. Cc: Stafford Horne

[PULL 0/4] OpenRISC fixes for QEMU 2022-05-15

The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947: Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-03 09:13:17 -0700) are available in the Git repository at: https://github.com/stffrdhrn/qemu.git

Re: [RFC PATCH 9/9] iotests: use tests/venv for running tests

On Fri, May 13, 2022, 11:33 AM Paolo Bonzini wrote: > On 5/13/22 16:38, John Snow wrote: > > It *should*, because "#!/usr/bin/env python3" is the preferred shebang > > for Python scripts. > > > > https://peps.python.org/pep-0394/ > > > > 'python3' "should" be

[PATCH qemu v5 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 26 + 2 files changed, 38 insertions(+) diff --git

[PATCH qemu v5 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c

[PATCH qemu v5 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) diff --git

[PATCH qemu v5 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior

From: eopXD According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple

[PATCH qemu v5 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 5 target/riscv/vector_helper.c| 35 + 2 files changed, 29 insertions(+), 11 deletions(-) diff --git

[PATCH qemu v5 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) diff --git

[PATCH qemu v5 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 26 +++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git

[PATCH qemu v5 00/10] Add mask agnostic behavior for rvv instructions

According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for

[PATCH qemu v5 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH qemu v5 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are

[PATCH qemu v5 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH] linux-user/syscall.c: fix build without RLIMIT_RTTIME

RLIMIT_RTTIME is not provided by uclibc-ng or by musl prior to version 1.2.0 and https://github.com/bminor/musl/commit/2507e7f5312e79620f6337935d0a6c9045ccba09 resulting in the following build failure since https://git.qemu.org/?p=qemu.git;a=commit;h=244fd08323088db73590ff2317dfe86f810b51d7:

[PATCH] block/nvme: separate nvme_get_free_req cases for coroutine/non-coroutine context

nvme_get_free_req has very difference semantics when called in coroutine context (when it waits) and in non-coroutine context (when it doesn't). Split the two cases to make it clear what is being requested. Cc: qemu-bl...@nongnu.org Signed-off-by: Paolo Bonzini --- block/nvme.c | 48

Re: [PATCH v2 07/26] block: add missing coroutine_fn annotations

On 5/13/22 23:26, Eric Blake wrote: +int coroutine_fn blk_pwrite_zeroes(BlockBackend *blk, int64_t offset, + int64_t bytes, BdrvRequestFlags flags) Tracking down all callers of blk_pwrite_zeroes is not as trivial as in the previous patches. But the very first

Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

On Fri, May 13, 2022 at 11:58 PM Atish Kumar Patra wrote: > On Thu, May 12, 2022 at 11:29 PM Frank Chang > wrote: > > > > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote: > >> > >> From: Atish Patra > >> > >> mcycle/minstret are actually WARL registers and can be written with any > >> given

Re: [PATCH 2/2] hw: aspeed: Init all UART's with serial devices

> On May 14, 2022, at 12:30 AM, Cédric Le Goater wrote: > > On 5/13/22 23:08, Peter Delevoryas wrote: >>> On May 12, 2022, at 10:31 PM, Cédric Le Goater wrote: >>> >>> On 5/13/22 06:02, Peter Delevoryas wrote: Usually, QEMU users just provide one serial device on the command line,

Re: [PATCH 2/2] hw: aspeed: Init all UART's with serial devices

On 5/13/22 23:08, Peter Delevoryas wrote: On May 12, 2022, at 10:31 PM, Cédric Le Goater wrote: On 5/13/22 06:02, Peter Delevoryas wrote: Usually, QEMU users just provide one serial device on the command line, either through "-nographic" or "-serial stdio -display none", or just using VNC

[PATCH v3 2/3] thread-pool: replace semaphore with condition variable

Since commit f9fc8932b1 ("thread-posix: remove the posix semaphore support", 2022-04-06) QemuSemaphore has its own mutex and condition variable; this adds unnecessary overhead on I/O with small block sizes. Check the QTAILQ directly instead of adding the indirection of a semaphore's count. Using

Re: [PATCH] whpx: Added support for saving/restoring VM state

On 5/14/22 03:29, Ivan Shcherbakov wrote: +/* + * As of Windows 10 21H1, the layout of the XSAVE data returned by the WHPX API + * does not match the layout used by QEMU. + * + * Specifically, trying to pass the state returned by x86_cpu_xsave_all_areas() + * to

[PATCH v3 1/3] thread-pool: optimize scheduling of completion bottom half

The completion bottom half was scheduled within the pool->lock critical section. That actually results in worse performance, because the worker thread can run its own small critical section and go to sleep before the bottom half starts running. Note that this simple change does not produce an

[PATCH v2 2/2] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

If specified CPU configuration is not valid, not just it prints error message, it aborts and generates core dumps (depends on the operating system). This kind of error handling should be used only when a serious runtime error occurs. This commit makes error handling on CPU configuration more

[PATCH v3 0/3] thread-pool: fix performance regression

Together, these two patches fix the performance regression induced by QemuSemaphore; individually they don't though. The third patch is a small cleanup on top, that was enabled by the recent introduction of min_threads/max_threads knobs for the thread pool. 6.2: iops: min=58051,

[PATCH v3 0/3] thread-pool: fix performance regression

Together, these two patches fix the performance regression induced by QemuSemaphore; individually they don't though. The third patch is a small cleanup on top, that was enabled by the recent introduction of min_threads/max_threads knobs for the thread pool. 6.2: iops: min=58051,

[PATCH v2 1/2] hw/riscv: Make CPU config error handling generous (virt/spike)

If specified CPU configuration is not valid, not just it prints error message, it aborts and generates core dumps (depends on the operating system). This kind of error handling should be used only when a serious runtime error occurs. This commit makes error handling on CPU configuration more

[PATCH v3 3/3] thread-pool: remove stopping variable

Just setting the max threads to 0 is enough to stop all workers. Signed-off-by: Paolo Bonzini --- util/thread-pool.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/util/thread-pool.c b/util/thread-pool.c index 6bbf24754a..507c998827 100644 --- a/util/thread-pool.c +++

[PATCH v2 0/2] hw/riscv: Make CPU config error handling generous

c.f. This patchset is functionally equivalent to v1 but fixes commit titles. Tsukasa OI (2): hw/riscv: Make CPU config error handling generous (virt/spike) hw/riscv: Make CPU config error handling generous

[PATCH] configure: remove duplicate help messages

These messages are already emitted by scripts/meson-parse-buildoptions.sh. Signed-off-by: Paolo Bonzini --- configure | 4 1 file changed, 4 deletions(-) diff --git a/configure b/configure index dda25f05bf..0cc8c876f7 100755 --- a/configure +++ b/configure @@ -1043,10 +1043,6 @@ Advanced

[PATCH] configure: remove duplicate help messages

These messages are already emitted by scripts/meson-parse-buildoptions.sh. Signed-off-by: Paolo Bonzini --- configure | 4 1 file changed, 4 deletions(-) diff --git a/configure b/configure index dda25f05bf..0cc8c876f7 100755 --- a/configure +++ b/configure @@ -1043,10 +1043,6 @@ Advanced