On 7/4/22 23:54, Peter Delevoryas wrote:
With the BIC, the easiest way to run everything is to create two pty's
for each SoC and reserve stdin/stdout for the monitor:
wget
https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
wget
On 7/4/22 23:54, Peter Delevoryas wrote:
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should
On 7/4/22 23:54, Peter Delevoryas wrote:
You can test booting the BMC with both '-device loader' and '-drive
file'. This is necessary because of how the fb-openbmc boot sequence
works (jump to 0x2000 after U-Boot SPL).
wget
On 7/4/22 23:54, Peter Delevoryas wrote:
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed.c | 2 +-
include/hw/arm/aspeed_soc.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c
On 7/4/22 23:54, Peter Delevoryas wrote:
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM
On 7/4/22 23:54, Peter Delevoryas wrote:
I added this helper in the Aspeed machine file a while ago to help
initialize fuji-bmc i2c devices. This moves it to the official pca954x
file so that other files can use it.
This does something very similar to pca954x_i2c_get_bus, but I think
this is
On Thu, Jun 30, 2022 at 4:27 PM Anup Patel wrote:
>
> On Thu, Jun 30, 2022 at 11:42 AM Anup Patel wrote:
> >
> > This series does fixes and improvements to have nested virtualization
> > on QEMU RISC-V.
> >
> > These patches can also be found in riscv_nested_fixes_v9 branch at:
> >
Leonardo Bras writes:
> Signed-off-by: Leonardo Bras
Acked-by: Markus Armbruster
Leonardo Brás writes:
> Thanks Daniel, Markus and Dave for the feedback!
>
> On Mon, 2022-07-04 at 14:14 +0100, Daniel P. Berrangé wrote:
>> On Mon, Jul 04, 2022 at 02:59:50PM +0200, Markus Armbruster wrote:
>> > Daniel P. Berrangé writes:
>> >
>> > > On Mon, Jul 04, 2022 at 02:04:41PM +0200,
On 7/1/22 08:21, Thomas Huth wrote:
According to commit cec07c0b612975 the code in the #else paths was required
for GCC < 5.0 and Clang < 3.8. We don't support such old compilers
at all anymore, so we can remove these lines now. We keep the wrapper
function, though, since they are easier to read
On 7/5/22 09:00, Richard Henderson wrote:
On 7/4/22 17:38, Peter Maydell wrote:
case TARGET_SVE_MAGIC:
+ if (sve || size < sizeof(struct target_sve_context)) {
+ goto err;
+ }
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
On 7/4/22 17:38, Peter Maydell wrote:
case TARGET_SVE_MAGIC:
+if (sve || size < sizeof(struct target_sve_context)) {
+goto err;
+}
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
vq = sve_vq(env);
On 7/4/22 17:38, Peter Maydell wrote:
I notice the kernel has a bunch of signal frame test
cases in tools/testing/selftests/arm64/signal/testcases --
do we pass those ?
Most but not all of them. The ones we don't pass are those for which SVE state has been
discarded across a syscall and so
On 7/4/22 17:32, Peter Maydell wrote:
@@ -177,9 +180,13 @@ static void target_setup_sve_record(struct
target_sve_context *sve,
{
int i, j;
+memset(sve, 0, sizeof(*sve));
__put_user(TARGET_SVE_MAGIC, >head.magic);
__put_user(size, >head.size);
__put_user(vq *
On 7/4/22 16:20, Peter Maydell wrote:
+void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
+uint8_t *pn = vpn, *pm = vpm;
+uint64_t *zda = vzda, *zn = vzn;
+
+for (row
On 7/4/22 16:09, Peter Maydell wrote:
+static void clear_vertical_h(void *vptr, size_t off, size_t len)
+{
+uint16_t *ptr = vptr;
+size_t i;
+
+for (i = 0; i < len / 2; ++i) {
+ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
+}
The code for the bigger-than-byte vertical
在 2022/6/21 上午7:15, Atish Patra 写道:
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for
Hi Alistair,
On Wed, Jun 29, 2022 at 4:09 AM Alistair Francis wrote:
> I have a Linux 5.8 test case that is failing due to this patch.
Before I started fixing things in random.c, there were a lot of early
boot bugs with the RNG in Linux. I backported the fixes for these to
all stable kernels.
Hi, all,
I want to use virtiofs to share folder between host and guest.
>From the guide, it must set the NUMA node.
>https://virtio-fs.gitlab.io/howto-qemu.html
But my guest doesn't support NUMA.
Is there any guide to use qemu + virtiofs without NUMA?
Or does qemu have any plan to support it?
On 7/4/22 20:52, Peter Maydell wrote:
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
Copy attrs, sharability, and the NS bit into the TLB.
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 8
target/arm/internals.h | 5 +
target/arm/tlb_helper.c | 14
On Mon, Jul 4, 2022 at 5:05 PM Ding Hui wrote:
>
> On 2022/7/4 15:10, Jason Wang wrote:
> >
> > 在 2022/6/29 17:40, Ding Hui 写道:
> >> @@ -1013,6 +1013,9 @@ e1000_receive_iov(NetClientState *nc, const
> >> struct iovec *iov, int iovcnt)
> >> DBGOUT(RX, "Null RX descriptor!!\n");
> >>
On Tue, Jul 05, 2022 at 05:40:31AM +0900, Stafford Horne wrote:
> riscv{LE}--->goldfish_rtc{LE}
> mips-longsoon3{LE}-->goldfish_rtc{LE}
> openrisc{BE}>goldfish_rtc{LE} (LE to BE conversion done in
> driver)
> m68k{BE}>goldfish_rtc{BE} (only
Hi Peter,
On Mon, Jul 04, 2022 at 03:42:55PM +0100, Peter Maydell wrote:
> We should also add a section to docs/about/deprecated.rst
> noting that the old name is deprecated in favour of the new one.
> I'll fold that in when I add the patch to target-arm.next, to
> save you doing a respin:
在 2022/7/4 下午11:26, Weiwei Li 写道:
在 2022/6/21 上午7:15, Atish Patra 写道:
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter
On 7/4/22 20:58, Peter Maydell wrote:
+ * Returns a pointer to the iotlb entry, with env_tlb(env)->c.lock
+ * still locked, for final additions to the iotlb entry. The caller
+ * must unlock the lock.
*/
-void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
-
在 2022/6/21 上午7:15, Atish Patra 写道:
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for
On 7/4/22 14:34, Cédric Le Goater wrote:
On 7/2/22 15:34, Daniel Henrique Barboza wrote:
On 7/2/22 03:24, Cédric Le Goater wrote:
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
The function can't just return 0 whether an error happened and call it a
day. We must provide a way of
wasmtime is a WebAssembly runtime, which includes a large testsuite.
This testsuite uses qemu-user (aarch64 and s390x are supported) in
order to exercise foreign architectures. Over time it found several
regressions in qemu itself, and it would be beneficial to catch the
similar ones earlier.
To
You can test booting the BMC with both '-device loader' and '-drive
file'. This is necessary because of how the fb-openbmc boot sequence
works (jump to 0x2000 after U-Boot SPL).
wget
https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
qemu-system-arm
With the BIC, the easiest way to run everything is to create two pty's
for each SoC and reserve stdin/stdout for the monitor:
wget
https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
wget
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
---
MAINTAINERS| 1 +
hw/arm/fby35.c | 39 +++
hw/arm/meson.build | 3 ++-
3 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/fby35.c
diff --git
From: Cédric Le Goater
The BMC boots from the first flash device by fetching instructions
from the flash contents. Add an alias region on 0x0 for this
purpose. There are currently performance issues with this method (TBs
being flushed too often), so as a faster alternative, install the
flash
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed.c | 2 +-
include/hw/arm/aspeed_soc.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cc395f988c..b2486a9e78 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -262,7
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM region though, for VM
migration. Since
I added this helper in the Aspeed machine file a while ago to help
initialize fuji-bmc i2c devices. This moves it to the official pca954x
file so that other files can use it.
This does something very similar to pca954x_i2c_get_bus, but I think
this is useful when you have a very complicated dts
On 6/27/22 20:52, Iris Chen wrote:
Signed-off-by: Iris Chen
---
hw/block/m25p80.c | 74 +++
1 file changed, 62 insertions(+), 12 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 50b523e5b1..0156a70f5e 100644
---
On Mon, Jul 04, 2022 at 12:23:23PM +0200, Laurent Vivier wrote:
> On 04/07/2022 12:21, Richard Henderson wrote:
> > On 7/4/22 15:46, Laurent Vivier wrote:
> > > On 04/07/2022 11:59, Richard Henderson wrote:
> > > > On 7/4/22 02:58, Stafford Horne wrote:
> > > > > -static const MemoryRegionOps
On Mon, Jul 04, 2022 at 03:29:57PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > -static const MemoryRegionOps goldfish_rtc_ops = {
> > -.read = goldfish_rtc_read,
> > -.write = goldfish_rtc_write,
> > -.endianness = DEVICE_NATIVE_ENDIAN,
> > -.valid
On Mon, Jul 04, 2022 at 03:33:26PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > The last_clk time was initialized at zero, this means when we calculate
> > the first delta we will calculate 0 vs current time which could cause
> > unnecessary hops.
> >
> >
On Mon, Jul 04, 2022 at 03:37:04PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > case TO_SPR(10, 1): /* TTCR */
> > -cpu_openrisc_count_update(cpu);
> > +if (cpu_openrisc_timer_has_advanced(cpu)) {
> > +qemu_mutex_lock_iothread();
>
On Mon, Jul 04, 2022 at 03:34:52PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > When we are tracing it's helpful to know which CPU's are getting
> > interrupted, att that detail to the log line.
>
> "at".
>
> Reviewed-by: Richard Henderson
Actually it should be
Some errors, like the lack of Scatter-Gather support by the network
interface(NETIF_F_SG) may cause sendmsg(...,MSG_ZEROCOPY) to fail on using
zero-copy, which causes it to fall back to the default copying mechanism.
After each full dirty-bitmap scan there should be a zero-copy flush
happening,
Signed-off-by: Leonardo Bras
---
qapi/migration.json | 7 ++-
migration/migration.c | 2 ++
monitor/hmp-cmds.c| 4
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index 7102e474a6..fed08b9b88 100644
--- a/qapi/migration.json
If flush is called when no buffer was sent with MSG_ZEROCOPY, it currently
returns 1. This return code should be used only when Linux fails to use
MSG_ZEROCOPY on a lot of sendmsg().
Fix this by returning early from flush if no sendmsg(...,MSG_ZEROCOPY)
was attempted.
Fixes: 2bc58ffc2926
The first patch avoid spuriously returning 1 [*] when zero-copy flush is
attempted before any buffer was sent using MSG_ZEROCOPY.
[*] zero-copy not being used, even though it's enabled and supported
by kernel
The second patch introduces a new migration stat
(dirty-sync-missed-zero-copy) that
In a multi-SoC board, we want to allow machines to construct shared
I2CBus's, so that we can have two SoC I2C controllers attached to a single
I2CBus. We already expose read-only access, this just adds a method for
setting and using an external I2CBus in the Aspeed I2C bus controller.
One issue
Signed-off-by: Peter Delevoryas
---
hw/arm/fby35.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index 1972948318..88923d88eb 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -15,6 +15,7 @@
#include
On Mon, Jul 4, 2022 at 5:28 PM Daniel P. Berrangé wrote:
> Have you done any measurement see how much of the overhead is from
> the checks you implemented, vs how much is inherantly forced on us
> by libclang ? ie what does it look like if you just load the libclang
> framework and run it actross
Are all these changes OK or is there anything else missing? I was
thinking in adding a QMP 'query-nvmm' command but I got pointed to this
thread as a better alternative to having a per-accelerator query command.
On 04/07/2022 15:04, Alberto Faria wrote:
On Mon, Jul 4, 2022 at 6:46 PM Víctor Colombo
wrote:
Yes, this line is present at the beginning of the output
Is this caused by problems with the code being analyzed or is it because
libclang is getting confused with something that is outside of our
Thanks Daniel, Markus and Dave for the feedback!
On Mon, 2022-07-04 at 14:14 +0100, Daniel P. Berrangé wrote:
> On Mon, Jul 04, 2022 at 02:59:50PM +0200, Markus Armbruster wrote:
> > Daniel P. Berrangé writes:
> >
> > > On Mon, Jul 04, 2022 at 02:04:41PM +0200, Markus Armbruster wrote:
> >
On Mon, Jul 4, 2022 at 6:46 PM Víctor Colombo
wrote:
> Yes, this line is present at the beginning of the output
> Is this caused by problems with the code being analyzed or is it because
> libclang is getting confused with something that is outside of our
> control?
I think I found the problem:
On 04/07/2022 13:57, Alberto Faria wrote:
Hi Víctor,
On Mon, Jul 4, 2022 at 3:18 PM Víctor Colombo
wrote:
And I receive an exception on the line above saying that node is of type
NoneType. Seems that `node = node.referenced` is setting `node` to None
in this case.
I was unable to understand
On 7/2/22 15:34, Daniel Henrique Barboza wrote:
On 7/2/22 03:24, Cédric Le Goater wrote:
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
The function can't just return 0 whether an error happened and call it a
day. We must provide a way of letting callers know if the zero return is
Hi Víctor,
On Mon, Jul 4, 2022 at 3:18 PM Víctor Colombo
wrote:
> And I receive an exception on the line above saying that node is of type
> NoneType. Seems that `node = node.referenced` is setting `node` to None
> in this case.
>
> I was unable to understand the root cause of it. Is this an
Ilya Leoshkevich wrote:
> zlib_send_prepare() compresses pages of a running VM. zlib does not
> make any thread-safety guarantees with respect to changing deflate()
> input concurrently with deflate() [1].
>
> One can observe problems due to this with the IBM zEnterprise Data
> Compression
zlib_send_prepare() compresses pages of a running VM. zlib does not
make any thread-safety guarantees with respect to changing deflate()
input concurrently with deflate() [1].
One can observe problems due to this with the IBM zEnterprise Data
Compression accelerator capable zlib [2]. When the
On Sat, Jul 02, 2022 at 12:33:23PM +0100, Alberto Faria wrote:
> This series introduces a static analyzer for QEMU. It consists of a
> single static-analyzer.py script that relies on libclang's Python
> bindings, and provides a common framework on which arbitrary static
> analysis checks can be
On Mon, Jul 4, 2022 at 2:52 PM Hanna Reitz wrote:
> There are a couple of places where you decided to replace “*len”
> variables that used to store the return value by a plain “ret”. That
> seems good to me, given how these functions no longer return length
> values, but you haven’t done so
Leonardo Brás wrote:
> Hello Juan,
>
> On Tue, 2022-06-21 at 16:05 +0200, Juan Quintela wrote:
>> We need to add a new flag to mean to sync at that point.
>> Notice that we still synchronize at the end of setup and at the end of
>> complete stages.
>>
>> Signed-off-by: Juan Quintela
>> ---
>>
On Mon, Jul 04, 2022 at 04:55:45PM +0100, Peter Maydell wrote:
> On Mon, 4 Jul 2022 at 16:50, Daniel P. Berrangé wrote:
> >
> > On Mon, Jul 04, 2022 at 04:47:16PM +0100, Peter Maydell wrote:
> > > On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé
> > > wrote:
> > > >
> > > > Signed-off-by: Daniel
On Mon, Jul 04, 2022 at 04:46:53PM +0100, Peter Maydell wrote:
> On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
> >
> > Historically QEMU has used the 'scripts/checkpatch.pl' script to
> > validate various style rules but there are a number of issues:
>
> > meson.build |
On Mon, Jul 4, 2022, 9:46 AM Daniel P. Berrangé wrote:
> On Mon, Jul 04, 2022 at 09:38:46AM -0600, Warner Losh wrote:
> > On Mon, Jul 4, 2022 at 9:28 AM Daniel P. Berrangé
> > wrote:
> >
> > > A few files relied on qemu/osdep.h being included via a common
> > > header. Another file didn't need
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> We used to synchronize all channels at the end of each RAM section
>> sent. That is not needed, so preparing to only synchronize once every
>> full round in latests patches.
>>
>> Notice that we initialize the
On Mon, 4 Jul 2022 at 15:58, Richard Henderson
wrote:
>
> On 7/4/22 20:24, Peter Maydell wrote:
> >> Previously, we had A-profile allocate separate mmu_idx for secure
> >> vs non-secure. I've done away with that. Now, I flush all mmu_idx
> >> when SCR_EL3.NS is changed. I did not see how we
On Mon, 4 Jul 2022 at 16:50, Daniel P. Berrangé wrote:
>
> On Mon, Jul 04, 2022 at 04:47:16PM +0100, Peter Maydell wrote:
> > On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
> > >
> > > Signed-off-by: Daniel P. Berrangé
> >
> > > +
> > > +sc_c_file_osdep_h:
> > > +
On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
>
> Signed-off-by: Daniel P. Berrangé
> ---
> --- a/docs/tools/qemu-pr-helper.rst
> +++ b/docs/tools/qemu-pr-helper.rst
> @@ -22,7 +22,7 @@ storage fabric. QEMU's SCSI passthrough devices
> ``scsi-block``
> and ``scsi-generic`` support
On Mon, Jul 04, 2022 at 04:47:16PM +0100, Peter Maydell wrote:
> On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
> >
> > Signed-off-by: Daniel P. Berrangé
>
> > +
> > +sc_c_file_osdep_h:
> > + @require='#include "qemu/osdep.h"' \
> > + in_vc_files='\.c$$' \
> > +
On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
>
> Signed-off-by: Daniel P. Berrangé
> +
> +sc_c_file_osdep_h:
> + @require='#include "qemu/osdep.h"' \
> + in_vc_files='\.c$$' \
> + halt='all C files must include qemu/osdep.h' \
> + $(_sc_search_regexp)
The rule
On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
>
> Historically QEMU has used the 'scripts/checkpatch.pl' script to
> validate various style rules but there are a number of issues:
> meson.build | 3 +
> tests/Makefile.include | 3 +-
> tests/meson.build| 19
On Mon, Jul 04, 2022 at 09:38:46AM -0600, Warner Losh wrote:
> On Mon, Jul 4, 2022 at 9:28 AM Daniel P. Berrangé
> wrote:
>
> > A few files relied on qemu/osdep.h being included via a common
> > header. Another file didn't need it because it was actually an
> > included file, so ought to have
On Mon, 4 Jul 2022 at 16:23, Daniel P. Berrangé wrote:
>
> Signed-off-by: Daniel P. Berrangé
> ---
> block/vhdx-log.c | 2 +-
> hw/xtensa/sim.c| 4 ++--
> nbd/client.c | 4 ++--
> target/i386/cpu-dump.c | 3 ++-
> ui/spice-display.c | 4 ++--
> 5 files changed, 9
On Mon, Jul 4, 2022 at 9:28 AM Daniel P. Berrangé
wrote:
> A few files relied on qemu/osdep.h being included via a common
> header. Another file didn't need it because it was actually an
> included file, so ought to have been named .c.inc
>
> Signed-off-by: Daniel P. Berrangé
> ---
>
On Mon, Jul 4, 2022 at 6:20 PM Pali Rohár wrote:
>
> On Sunday 03 July 2022 21:50:29 Pali Rohár wrote:
> > Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC
implementations")
> > changed core type of MPC8555 and MPC8560 from e500v1 to e500v2.
> >
> > But both MPC8555 and MPC8560 have
On 01.07.22 18:15, John Snow wrote:
On Fri, Jul 1, 2022 at 4:05 AM Hanna Reitz wrote:
On 16.06.22 16:26, John Snow wrote:
In certain container environments we may not have FUSE at all, so skip
the test in this circumstance too.
Signed-off-by: John Snow
---
tests/qemu-iotests/108 | 5
在 2022/6/21 上午7:15, Atish Patra 写道:
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
On 17.05.22 13:38, Alberto Faria wrote:
It does not mutate the buffer.
Signed-off-by: Alberto Faria
---
include/sysemu/block-backend-io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Hanna Reitz
On 17.05.22 13:38, Alberto Faria wrote:
We need to add include/sysemu/block-backend-io.h to the inputs of the
block-gen.c target defined in block/meson.build.
Signed-off-by: Alberto Faria
---
block/block-backend.c | 23 ---
block/coroutines.h|
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> Add an optional structure, controlled by TARGET_PAGE_ENTRY_EXTRA,
> that allows arbitrary extra data to be saved in the TLB for a
> given page. Set it with tlb_set_page_with_extra() and fetch it
> with probe_access_extra().
>
>
在 2022/6/21 上午7:15, Atish Patra 写道:
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many
On 17.05.22 13:37, Alberto Faria wrote:
For consistency with other I/O functions, and in preparation to
implement them using generated_co_wrapper.
Signed-off-by: Alberto Faria
---
block/block-backend.c | 6 +++---
include/sysemu/block-backend-io.h | 6 +++---
2 files changed, 6
A few files relied on qemu/osdep.h being included via a common
header. Another file didn't need it because it was actually an
included file, so ought to have been named .c.inc
Signed-off-by: Daniel P. Berrangé
---
bsd-user/arm/signal.c | 2 ++
bsd-user/arm/target_arch_cpu.c
This style check looks for cases where the words
the then in an on if is it but for or at and do to
are repeated in a sentence. It doesn't use the simple regex match logic
because it needs to match repeats across lines, so has a custom crafted
rule.
Signed-off-by: Daniel P. Berrangé
---
Signed-off-by: Daniel P. Berrangé
---
block/linux-aio.c | 2 +-
block/qcow2-bitmap.c | 8
contrib/plugins/cache.c| 2 +-
disas/libvixl/vixl/invalset.h | 2 +-
docs/devel/qom.rst | 4 ++--
Signed-off-by: Daniel P. Berrangé
---
tests/style-excludes.mak | 17 +
tests/style.mak | 6 ++
2 files changed, 23 insertions(+)
diff --git a/tests/style-excludes.mak b/tests/style-excludes.mak
index 931dd03a64..df158e1d9d 100644
--- a/tests/style-excludes.mak
+++
The first patch gives a detailed description, but the overall goal here
is to provide a code style checking facility to augment (and ideally
eventually replace) checkpatch.pl. The key conceptual differences are:
- Always applies to all code in tree, not merely patches
- Failures are always
Historically QEMU has used the 'scripts/checkpatch.pl' script to
validate various style rules but there are a number of issues:
- It requires the contributor to remember to run it as it
is not wired into 'make check'
- While it can be told to check whole files, in practice
it is usually
Signed-off-by: Daniel P. Berrangé
---
block/vhdx-log.c | 2 +-
hw/xtensa/sim.c| 4 ++--
nbd/client.c | 4 ++--
target/i386/cpu-dump.c | 3 ++-
ui/spice-display.c | 4 ++--
5 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/block/vhdx-log.c
The 'true' and 'false' constants should only ever be used with the
'bool' type, never 'int'.
Signed-off-by: Daniel P. Berrangé
---
tests/style.mak | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/style.mak b/tests/style.mak
index 32c7e706ba..ae658395c9 100644
---
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> Copy attrs, sharability, and the NS bit into the TLB.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu-param.h | 8
> target/arm/internals.h | 5 +
> target/arm/tlb_helper.c | 14 --
> 3 files
On 17.05.22 13:37, Alberto Faria wrote:
Swap 'buf' and 'bytes' around for consistency with
blk_co_{pread,pwrite}(), and in preparation to implement these functions
using generated_co_wrapper.
Callers were updated using this Coccinelle script:
@@ expression blk, offset, buf, bytes, flags;
在 2022/6/21 上午7:15, Atish Patra 写道:
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between
://gitlab.com/rth7680/qemu.git tags/pull-la-20220704
for you to fetch changes up to eb1e9ff8bba91674b4321f2b075c55aa8d9948cc:
target/loongarch: Add lock when writing timer clear reg (2022-07-04 11:08:58
+0530)
LoongArch patch queue
On 01/07/2022 10.53, Kashyap Chamarthy wrote:
Ping.
Thomas/Peter: when you get some time, please have a look at this.
I still had a question/request here that was not answered:
https://lore.kernel.org/qemu-devel/2fca7b7e-f95d-eae1-9973-9ede30cac...@redhat.com/
Also, for the first patch, I'd
On 7/1/22 20:02, John Snow wrote:
On Wed, Jun 29, 2022 at 7:18 PM Richard Henderson
wrote:
On 6/29/22 13:45, Vladimir Sementsov-Ogievskiy wrote:
The following changes since commit ad4c7f529a279685da84297773b4ec8080153c2d:
Merge tag 'pull-semi-20220628' of https://gitlab.com/rth7680/qemu
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS
On 7/4/22 20:24, Peter Maydell wrote:
Previously, we had A-profile allocate separate mmu_idx for secure
vs non-secure. I've done away with that. Now, I flush all mmu_idx
when SCR_EL3.NS is changed. I did not see how we could reasonably
add 8 more mmu_idx for Realm. Moreover, I had a look
On 04/07/2022 09.58, Claudio Fontana wrote:
detected with GCC 13 [-Werror=enum-int-mismatch]
Solves Issue #1096.
Signed-off-by: Claudio Fontana
Cc: Pavel Dovgalyuk
---
stubs/replay-tools.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/stubs/replay-tools.c
On 13/06/2022 14.37, Andrij Mizyk wrote:
Signed-off-by: Andrij Mizyk
---
po/LINGUAS | 1 +
po/uk.po | 75 ++
2 files changed, 76 insertions(+)
create mode 100644 po/uk.po
Thanks!
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