Re: [PATCH v10 3/7] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

Damien Le Moal 于2022年10月4日周二 07:23写道： > > On 2022/10/04 2:47, Stefan Hajnoczi wrote: > > On Thu, Sep 29, 2022 at 04:36:27PM +0800, Sam Li wrote: > >> Add a new zoned_host_device BlockDriver. The zoned_host_device option > >> accepts only zoned host block devices. By adding zone management > >>

Re: [PATCH v3] win32: set threads name

On Fri, Sep 30, 2022 at 10:19 PM wrote: > > From: Marc-André Lureau > > As described in: > https://learn.microsoft.com/en-us/visualstudio/debugger/how-to-set-a-thread-name-in-native-code?view=vs-2022 > > SetThreadDescription() is available since Windows 10, version 1607 and > in some versions

Re: [PATCH v10 3/7] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

Stefan Hajnoczi 于2022年10月4日周二 02:32写道： > > On Thu, Sep 29, 2022 at 04:36:27PM +0800, Sam Li wrote: > > Add a new zoned_host_device BlockDriver. The zoned_host_device option > > accepts only zoned host block devices. By adding zone management > > operations in this new BlockDriver, users can use

Re: [PATCH v5 17/18] .gitlab-ci.d/windows.yml: Increase the timeout to 90 minutes

On Fri, Oct 7, 2022 at 5:57 PM Marc-André Lureau wrote: > > Hi > > On Thu, Oct 6, 2022 at 8:16 PM Bin Meng wrote: >> >> From: Bin Meng >> >> commit 9f8e6cad65a6 ("gitlab-ci: Speed up the msys2-64bit job by using >> --without-default-devices" >> changed to compile QEMU with the

Re: [PATCH v2] tests: Add sndio to the FreeBSD CI containers / VM

On Fri, Oct 7, 2022 at 4:27 PM Brad Smith wrote: > On 10/7/2022 4:33 PM, Warner Losh wrote: > > > > On Fri, Oct 7, 2022 at 1:21 AM Brad Smith wrote: > >> tests: Add sndio to the FreeBSD CI containers / VM >> >> --- >> .gitlab-ci.d/cirrus/freebsd-12.vars | 2 +- >>

Re: [PATCH v2] tests: Add sndio to the FreeBSD CI containers / VM

On 10/7/2022 4:33 PM, Warner Losh wrote: On Fri, Oct 7, 2022 at 1:21 AM Brad Smith wrote: tests: Add sndio to the FreeBSD CI containers / VM ---  .gitlab-ci.d/cirrus/freebsd-12.vars           |   2 +-  .gitlab-ci.d/cirrus/freebsd-13.vars           |   2 +-  

Re: [PATCH v8 2/8] KVM: Extend the memslot to support fd-based private memory

On Fri, Oct 07, 2022 at 02:58:54PM +, Sean Christopherson wrote: > On Fri, Oct 07, 2022, Jarkko Sakkinen wrote: > > On Thu, Oct 06, 2022 at 03:34:58PM +, Sean Christopherson wrote: > > > On Thu, Oct 06, 2022, Jarkko Sakkinen wrote: > > > > On Thu, Oct 06, 2022 at 05:58:03PM +0300, Jarkko

Re: [PATCH RESEND] linux-user: Fix struct statfs ABI on loongarch64

Am Donnerstag, 6. Oktober 2022, 12:07:10 CEST schrieb WANG Xuerui: > Previously the 32-bit version was incorrectly chosen, leading to funny > but incorrect output from e.g. df(1). Simply select the version > corresponding to the 64-bit asm-generic definition. > > For reference, this program

Re: [PATCH] linux-user: Fix more MIPS n32 syscall ABI issues

Am Donnerstag, 6. Oktober 2022, 10:55:00 CEST schrieb WANG Xuerui: > In commit 80f0fe3a85 ("linux-user: Fix syscall parameter handling for > MIPS n32") the ABI problem regarding offset64 on MIPS n32 was fixed, > but still some cases remain where the n32 is incorrectly treated as any > other 32-bit

Re: [PATCH RFC] hw/cxl: type 3 devices can now present volatile or persistent memory

On Fri, 07 Oct 2022, Gregory Price wrote: Spec says that volatile devices `may` implement an lsa. Right you are. Get LSA (Opcode 4102h) The Label Storage Area (LSA) shall be supported by a memory device that provides persistent memory capacity and may be supported by a device that provides

Re: [PATCH RFC] hw/cxl: type 3 devices can now present volatile or persistent memory

On Thu, 06 Oct 2022, Jonathan Cameron wrote: One of the blockers for volatile support was that we had no means to poke it properly as the kernel doesn't yet support volatile capacity and no one has done the relevant work in EDK2 or similar to do it before the kernel boots. There has been some

Re: [PATCH 2/6] target/ppc: fix msgsync insns flags

Matheus Ferst writes: > This instruction was added by Power ISA 3.0, using PPC2_PRCNTL makes it > available for older processors, like de e5500 and e6500. > > Fixes: 7af1e7b02264 ("target/ppc: add support for hypervisor doorbells on > book3s CPUs") > Signed-off-by: Matheus Ferst Reviewed-by:

Re: [PATCH 1/6] target/ppc: fix msgclr/msgsnd insns flags

Matheus Ferst writes: > On Power ISA v2.07, the category for these instructions became > "Embedded.Processor Control" or "Book S". > > Signed-off-by: Matheus Ferst Reviewed-by: Fabiano Rosas > --- > target/ppc/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff

Re: [PATCH 3/6] target/ppc: fix REQUIRE_HV macro definition

Matheus Ferst writes: > The macro is missing a '{' after the if condition. Any use of REQUIRE_HV > would cause a compilation error. > > Fixes: fc34e81acd51 ("target/ppc: add macros to check privilege level") > Signed-off-by: Matheus Ferst Reviewed-by: Fabiano Rosas > --- >

Re: [PATCH RFC] hw/cxl: type 3 devices can now present volatile or persistent memory

On Fri, Oct 07, 2022 at 11:16:19AM -0700, Davidlohr Bueso wrote: > > Yeah, putting this back together was on my todo list, but happy to see > patches are out. Recollecting my thoughts on this, my original approach > was also to support only volatile or persistent capacities, but through > two

Re: [PATCH RFC] hw/cxl: type 3 devices can now present volatile or persistent memory

On Thu, 06 Oct 2022, Jonathan Cameron wrote: 3) Upstream linux drivers haven't touched ram configurations yet. I just configured this with Dan Williams yesterday on IRC. My understanding is that it's been worked on but nothing has been upstreamed, in part because there are only a very small

Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL

On Thu, 06 Oct 2022, Gregory Price wrote: Current code sets to STORAGE_EXPRESS and then overrides it. Good catch. Reviewed-by: Davidlohr Bueso Signed-off-by: Gregory Price --- hw/mem/cxl_type3.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/mem/cxl_type3.c

Re: [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS

On 10/7/22 09:50, Peter Maydell wrote: On Fri, 7 Oct 2022 at 17:45, Richard Henderson wrote: On 10/7/22 06:47, Peter Maydell wrote: Are there definitely no code paths where we might try to do a page table walk with the iothread already locked ? I'll double-check, but another possibility is

Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL

On Thu, 06 Oct 2022, Gregory Price wrote: Current code sets to STORAGE_EXPRESS and then overrides it. Good catch. Reviewed-by: Davidlohr Bueso

Re: [PATCH v6 02/13] blkio: add libblkio block driver

On Fri, 7 Oct 2022 at 11:41, Markus Armbruster wrote: > > Stefan Hajnoczi writes: > > > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for > > high-performance disk I/O. It currently supports io_uring, > > virtio-blk-vhost-user, and virtio-blk-vhost-vdpa with additional drivers >

[PATCH v3] mips/malta: pass RNG seed to to kernel via env var

As of the kernel commit linked below, Linux ingests an RNG seed passed as part of the environment block by the bootloader or firmware. This mechanism works across all different environment block types, generically, which pass some block via the second firmware argument. On malta, this has been

Re: [PATCH v1] vhost-vdpa : add support for vIOMMU

On Thu, Oct 6, 2022 at 7:44 AM Cindy Lu wrote: > > Add support for vIOMMU. Register a memory listener to dma_as in > vhost_vdpa_dev_start > - during region_add register a specific IOMMU notifier, and store all > notifiers in a list. > - during region_del, compare and delete the IOMMU notifier

Re: [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters

On Fri, 7 Oct 2022 at 17:13, Richard Henderson wrote: > > On 10/7/22 09:11, Peter Maydell wrote: > > On Fri, 7 Oct 2022 at 16:37, Richard Henderson > > wrote: > >> > >> On 10/7/22 02:24, Peter Maydell wrote: > +.ha = ha, > +.hd = ha & hd, > >>> > >>> This is a bitwise

Re: [PATCH v3] virtio-scsi: Send "REPORTED LUNS CHANGED" sense data upon disk hotplug events.

On 2022-10-07 06:55:15 -0400, Paolo Bonzini wrote: > Il gio 6 ott 2022, 15:25 Venu Busireddy ha > scritto: > > > I do see that the Solaris driver does send the 0x1a command during > > the initialization, perhaps (?) seeking the value of UA_INTLCK_CTRL. > > Since QEMU currently does not support

Re: [PATCH v2 03/11] bdrv_change_aio_context: use hash table instead of list of visited nodes

Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben: > Minor performance improvement, but given that we have hash tables > available, avoid iterating in the visited nodes list every time just > to check if a node has been already visited. > > The data structure is not actually a

Re: [PATCH 1/2] vhost-user: Refactor vhost acked features saving

在 2022/10/7 22:01, Michael S. Tsirkin 写道: On Mon, Sep 26, 2022 at 02:36:40PM +0800, huang...@chinatelecom.cn wrote: From: Hyman Huang(黄勇) Abstract vhost acked features saving into vhost_user_save_acked_features, export it as util function. Signed-off-by: Hyman Huang(黄勇) Signed-off-by:

Re: [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters

On 10/7/22 02:24, Peter Maydell wrote: +.ha = ha, +.hd = ha & hd, This is a bitwise operation on two bools, should be && ? Bitwise works fine, but I can use boolean if you like. I'd be surprised (and filing a missed optimization bug) if the compiler treated these two

Re: [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS

On Fri, 7 Oct 2022 at 17:45, Richard Henderson wrote: > > On 10/7/22 06:47, Peter Maydell wrote: > > Are there definitely no code paths where we might try to do > > a page table walk with the iothread already locked ? > > I'll double-check, but another possibility is to simply perform the atomic

Re: [PATCH] target/arm: Make the final stage1+2 write to secure be unconditional

On 10/7/22 09:20, Peter Maydell wrote: -/* Check if IPA translates to secure or non-secure PA space. */ -if (is_secure) { -if (ipa_secure) { -result->attrs.secure = -!(env->cp15.vstcr_el2 & (VSTCR_SA |

Re: [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters

On Fri, 7 Oct 2022 at 16:37, Richard Henderson wrote: > > On 10/7/22 02:24, Peter Maydell wrote: > >> +.ha = ha, > >> +.hd = ha & hd, > > > > This is a bitwise operation on two bools, should be && ? > > Bitwise works fine, but I can use boolean if you like. > > I'd be surprised

Re: [PATCH] error handling: Use TFR() macro where applicable

On Fri, 7 Oct 2022 at 12:44, Nikita Ivanov wrote: > > Hi! > Sorry for such a long absence, I've been resolving some other issues in my > life for a while. I've adjusted the patch according to your latest comments. > Could you check it out, please? Hi; thanks for coming back to this. (I'd been

Re: [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS

On 10/7/22 06:47, Peter Maydell wrote: On Sat, 1 Oct 2022 at 18:04, Richard Henderson wrote: Perform the atomic update for hardware management of the access flag and the dirty bit. A limitation of the implementation so far is that the page table itself must already be writable, i.e. the

Re: [PATCH v2 02/11] block: use transactions as a replacement of ->{can_}set_aio_context()

Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben: > Simplify the way the aiocontext can be changed in a BDS graph. > There are currently two problems in bdrv_try_set_aio_context: > - There is a confusion of AioContext locks taken and released, because > we assume that old

[PATCH v7 4/5] hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange

From: Huai-Cheng Kuo The CDAT can be specified in two ways. One is to add ",cdat=" in "-device cxl-type3"'s command option. The file is required to provide the whole CDAT table in binary mode. The other is to use the default that provides some 'reasonable' numbers based on type of memory and

Re: [PATCH v1 5/8] migration: Export dirty-limit time info

在 2022/10/7 23:09, Markus Armbruster 写道: Hyman Huang writes: 在 2022/10/2 2:31, Markus Armbruster 写道: huang...@chinatelecom.cn writes: From: Hyman Huang(黄勇) Export dirty limit throttle time and estimated ring full time, through which we can observe the process of dirty limit during

[PATCH v7 3/5] hw/cxl/cdat: CXL CDAT Data Object Exchange implementation

From: Huai-Cheng Kuo The Data Object Exchange implementation of CXL Coherent Device Attribute Table (CDAT). This implementation is referring to "Coherent Device Attribute Table Specification, Rev. 1.02, Oct. 2020" and "Compute Express Link Specification, Rev. 2.0, Oct. 2020" This patch adds

Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL

On Thu, 6 Oct 2022 19:37:01 -0400 Gregory Price wrote: > Current code sets to STORAGE_EXPRESS and then overrides it. > > Signed-off-by: Gregory Price I'm carry the same patch after you reported it the other day. Reviewed-by: Jonathan Cameron > --- > hw/mem/cxl_type3.c | 3 +-- > 1 file

Re: [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters

On 10/7/22 09:11, Peter Maydell wrote: On Fri, 7 Oct 2022 at 16:37, Richard Henderson wrote: On 10/7/22 02:24, Peter Maydell wrote: +.ha = ha, +.hd = ha & hd, This is a bitwise operation on two bools, should be && ? Bitwise works fine, but I can use boolean if you like.

Re: [PATCH] block/io_uring: revert "Use io_uring_register_ring_fd() to skip fd operations"

Yes, we did hit this bug as well, in the QEMU 7.1 package, for openSUSE Tumbleweed (more info here: https://bugzilla.suse.com/show_bug.cgi?id=1204082) FWIW, I can confirm that applying this patch fixes the issue, so this can have: On Sat, 2022-09-24 at 22:48 +0800, Sam Li wrote: > Resolves:

[PATCH v7 0/5] QEMU PCIe DOE for PCIe 4.0/5.0 and CXL 2.0

Whilst I have carried on Huai-Cheng Kuo's series version numbering and naming, there have been very substantial changes since v6 so I would suggest fresh review makes sense for anyone who has looked at this before. In particularly if the Avery design folks could check I haven't broken anything

Re: [PATCH] target/arm: Make the final stage1+2 write to secure be unconditional

On Fri, 7 Oct 2022 at 16:22, Richard Henderson wrote: > > While the stage2 call to get_phys_addr_lpae should never set > attrs.secure when given a non-secure input, it's just as easy > to make the final update to attrs.secure be unconditional and > false in the case of non-secure input. > >

Re: [PATCH v2 04/11] bdrv_child_try_change_aio_context: add transaction parameter

Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben: > This enables the caller to use the same transaction to also > keep track of aiocontext changes. > > Signed-off-by: Emanuele Giuseppe Esposito What you're really doing here is factoring out the recursive phase. However, the

Re: [PATCH v2 0/3] fix for two ACPI GTDT physical addresses

On Fri, Oct 7, 2022 at 8:16 PM Miguel Luis wrote: > > The ACPI GTDT table contains two invalid 64-bit physical addresses according > to > the ACPI spec. 6.5 [1]. Those are the Counter Control Base physical address > and > the Counter Read Base physical address. Those fields of the GTDT table

Re: [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS

On Fri, 7 Oct 2022 at 14:47, Peter Maydell wrote: > Do we really need to go all the way back to restart_atomic_update? > Are we allowed to do the access and dirty bit updates with separate > atomic accesses? I've just discovered that the latest revision of the Arm ARM (rev I.a) is clearer on

Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking

On Fri, 7 Oct 2022 at 16:27, Richard Henderson wrote: > > On 10/7/22 02:01, Peter Maydell wrote: > > The upcoming v8R support has its stage 2 attributes in the MAIR > > format, so it might be a little awkward to assume the v8A-stage-2 > > format here rather than being able to add the "if

Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking

On 10/7/22 02:01, Peter Maydell wrote: The upcoming v8R support has its stage 2 attributes in the MAIR format, so it might be a little awkward to assume the v8A-stage-2 format here rather than being able to add the "if !is_s2_format" condition. I guess we'll deal with that when we get to it...

Re: [PATCH v1 5/8] migration: Export dirty-limit time info

Hyman Huang writes: > 在 2022/10/2 2:31, Markus Armbruster 写道: >> huang...@chinatelecom.cn writes: >> >>> From: Hyman Huang(黄勇) >>> >>> Export dirty limit throttle time and estimated ring full >>> time, through which we can observe the process of dirty >>> limit during live migration. >>> >>>

Re: [PATCH] m25p80: Add the w25q01jvq SFPD table

On [2022 Oct 06] Thu 17:44:24, Patrick Williams wrote: > Generated from hardware using the following command and then padding > with 0xff to fill out a power-of-2: > hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp` > > Signed-off-by: Patrick Williams > --- > hw/block/m25p80.c | 3 ++- >

Re: [PATCH] vhost-vdpa: fix assert !virtio_net_get_subqueue(nc)->async_tx.elem in virtio_net_reset

On Tue, Oct 4, 2022 at 11:05 PM Si-Wei Liu wrote: > > The citing commit has incorrect code in vhost_vdpa_receive() that returns > zero instead of full packet size to the caller. This renders pending packets > unable to be freed so then get clogged in the tx queue forever. When device > is being

Re: [RFC PATCH 0/4] Idea for using hardfloat in PPC

On 10/7/22 06:42, Alex Bennée wrote: Is ppc unique in not persisting the inexact flag from previous operations? Better phrased as "having an additional per-operation flags for inexact and 'rounded'", because ppc also has the standard ieee sticky inexact flag. But yes, as far as I know ppc

Re: [PATCH v3 30/42] target/arm: Add ptw_idx argument to S1_ptw_translate

On 10/7/22 02:19, Peter Maydell wrote: I don't think this works, because the s2_mmu_idx is not necessarily the same through the whole of a page table walk. See the comment in get_phys_addr_lpae(): /* * Secure accesses start with the page table in secure memory and * can be

Re: [PATCH] vhost-vdpa: allow passing opened vhostfd to vhost-vdpa

On Tue, Oct 4, 2022 at 11:09 PM Si-Wei Liu wrote: > > Similar to other vhost backends, vhostfd can be passed to vhost-vdpa > backend as another parameter to instantiate vhost-vdpa net client. > This would benefit the use case where only open fd's, as oppposed to s/oppposed/opposed/ (realized by

[PATCH v2] linux-user: mprotect() should returns 0 when len is 0.

From: sisshiki1969 On Fri, Oct 7, 2022 at 9:38 AM Richard Henderson wrote: | Although, sorta, this smells like a kernel bug. | Why should mprotect(-4096, 0, 0) succeed while mprotect(-4096, 4096, 0) fails? This may be kinda bug compatibility... | But anyway, if we're going to fix len == 0 to

Re: [PATCH v6 02/13] blkio: add libblkio block driver

Stefan Hajnoczi writes: > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for > high-performance disk I/O. It currently supports io_uring, > virtio-blk-vhost-user, and virtio-blk-vhost-vdpa with additional drivers > under development. > > One of the reasons for developing libblkio

Re: [External] : Re: [PATCH v2 0/3] fix for two ACPI GTDT physical addresses

> On 7 Oct 2022, at 15:21, Ani Sinha wrote: > > On Fri, Oct 7, 2022 at 8:16 PM Miguel Luis wrote: >> >> The ACPI GTDT table contains two invalid 64-bit physical addresses according >> to >> the ACPI spec. 6.5 [1]. Those are the Counter Control Base physical address >> and >> the Counter

Re: [PATCH v3 6/8] m25p80: Add the w25q256 SFPD table

On [2022 Jul 22] Fri 08:36:00, Cédric Le Goater wrote: > The SFDP table size is 0x100 bytes long. Only the mandatory table for > basic features is available at byte 0x80. > > Signed-off-by: Cédric Le Goater > --- > hw/block/m25p80_sfdp.h | 2 ++ > hw/block/m25p80.c | 3 ++- >

[PATCH] target/arm: Make the final stage1+2 write to secure be unconditional

While the stage2 call to get_phys_addr_lpae should never set attrs.secure when given a non-secure input, it's just as easy to make the final update to attrs.secure be unconditional and false in the case of non-secure input. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- Hi

[PATCH v7 5/5] hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE

This Data Object Exchange Mailbox allows software to query the latency and bandwidth between ports on the switch. For now only provide information on routes between the upstream port and each downstream port (not p2p). Signed-off-by: Jonathan Cameron --- hw/pci-bridge/cxl_upstream.c | 182

Re: [PATCH v3] win32: set threads name

On 10/7/22 02:52, Marc-André Lureau wrote: Hi On Fri, Oct 7, 2022 at 1:04 AM Richard Henderson > wrote: On 10/6/22 05:51, Marc-André Lureau wrote: > Hi Richard > > On Mon, Oct 3, 2022 at 11:39 AM Marc-André Lureau

[PATCH v7 2/5] hw/mem/cxl-type3: Add MSIX support

This will be used by several upcoming patch sets so break it out such that it doesn't matter which one lands first. Signed-off-by: Jonathan Cameron --- hw/mem/cxl_type3.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index

Re: [PATCH v3 7/8] m25p80: Add the w25q512jv SFPD table

On [2022 Jul 22] Fri 08:36:01, Cédric Le Goater wrote: > The SFDP table size is 0x100 bytes long. The mandatory table for basic > features is available at byte 0x80 and two extra Winbond specifics > table are available at 0xC0 and 0xF0. > > Signed-off-by: Cédric Le Goater > --- >

Re: [PATCH 0/4] Add a new backend for cryptodev

On Mon, Sep 19, 2022 at 11:53:16AM +0800, Lei He wrote: > This patch adds a new backend called LKCF to cryptodev, LKCF stands > for Linux Kernel Cryptography Framework. If a cryptographic > accelerator that supports LKCF is installed on the the host (you can > see which algorithms are supported in

[PATCH v7 1/5] hw/pci: PCIe Data Object Exchange emulation

From: Huai-Cheng Kuo Emulation of PCIe Data Object Exchange (DOE) PCIE Base Specification r6.0 6.3 Data Object Exchange Supports multiple DOE PCIe Extended Capabilities for a single PCIe device. For each capability, a static array of DOEProtocol should be passed to pcie_doe_init(). The

Re: [PATCH 1/2] vhost-user: Refactor vhost acked features saving

On Fri, Oct 07, 2022 at 10:01:21AM -0400, Michael S. Tsirkin wrote: On Mon, Sep 26, 2022 at 02:36:40PM +0800, huang...@chinatelecom.cn wrote: From: Hyman Huang(黄勇) Abstract vhost acked features saving into vhost_user_save_acked_features, export it as util function. Signed-off-by: Hyman

[PATCH v2 3/3] tests/acpi: virt: update ACPI GTDT binaries

Step 6 & 7 of the bios-tables-test.c documented procedure. Differences between disassembled ASL files for GTDT: @@ -13,14 +13,14 @@ [000h 4]Signature : "GTDT"[Generic Timer Description Table] [004h 0004 4] Table Length : 0060

Re: [PATCH v3 2/8] m25p80: Add the n25q256a SFDP table

On [2022 Jul 22] Fri 08:35:56, Cédric Le Goater wrote: > The same values were collected on 4 differents OpenPower systems, > palmettos, romulus and tacoma. > > The SFDP table size is defined as being 0x100 bytes but it could be > bigger. Only the mandatory table for basic features is available at

Re: [PATCH v3 5/8] m25p80: Add the mx66l1g45g SFDP table

On [2022 Jul 22] Fri 08:35:59, Cédric Le Goater wrote: > The SFDP table size is 0x200 bytes long. The mandatory table for basic > features is available at byte 0x30 plus some more Macronix specific > tables. > > Signed-off-by: Cédric Le Goater > --- > hw/block/m25p80_sfdp.h | 2 +- >

Re: [PATCH 1/2] vhost-user: Refactor vhost acked features saving

On Mon, Sep 26, 2022 at 02:36:40PM +0800, huang...@chinatelecom.cn wrote: > From: Hyman Huang(黄勇) > > Abstract vhost acked features saving into > vhost_user_save_acked_features, export it as util function. > > Signed-off-by: Hyman Huang(黄勇) > Signed-off-by: Guoyi Tu > --- >

[PATCH v2 1/3] tests/acpi: virt: allow acpi GTDT changes

Step 3 from bios-tables-test.c documented procedure. Signed-off-by: Miguel Luis Acked-by: Ani Sinha --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h

Re: [PATCH v3 1/2] qpci_device_enable: Allow for command bits hardwired to 0

On Sun, Sep 25, 2022 at 09:37:58AM +, Lev Kujawski wrote: > Devices like the PIIX3/4 IDE controller do not support certain modes > of operation, such as memory space accesses, and indicate this lack of > support by hardwiring the applicable bits to zero. Extend the QEMU > PCI device testing

Re: [PATCH RFC] hw/cxl: type 3 devices can now present volatile or persistent memory

Now that i've had some time to look at the spec, the DVSEC CXL Capability register (8.1.3.1 in 3.0 spec) only supports enabling two HDM ranges at the moment, which to me means we should implement memdev0=..., memdev1=... Yesterday I pushed a patch proposal that separated the regions into

Re: [PATCH v8 2/8] KVM: Extend the memslot to support fd-based private memory

On Fri, Oct 07, 2022, Jarkko Sakkinen wrote: > On Thu, Oct 06, 2022 at 03:34:58PM +, Sean Christopherson wrote: > > On Thu, Oct 06, 2022, Jarkko Sakkinen wrote: > > > On Thu, Oct 06, 2022 at 05:58:03PM +0300, Jarkko Sakkinen wrote: > > > > On Thu, Sep 15, 2022 at 10:29:07PM +0800, Chao Peng

[PATCH v2 0/3] fix for two ACPI GTDT physical addresses

The ACPI GTDT table contains two invalid 64-bit physical addresses according to the ACPI spec. 6.5 [1]. Those are the Counter Control Base physical address and the Counter Read Base physical address. Those fields of the GTDT table should be set to 0x if not provided, rather than

Re: [PATCH] error handling: Use TFR() macro where applicable

On Freitag, 7. Oktober 2022 13:44:28 CEST Nikita Ivanov wrote: > Hi! Hi Nikita! > Sorry for such a long absence, I've been resolving some other issues in my > life for a while. I've adjusted the patch according to your latest > comments. Could you check it out, please? Sorry for the drill, but

Re: [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS

On Sat, 1 Oct 2022 at 18:04, Richard Henderson wrote: > > Perform the atomic update for hardware management of the access flag > and the dirty bit. > > A limitation of the implementation so far is that the page table > itself must already be writable, i.e. the dirty bit for the stage2 > page

[PATCH v2 2/3] acpi: arm/virt: build_gtdt: fix invalid 64-bit physical addresses

Per the ACPI 6.5 specification, on the GTDT Table Structure, the Counter Control Block Address and Counter Read Block Address fields of the GTDT table should be set to 0x if not provided, rather than 0x0. Fixes: 41041e57085 ("acpi: arm/virt: build_gtdt: use

Re: [External] : Re: [PATCH 3/3] tests/acpi: virt: update ACPI GTDT binaries

> On 21 Sep 2022, at 03:39, Ani Sinha wrote: > > > > On Tue, 20 Sep 2022, Miguel Luis wrote: > >> Step 6 & 7 of the bios-tables-test.c documented procedure. >> >> Differences between disassembled ASL files for GTDT: >> >>@@ -13,14 +13,14 @@ >> [000h 4]

Re: [RFC PATCH 0/4] Idea for using hardfloat in PPC

Richard Henderson writes: > On 10/5/22 07:37, Víctor Colombo wrote: >> However, the impact in performance was not the expected. In x86_64 I >> had a small 3% improvement, while in a Power9 machine there was a small >> performance loss, as can be seem below (100 executions). >> || min

Re: [PATCH v3 4/8] m25p80: Add the mx25l25635f SFPD table

On [2022 Jul 22] Fri 08:35:58, Cédric Le Goater wrote: > The mx25l25635e and mx25l25635f chips have the same JEDEC id but the > mx25l25635f has more capabilities reported in the SFDP table. Support > for 4B opcodes is of interest because it is exploited by the Linux > kernel. > > The SFDP table

Re: [PATCH v4] x86: add etc/phys-bits fw_cfg file

On Fri, Sep 23, 2022 at 08:23:12AM +0200, Gerd Hoffmann wrote: > Hi, > > > > Given newer processors have more than 40 and for older ones we know > > > the possible values for the two relevant x86 vendors we could do > > > something along the lines of: > > > > > >phys-bits >= 41

Re: [PATCH v3 2/2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

On Sun, Sep 25, 2022 at 09:37:59AM +, Lev Kujawski wrote: > One method to enable PCI bus mastering for IDE controllers, often used > by x86 firmware, is to write 0x7 to the PCI command register. Neither > the PIIX3 specification nor actual hardware (a Tyan S1686D system) > permit modification

Re: [PATCH v2 01/11] block.c: assert bs->aio_context is written under BQL and drains

Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben: > Also here ->aio_context is read by I/O threads and written > under BQL. > > Reviewed-by: Hanna Reitz > Signed-off-by: Emanuele Giuseppe Esposito Reviewed-by: Kevin Wolf

Re: [PATCH 1/4] hw/acpi/aml-build: Only generate cluster node in PPTT when specified

On Thu, Sep 22, 2022 at 09:11:40PM +0800, Yicong Yang wrote: > From: Yicong Yang > > Currently we'll always generate a cluster node no matter user has > specified '-smp clusters=X' or not. Cluster is an optional level > and it's unncessary to build it if user don't need. So only generate > it

Re: [PATCH v3 8/8] arm/aspeed: Replace mx25l25635e chip model

On [2022 Jul 22] Fri 08:36:02, Cédric Le Goater wrote: > A mx25l25635f chip model is generally found on these machines. It's > newer and uses 4B opcodes which is better to exercise the support in > the Linux kernel. > > Signed-off-by: Cédric Le Goater Reviewed-by: Francisco Iglesias > --- >

Re: [PATCH v3 3/8] m25p80: Add the mx25l25635e SFPD table

Hi Cedric, On [2022 Jul 22] Fri 08:35:57, Cédric Le Goater wrote: > The SFDP table is 0x80 bytes long. The mandatory table for basic > features is available at byte 0x30 and an extra Macronix specific > table is available at 0x60. > > 4B opcodes are not supported. > > Signed-off-by: Cédric Le

Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr

On Thu, 6 Oct 2022 at 21:58, Richard Henderson wrote: > > On 10/6/22 11:55, Peter Maydell wrote: > > On Thu, 6 Oct 2022 at 19:20, Richard Henderson > > wrote: > >> > >> On 10/6/22 08:22, Peter Maydell wrote: > >>> Yeah, cleared-at-start is fine. But here we're also relying on > >>> the stage 2

Re: [PATCH v2] hw/arm/aspeed: increase Bletchley memory size

On 10/7/22 13:05, Patrick Williams wrote: For the PVT-class hardware we have increased the memory size of this device to 2 GiB. Adjust the device model accordingly. Signed-off-by: Patrick Williams Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed.c | 9 - 1 file

Re: [PATCH 0/4] Only generate cluster node in PPTT when specified

On Thu, Sep 22, 2022 at 09:11:39PM +0800, Yicong Yang wrote: > From: Yicong Yang > > This series mainly change the policy for building a cluster topology node > in PPTT. Previously we'll always build a cluster node in PPTT without > asking the user, after this set the cluster node will be built

Re: [PATCH v4 5/5] test/acpi/bios-tables-test: SSDT: update golden master binaries

Ping... On Tue, 2022-09-27 at 08:30 +0800, Robert Hoo wrote: > On Mon, 2022-09-26 at 15:22 +0200, Igor Mammedov wrote: > > > > 0800200c9a66"), One, 0x05, Local0, One) > > > > +CreateDWordField (Local3, Zero, STTS) > > > > +CreateField (Local3, 0x20, (LEN <<

Re: [External] : Re: [RFC PATCH 2/4] acpi: fadt: support revision 6.0 of the ACPI specification

Hi Ani, > On 7 Oct 2022, at 04:25, Ani Sinha wrote: > > > > On Thu, 6 Oct 2022, Miguel Luis wrote: > >> Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI >> specification adding the field "Hypervisor Vendor Identity" that was missing. >> >> This field's description

Re: ublk-qcow2: ublk-qcow2 is available

On Fri, Oct 07, 2022 at 07:21:51PM +0800, Yongji Xie wrote: > On Fri, Oct 7, 2022 at 6:51 PM Ming Lei wrote: > > > > On Fri, Oct 07, 2022 at 06:04:29PM +0800, Yongji Xie wrote: > > > On Thu, Oct 6, 2022 at 7:24 PM Ming Lei wrote: > > > > > > > > On Wed, Oct 05, 2022 at 08:21:45AM -0400, Stefan

Re: [PATCH v8 2/8] KVM: Extend the memslot to support fd-based private memory

On Thu, Oct 06, 2022 at 03:34:58PM +, Sean Christopherson wrote: > On Thu, Oct 06, 2022, Jarkko Sakkinen wrote: > > On Thu, Oct 06, 2022 at 05:58:03PM +0300, Jarkko Sakkinen wrote: > > > On Thu, Sep 15, 2022 at 10:29:07PM +0800, Chao Peng wrote: > > > > This new extension, indicated by the new

Re: [PATCH] gitmodules: recurse by default

On Fri, Oct 07, 2022 at 11:45:56AM +0100, Daniel P. Berrangé wrote: > On Fri, Oct 07, 2022 at 06:11:25AM -0400, Michael S. Tsirkin wrote: > > On Fri, Oct 07, 2022 at 09:07:17AM +0100, Daniel P. Berrangé wrote: > > > On Thu, Oct 06, 2022 at 08:24:01PM -0400, Michael S. Tsirkin wrote: > > > > On

Re: [PATCH] error handling: Use TFR() macro where applicable

Hi! Sorry for such a long absence, I've been resolving some other issues in my life for a while. I've adjusted the patch according to your latest comments. Could you check it out, please? >From 5389c5ccc8789f8f666ab99e50d38af728bd2c9c Mon Sep 17 00:00:00 2001 From: Nikita Ivanov Date: Wed, 3 Aug

Re: [PATCH v6 09/13] block: add BlockRAMRegistrar

On Thu, Oct 06, 2022 at 05:35:03PM -0400, Stefan Hajnoczi wrote: Emulated devices and other BlockBackend users wishing to take advantage of blk_register_buf() all have the same repetitive job: register RAMBlocks with the BlockBackend using RAMBlockNotifier. Add a BlockRAMRegistrar API to do

[PULL 11/50] nbd: add missing coroutine_fn annotations

From: Paolo Bonzini Callers of coroutine_fn must be coroutine_fn themselves, or the call must be within "if (qemu_in_coroutine())". Apply coroutine_fn to functions where this holds. Reviewed-by: Alberto Faria Reviewed-by: Eric Blake Signed-off-by: Paolo Bonzini Message-Id:

Re: [PATCH] i386: Fix KVM_CAP_ADJUST_CLOCK capability check

Paolo Bonzini writes: > Hi, a similar patch is now in. > Indeed, commit c4ef867f2949bf2a2ae18a4e27cf1a34bbc8aecb Author: Ray Zhang Date: Thu Sep 22 18:05:23 2022 +0800 target/i386/kvm: fix kvmclock_current_nsec: Assertion `time.tsc_timestamp <= migration_tsc' failed solves the

[PULL 48/50] blockjob: remove unused functions

From: Emanuele Giuseppe Esposito These public functions are not used anywhere, thus can be dropped. Signed-off-by: Emanuele Giuseppe Esposito Reviewed-by: Stefan Hajnoczi Reviewed-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id:

Re: [PATCH] i386: Fix KVM_CAP_ADJUST_CLOCK capability check

Hi, a similar patch is now in. Paolo Il ven 7 ott 2022, 05:26 Vitaly Kuznetsov ha scritto: > Vitaly Kuznetsov writes: > > > Vitaly Kuznetsov writes: > > > >> KVM commit c68dc1b577ea ("KVM: x86: Report host tsc and realtime values > in > >> KVM_GET_CLOCK") broke migration of certain

[PULL 49/50] job: remove unused functions

From: Emanuele Giuseppe Esposito These public functions are not used anywhere, thus can be dropped. Also, since this is the final job API that doesn't use AioContext lock and replaces it with job_lock, adjust all remaining function documentation to clearly specify if the job lock is taken or

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