[PATCH v3] target/arm: align exposed ID registers with Linux

[Zhuojia Shen]

In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed.  This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.

Specifically, the following new ID registers/fields are exposed to
userspace:

ID_AA64PFR1_EL1.BT:   bits 3-0
ID_AA64PFR1_EL1.MTE:  bits 11-8
ID_AA64PFR1_EL1.SME:  bits 27-24

ID_AA64ZFR0_EL1.SVEver:   bits 3-0
ID_AA64ZFR0_EL1.AES:  bits 7-4
ID_AA64ZFR0_EL1.BitPerm:  bits 19-16
ID_AA64ZFR0_EL1.BF16: bits 23-20
ID_AA64ZFR0_EL1.SHA3: bits 35-32
ID_AA64ZFR0_EL1.SM4:  bits 43-40
ID_AA64ZFR0_EL1.I8MM: bits 47-44
ID_AA64ZFR0_EL1.F32MM:bits 55-52
ID_AA64ZFR0_EL1.F64MM:bits 59-56

ID_AA64SMFR0_EL1.F32F32:  bit 32
ID_AA64SMFR0_EL1.B16F32:  bit 34
ID_AA64SMFR0_EL1.F16F32:  bit 35
ID_AA64SMFR0_EL1.I8I32:   bits 39-36
ID_AA64SMFR0_EL1.F64F64:  bit 48
ID_AA64SMFR0_EL1.I16I64:  bits 55-52
ID_AA64SMFR0_EL1.FA64:bit 63

ID_AA64MMFR0_EL1.ECV: bits 63-60

ID_AA64MMFR1_EL1.AFP: bits 47-44

ID_AA64MMFR2_EL1.AT:  bits 35-32

ID_AA64ISAR0_EL1.RNDR:bits 63-60

ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
ID_AA64ISAR1_EL1.BF16:bits 47-44
ID_AA64ISAR1_EL1.DGH: bits 51-48
ID_AA64ISAR1_EL1.I8MM:bits 55-52

ID_AA64ISAR2_EL1.WFxT:bits 3-0
ID_AA64ISAR2_EL1.RPRES:   bits 7-4
ID_AA64ISAR2_EL1.GPA3:bits 11-8
ID_AA64ISAR2_EL1.APA3:bits 15-12

The code is also refactored to use symbolic names for ID register fields
for better readability and maintainability.

The test case in tests/tcg/aarch64/sysregs.c is also updated to match
the intended behavior.

Signed-off-by: Zhuojia Shen 
---
This incorporates updates to a test case in tests/tcg/aarch64/sysregs.c
and to the Makefile that builds the test (it requires a more recent
-march flag to test id_aa64smfr0_el1), as well as a fix to a bug that
mistakenly exposed some fields in id_aa64mmfr0_el1 which should not be
exposed otherwise, thanks to Peter Maydell 
for running the test and spotting the error.

 target/arm/helper.c   | 96 +--
 tests/tcg/aarch64/Makefile.target |  7 ++-
 tests/tcg/aarch64/sysregs.c   | 17 --
 3 files changed, 96 insertions(+), 24 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index bac2ea62c4..9feb8789e8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7864,31 +7864,89 @@ void register_cp_regs_for_features(ARMCPU *cpu)
 #ifdef CONFIG_USER_ONLY
 static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
 { .name = "ID_AA64PFR0_EL1",
-  .exported_bits = 0x000f000f00ff,
-  .fixed_bits= 0x0011 },
+  .exported_bits = R_ID_AA64PFR0_FP_MASK |
+   R_ID_AA64PFR0_ADVSIMD_MASK |
+   R_ID_AA64PFR0_SVE_MASK |
+   R_ID_AA64PFR0_DIT_MASK,
+  .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
+(0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
 { .name = "ID_AA64PFR1_EL1",
-  .exported_bits = 0x00f0 },
+  .exported_bits = R_ID_AA64PFR1_BT_MASK |
+   R_ID_AA64PFR1_SSBS_MASK |
+   R_ID_AA64PFR1_MTE_MASK |
+   R_ID_AA64PFR1_SME_MASK },
 { .name = "ID_AA64PFR*_EL1_RESERVED",
-  .is_glob = true },
-{ .name = "ID_AA64ZFR0_EL1"   },
+  .is_glob = true },
+{ .name = "ID_AA64ZFR0_EL1",
+  .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
+   R_ID_AA64ZFR0_AES_MASK |
+   R_ID_AA64ZFR0_BITPERM_MASK |
+   R_ID_AA64ZFR0_BFLOAT16_MASK |
+   R_ID_AA64ZFR0_SHA3_MASK |
+   R_ID_AA64ZFR0_SM4_MASK |
+   R_ID_AA64ZFR0_I8MM_MASK |
+   R_ID_AA64ZFR0_F32MM_MASK |
+   R_ID_AA64ZFR0_F64MM_MASK },
+{ .name = "ID_AA64SMFR0_EL1",
+  .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
+   R_ID_AA64SMFR0_B16F32_MASK |
+   R_ID_AA64SMFR0_F16F32_MASK |
+   R_ID_AA64SMFR0_I8I32_MASK |
+   R_ID_AA64SMFR0_F64F64_MASK |
+   R_ID_AA64SMFR0_I16I64_MASK |
+   R_ID_AA64SMFR0_FA64_MASK },
 { .name = "ID_AA64MMFR0_EL1",
-  .fixed_bits= 0xff00 },
-{ .name = "ID_AA64MMFR1_EL1"  },
+  .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
+  .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
+(0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
+{ .name = 

Re: [PATCH 5/5] target/s390x/tcg/excp_helper: Restrict system headers to sysemu

[Richard Henderson]

On 12/16/22 14:04, Philippe Mathieu-Daudé wrote:

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/s390x/tcg/excp_helper.c | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index fe02d82201..e9eb7c455e 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -21,15 +21,15 @@
  #include "qemu/osdep.h"
  #include "qemu/log.h"
  #include "cpu.h"
-#include "s390x-internal.h"
  #include "exec/helper-proto.h"
-#include "qemu/timer.h"
  #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
-#include "hw/s390x/ioinst.h"
-#include "exec/address-spaces.h"
+#include "s390x-internal.h"
  #include "tcg_s390x.h"
  #ifndef CONFIG_USER_ONLY
+#include "qemu/timer.h"
+#include "exec/cpu_ldst.h"


cpu_ldst.h is not a system header.  The others look plausible.


r~


+#include "exec/address-spaces.h"
+#include "hw/s390x/ioinst.h"
  #include "hw/s390x/s390_flic.h"
  #include "hw/boards.h"
  #endif

Re: [PATCH 4/5] target/s390x/tcg/misc_helper: Remove unused "memory.h" include

[Richard Henderson]

On 12/16/22 14:04, Philippe Mathieu-Daudé wrote:

Signed-off-by: Philippe Mathieu-Daudé
---
  target/s390x/tcg/misc_helper.c | 1 -
  1 file changed, 1 deletion(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 1/5] exec/memory: Expose memory_region_access_valid()

[Richard Henderson]

On 12/16/22 14:04, Philippe Mathieu-Daudé wrote:

Instead of having hardware device poking into memory
internal API, expose memory_region_access_valid().

Signed-off-by: Philippe Mathieu-Daudé
---
  hw/s390x/s390-pci-inst.c   | 2 +-
  include/exec/memory-internal.h | 4 
  include/exec/memory.h  | 4 
  3 files changed, 5 insertions(+), 5 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 10/10] target/xtensa/cpu: Include missing "memory.h" header

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

Under system emulation, xtensa_cpu_initfn() calls
memory_region_init_io(), itself declared in "exec/memory.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/xtensa/cpu.c | 3 +++
  1 file changed, 3 insertions(+)


Reviewed-by: Richard Henderson 


r~

Re: [PATCH 08/10] target/riscv/cpu: Restrict sysemu-specific fields from CPUArchState

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

The 'hwaddr' type is only available / meaningful on system emulation.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/riscv/cpu.h | 34 ++
  1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fc1f72e5c3..bd4e16d946 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -368,16 +368,6 @@ struct CPUArchState {
  uint64_t menvcfg;
  target_ulong senvcfg;
  uint64_t henvcfg;
-#endif
-target_ulong cur_pmmask;
-target_ulong cur_pmbase;
-
-float_status fp_status;
-
-/* Fields from here on are preserved across CPU reset. */
-QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
-QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
-bool vstime_irq;
  
  hwaddr kernel_addr;

  hwaddr fdt_addr;
@@ -388,6 +378,16 @@ struct CPUArchState {
  uint64_t kvm_timer_compare;
  uint64_t kvm_timer_state;
  uint64_t kvm_timer_frequency;
+#endif
+target_ulong cur_pmmask;
+target_ulong cur_pmbase;
+
+float_status fp_status;
+
+/* Fields from here on are preserved across CPU reset. */
+QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
+QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
+bool vstime_irq;
  };


Except for fp_status, all of the other fields that you move are sysemu specific.


r~

Re: [PATCH 07/10] target/ppc/internal: Restrict MMU declarations to sysemu

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/ppc/internal.h | 5 +
  1 file changed, 5 insertions(+)

diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 337a362205..901bae6d39 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -242,9 +242,12 @@ static inline int prot_for_access_type(MMUAccessType 
access_type)
  g_assert_not_reached();
  }
  
+#ifndef CONFIG_USER_ONLY

+
  /* PowerPC MMU emulation */
  
  typedef struct mmu_ctx_t mmu_ctx_t;

+
  bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
int mmu_idx, bool guest_visible);
@@ -266,6 +269,8 @@ struct mmu_ctx_t {
  int nx;/* Non-execute area  */
  };
  
+#endif /* !CONFIG_USER_ONLY */


Eh.  I suppose.

Reviewed-by: Richard Henderson 


r~

Re: [PATCH 04/10] target/loongarch/cpu: Restrict "memory.h" header to sysemu

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

Missed in 0093b9a5ee ("target/loongarch: Adjust functions
and structure to support user-mode") while cleaning commit
f84a2aacf5 ("target/loongarch: Add LoongArch IOCSR instruction").

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/loongarch/cpu.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index c8612f5466..2f17ac6b47 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -12,7 +12,9 @@
  #include "fpu/softfloat-types.h"
  #include "hw/registerfields.h"
  #include "qemu/timer.h"
+#ifndef CONFIG_USER_ONLY
  #include "exec/memory.h"
+#endif
  #include "cpu-csr.h"

Reviewed-by: Richard Henderson 


r~

Re: [PATCH 06/10] target/ppc/helper: Include missing "cpu.h" header

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

'dh_ctype_*' are defined as 'ppc_avr_t/ppc_vsr_t/ppc_acc_t',
themselves declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/ppc/helper.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8dd22a35e4..a02db8d893 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -1,3 +1,5 @@
+#include "cpu.h"


No, see patch 1.


r~

Re: [PATCH 05/10] target/m68k/helper: Include missing "cpu.h" header

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

'dh_ctype_fp' is defined as 'FPReg *', itself declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/m68k/helper.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index c9bed2b884..aaf0e1668e 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -1,3 +1,5 @@
+#include "cpu.h"
+
  DEF_HELPER_1(bitrev, i32, i32)
  DEF_HELPER_1(ff1, i32, i32)
  DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32)


No, see patch 1.

r~

Re: [PATCH 03/10] target/loongarch/cpu: Remove unused "sysbus.h" header

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

Nothing requires SysBus declarations here.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/loongarch/cpu.h | 1 -
  1 file changed, 1 deletion(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 02/10] target/hexagon: Declare hexagon_regnames[] in "cpu.h"

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

The hexagon_regnames array has TOTAL_PER_THREAD_REGS elements.
TOTAL_PER_THREAD_REGS is defined in "cpu.h". Instead of pulling
"cpu.h" in "internal.h", move the hexagon_regnames[] declaration
to "cpu.h".


I don't think this is correct.
I would have expected cpu.h to already be included by all users of internal.h, thus any 
formal re-inclusion of cpu.h at the top of internal.h should be a no-op.



r~

Re: [PATCH 01/10] target/hppa/helper: Include missing "cpu.h" header

[Richard Henderson]

On 12/16/22 14:05, Philippe Mathieu-Daudé wrote:

'dh_ctype_tr' is defined as 'target_ureg', itself declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/hppa/helper.h | 2 ++
  1 file changed, 2 insertions(+)


No, helper.h is multiply included.
It should probably be renamed across all target/*/.


r~

Re: [PATCH 2/2] sysemu/kvm: Reduce target-specific declarations

[Richard Henderson]

On 12/16/22 14:07, Philippe Mathieu-Daudé wrote:

Only the declarations using the target_ulong type are
target specific.

Signed-off-by: Philippe Mathieu-Daudé 
---
  include/sysemu/kvm.h | 25 -
  1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index c8281c07a7..a53d6dab49 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -242,9 +242,6 @@ bool kvm_arm_supports_user_irq(void);
  int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
  int kvm_on_sigbus(int code, void *addr);
  
-#ifdef NEED_CPU_H

-#include "cpu.h"
-
  void kvm_flush_coalesced_mmio_buffer(void);
  
  /**

@@ -410,6 +407,9 @@ void kvm_get_apic_state(DeviceState *d, struct 
kvm_lapic_state *kapic);
  struct kvm_guest_debug;
  struct kvm_debug_exit_arch;
  
+#ifdef NEED_CPU_H

+#include "cpu.h"
+
  struct kvm_sw_breakpoint {
  target_ulong pc;
  target_ulong saved_insn;
@@ -436,6 +436,15 @@ void kvm_arch_update_guest_debug(CPUState *cpu, struct 
kvm_guest_debug *dbg);
  
  bool kvm_arch_stop_on_emulation_error(CPUState *cpu);
  
+uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,

+  uint32_t index, int reg);
+uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
+
+int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
+   hwaddr *phys_addr);


Why did these need to move?


r~


+
+#endif /* NEED_CPU_H */
+
  int kvm_check_extension(KVMState *s, unsigned int extension);
  
  int kvm_vm_check_extension(KVMState *s, unsigned int extension);

@@ -464,18 +473,8 @@ int kvm_vm_check_extension(KVMState *s, unsigned int 
extension);
  kvm_vcpu_ioctl(cpu, KVM_ENABLE_CAP, );   \
  })
  
-uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,

-  uint32_t index, int reg);
-uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
-
-
  void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len);
  
-int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,

-   hwaddr *phys_addr);
-
-#endif /* NEED_CPU_H */
-
  void kvm_cpu_synchronize_state(CPUState *cpu);
  
  void kvm_init_cpu_signals(CPUState *cpu);

Re: [PATCH 1/2] sysemu/kvm: Remove CONFIG_USER_ONLY guard

[Richard Henderson]

On 12/16/22 14:07, Philippe Mathieu-Daudé wrote:

User emulation shouldn't really include this header; if included
these declarations are guarded by CONFIG_KVM_IS_POSSIBLE.

Signed-off-by: Philippe Mathieu-Daudé
---
  include/sysemu/kvm.h | 2 --
  1 file changed, 2 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 5/5] hw/i386/x86: Reduce init_topo_info() scope

[Richard Henderson]

On 12/16/22 14:01, Philippe Mathieu-Daudé wrote:

This function is not used anywhere outside this file, so
we can delete the prototype from include/hw/i386/x86.h and
make the function "static void".

This fixes when building with -Wall and using Clang
("Apple clang version 14.0.0 (clang-1400.0.29.202)"):

   ../hw/i386/x86.c:70:24: error: static function 'MACHINE' is used in an 
inline function with external linkage [-Werror,-Wstatic-in-inline]
   MachineState *ms = MACHINE(x86ms);
  ^
   include/hw/i386/x86.h:101:1: note: use 'static' to give inline function 
'init_topo_info' internal linkage
   void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
   ^
   static
   include/hw/boards.h:24:49: note: 'MACHINE' declared here
   OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
   ^

Reported-by: Stefan Weil
Suggested-by: Peter Maydell
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
  hw/i386/x86.c | 2 +-
  include/hw/i386/x86.h | 3 ---
  2 files changed, 1 insertion(+), 4 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 4/5] target/i386: Remove x86_cpu_dump_local_apic_state() dead stub

[Richard Henderson]

On 12/16/22 14:01, Philippe Mathieu-Daudé wrote:

x86_cpu_dump_local_apic_state() is called from monitor.c which
is only compiled for system emulation since commit bf95728400
("monitor: remove target-specific code from monitor.c").

Interestingly this stub was added few weeks later in commit
1f871d49e3 ("hmp: added local apic dump state") and was not
necessary by that time.


Crossed in-flight, presumably.

Reviewed-by: Richard Henderson 


r~

Re: [PATCH 3/5] target/i386/ops_sse: Include missing "cpu.h" header

[Richard Henderson]

On 12/16/22 14:01, Philippe Mathieu-Daudé wrote:

'Reg' is defined as 'MMXReg', itself declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/i386/ops_sse.h| 1 +
  target/i386/ops_sse_header.h | 3 +++
  2 files changed, 4 insertions(+)


No, both of these are multiply included.
If you like, rename them "*.inc.h".


r~

Re: [PATCH 2/5] target/i386/cpu: Remove dead helper_lock() declaration

[Richard Henderson]

On 12/16/22 14:01, Philippe Mathieu-Daudé wrote:

Missed in commit 37b995f6e7 ("target-i386: remove helper_lock()").

Signed-off-by: Philippe Mathieu-Daudé
---
  target/i386/cpu.h | 3 ---
  1 file changed, 3 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 1/5] target/i386: Remove NEED_CPU_H guard from target-specific headers

[Richard Henderson]

On 12/16/22 14:01, Philippe Mathieu-Daudé wrote:

NEED_CPU_H is always defined for these target-specific headers.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/i386/hax/hax-i386.h | 2 --
  target/i386/hvf/hvf-i386.h | 4 
  2 files changed, 6 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 5/5] target/arm: only perform TCG cpu and machine inits if TCG enabled

[Richard Henderson]

On 12/16/22 13:29, Fabiano Rosas wrote:

-/*
- * Misaligned thumb pc is architecturally impossible.
- * We have an assert in thumb_tr_translate_insn to verify this.
- * Fail an incoming migrate to avoid this assert.
- */
-if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-return -1;
-}
+/*
+ * Misaligned thumb pc is architecturally impossible.
+ * We have an assert in thumb_tr_translate_insn to verify this.
+ * Fail an incoming migrate to avoid this assert.
+ */
+if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+return -1;
+}


This is a sanity check rejecting malformed vmsave.  While hw virt won't have the same 
assert as mentioned in the comment, it won't be happy and will raise some sort of cpu 
exception later.  I think it's better to reject the bad vmload early.  I suppose we could 
expand the comment to that effect, so that it doesn't appear to be wholly tcg inspired.


Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH 3/5] target/arm: wrap semihosting and psci calls with tcg_enabled

[Richard Henderson]

On 12/16/22 13:29, Fabiano Rosas wrote:

-if (arm_is_psci_call(cpu, cs->exception_index)) {
-arm_handle_psci_call(cpu);
-qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
-return;
-}
+if (tcg_enabled()) {
+if (arm_is_psci_call(cpu, cs->exception_index)) {


This could be

if (tcg_enabled() && arm_is_psci_call(...))

because...


-/*
- * Semihosting semantics depend on the register width of the code
- * that caused the exception, not the target exception level, so
- * must be handled here.
- */
+/*
+ * Semihosting semantics depend on the register width of the code
+ * that caused the exception, not the target exception level, so
+ * must be handled here.
+ */
  #ifdef CONFIG_TCG
-if (cs->exception_index == EXCP_SEMIHOST) {
-tcg_handle_semihosting(cs);
-return;
-}
+if (cs->exception_index == EXCP_SEMIHOST) {


If you were able to replace the ifdef, that would be one thing, but since you aren't I 
don't think this requires a separate check.  There is no way to generate EXCP_SEMIHOST 
except via TCG.


I guess I don't insist, since you're working toward Claudio's much larger patch 
set, so

Reviewed-by: Richard Henderson 


r~

Re: [PATCH 2/5] target/arm: rename handle_semihosting to tcg_handle_semihosting

[Richard Henderson]

On 12/16/22 13:29, Fabiano Rosas wrote:

From: Claudio Fontana 

make it clearer from the name that this is a tcg-only function.

Signed-off-by: Claudio Fontana 
Signed-off-by: Fabiano Rosas 
---
This function moves elsewhere in the original series, but the name
change doesn't need to wait.

Originally from:
[RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting
https://lore.kernel.org/r/20210416162824.25131-39-cfont...@suse.de


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v3 1/5] dump: Include missing "cpu.h" header for tswap32/tswap64() declarations

[Richard Henderson]

On 12/16/22 13:55, Philippe Mathieu-Daudé wrote:

Signed-off-by: Philippe Mathieu-Daudé 
---
  dump/dump.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/dump/dump.c b/dump/dump.c
index 279b07f09b..c62dc94213 100644
--- a/dump/dump.c
+++ b/dump/dump.c
@@ -29,6 +29,7 @@
  #include "qemu/main-loop.h"
  #include "hw/misc/vmcoreinfo.h"
  #include "migration/blocker.h"
+#include "cpu.h"


Does it work to include "exec/cpu-all.h" instead?


r~

Re: [PATCH v2 2/2] hw/arm/smmu-common: Avoid using inlined functions with external linkage

[Richard Henderson]

On 12/16/22 13:49, Philippe Mathieu-Daudé wrote:

When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
and building with -Wall we get:

   hw/arm/smmu-common.c:173:33: warning: static function 
'smmu_hash_remove_by_asid_iova' is used in an inline function with external 
linkage [-Wstatic-in-inline]
   hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 
'smmu_iotlb_inv_iova' internal linkage
 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
 ^
 static

None of our code base require / use inlined functions with external
linkage. Some places use internal inlining in the hot path. These
two functions are certainly not in any hot path and don't justify
any inlining, so these are likely oversights rather than intentional.

Reported-by: Stefan Weil
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
  hw/arm/smmu-common.c | 13 ++---
  1 file changed, 6 insertions(+), 7 deletions(-)



Reviewed-by: Richard Henderson 


r~

Re: [PATCH v2 1/2] hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope

[Richard Henderson]

On 12/16/22 13:49, Philippe Mathieu-Daudé wrote:

This function is not used anywhere outside this file,
so we can make the function "static void".

Signed-off-by: Philippe Mathieu-Daudé 


Reviewed-by: Richard Henderson 

r~

Re: [PATCH] scripts/git.orderfile: Display MAINTAINERS changes first

[Richard Henderson]

On 12/16/22 14:55, Philippe Mathieu-Daudé wrote:

If we get custom to see MAINTAINERS changes first,
we might catch missing MAINTAINERS updates easier.

Signed-off-by: Philippe Mathieu-Daudé 
---
  scripts/git.orderfile | 2 ++
  1 file changed, 2 insertions(+)


Reviewed-by: Richard Henderson 


r~

Re: [PATCH 2/2] meson: Set avx512f option to auto

[Richard Henderson]

On 12/16/22 15:08, Paolo Bonzini wrote:
Because that's what configure used to do 
(https://lists.nongnu.org/archive/html/qemu-devel/2022-02/msg00650.html). 
..


Yeah, but I wondered if that was just a bug.

It can surely be changed but AVX512 is known to limit processor frequency. I am not sure 
if the limitation is per core or extends to multiple cores, and it would be a pity if 
guests were slowed down even further during migration.


Hmm.  Should we simply remove it?

Especially after the bulk phase buffer_is_zero performance matters a lot less so you'd pay 
the price of AVX512 for little gain. After the bulk phase it may even make sense to just 
use SSE, since even AVX requires a voltage transition[1] from what I saw at 
https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html 
.


Ouch, never heard of that.

I'm not going to worry about it, because glibc str* routines make the same choice to use 
AVX2, as does TCG, so I can only imagine that for the most part we're continually in and 
out of 256-bit avx mode.


Anyway, I'll drop this patch.


r~

Re: [PATCH 2/5] hw/s390x/pv: Un-inline s390_pv_init()

[Philippe Mathieu-Daudé]

On 16/12/22 23:04, Philippe Mathieu-Daudé wrote:

There is no point in having s390_pv_init() inlined.

Signed-off-by: Philippe Mathieu-Daudé 
---
  hw/s390x/pv.c | 13 +
  include/hw/s390x/pv.h | 14 +-
  2 files changed, 14 insertions(+), 13 deletions(-)




diff --git a/include/hw/s390x/pv.h b/include/hw/s390x/pv.h
index 9360aa1091..5bca5bcaf1 100644
--- a/include/hw/s390x/pv.h
+++ b/include/hw/s390x/pv.h
@@ -12,7 +12,6 @@
  #ifndef HW_S390_PV_H
  #define HW_S390_PV_H
  
-#include "qapi/error.h"

  #include "sysemu/kvm.h"
  
  #ifdef CONFIG_KVM

@@ -78,17 +77,6 @@ static inline int kvm_s390_dump_completion_data(void *buff) 
{ return 0; }
  #endif /* CONFIG_KVM */
  
  int s390_pv_kvm_init(ConfidentialGuestSupport *cgs, Error **errp);

-static inline int s390_pv_init(ConfidentialGuestSupport *cgs, Error **errp)
-{
-if (!cgs) {
-return 0;
-}
-if (kvm_enabled()) {
-return s390_pv_kvm_init(cgs, errp);
-}
-
-error_setg(errp, "Protected Virtualization requires KVM");
-return -1;
-}
+int s390_pv_init(ConfidentialGuestSupport *cgs, Error **errp);


OK I understood why this function is inlined. It is called from:

$ git grep s390_pv_init
hw/s390x/pv.c:29:int s390_pv_init(ConfidentialGuestSupport *cgs, Error 
**errp)

hw/s390x/s390-virtio-ccw.c:259:s390_pv_init(machine->cgs, _fatal);
include/hw/s390x/pv.h:86:int s390_pv_init(ConfidentialGuestSupport *cgs, 
Error **errp);


Now note in meson.build:

s390x_ss.add(when: 'CONFIG_KVM', if_true: files(
  'tod-kvm.c',
  's390-skeys-kvm.c',
  's390-stattrib-kvm.c',
  'pv.c',
  's390-pci-kvm.c',
))

So when CONFIG_KVM=false s390-virtio-ccw.c doesn't have to link with
the kvm-specific pv.o.

I'll rework this patch.

Re: [PATCH 2/2] meson: Set avx512f option to auto

[Paolo Bonzini]

Because that's what configure used to do (
https://lists.nongnu.org/archive/html/qemu-devel/2022-02/msg00650.html)...

It can surely be changed but AVX512 is known to limit processor frequency.
I am not sure if the limitation is per core or extends to multiple cores,
and it would be a pity if guests were slowed down even further during
migration.

Especially after the bulk phase buffer_is_zero performance matters a lot
less so you'd pay the price of AVX512 for little gain. After the bulk phase
it may even make sense to just use SSE, since even AVX requires a voltage
transition[1] from what I saw at
https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html.

Paolo

[1] voltage transitions slow down the processor during the transition

Il dom 4 dic 2022, 02:51 Richard Henderson 
ha scritto:

> I'm not sure why this option wasn't set the same as avx2.
>
> Signed-off-by: Richard Henderson 
> ---
>  meson_options.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/meson_options.txt b/meson_options.txt
> index 4b749ca549..f98ee101e2 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -102,7 +102,7 @@ option('membarrier', type: 'feature', value:
> 'disabled',
>
>  option('avx2', type: 'feature', value: 'auto',
> description: 'AVX2 optimizations')
> -option('avx512f', type: 'feature', value: 'disabled',
> +option('avx512f', type: 'feature', value: 'auto',
> description: 'AVX512F optimizations')
>  option('keyring', type: 'feature', value: 'auto',
> description: 'Linux keyring support')
> --
> 2.34.1
>
>

[PATCH] scripts/git.orderfile: Display MAINTAINERS changes first

[Philippe Mathieu-Daudé]

If we get custom to see MAINTAINERS changes first,
we might catch missing MAINTAINERS updates easier.

Signed-off-by: Philippe Mathieu-Daudé 
---
 scripts/git.orderfile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/scripts/git.orderfile b/scripts/git.orderfile
index b32203b710..8edac0380b 100644
--- a/scripts/git.orderfile
+++ b/scripts/git.orderfile
@@ -9,6 +9,8 @@
 #   git config diff.orderFile scripts/git.orderfile
 #
 
+MAINTAINERS
+
 # Documentation
 docs/*
 *.rst
-- 
2.38.1

[PATCH] exec/helper-head: Include missing "fpu/softfloat-types.h" header

[Philippe Mathieu-Daudé]

'dh_ctype_f32' is defined as 'float32', itself declared
in "fpu/softfloat-types.h". Include this header to avoid
when refactoring other headers:

  In file included from include/exec/helper-proto.h:7,
   from include/tcg/tcg-op.h:29,
   from ../../tcg/tcg-op-vec.c:22:
  include/exec/helper-head.h:44:22: error: unknown type name ‘float32’; did you 
mean ‘_Float32’?
 44 | #define dh_ctype_f32 float32
|  ^~~

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/exec/helper-head.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 584b120312..325a42b14e 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -18,6 +18,8 @@
 #ifndef EXEC_HELPER_HEAD_H
 #define EXEC_HELPER_HEAD_H
 
+#include "fpu/softfloat-types.h"
+
 #define HELPER(name) glue(helper_, name)
 
 /* Some types that make sense in C, but not for TCG.  */
-- 
2.38.1

RE: [PATCH 02/10] target/hexagon: Declare hexagon_regnames[] in "cpu.h"

[Taylor Simpson]

> -Original Message-
> From: Philippe Mathieu-Daudé 
> Sent: Friday, December 16, 2022 4:06 PM
> To: qemu-devel@nongnu.org
> Cc: Daniel Henrique Barboza ; David Gibson
> ; Xiaojuan Yang
> ; Mark Cave-Ayland  ayl...@ilande.co.uk>; Bin Meng ; Richard
> Henderson ; Artyom Tarasenko
> ; Cédric Le Goater ; Song Gao
> ; Alistair Francis ; qemu-
> p...@nongnu.org; Laurent Vivier ; Palmer Dabbelt
> ; Taylor Simpson ; Greg
> Kurz ; qemu-ri...@nongnu.org; Max Filippov
> ; Philippe Mathieu-Daudé 
> Subject: [PATCH 02/10] target/hexagon: Declare hexagon_regnames[] in
> "cpu.h"
> 
> The hexagon_regnames array has TOTAL_PER_THREAD_REGS elements.
> TOTAL_PER_THREAD_REGS is defined in "cpu.h". Instead of pulling "cpu.h" in
> "internal.h", move the hexagon_regnames[] declaration to "cpu.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/hexagon/cpu.h  | 2 ++
>  target/hexagon/internal.h | 2 --
>  2 files changed, 2 insertions(+), 2 deletions(-)

Why is this needed?  internal.h doesn't directly include cpu.h.

If the goal is to reduce the number of places where internal.h is included, 
then there would be additional changes.

If the concern is the dependence on TOTAL_PER_THREAD_REGS in internal.h, just 
change it to
extern const char * const hexagon_regnames[];

Thanks,
Taylor

[PATCH 5/5] target/s390x/tcg/excp_helper: Restrict system headers to sysemu

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/s390x/tcg/excp_helper.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index fe02d82201..e9eb7c455e 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -21,15 +21,15 @@
 #include "qemu/osdep.h"
 #include "qemu/log.h"
 #include "cpu.h"
-#include "s390x-internal.h"
 #include "exec/helper-proto.h"
-#include "qemu/timer.h"
 #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
-#include "hw/s390x/ioinst.h"
-#include "exec/address-spaces.h"
+#include "s390x-internal.h"
 #include "tcg_s390x.h"
 #ifndef CONFIG_USER_ONLY
+#include "qemu/timer.h"
+#include "exec/cpu_ldst.h"
+#include "exec/address-spaces.h"
+#include "hw/s390x/ioinst.h"
 #include "hw/s390x/s390_flic.h"
 #include "hw/boards.h"
 #endif
-- 
2.38.1

[PATCH 02/10] target/hexagon: Declare hexagon_regnames[] in "cpu.h"

[Philippe Mathieu-Daudé]

The hexagon_regnames array has TOTAL_PER_THREAD_REGS elements.
TOTAL_PER_THREAD_REGS is defined in "cpu.h". Instead of pulling
"cpu.h" in "internal.h", move the hexagon_regnames[] declaration
to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/hexagon/cpu.h  | 2 ++
 target/hexagon/internal.h | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 2a65a57bab..9e8cd5a257 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -178,6 +178,8 @@ typedef HexagonCPU ArchCPU;
 
 void hexagon_translate_init(void);
 
+extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
+
 #include "exec/cpu-all.h"
 
 #endif /* HEXAGON_CPU_H */
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index b1bfadc3f5..1a6386e0ac 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -38,6 +38,4 @@ void hexagon_debug_vreg(CPUHexagonState *env, int regnum);
 void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
 void hexagon_debug(CPUHexagonState *env);
 
-extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
-
 #endif
-- 
2.38.1

[PULL 20/36] target/mips: Convert to 3-phase reset

[Peter Maydell]

Convert the mips CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-11-peter.mayd...@linaro.org
---
 target/mips/cpu-qom.h |  4 ++--
 target/mips/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index e28b5296073..0dffab453b2 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
 /**
  * MIPSCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A MIPS CPU model.
  */
@@ -44,7 +44,7 @@ struct MIPSCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 const struct mips_def_t *cpu_def;
 
 /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 7a565466cb3..c614b04607a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -182,14 +182,16 @@ static bool mips_cpu_has_work(CPUState *cs)
 
 #include "cpu-defs.c.inc"
 
-static void mips_cpu_reset(DeviceState *dev)
+static void mips_cpu_reset_hold(Object *obj)
 {
-CPUState *cs = CPU(dev);
+CPUState *cs = CPU(obj);
 MIPSCPU *cpu = MIPS_CPU(cs);
 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 CPUMIPSState *env = >env;
 
-mcc->parent_reset(dev);
+if (mcc->parent_phases.hold) {
+mcc->parent_phases.hold(obj);
+}
 
 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 
@@ -562,10 +564,12 @@ static void mips_cpu_class_init(ObjectClass *c, void 
*data)
 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 CPUClass *cc = CPU_CLASS(c);
 DeviceClass *dc = DEVICE_CLASS(c);
+ResettableClass *rc = RESETTABLE_CLASS(c);
 
 device_class_set_parent_realize(dc, mips_cpu_realizefn,
 >parent_realize);
-device_class_set_parent_reset(dc, mips_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = mips_cpu_class_by_name;
 cc->has_work = mips_cpu_has_work;
-- 
2.25.1

[PULL 23/36] target/ppc: Convert to 3-phase reset

[Peter Maydell]

Convert the ppc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Reviewed-by: Greg Kurz 
Message-id: 20221124115023.2437291-14-peter.mayd...@linaro.org
---
 target/ppc/cpu-qom.h  |  4 ++--
 target/ppc/cpu_init.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 89ff88f28c9..0fbd8b72468 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -143,7 +143,7 @@ typedef struct PPCHash64Options PPCHash64Options;
 /**
  * PowerPCCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A PowerPC CPU model.
  */
@@ -154,7 +154,7 @@ struct PowerPCCPUClass {
 
 DeviceRealize parent_realize;
 DeviceUnrealize parent_unrealize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 void (*parent_parse_features)(const char *type, char *str, Error **errp);
 
 uint32_t pvr;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cbf00813743..95d25856a0e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7031,16 +7031,18 @@ static bool ppc_cpu_has_work(CPUState *cs)
 return cs->interrupt_request & CPU_INTERRUPT_HARD;
 }
 
-static void ppc_cpu_reset(DeviceState *dev)
+static void ppc_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 PowerPCCPU *cpu = POWERPC_CPU(s);
 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 CPUPPCState *env = >env;
 target_ulong msr;
 int i;
 
-pcc->parent_reset(dev);
+if (pcc->parent_phases.hold) {
+pcc->parent_phases.hold(obj);
+}
 
 msr = (target_ulong)0;
 msr |= (target_ulong)MSR_HVB;
@@ -7267,6 +7269,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void 
*data)
 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
 CPUClass *cc = CPU_CLASS(oc);
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, ppc_cpu_realize,
 >parent_realize);
@@ -7275,7 +7278,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void 
*data)
 pcc->pvr_match = ppc_pvr_match_default;
 device_class_set_props(dc, ppc_cpu_properties);
 
-device_class_set_parent_reset(dc, ppc_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = ppc_cpu_class_by_name;
 cc->has_work = ppc_cpu_has_work;
-- 
2.25.1

[PATCH 01/10] target/hppa/helper: Include missing "cpu.h" header

[Philippe Mathieu-Daudé]

'dh_ctype_tr' is defined as 'target_ureg', itself declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/hppa/helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index c7e35ce8c7..621bc9738e 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -1,3 +1,5 @@
+#include "cpu.h"
+
 #if TARGET_REGISTER_BITS == 64
 # define dh_alias_tr i64
 # define dh_typecode_tr  dh_typecode_i64
-- 
2.38.1

Re: [PATCH 1/5] target/arm: only build psci for TCG

[Alexander Graf]

Hi Claudio,

If the PSCI implementation becomes TCG only, can we also move to a tcg accel 
directory? It slowly gets super confusing to keep track of which files are 
supposed to be generic target code and which ones TCG specific.

Alex

> Am 16.12.2022 um 22:37 schrieb Fabiano Rosas :
> 
> From: Claudio Fontana 
> 
> Signed-off-by: Claudio Fontana 
> Cc: Alexander Graf 
> Reviewed-by: Richard Henderson 
> Reviewed-by: Alex Bennée 
> Signed-off-by: Fabiano Rosas 
> ---
> Originally from:
> [RFC v14 09/80] target/arm: only build psci for TCG
> https://lore.kernel.org/r/20210416162824.25131-10-cfont...@suse.de
> ---
> target/arm/meson.build | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 87e911b27f..26e425418f 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -61,10 +61,13 @@ arm_softmmu_ss.add(files(
>   'arm-powerctl.c',
>   'machine.c',
>   'monitor.c',
> -  'psci.c',
>   'ptw.c',
> ))
> 
> +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
> +  'psci.c',
> +))
> +
> subdir('hvf')
> 
> target_arch += {'arm': arm_ss}
> -- 
> 2.35.3
> 

[PULL 27/36] target/sparc: Convert to 3-phase reset

[Peter Maydell]

Convert the sparc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Reviewed-by: Greg Kurz 
Reviewed-by: Mark Cave-Ayland 
Message-id: 20221124115023.2437291-18-peter.mayd...@linaro.org
---
 target/sparc/cpu-qom.h |  4 ++--
 target/sparc/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 86ed37d9333..78bf00b9a23 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -35,7 +35,7 @@ typedef struct sparc_def_t sparc_def_t;
 /**
  * SPARCCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A SPARC CPU model.
  */
@@ -45,7 +45,7 @@ struct SPARCCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 sparc_def_t *cpu_def;
 };
 
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 4c3d08a8751..1734ef8dc6b 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -28,14 +28,16 @@
 
 //#define DEBUG_FEATURES
 
-static void sparc_cpu_reset(DeviceState *dev)
+static void sparc_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 SPARCCPU *cpu = SPARC_CPU(s);
 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
 CPUSPARCState *env = >env;
 
-scc->parent_reset(dev);
+if (scc->parent_phases.hold) {
+scc->parent_phases.hold(obj);
+}
 
 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
 env->cwp = 0;
@@ -889,12 +891,14 @@ static void sparc_cpu_class_init(ObjectClass *oc, void 
*data)
 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
 CPUClass *cc = CPU_CLASS(oc);
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, sparc_cpu_realizefn,
 >parent_realize);
 device_class_set_props(dc, sparc_cpu_properties);
 
-device_class_set_parent_reset(dc, sparc_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = sparc_cpu_class_by_name;
 cc->parse_features = sparc_cpu_parse_features;
-- 
2.25.1

[PATCH 5/5] hw/i386/x86: Reduce init_topo_info() scope

[Philippe Mathieu-Daudé]

This function is not used anywhere outside this file, so
we can delete the prototype from include/hw/i386/x86.h and
make the function "static void".

This fixes when building with -Wall and using Clang
("Apple clang version 14.0.0 (clang-1400.0.29.202)"):

  ../hw/i386/x86.c:70:24: error: static function 'MACHINE' is used in an inline 
function with external linkage [-Werror,-Wstatic-in-inline]
  MachineState *ms = MACHINE(x86ms);
 ^
  include/hw/i386/x86.h:101:1: note: use 'static' to give inline function 
'init_topo_info' internal linkage
  void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
  ^
  static
  include/hw/boards.h:24:49: note: 'MACHINE' declared here
  OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
  ^

Reported-by: Stefan Weil 
Suggested-by: Peter Maydell 
Reviewed-by: Peter Maydell 
Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/i386/x86.c | 2 +-
 include/hw/i386/x86.h | 3 ---
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 78cc131926..b6ba0b2d00 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -64,7 +64,7 @@
 /* Physical Address of PVH entry point read from kernel ELF NOTE */
 static size_t pvh_start_addr;
 
-inline void init_topo_info(X86CPUTopoInfo *topo_info,
+static void init_topo_info(X86CPUTopoInfo *topo_info,
const X86MachineState *x86ms)
 {
 MachineState *ms = MACHINE(x86ms);
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 62fa5774f8..5d3047a1d1 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -20,7 +20,6 @@
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 
-#include "hw/i386/topology.h"
 #include "hw/boards.h"
 #include "hw/nmi.h"
 #include "hw/isa/isa.h"
@@ -98,8 +97,6 @@ struct X86MachineState {
 #define TYPE_X86_MACHINE   MACHINE_TYPE_NAME("x86")
 OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
 
-void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
-
 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
 unsigned int cpu_index);
 
-- 
2.38.1

[PULL 21/36] target/nios2: Convert to 3-phase reset

[Peter Maydell]

Convert the nios2 CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-12-peter.mayd...@linaro.org
---
 target/nios2/cpu.h |  4 ++--
 target/nios2/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index f85581ee560..b1a55490747 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -37,7 +37,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
 
 /**
  * Nios2CPUClass:
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A Nios2 CPU model.
  */
@@ -47,7 +47,7 @@ struct Nios2CPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 #define TARGET_HAS_ICE 1
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 9a5351bc81d..cff30823dad 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -57,14 +57,16 @@ static bool nios2_cpu_has_work(CPUState *cs)
 return cs->interrupt_request & CPU_INTERRUPT_HARD;
 }
 
-static void nios2_cpu_reset(DeviceState *dev)
+static void nios2_cpu_reset_hold(Object *obj)
 {
-CPUState *cs = CPU(dev);
+CPUState *cs = CPU(obj);
 Nios2CPU *cpu = NIOS2_CPU(cs);
 Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
 CPUNios2State *env = >env;
 
-ncc->parent_reset(dev);
+if (ncc->parent_phases.hold) {
+ncc->parent_phases.hold(obj);
+}
 
 memset(env->ctrl, 0, sizeof(env->ctrl));
 env->pc = cpu->reset_addr;
@@ -371,11 +373,13 @@ static void nios2_cpu_class_init(ObjectClass *oc, void 
*data)
 DeviceClass *dc = DEVICE_CLASS(oc);
 CPUClass *cc = CPU_CLASS(oc);
 Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, nios2_cpu_realizefn,
 >parent_realize);
 device_class_set_props(dc, nios2_properties);
-device_class_set_parent_reset(dc, nios2_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, nios2_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = nios2_cpu_class_by_name;
 cc->has_work = nios2_cpu_has_work;
-- 
2.25.1

[PATCH 1/5] exec/memory: Expose memory_region_access_valid()

[Philippe Mathieu-Daudé]

Instead of having hardware device poking into memory
internal API, expose memory_region_access_valid().

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/s390x/s390-pci-inst.c   | 2 +-
 include/exec/memory-internal.h | 4 
 include/exec/memory.h  | 4 
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 66e764f901..35dbe4 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -13,7 +13,7 @@
 
 #include "qemu/osdep.h"
 #include "exec/memop.h"
-#include "exec/memory-internal.h"
+#include "exec/memory.h"
 #include "qemu/error-report.h"
 #include "sysemu/hw_accel.h"
 #include "hw/s390x/s390-pci-inst.h"
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 9fcc2af25c..100c1237ac 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -38,10 +38,6 @@ void flatview_unref(FlatView *view);
 
 extern const MemoryRegionOps unassigned_mem_ops;
 
-bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
-unsigned size, bool is_write,
-MemTxAttrs attrs);
-
 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
 void address_space_dispatch_compact(AddressSpaceDispatch *d);
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 91f8a2395a..c37ffdbcd1 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -2442,6 +2442,10 @@ void memory_global_dirty_log_stop(unsigned int flags);
 
 void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled);
 
+bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
+unsigned size, bool is_write,
+MemTxAttrs attrs);
+
 /**
  * memory_region_dispatch_read: perform a read directly to the specified
  * MemoryRegion.
-- 
2.38.1

[PATCH v3 4/5] target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu

[Philippe Mathieu-Daudé]

The 'hwaddr' type is only available / meaningful on system emulation.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/alpha/cpu.h  | 2 +-
 target/arm/cpu.h| 2 +-
 target/cris/cpu.h   | 3 +--
 target/hppa/cpu.h   | 2 +-
 target/i386/cpu.h   | 5 ++---
 target/m68k/cpu.h   | 2 +-
 target/microblaze/cpu.h | 4 ++--
 target/nios2/cpu.h  | 2 +-
 target/openrisc/cpu.h   | 3 ++-
 target/ppc/cpu.h| 2 +-
 target/riscv/cpu.h  | 2 +-
 target/rx/cpu.h | 2 +-
 target/rx/helper.c  | 4 ++--
 target/sh4/cpu.h| 2 +-
 target/sparc/cpu.h  | 3 ++-
 target/xtensa/cpu.h | 2 +-
 16 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index d0abc949a8..5e67304d81 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -276,9 +276,9 @@ extern const VMStateDescription vmstate_alpha_cpu;
 
 void alpha_cpu_do_interrupt(CPUState *cpu);
 bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
+hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 #endif /* !CONFIG_USER_ONLY */
 void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
-hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2b4bd20f9d..38c7e5c8af 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1085,10 +1085,10 @@ extern const VMStateDescription vmstate_arm_cpu;
 
 void arm_cpu_do_interrupt(CPUState *cpu);
 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
-#endif /* !CONFIG_USER_ONLY */
 
 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
  MemTxAttrs *attrs);
+#endif /* !CONFIG_USER_ONLY */
 
 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index e6776f25b1..71fa1f96e0 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -193,12 +193,11 @@ bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
 bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 #endif
 
 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
 
-hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-
 int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 6f3b6beecf..b595ef25a9 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -322,11 +322,11 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState 
*env) { }
 void cpu_hppa_change_prot_id(CPUHPPAState *env);
 #endif
 
-hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
 #ifndef CONFIG_USER_ONLY
+hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d4bc19577a..f729e0f09c 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1987,9 +1987,6 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, 
MemoryMappingList *list,
 
 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
 
-hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
-
 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
@@ -1997,6 +1994,8 @@ void x86_cpu_list(void);
 int cpu_x86_support_mca_broadcast(CPUX86State *env);
 
 #ifndef CONFIG_USER_ONLY
+hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
 int cpu_get_pic_interrupt(CPUX86State *s);
 
 /* MSDOS compatibility mode FPU exception support */
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 3a9cfe2f33..68ed531fc3 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -176,9 +176,9 @@ struct ArchCPU {
 #ifndef CONFIG_USER_ONLY
 void m68k_cpu_do_interrupt(CPUState *cpu);
 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
+hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr 

[PATCH 0/5] target/s390x: Header cleanups around "cpu.h"

[Philippe Mathieu-Daudé]

These patches are part of a big refactor cleanup
around "cpu.h". Most changes should be trivial IMHO.

Philippe Mathieu-Daudé (5):
  exec/memory: Expose memory_region_access_valid()
  hw/s390x/pv: Un-inline s390_pv_init()
  hw/s390x/pv: Simplify s390_is_pv() for user emulation
  target/s390x/tcg/misc_helper: Remove unused "memory.h" include
  target/s390x/tcg/excp_helper: Restrict system headers to sysemu

 hw/s390x/pv.c  | 13 +
 hw/s390x/s390-pci-inst.c   |  2 +-
 include/exec/memory-internal.h |  4 
 include/exec/memory.h  |  4 
 include/hw/s390x/pv.h  | 20 
 target/s390x/tcg/excp_helper.c | 10 +-
 target/s390x/tcg/misc_helper.c |  1 -
 7 files changed, 31 insertions(+), 23 deletions(-)

-- 
2.38.1

[PATCH 4/5] target/s390x/tcg/misc_helper: Remove unused "memory.h" include

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/s390x/tcg/misc_helper.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
index 71388a7119..576157b1f3 100644
--- a/target/s390x/tcg/misc_helper.c
+++ b/target/s390x/tcg/misc_helper.c
@@ -23,7 +23,6 @@
 #include "qemu/main-loop.h"
 #include "cpu.h"
 #include "s390x-internal.h"
-#include "exec/memory.h"
 #include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
 #include "qemu/timer.h"
-- 
2.38.1

[PATCH] exec: Rename NEED_CPU_H -> CONFIG_TARGET

[Philippe Mathieu-Daudé]

'NEED_CPU_H' guard target-specific code; it is defined by meson
altogether with the 'CONFIG_TARGET' definition. Since the latter
name is more meaningful, directly use it.

Inspired-by: Peter Maydell 
Signed-off-by: Philippe Mathieu-Daudé 
---
Based-on: <20221216220738.7355-1-phi...@linaro.org>
  sysemu/kvm: Header cleanups around "cpu.h"
Based-on: <20221216220158.6317-1-phi...@linaro.org>
  target/i386: Header cleanups around "cpu.h"
---
 include/disas/disas.h | 2 +-
 include/exec/cpu-defs.h   | 2 +-
 include/exec/gdbstub.h| 4 ++--
 include/exec/helper-head.h| 4 ++--
 include/exec/memop.h  | 6 +++---
 include/exec/memory.h | 4 ++--
 include/hw/core/cpu.h | 4 ++--
 include/hw/core/tcg-cpu-ops.h | 4 ++--
 include/qemu/osdep.h  | 4 ++--
 include/sysemu/hax.h  | 4 ++--
 include/sysemu/hvf.h  | 4 ++--
 include/sysemu/kvm.h  | 8 
 include/sysemu/nvmm.h | 4 ++--
 include/sysemu/whpx.h | 4 ++--
 include/sysemu/xen.h  | 4 ++--
 meson.build   | 6 ++
 scripts/analyze-inclusions| 6 +++---
 target/arm/kvm-consts.h   | 2 +-
 18 files changed, 37 insertions(+), 39 deletions(-)

diff --git a/include/disas/disas.h b/include/disas/disas.h
index d363e95ede..1f6706a374 100644
--- a/include/disas/disas.h
+++ b/include/disas/disas.h
@@ -3,7 +3,7 @@
 
 #include "exec/hwaddr.h"
 
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 #include "cpu.h"
 
 /* Disassemble this for me please... (debugging). */
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 21309cf567..9775634ff6 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -19,7 +19,7 @@
 #ifndef CPU_DEFS_H
 #define CPU_DEFS_H
 
-#ifndef NEED_CPU_H
+#ifndef CONFIG_TARGET
 #error cpu.h included from common code
 #endif
 
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index f667014888..49f63d3c50 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -71,7 +71,7 @@ struct gdb_timeval {
   uint64_t tv_usec;   /* microsecond */
 } QEMU_PACKED;
 
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 #include "cpu.h"
 
 typedef void (*gdb_syscall_complete_cb)(CPUState *cpu, uint64_t ret, int err);
@@ -214,7 +214,7 @@ static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf, 
int len)
 #define ldtul_p(addr) ldl_p(addr)
 #endif
 
-#endif /* NEED_CPU_H */
+#endif /* CONFIG_TARGET */
 
 /**
  * gdbserver_start: start the gdb server
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index e242fed46e..584b120312 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -49,7 +49,7 @@
 #define dh_ctype_noreturn G_NORETURN void
 #define dh_ctype(t) dh_ctype_##t
 
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 # ifdef TARGET_LONG_BITS
 #  if TARGET_LONG_BITS == 32
 #   define dh_alias_tl i32
@@ -63,7 +63,7 @@
 # define dh_alias_env ptr
 # define dh_ctype_env CPUArchState *
 # define dh_typecode_env dh_typecode_ptr
-#endif
+#endif /* CONFIG_TARGET */
 
 /* We can't use glue() here because it falls foul of C preprocessor
recursive expansion rules.  */
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 25d027434a..ebf6c5f69d 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -35,7 +35,7 @@ typedef enum MemOp {
 MO_LE= 0,
 MO_BE= MO_BSWAP,
 #endif
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 #if TARGET_BIG_ENDIAN
 MO_TE= MO_BE,
 #else
@@ -65,7 +65,7 @@ typedef enum MemOp {
  */
 MO_ASHIFT = 5,
 MO_AMASK = 0x7 << MO_ASHIFT,
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 #ifdef TARGET_ALIGNED_ONLY
 MO_ALIGN = 0,
 MO_UNALN = MO_AMASK,
@@ -107,7 +107,7 @@ typedef enum MemOp {
 MO_BESL  = MO_BE | MO_SL,
 MO_BESQ  = MO_BE | MO_SQ,
 
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 MO_TEUW  = MO_TE | MO_UW,
 MO_TEUL  = MO_TE | MO_UL,
 MO_TEUQ  = MO_TE | MO_UQ,
diff --git a/include/exec/memory.h b/include/exec/memory.h
index c37ffdbcd1..2d1fd6e475 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -2938,7 +2938,7 @@ address_space_write_cached(MemoryRegionCache *cache, 
hwaddr addr,
 MemTxResult address_space_set(AddressSpace *as, hwaddr addr,
   uint8_t c, hwaddr len, MemTxAttrs attrs);
 
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 /* enum device_endian to MemOp.  */
 static inline MemOp devend_memop(enum device_endian end)
 {
@@ -2956,7 +2956,7 @@ static inline MemOp devend_memop(enum device_endian end)
 return (end == non_host_endianness) ? MO_BSWAP : 0;
 #endif
 }
-#endif
+#endif /* CONFIG_TARGET */
 
 /*
  * Inhibit technologies that require discarding of pages in RAM blocks, e.g.,
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index bc3229ae13..5ab6244bc8 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1044,7 +1044,7 @@ bool target_words_bigendian(void);
 
 void page_size_init(void);
 
-#ifdef NEED_CPU_H
+#ifdef CONFIG_TARGET
 
 #ifdef 

[PATCH 2/2] sysemu/kvm: Reduce target-specific declarations

[Philippe Mathieu-Daudé]

Only the declarations using the target_ulong type are
target specific.

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/sysemu/kvm.h | 25 -
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index c8281c07a7..a53d6dab49 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -242,9 +242,6 @@ bool kvm_arm_supports_user_irq(void);
 int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
 int kvm_on_sigbus(int code, void *addr);
 
-#ifdef NEED_CPU_H
-#include "cpu.h"
-
 void kvm_flush_coalesced_mmio_buffer(void);
 
 /**
@@ -410,6 +407,9 @@ void kvm_get_apic_state(DeviceState *d, struct 
kvm_lapic_state *kapic);
 struct kvm_guest_debug;
 struct kvm_debug_exit_arch;
 
+#ifdef NEED_CPU_H
+#include "cpu.h"
+
 struct kvm_sw_breakpoint {
 target_ulong pc;
 target_ulong saved_insn;
@@ -436,6 +436,15 @@ void kvm_arch_update_guest_debug(CPUState *cpu, struct 
kvm_guest_debug *dbg);
 
 bool kvm_arch_stop_on_emulation_error(CPUState *cpu);
 
+uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
+  uint32_t index, int reg);
+uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
+
+int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
+   hwaddr *phys_addr);
+
+#endif /* NEED_CPU_H */
+
 int kvm_check_extension(KVMState *s, unsigned int extension);
 
 int kvm_vm_check_extension(KVMState *s, unsigned int extension);
@@ -464,18 +473,8 @@ int kvm_vm_check_extension(KVMState *s, unsigned int 
extension);
 kvm_vcpu_ioctl(cpu, KVM_ENABLE_CAP, );   \
 })
 
-uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
-  uint32_t index, int reg);
-uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
-
-
 void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len);
 
-int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
-   hwaddr *phys_addr);
-
-#endif /* NEED_CPU_H */
-
 void kvm_cpu_synchronize_state(CPUState *cpu);
 
 void kvm_init_cpu_signals(CPUState *cpu);
-- 
2.38.1

[PULL 34/36] hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset()

[Peter Maydell]

The realize method for the TYPE_ICS class uses qemu_register_reset()
to register a reset handler, as a workaround for the fact that
currently objects which directly inherit from TYPE_DEVICE don't get
automatically reset.  However, the reset function directly calls
ics_reset(), which is the function that implements the legacy reset
method.  This means that only the parent class's data gets reset, and
a subclass which also needs to handle reset, like TYPE_PHB3_MSI, has
to register its own reset function.

Make the TYPE_ICS reset function call device_cold_reset() instead:
this will handle reset for both the parent class and the subclass,
and will work whether the classes are using legacy reset or 3-phase
reset. This allows us to remove the reset function that the subclass
currently has to set up.

Signed-off-by: Peter Maydell 
Tested-by: Daniel Henrique Barboza 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Greg Kurz 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221125115240.3005559-6-peter.mayd...@linaro.org
---
 hw/intc/xics.c | 2 +-
 hw/pci-host/pnv_phb3_msi.c | 7 ---
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index dcd021af668..dd130467ccc 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -593,7 +593,7 @@ static void ics_reset(DeviceState *dev)
 
 static void ics_reset_handler(void *dev)
 {
-ics_reset(dev);
+device_cold_reset(dev);
 }
 
 static void ics_realize(DeviceState *dev, Error **errp)
diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c
index 2f4112907b8..ae908fd9e41 100644
--- a/hw/pci-host/pnv_phb3_msi.c
+++ b/hw/pci-host/pnv_phb3_msi.c
@@ -239,11 +239,6 @@ static void phb3_msi_reset(DeviceState *dev)
 msi->rba_sum = 0;
 }
 
-static void phb3_msi_reset_handler(void *dev)
-{
-phb3_msi_reset(dev);
-}
-
 void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base,
 uint32_t count)
 {
@@ -272,8 +267,6 @@ static void phb3_msi_realize(DeviceState *dev, Error **errp)
 }
 
 msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs);
-
-qemu_register_reset(phb3_msi_reset_handler, dev);
 }
 
 static void phb3_msi_instance_init(Object *obj)
-- 
2.25.1

[PULL 09/36] hw/misc/mos6522: Convert TYPE_MOS6522 to 3-phase reset

[Peter Maydell]

Convert the TYPE_MOS6522 parent class to use 3-phase reset.  This is
a prerequisite for converting its subclasses.

Signed-off-by: Peter Maydell 
Acked-by: Mark Cave-Ayland 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-id: 20221110143459.3833425-2-peter.mayd...@linaro.org
---
 hw/misc/mos6522.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index fe38c44426b..0ed631186c3 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -643,9 +643,9 @@ const VMStateDescription vmstate_mos6522 = {
 }
 };
 
-static void mos6522_reset(DeviceState *dev)
+static void mos6522_reset_hold(Object *obj)
 {
-MOS6522State *s = MOS6522(dev);
+MOS6522State *s = MOS6522(obj);
 
 s->b = 0;
 s->a = 0;
@@ -705,9 +705,10 @@ static Property mos6522_properties[] = {
 static void mos6522_class_init(ObjectClass *oc, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
 
-dc->reset = mos6522_reset;
+rc->phases.hold = mos6522_reset_hold;
 dc->vmsd = _mos6522;
 device_class_set_props(dc, mos6522_properties);
 mdc->portB_write = mos6522_portB_write;
-- 
2.25.1

[PATCH 3/5] hw/s390x/pv: Simplify s390_is_pv() for user emulation

[Philippe Mathieu-Daudé]

Protected Virtualization is irrelevant in user emulation.

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/hw/s390x/pv.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/hw/s390x/pv.h b/include/hw/s390x/pv.h
index 5bca5bcaf1..a4814ce303 100644
--- a/include/hw/s390x/pv.h
+++ b/include/hw/s390x/pv.h
@@ -12,6 +12,12 @@
 #ifndef HW_S390_PV_H
 #define HW_S390_PV_H
 
+#ifdef CONFIG_USER_ONLY
+
+static inline bool s390_is_pv(void) { return false; }
+
+#else /* !CONFIG_USER_ONLY */
+
 #include "sysemu/kvm.h"
 
 #ifdef CONFIG_KVM
@@ -79,4 +85,6 @@ static inline int kvm_s390_dump_completion_data(void *buff) { 
return 0; }
 int s390_pv_kvm_init(ConfidentialGuestSupport *cgs, Error **errp);
 int s390_pv_init(ConfidentialGuestSupport *cgs, Error **errp);
 
+#endif /* CONFIG_USER_ONLY */
+
 #endif /* HW_S390_PV_H */
-- 
2.38.1

[PATCH 03/10] target/loongarch/cpu: Remove unused "sysbus.h" header

[Philippe Mathieu-Daudé]

Nothing requires SysBus declarations here.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/loongarch/cpu.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index e15c633b0b..c8612f5466 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -13,7 +13,6 @@
 #include "hw/registerfields.h"
 #include "qemu/timer.h"
 #include "exec/memory.h"
-#include "hw/sysbus.h"
 #include "cpu-csr.h"
 
 #define IOCSRF_TEMP 0
-- 
2.38.1

[PATCH v2 0/2] hw/arm/smmu-common: Avoid using inlined functions with external linkage

[Philippe Mathieu-Daudé]

Avoid inlined functions with external linkage,
convert 'inline' header to 'static inline' in source.

Supersedes: <20221208161152.28976-1-phi...@linaro.org>

Philippe Mathieu-Daudé (2):
  hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
  hw/arm/smmu-common: Avoid using inlined functions with external
linkage

 hw/arm/smmu-common.c | 15 +++
 include/hw/arm/smmu-common.h |  3 ---
 2 files changed, 7 insertions(+), 11 deletions(-)

-- 
2.38.1

[PULL 12/36] target/arm: Convert to 3-phase reset

[Peter Maydell]

Convert the Arm CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Message-id: 20221124115023.2437291-3-peter.mayd...@linaro.org
---
 target/arm/cpu-qom.h |  4 ++--
 target/arm/cpu.c | 13 +
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 64c44cef2dd..514c22ced9b 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -43,7 +43,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
 /**
  * ARMCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * An ARM CPU model.
  */
@@ -54,7 +54,7 @@ struct ARMCPUClass {
 
 const ARMCPUInfo *info;
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0f55004d7e7..2fa022f62ba 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -202,14 +202,16 @@ static void cp_reg_check_reset(gpointer key, gpointer 
value,  gpointer opaque)
 assert(oldvalue == newvalue);
 }
 
-static void arm_cpu_reset(DeviceState *dev)
+static void arm_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 ARMCPU *cpu = ARM_CPU(s);
 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 CPUARMState *env = >env;
 
-acc->parent_reset(dev);
+if (acc->parent_phases.hold) {
+acc->parent_phases.hold(obj);
+}
 
 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 
@@ -2211,12 +2213,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void 
*data)
 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 CPUClass *cc = CPU_CLASS(acc);
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, arm_cpu_realizefn,
 >parent_realize);
 
 device_class_set_props(dc, arm_cpu_properties);
-device_class_set_parent_reset(dc, arm_cpu_reset, >parent_reset);
+
+resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = arm_cpu_class_by_name;
 cc->has_work = arm_cpu_has_work;
-- 
2.25.1

[PULL 03/36] hw/hyperv/vmbus: Use device_cold_reset() and bus_cold_reset()

[Peter Maydell]

In the vmbus code we currently use the legacy functions
qdev_reset_all() and qbus_reset_all().  These perform a recursive
reset, starting from either a qbus or a qdev.  However they do not
permit any of the devices in the tree to use three-phase reset,
because device reset goes through the device_legacy_reset() function
that only calls the single DeviceClass::reset method.

Switch to using the device_cold_reset() and bus_cold_reset()
functions.  These also perform a recursive reset, where first the
children are reset and then finally the parent, but they use the new
(...in 2020...) Resettable mechanism, which supports both the old
style single-reset method and also the new 3-phase reset handling.

This should be a no-behaviour-change commit which just reduces the
use of a deprecated API.

Commit created with:
  sed -i -e 
's/qdev_reset_all/device_cold_reset/g;s/qbus_reset_all/bus_cold_reset/g' 
hw/hyperv/*.c

Signed-off-by: Peter Maydell 
---
 hw/hyperv/vmbus.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
index 8ee08aea46c..271289f902f 100644
--- a/hw/hyperv/vmbus.c
+++ b/hw/hyperv/vmbus.c
@@ -1578,7 +1578,7 @@ static bool vmbus_initialized(VMBus *vmbus)
 
 static void vmbus_reset_all(VMBus *vmbus)
 {
-qbus_reset_all(BUS(vmbus));
+bus_cold_reset(BUS(vmbus));
 }
 
 static void post_msg(VMBus *vmbus, void *msgdata, uint32_t msglen)
@@ -2035,7 +2035,7 @@ static void vdev_reset_on_close(VMBusDevice *vdev)
 }
 
 /* all channels closed -- reset device */
-qdev_reset_all(DEVICE(vdev));
+device_cold_reset(DEVICE(vdev));
 }
 
 static void handle_close_channel(VMBus *vmbus, vmbus_message_close_channel 
*msg,
-- 
2.25.1

[PATCH v3 0/5] target/cpu: System/User cleanups around hwaddr/vaddr

[Philippe Mathieu-Daudé]

Missing review: #1

We are not supposed to use the 'hwaddr' type on user emulation.

This series is a preparatory cleanup before few refactors to
isolate further System vs User code.

Since v1:
- only restrict SavedIOTLB in header (Alex)
- convert insert/remove_breakpoint implementations (Peter)

Since v2:
- added 'dump' patch
- collected R-b tags

Philippe Mathieu-Daudé (5):
  dump: Include missing "cpu.h" header for tswap32/tswap64()
declarations
  cputlb: Restrict SavedIOTLB to system emulation
  gdbstub: Use vaddr type for generic insert/remove_breakpoint() API
  target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu
  target/cpu: Restrict do_transaction_failed() handlers to sysemu

 accel/kvm/kvm-all.c|  4 ++--
 accel/kvm/kvm-cpus.h   |  4 ++--
 accel/tcg/tcg-accel-ops.c  |  4 ++--
 dump/dump.c|  1 +
 gdbstub/gdbstub.c  |  1 -
 gdbstub/internals.h|  6 --
 gdbstub/softmmu.c  |  5 ++---
 gdbstub/user.c |  5 ++---
 include/hw/core/cpu.h  |  6 --
 include/sysemu/accel-ops.h |  6 +++---
 target/alpha/cpu.h |  2 +-
 target/arm/cpu.h   |  2 +-
 target/arm/internals.h |  2 ++
 target/cris/cpu.h  |  3 +--
 target/hppa/cpu.h  |  2 +-
 target/i386/cpu.h  |  5 ++---
 target/m68k/cpu.h  |  4 +++-
 target/microblaze/cpu.h|  4 ++--
 target/nios2/cpu.h |  2 +-
 target/openrisc/cpu.h  |  3 ++-
 target/ppc/cpu.h   |  2 +-
 target/riscv/cpu.h | 12 ++--
 target/rx/cpu.h|  2 +-
 target/rx/helper.c |  4 ++--
 target/sh4/cpu.h   |  2 +-
 target/sparc/cpu.h |  3 ++-
 target/xtensa/cpu.h|  2 +-
 27 files changed, 52 insertions(+), 46 deletions(-)

-- 
2.38.1

[PULL 33/36] pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset

[Peter Maydell]

Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to
3-phase reset, so they don't need to use the deprecated
device_class_set_parent_reset() function any more.

We have to do both in the same commit, because they keep the
parent_reset field in their common parent class's class struct.

Note that pnv_phb_root_port_class_init() was pointlessly setting
dc->reset twice, once by calling device_class_set_parent_reset()
and once directly.

Signed-off-by: Peter Maydell 
Tested-by: Daniel Henrique Barboza 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221125115240.3005559-5-peter.mayd...@linaro.org
---
 include/hw/pci/pcie_port.h|  2 +-
 hw/pci-bridge/cxl_root_port.c | 14 +-
 hw/pci-host/pnv_phb.c | 18 ++
 3 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h
index 7b8193061ac..d9b5d075049 100644
--- a/include/hw/pci/pcie_port.h
+++ b/include/hw/pci/pcie_port.h
@@ -80,7 +80,7 @@ DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
 struct PCIERootPortClass {
 PCIDeviceClass parent_class;
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 
 uint8_t (*aer_vector)(const PCIDevice *dev);
 int (*interrupts_init)(PCIDevice *dev, Error **errp);
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index fb213fa06ef..6664783974c 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp)
  component_bar);
 }
 
-static void cxl_rp_reset(DeviceState *dev)
+static void cxl_rp_reset_hold(Object *obj)
 {
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-CXLRootPort *crp = CXL_ROOT_PORT(dev);
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
+CXLRootPort *crp = CXL_ROOT_PORT(obj);
 
-rpc->parent_reset(dev);
+if (rpc->parent_phases.hold) {
+rpc->parent_phases.hold(obj);
+}
 
 latch_registers(crp);
 }
@@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, void 
*data)
 {
 DeviceClass *dc= DEVICE_CLASS(oc);
 PCIDeviceClass *k  = PCI_DEVICE_CLASS(oc);
+ResettableClass *rc= RESETTABLE_CLASS(oc);
 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
 
 k->vendor_id = PCI_VENDOR_ID_INTEL;
@@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, void 
*data)
 k->config_write = cxl_rp_write_config;
 
 device_class_set_parent_realize(dc, cxl_rp_realize, >parent_realize);
-device_class_set_parent_reset(dc, cxl_rp_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL,
+   >parent_phases);
 
 rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
 rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 0b26b43736f..c62b08538ac 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -199,14 +199,16 @@ static void pnv_phb_class_init(ObjectClass *klass, void 
*data)
 dc->user_creatable = true;
 }
 
-static void pnv_phb_root_port_reset(DeviceState *dev)
+static void pnv_phb_root_port_reset_hold(Object *obj)
 {
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
-PCIDevice *d = PCI_DEVICE(dev);
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
+PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
+PCIDevice *d = PCI_DEVICE(obj);
 uint8_t *conf = d->config;
 
-rpc->parent_reset(dev);
+if (rpc->parent_phases.hold) {
+rpc->parent_phases.hold(obj);
+}
 
 if (phb_rp->version == 3) {
 return;
@@ -300,6 +302,7 @@ static Property pnv_phb_root_port_properties[] = {
 static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
 
@@ -308,9 +311,8 @@ static void pnv_phb_root_port_class_init(ObjectClass 
*klass, void *data)
 device_class_set_props(dc, pnv_phb_root_port_properties);
 device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
 >parent_realize);
-device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
-  >parent_reset);
-dc->reset = _phb_root_port_reset;
+resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold,
+   NULL, >parent_phases);
 dc->user_creatable = true;
 
 k->vendor_id = PCI_VENDOR_ID_IBM;
-- 
2.25.1

[PULL 15/36] target/hexagon: Convert to 3-phase reset

[Peter Maydell]

Convert the hexagon CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-6-peter.mayd...@linaro.org
---
 target/hexagon/cpu.h |  2 +-
 target/hexagon/cpu.c | 12 
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 2a65a57bab3..794a0453fd4 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -137,7 +137,7 @@ typedef struct HexagonCPUClass {
 CPUClass parent_class;
 /*< public >*/
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 } HexagonCPUClass;
 
 struct ArchCPU {
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 03221fbdc28..658ca4ff783 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -281,14 +281,16 @@ static void hexagon_restore_state_to_opc(CPUState *cs,
 env->gpr[HEX_REG_PC] = data[0];
 }
 
-static void hexagon_cpu_reset(DeviceState *dev)
+static void hexagon_cpu_reset_hold(Object *obj)
 {
-CPUState *cs = CPU(dev);
+CPUState *cs = CPU(obj);
 HexagonCPU *cpu = HEXAGON_CPU(cs);
 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
 CPUHexagonState *env = >env;
 
-mcc->parent_reset(dev);
+if (mcc->parent_phases.hold) {
+mcc->parent_phases.hold(obj);
+}
 
 set_default_nan_mode(1, >fp_status);
 set_float_detect_tininess(float_tininess_before_rounding, >fp_status);
@@ -339,11 +341,13 @@ static void hexagon_cpu_class_init(ObjectClass *c, void 
*data)
 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
 CPUClass *cc = CPU_CLASS(c);
 DeviceClass *dc = DEVICE_CLASS(c);
+ResettableClass *rc = RESETTABLE_CLASS(c);
 
 device_class_set_parent_realize(dc, hexagon_cpu_realize,
 >parent_realize);
 
-device_class_set_parent_reset(dc, hexagon_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = hexagon_cpu_class_by_name;
 cc->has_work = hexagon_cpu_has_work;
-- 
2.25.1

[PATCH 05/10] target/m68k/helper: Include missing "cpu.h" header

[Philippe Mathieu-Daudé]

'dh_ctype_fp' is defined as 'FPReg *', itself declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/m68k/helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index c9bed2b884..aaf0e1668e 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -1,3 +1,5 @@
+#include "cpu.h"
+
 DEF_HELPER_1(bitrev, i32, i32)
 DEF_HELPER_1(ff1, i32, i32)
 DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-- 
2.38.1

[PATCH 00/10] target/misc: Header cleanups around "cpu.h"

[Philippe Mathieu-Daudé]

These patches are part of a big refactor cleanup
around "cpu.h". Most changes should be trivial IMHO.

Philippe Mathieu-Daudé (10):
  target/hppa/helper: Include missing "cpu.h" header
  target/hexagon: Declare hexagon_regnames[] in "cpu.h"
  target/loongarch/cpu: Remove unused "sysbus.h" header
  target/loongarch/cpu: Restrict "memory.h" header to sysemu
  target/m68k/helper: Include missing "cpu.h" header
  target/ppc/helper: Include missing "cpu.h" header
  target/ppc/internal: Restrict MMU declarations to sysemu
  target/riscv/cpu: Restrict sysemu-specific fields from CPUArchState
  target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard
  target/xtensa/cpu: Include missing "memory.h" header

 target/hexagon/cpu.h  |  2 ++
 target/hexagon/internal.h |  2 --
 target/hppa/helper.h  |  2 ++
 target/loongarch/cpu.h|  3 ++-
 target/m68k/helper.h  |  2 ++
 target/ppc/helper.h   |  2 ++
 target/ppc/internal.h |  5 +
 target/riscv/cpu.h| 34 ++
 target/sparc/mmu_helper.c |  2 --
 target/xtensa/cpu.c   |  3 +++
 10 files changed, 36 insertions(+), 21 deletions(-)

-- 
2.38.1

[PULL 05/36] qdev: Remove qdev_reset_all() and qbus_reset_all()

[Peter Maydell]

Remove the qdev_reset_all() and qbus_reset_all() functions, now we
have moved all the callers over to the new device_cold_reset() and
bus_cold_reset() functions.

Signed-off-by: Peter Maydell 
---
 include/hw/qdev-core.h | 26 
 hw/core/qdev.c | 54 --
 hw/core/trace-events   |  5 
 3 files changed, 85 deletions(-)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 785dd5a56ef..c7eda169d78 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -743,32 +743,6 @@ int qdev_walk_children(DeviceState *dev,
qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
void *opaque);
 
-/**
- * @qdev_reset_all:
- * Reset @dev. See @qbus_reset_all() for more details.
- *
- * Note: This function is deprecated and will be removed when it becomes 
unused.
- * Please use device_cold_reset() now.
- */
-void qdev_reset_all(DeviceState *dev);
-void qdev_reset_all_fn(void *opaque);
-
-/**
- * @qbus_reset_all:
- * @bus: Bus to be reset.
- *
- * Reset @bus and perform a bus-level ("hard") reset of all devices connected
- * to it, including recursive processing of all buses below @bus itself.  A
- * hard reset means that qbus_reset_all will reset all state of the device.
- * For PCI devices, for example, this will include the base address registers
- * or configuration space.
- *
- * Note: This function is deprecated and will be removed when it becomes 
unused.
- * Please use bus_cold_reset() now.
- */
-void qbus_reset_all(BusState *bus);
-void qbus_reset_all_fn(void *opaque);
-
 /**
  * device_cold_reset:
  * Reset device @dev and perform a recursive processing using the resettable
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index c0b77a62954..c5ea0adc713 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -250,60 +250,6 @@ void qdev_set_legacy_instance_id(DeviceState *dev, int 
alias_id,
 dev->alias_required_for_version = required_for_version;
 }
 
-static int qdev_prereset(DeviceState *dev, void *opaque)
-{
-trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev)));
-return 0;
-}
-
-static int qbus_prereset(BusState *bus, void *opaque)
-{
-trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus)));
-return 0;
-}
-
-static int qdev_reset_one(DeviceState *dev, void *opaque)
-{
-device_legacy_reset(dev);
-
-return 0;
-}
-
-static int qbus_reset_one(BusState *bus, void *opaque)
-{
-BusClass *bc = BUS_GET_CLASS(bus);
-trace_qbus_reset(bus, object_get_typename(OBJECT(bus)));
-if (bc->reset) {
-bc->reset(bus);
-}
-return 0;
-}
-
-void qdev_reset_all(DeviceState *dev)
-{
-trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev)));
-qdev_walk_children(dev, qdev_prereset, qbus_prereset,
-   qdev_reset_one, qbus_reset_one, NULL);
-}
-
-void qdev_reset_all_fn(void *opaque)
-{
-qdev_reset_all(DEVICE(opaque));
-}
-
-void qbus_reset_all(BusState *bus)
-{
-trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus)));
-qbus_walk_children(bus, qdev_prereset, qbus_prereset,
-   qdev_reset_one, qbus_reset_one, NULL);
-}
-
-void qbus_reset_all_fn(void *opaque)
-{
-BusState *bus = opaque;
-qbus_reset_all(bus);
-}
-
 void device_cold_reset(DeviceState *dev)
 {
 resettable_reset(OBJECT(dev), RESET_TYPE_COLD);
diff --git a/hw/core/trace-events b/hw/core/trace-events
index 9b3ecce3b2f..6da317247f4 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -3,11 +3,6 @@ loader_write_rom(const char *name, uint64_t gpa, uint64_t 
size, bool isrom) "%s:
 
 # qdev.c
 qdev_reset(void *obj, const char *objtype) "obj=%p(%s)"
-qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
-qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
-qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
-qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
-qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
 qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char 
*oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) 
new_parent=%p(%s)"
 
 # resettable.c
-- 
2.25.1

[PATCH 1/5] target/i386: Remove NEED_CPU_H guard from target-specific headers

[Philippe Mathieu-Daudé]

NEED_CPU_H is always defined for these target-specific headers.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/i386/hax/hax-i386.h | 2 --
 target/i386/hvf/hvf-i386.h | 4 
 2 files changed, 6 deletions(-)

diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h
index efbb346238..409ebdb4af 100644
--- a/target/i386/hax/hax-i386.h
+++ b/target/i386/hax/hax-i386.h
@@ -49,7 +49,6 @@ struct hax_vm {
 struct hax_vcpu_state **vcpus;
 };
 
-#ifdef NEED_CPU_H
 /* Functions exported to host specific mode */
 hax_fd hax_vcpu_get_fd(CPUArchState *env);
 int valid_hax_tunnel_size(uint16_t size);
@@ -66,7 +65,6 @@ int hax_sync_vcpu_state(CPUArchState *env, struct 
vcpu_state_t *state,
 int set);
 int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set);
 int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set);
-#endif
 
 int hax_vm_destroy(struct hax_vm *vm);
 int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap);
diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
index 76e9235524..95b47c1c2e 100644
--- a/target/i386/hvf/hvf-i386.h
+++ b/target/i386/hvf/hvf-i386.h
@@ -24,11 +24,7 @@
 
 void hvf_handle_io(CPUArchState *, uint16_t, void *, int, int, int);
 
-#ifdef NEED_CPU_H
-/* Functions exported to host specific mode */
-
 /* Host specific functions */
 int hvf_inject_interrupt(CPUArchState *env, int vector);
-#endif
 
 #endif
-- 
2.38.1

[PULL 11/36] hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset

[Peter Maydell]

Convert the parent class TYPE_CPU to 3-phase reset. This
is a necessary prerequisite to converting the subclasses.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Message-id: 20221124115023.2437291-2-peter.mayd...@linaro.org
---
 hw/core/cpu-common.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index f9fdd46b9d7..78b5f350a00 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -116,9 +116,9 @@ void cpu_reset(CPUState *cpu)
 trace_guest_cpu_reset(cpu);
 }
 
-static void cpu_common_reset(DeviceState *dev)
+static void cpu_common_reset_hold(Object *obj)
 {
-CPUState *cpu = CPU(dev);
+CPUState *cpu = CPU(obj);
 CPUClass *cc = CPU_GET_CLASS(cpu);
 
 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
@@ -259,6 +259,7 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
 static void cpu_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 CPUClass *k = CPU_CLASS(klass);
 
 k->parse_features = cpu_common_parse_features;
@@ -269,7 +270,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
 dc->realize = cpu_common_realizefn;
 dc->unrealize = cpu_common_unrealizefn;
-dc->reset = cpu_common_reset;
+rc->phases.hold = cpu_common_reset_hold;
 cpu_class_init_props(dc);
 /*
  * Reason: CPUs still need special care by board code: wiring up
-- 
2.25.1

[PATCH v2 1/2] hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope

[Philippe Mathieu-Daudé]

This function is not used anywhere outside this file,
so we can make the function "static void".

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/arm/smmu-common.c | 2 +-
 include/hw/arm/smmu-common.h | 3 ---
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 220838525d..9f196625a2 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -483,7 +483,7 @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n)
 }
 
 /* Unmap all notifiers attached to @mr */
-inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
+static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
 {
 IOMMUNotifier *n;
 
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 21e62342e9..c5683af07d 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -173,7 +173,4 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t 
iova,
 /* Unmap the range of all the notifiers registered to any IOMMU mr */
 void smmu_inv_notifiers_all(SMMUState *s);
 
-/* Unmap the range of all the notifiers registered to @mr */
-void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
-
 #endif /* HW_ARM_SMMU_COMMON_H */
-- 
2.38.1

[PATCH 1/2] sysemu/kvm: Remove CONFIG_USER_ONLY guard

[Philippe Mathieu-Daudé]

User emulation shouldn't really include this header; if included
these declarations are guarded by CONFIG_KVM_IS_POSSIBLE.

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/sysemu/kvm.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index e9a97eda8c..c8281c07a7 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -471,10 +471,8 @@ uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, 
uint32_t index);
 
 void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len);
 
-#if !defined(CONFIG_USER_ONLY)
 int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
hwaddr *phys_addr);
-#endif
 
 #endif /* NEED_CPU_H */
 
-- 
2.38.1

[PATCH v3 3/5] gdbstub: Use vaddr type for generic insert/remove_breakpoint() API

[Philippe Mathieu-Daudé]

Both insert/remove_breakpoint() handlers are used in system and
user emulation. We can not use the 'hwaddr' type on user emulation,
we have to use 'vaddr' which is defined as "wide enough to contain
any #target_ulong virtual address".

gdbstub.c doesn't require to include "exec/hwaddr.h" anymore.

Reviewed-by: Richard Henderson 
Reviewed-by: Fabiano Rosas 
Signed-off-by: Philippe Mathieu-Daudé 
---
 accel/kvm/kvm-all.c| 4 ++--
 accel/kvm/kvm-cpus.h   | 4 ++--
 accel/tcg/tcg-accel-ops.c  | 4 ++--
 gdbstub/gdbstub.c  | 1 -
 gdbstub/internals.h| 6 --
 gdbstub/softmmu.c  | 5 ++---
 gdbstub/user.c | 5 ++---
 include/sysemu/accel-ops.h | 6 +++---
 8 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index e86c33e0e6..1bb324917a 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -3219,7 +3219,7 @@ bool kvm_supports_guest_debug(void)
 return kvm_has_guest_debug;
 }
 
-int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
+int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len)
 {
 struct kvm_sw_breakpoint *bp;
 int err;
@@ -3257,7 +3257,7 @@ int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr 
addr, hwaddr len)
 return 0;
 }
 
-int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
+int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len)
 {
 struct kvm_sw_breakpoint *bp;
 int err;
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h
index fd63fe6a59..ca40add32c 100644
--- a/accel/kvm/kvm-cpus.h
+++ b/accel/kvm/kvm-cpus.h
@@ -19,8 +19,8 @@ void kvm_cpu_synchronize_post_reset(CPUState *cpu);
 void kvm_cpu_synchronize_post_init(CPUState *cpu);
 void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu);
 bool kvm_supports_guest_debug(void);
-int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len);
-int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len);
+int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len);
+int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len);
 void kvm_remove_all_breakpoints(CPUState *cpu);
 
 #endif /* KVM_CPUS_H */
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 19cbf1db3a..d9228fd403 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -116,7 +116,7 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
 return cputype;
 }
 
-static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr 
len)
+static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
 {
 CPUState *cpu;
 int err = 0;
@@ -147,7 +147,7 @@ static int tcg_insert_breakpoint(CPUState *cs, int type, 
hwaddr addr, hwaddr len
 }
 }
 
-static int tcg_remove_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr 
len)
+static int tcg_remove_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
 {
 CPUState *cpu;
 int err = 0;
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index be88ca0d71..c3fbc31123 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -48,7 +48,6 @@
 #include "sysemu/runstate.h"
 #include "semihosting/semihost.h"
 #include "exec/exec-all.h"
-#include "exec/hwaddr.h"
 #include "sysemu/replay.h"
 
 #include "internals.h"
diff --git a/gdbstub/internals.h b/gdbstub/internals.h
index eabb0341d1..b23999f951 100644
--- a/gdbstub/internals.h
+++ b/gdbstub/internals.h
@@ -9,9 +9,11 @@
 #ifndef _INTERNALS_H_
 #define _INTERNALS_H_
 
+#include "exec/cpu-common.h"
+
 bool gdb_supports_guest_debug(void);
-int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len);
-int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len);
+int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len);
+int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len);
 void gdb_breakpoint_remove_all(CPUState *cs);
 
 #endif /* _INTERNALS_H_ */
diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c
index f208c6cf15..129575e510 100644
--- a/gdbstub/softmmu.c
+++ b/gdbstub/softmmu.c
@@ -11,7 +11,6 @@
 
 #include "qemu/osdep.h"
 #include "exec/gdbstub.h"
-#include "exec/hwaddr.h"
 #include "sysemu/cpus.h"
 #include "internals.h"
 
@@ -24,7 +23,7 @@ bool gdb_supports_guest_debug(void)
 return false;
 }
 
-int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
+int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len)
 {
 const AccelOpsClass *ops = cpus_get_accel();
 if (ops->insert_breakpoint) {
@@ -33,7 +32,7 @@ int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr 
addr, hwaddr len)
 return -ENOSYS;
 }
 
-int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len)
+int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len)
 {
 const AccelOpsClass *ops = cpus_get_accel();
 if 

[PATCH 10/10] target/xtensa/cpu: Include missing "memory.h" header

[Philippe Mathieu-Daudé]

Under system emulation, xtensa_cpu_initfn() calls
memory_region_init_io(), itself declared in "exec/memory.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/xtensa/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 09923301c4..879710f8d1 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -35,6 +35,9 @@
 #include "qemu/module.h"
 #include "migration/vmstate.h"
 #include "hw/qdev-clock.h"
+#ifndef CONFIG_USER_ONLY
+#include "exec/memory.h"
+#endif
 
 
 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
-- 
2.38.1

[PATCH v3 1/5] dump: Include missing "cpu.h" header for tswap32/tswap64() declarations

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 dump/dump.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/dump/dump.c b/dump/dump.c
index 279b07f09b..c62dc94213 100644
--- a/dump/dump.c
+++ b/dump/dump.c
@@ -29,6 +29,7 @@
 #include "qemu/main-loop.h"
 #include "hw/misc/vmcoreinfo.h"
 #include "migration/blocker.h"
+#include "cpu.h"
 
 #ifdef TARGET_X86_64
 #include "win_dump.h"
-- 
2.38.1

[PATCH 09/10] target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard

[Philippe Mathieu-Daudé]

Commit caac44a52a ("target/sparc: Make sparc_cpu_tlb_fill sysemu
only") restricted mmu_helper.c to system emulation. Checking
whether CONFIG_USER_ONLY is defined is now pointless.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/sparc/mmu_helper.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 919448a494..a7e51e4b7d 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -924,7 +924,6 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr 
addr)
 return phys_addr;
 }
 
-#ifndef CONFIG_USER_ONLY
 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
   MMUAccessType access_type,
   int mmu_idx,
@@ -942,4 +941,3 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, 
vaddr addr,
 
 cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
 }
-#endif /* !CONFIG_USER_ONLY */
-- 
2.38.1

[PATCH 2/5] hw/s390x/pv: Un-inline s390_pv_init()

[Philippe Mathieu-Daudé]

There is no point in having s390_pv_init() inlined.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/s390x/pv.c | 13 +
 include/hw/s390x/pv.h | 14 +-
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/s390x/pv.c b/hw/s390x/pv.c
index 8dfe92d8df..9c511369b2 100644
--- a/hw/s390x/pv.c
+++ b/hw/s390x/pv.c
@@ -26,6 +26,19 @@ static bool info_valid;
 static struct kvm_s390_pv_info_vm info_vm;
 static struct kvm_s390_pv_info_dump info_dump;
 
+int s390_pv_init(ConfidentialGuestSupport *cgs, Error **errp)
+{
+if (!cgs) {
+return 0;
+}
+if (kvm_enabled()) {
+return s390_pv_kvm_init(cgs, errp);
+}
+
+error_setg(errp, "Protected Virtualization requires KVM");
+return -1;
+}
+
 static int __s390_pv_cmd(uint32_t cmd, const char *cmdname, void *data)
 {
 struct kvm_pv_cmd pv_cmd = {
diff --git a/include/hw/s390x/pv.h b/include/hw/s390x/pv.h
index 9360aa1091..5bca5bcaf1 100644
--- a/include/hw/s390x/pv.h
+++ b/include/hw/s390x/pv.h
@@ -12,7 +12,6 @@
 #ifndef HW_S390_PV_H
 #define HW_S390_PV_H
 
-#include "qapi/error.h"
 #include "sysemu/kvm.h"
 
 #ifdef CONFIG_KVM
@@ -78,17 +77,6 @@ static inline int kvm_s390_dump_completion_data(void *buff) 
{ return 0; }
 #endif /* CONFIG_KVM */
 
 int s390_pv_kvm_init(ConfidentialGuestSupport *cgs, Error **errp);
-static inline int s390_pv_init(ConfidentialGuestSupport *cgs, Error **errp)
-{
-if (!cgs) {
-return 0;
-}
-if (kvm_enabled()) {
-return s390_pv_kvm_init(cgs, errp);
-}
-
-error_setg(errp, "Protected Virtualization requires KVM");
-return -1;
-}
+int s390_pv_init(ConfidentialGuestSupport *cgs, Error **errp);
 
 #endif /* HW_S390_PV_H */
-- 
2.38.1

[PATCH v3 2/5] cputlb: Restrict SavedIOTLB to system emulation

[Philippe Mathieu-Daudé]

Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in
case of reset") added the SavedIOTLB structure -- which is
system emulation specific -- in the generic CPUState structure.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 include/hw/core/cpu.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8830546121..bc3229ae13 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -222,7 +222,7 @@ struct CPUWatchpoint {
 QTAILQ_ENTRY(CPUWatchpoint) entry;
 };
 
-#ifdef CONFIG_PLUGIN
+#if defined(CONFIG_PLUGIN) && !defined(CONFIG_USER_ONLY)
 /*
  * For plugins we sometime need to save the resolved iotlb data before
  * the memory regions get moved around  by io_writex.
@@ -406,9 +406,11 @@ struct CPUState {
 
 #ifdef CONFIG_PLUGIN
 GArray *plugin_mem_cbs;
+#if !defined(CONFIG_USER_ONLY)
 /* saved iotlb data from io_writex */
 SavedIOTLB saved_iotlb;
-#endif
+#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_PLUGIN */
 
 /* TODO Move common fields from CPUArchState here. */
 int cpu_index;
-- 
2.38.1

[PULL 32/36] pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset

[Peter Maydell]

Convert the TYPE_PCIE_ROOT_PORT device to 3-phase reset; this is a
necessary precursor to converting any of its child classes.

Signed-off-by: Peter Maydell 
Tested-by: Daniel Henrique Barboza 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221125115240.3005559-4-peter.mayd...@linaro.org
---
 hw/pci-bridge/pcie_root_port.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
index 460e48269d4..36bc0bafa7e 100644
--- a/hw/pci-bridge/pcie_root_port.c
+++ b/hw/pci-bridge/pcie_root_port.c
@@ -43,9 +43,10 @@ static void rp_write_config(PCIDevice *d, uint32_t address,
 pcie_aer_root_write_config(d, address, val, len, root_cmd);
 }
 
-static void rp_reset(DeviceState *qdev)
+static void rp_reset_hold(Object *obj)
 {
-PCIDevice *d = PCI_DEVICE(qdev);
+PCIDevice *d = PCI_DEVICE(obj);
+DeviceState *qdev = DEVICE(obj);
 
 rp_aer_vector_update(d);
 pcie_cap_root_reset(d);
@@ -171,13 +172,14 @@ static void rp_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 
 k->is_bridge = true;
 k->config_write = rp_write_config;
 k->realize = rp_realize;
 k->exit = rp_exit;
 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
-dc->reset = rp_reset;
+rc->phases.hold = rp_reset_hold;
 device_class_set_props(dc, rp_props);
 }
 
-- 
2.25.1

[PULL 30/36] hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset

[Peter Maydell]

Convert the TYPE_VIRTIO_PCI class to 3-phase reset.  This is
necessary so that we can convert the subclass TYPE_VIRTIO_VGA_BASE
also to 3-phase reset.

Signed-off-by: Peter Maydell 
Tested-by: Daniel Henrique Barboza 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221125115240.3005559-2-peter.mayd...@linaro.org
---
 hw/virtio/virtio-pci.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index a1c9dfa7bb5..7873083b860 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -2008,9 +2008,10 @@ static void virtio_pci_reset(DeviceState *qdev)
 }
 }
 
-static void virtio_pci_bus_reset(DeviceState *qdev)
+static void virtio_pci_bus_reset_hold(Object *obj)
 {
-PCIDevice *dev = PCI_DEVICE(qdev);
+PCIDevice *dev = PCI_DEVICE(obj);
+DeviceState *qdev = DEVICE(obj);
 
 virtio_pci_reset(qdev);
 
@@ -2071,6 +2072,7 @@ static void virtio_pci_class_init(ObjectClass *klass, 
void *data)
 DeviceClass *dc = DEVICE_CLASS(klass);
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 
 device_class_set_props(dc, virtio_pci_properties);
 k->realize = virtio_pci_realize;
@@ -2080,7 +2082,7 @@ static void virtio_pci_class_init(ObjectClass *klass, 
void *data)
 k->class_id = PCI_CLASS_OTHERS;
 device_class_set_parent_realize(dc, virtio_pci_dc_realize,
 >parent_dc_realize);
-dc->reset = virtio_pci_bus_reset;
+rc->phases.hold = virtio_pci_bus_reset_hold;
 }
 
 static const TypeInfo virtio_pci_info = {
-- 
2.25.1

[PULL 08/36] hw/input/ps2.c: Convert TYPE_PS2_{KBD, MOUSE}_DEVICE to 3-phase reset

[Peter Maydell]

Convert the child classes TYPE_PS2_KBD_DEVICE and
TYPE_PS2_MOUSE_DEVICE to the 3-phase reset system.  This allows us to
stop using the old device_class_set_parent_reset() function.

We don't need to register an 'exit' phase function for the
subclasses, because they have no work to do in that phase.  Passing
NULL to resettable_class_set_parent_phases() will result in the
parent class method being called for that phase, so we don't need to
register a function purely to chain to the parent 'exit' phase
function.

Signed-off-by: Peter Maydell 
Reviewed-by: Richard Henderson 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221109170009.3498451-3-peter.mayd...@linaro.org
---
 include/hw/input/ps2.h |  2 +-
 hw/input/ps2.c | 31 ---
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index ff777582cd6..cd61a634c39 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -36,7 +36,7 @@
 struct PS2DeviceClass {
 SysBusDeviceClass parent_class;
 
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 /*
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 47a5d68e300..3253ab6a92c 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -1042,13 +1042,16 @@ static void ps2_common_post_load(PS2State *s)
 q->cwptr = ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1;
 }
 
-static void ps2_kbd_reset(DeviceState *dev)
+static void ps2_kbd_reset_hold(Object *obj)
 {
-PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(dev);
-PS2KbdState *s = PS2_KBD_DEVICE(dev);
+PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
+PS2KbdState *s = PS2_KBD_DEVICE(obj);
 
 trace_ps2_kbd_reset(s);
-ps2dc->parent_reset(dev);
+
+if (ps2dc->parent_phases.hold) {
+ps2dc->parent_phases.hold(obj);
+}
 
 s->scan_enabled = 1;
 s->translate = 0;
@@ -1056,13 +1059,16 @@ static void ps2_kbd_reset(DeviceState *dev)
 s->modifiers = 0;
 }
 
-static void ps2_mouse_reset(DeviceState *dev)
+static void ps2_mouse_reset_hold(Object *obj)
 {
-PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(dev);
-PS2MouseState *s = PS2_MOUSE_DEVICE(dev);
+PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
+PS2MouseState *s = PS2_MOUSE_DEVICE(obj);
 
 trace_ps2_mouse_reset(s);
-ps2dc->parent_reset(dev);
+
+if (ps2dc->parent_phases.hold) {
+ps2dc->parent_phases.hold(obj);
+}
 
 s->mouse_status = 0;
 s->mouse_resolution = 0;
@@ -1245,10 +1251,12 @@ static void ps2_mouse_realize(DeviceState *dev, Error 
**errp)
 static void ps2_kbd_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
 
 dc->realize = ps2_kbd_realize;
-device_class_set_parent_reset(dc, ps2_kbd_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, ps2_kbd_reset_hold, NULL,
+   >parent_phases);
 dc->vmsd = _ps2_keyboard;
 }
 
@@ -1262,11 +1270,12 @@ static const TypeInfo ps2_kbd_info = {
 static void ps2_mouse_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
 
 dc->realize = ps2_mouse_realize;
-device_class_set_parent_reset(dc, ps2_mouse_reset,
-  >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, ps2_mouse_reset_hold, NULL,
+   >parent_phases);
 dc->vmsd = _ps2_mouse;
 }
 
-- 
2.25.1

[PULL 31/36] hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset

[Peter Maydell]

Convert the TYPE_VIRTIO_VGA_BASE class to 3-phase reset, so we
don't need to use device_class_set_parent_reset() any more.

Note that this is an abstract class itself; none of the subclasses
override its reset method.

Signed-off-by: Peter Maydell 
Tested-by: Daniel Henrique Barboza 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221125115240.3005559-3-peter.mayd...@linaro.org
---
 hw/display/virtio-vga.h |  2 +-
 hw/display/virtio-vga.c | 15 +--
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/hw/display/virtio-vga.h b/hw/display/virtio-vga.h
index 977ad5edc29..0bd9db1ceea 100644
--- a/hw/display/virtio-vga.h
+++ b/hw/display/virtio-vga.h
@@ -23,7 +23,7 @@ struct VirtIOVGABase {
 struct VirtIOVGABaseClass {
 VirtioPCIClass parent_class;
 
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 #endif /* VIRTIO_VGA_H */
diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c
index 4dcb34c4a74..e6fb0aa876c 100644
--- a/hw/display/virtio-vga.c
+++ b/hw/display/virtio-vga.c
@@ -165,13 +165,15 @@ static void virtio_vga_base_realize(VirtIOPCIProxy 
*vpci_dev, Error **errp)
 }
 }
 
-static void virtio_vga_base_reset(DeviceState *dev)
+static void virtio_vga_base_reset_hold(Object *obj)
 {
-VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev);
-VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev);
+VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj);
+VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj);
 
 /* reset virtio-gpu */
-klass->parent_reset(dev);
+if (klass->parent_phases.hold) {
+klass->parent_phases.hold(obj);
+}
 
 /* reset vga */
 vga_common_reset(>vga);
@@ -203,13 +205,14 @@ static void virtio_vga_base_class_init(ObjectClass 
*klass, void *data)
 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
 VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 
 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 device_class_set_props(dc, virtio_vga_base_properties);
 dc->vmsd = _virtio_vga_base;
 dc->hotpluggable = false;
-device_class_set_parent_reset(dc, virtio_vga_base_reset,
-  >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, virtio_vga_base_reset_hold,
+   NULL, >parent_phases);
 
 k->realize = virtio_vga_base_realize;
 pcidev_k->romfile = "vgabios-virtio.bin";
-- 
2.25.1

Re: [PULL 0/8] QEMU Guest Agent misc patches

[Peter Maydell]

On Fri, 16 Dec 2022 at 13:54, Konstantin Kostiuk  wrote:
>
> The following changes since commit edc93f455fa823a9a5fcb3a8da430104c7375a0a:
>
>   Revert "hw/loongarch/virt: Add cfi01 pflash device" (2022-12-05 11:24:35 
> -0500)
>
> are available in the Git repository at:
>
>   g...@github.com:kostyanf14/qemu.git tags/qga-pull-2022-12-16
>
> for you to fetch changes up to 10d83e7d59af4464ba4382bcbf31ed162db87656:
>
>   qga: map GLib log levels to system levels (2022-12-16 14:24:36 +0200)
>
> 
> qga-pull-2022-12-16

Hi; I'm afraid this doesn't apply because Markus' qapi pullreq
has changed the implementation of qmp_guest_fstrim() to not use
the no-longer-existing 'has_*' fields in QAPI-generated structs;
can you rebase and resend, please?


thanks
-- PMM

[PULL 29/36] target/xtensa: Convert to 3-phase reset

[Peter Maydell]

Convert the xtensa CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Reviewed-by: Greg Kurz 
Reviewed-by: Mark Cave-Ayland 
Message-id: 20221124115023.2437291-20-peter.mayd...@linaro.org
---
 target/xtensa/cpu-qom.h |  4 ++--
 target/xtensa/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 4fc35ee49b8..419c7d8e4a3 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -41,7 +41,7 @@ typedef struct XtensaConfig XtensaConfig;
 /**
  * XtensaCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  * @config: The CPU core configuration.
  *
  * An Xtensa CPU model.
@@ -52,7 +52,7 @@ struct XtensaCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 
 const XtensaConfig *config;
 };
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 09923301c40..2dc8f2d232f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -85,16 +85,18 @@ bool xtensa_abi_call0(void)
 }
 #endif
 
-static void xtensa_cpu_reset(DeviceState *dev)
+static void xtensa_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 XtensaCPU *cpu = XTENSA_CPU(s);
 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
 CPUXtensaState *env = >env;
 bool dfpu = xtensa_option_enabled(env->config,
   XTENSA_OPTION_DFP_COPROCESSOR);
 
-xcc->parent_reset(dev);
+if (xcc->parent_phases.hold) {
+xcc->parent_phases.hold(obj);
+}
 
 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
 env->sregs[LITBASE] &= ~1;
@@ -240,11 +242,13 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void 
*data)
 DeviceClass *dc = DEVICE_CLASS(oc);
 CPUClass *cc = CPU_CLASS(oc);
 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
 >parent_realize);
 
-device_class_set_parent_reset(dc, xtensa_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = xtensa_cpu_class_by_name;
 cc->has_work = xtensa_cpu_has_work;
-- 
2.25.1

[PATCH 04/10] target/loongarch/cpu: Restrict "memory.h" header to sysemu

[Philippe Mathieu-Daudé]

Missed in 0093b9a5ee ("target/loongarch: Adjust functions
and structure to support user-mode") while cleaning commit
f84a2aacf5 ("target/loongarch: Add LoongArch IOCSR instruction").

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/loongarch/cpu.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index c8612f5466..2f17ac6b47 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -12,7 +12,9 @@
 #include "fpu/softfloat-types.h"
 #include "hw/registerfields.h"
 #include "qemu/timer.h"
+#ifndef CONFIG_USER_ONLY
 #include "exec/memory.h"
+#endif
 #include "cpu-csr.h"
 
 #define IOCSRF_TEMP 0
-- 
2.38.1

[PATCH 2/5] target/i386/cpu: Remove dead helper_lock() declaration

[Philippe Mathieu-Daudé]

Missed in commit 37b995f6e7 ("target-i386: remove helper_lock()").

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/i386/cpu.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f729e0f09c..9824b7f8f2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2313,9 +2313,6 @@ static inline void cpu_set_fpuc(CPUX86State *env, 
uint16_t fpuc)
  }
 }
 
-/* mem_helper.c */
-void helper_lock_init(void);
-
 /* svm_helper.c */
 #ifdef CONFIG_USER_ONLY
 static inline void
-- 
2.38.1

[PATCH 0/5] target/i386: Header cleanups around "cpu.h"

[Philippe Mathieu-Daudé]

These patches are part of a big refactor cleanup
around "cpu.h". Most changes should be trivial IMHO.

Philippe Mathieu-Daudé (5):
  target/i386: Remove NEED_CPU_H guard from target-specific headers
  target/i386/cpu: Remove dead helper_lock() declaration
  target/i386/ops_sse: Include missing "cpu.h" header
  target/i386: Remove x86_cpu_dump_local_apic_state() dead stub
  hw/i386/x86: Reduce init_topo_info() scope

 hw/i386/x86.c| 2 +-
 include/hw/i386/x86.h| 3 ---
 target/i386/cpu-dump.c   | 5 +
 target/i386/cpu.h| 7 ---
 target/i386/hax/hax-i386.h   | 2 --
 target/i386/hvf/hvf-i386.h   | 4 
 target/i386/ops_sse.h| 1 +
 target/i386/ops_sse_header.h | 3 +++
 8 files changed, 10 insertions(+), 17 deletions(-)

-- 
2.38.1

[PULL 04/36] Replace use of qdev_reset_all() with device_cold_reset()

[Peter Maydell]

The legacy function qdev_reset_all() performs a recursive reset,
starting from a qdev.  However, it does not permit any of the devices
in the tree to use three-phase reset, because device reset goes
through the device_legacy_reset() function that only calls the single
DeviceClass::reset method.

Switch to using the device_cold_reset() function instead.  This also
performs a recursive reset, where first the children are reset and
then finally the parent, but it uses the new (...in 2020...)
Resettable mechanism, which supports both the old style single-reset
method and also the new 3-phase reset handling.

This commit changes the five remaining uses of this function.

Commit created with:
 sed -i -e 's/qdev_reset_all/device_cold_reset/g' hw/i386/xen/xen_platform.c 
hw/input/adb.c hw/remote/vfio-user-obj.c hw/s390x/s390-virtio-ccw.c 
hw/usb/dev-uas.c

Signed-off-by: Peter Maydell 
---
 hw/i386/xen/xen_platform.c | 2 +-
 hw/input/adb.c | 2 +-
 hw/remote/vfio-user-obj.c  | 2 +-
 hw/s390x/s390-virtio-ccw.c | 2 +-
 hw/usb/dev-uas.c   | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c
index a64265cca07..7db0d94ec28 100644
--- a/hw/i386/xen/xen_platform.c
+++ b/hw/i386/xen/xen_platform.c
@@ -177,7 +177,7 @@ static void pci_xen_ide_unplug(DeviceState *dev, bool aux)
 blk_unref(blk);
 }
 }
-qdev_reset_all(dev);
+device_cold_reset(dev);
 }
 
 static void unplug_disks(PCIBus *b, PCIDevice *d, void *opaque)
diff --git a/hw/input/adb.c b/hw/input/adb.c
index 84331b9fce6..214ae6f42b3 100644
--- a/hw/input/adb.c
+++ b/hw/input/adb.c
@@ -43,7 +43,7 @@ static const char *adb_commands[] = {
 
 static void adb_device_reset(ADBDevice *d)
 {
-qdev_reset_all(DEVICE(d));
+device_cold_reset(DEVICE(d));
 }
 
 static int do_adb_request(ADBBusState *s, uint8_t *obuf, const uint8_t *buf,
diff --git a/hw/remote/vfio-user-obj.c b/hw/remote/vfio-user-obj.c
index 6d0310cec97..fe1fdfb5f70 100644
--- a/hw/remote/vfio-user-obj.c
+++ b/hw/remote/vfio-user-obj.c
@@ -678,7 +678,7 @@ static int vfu_object_device_reset(vfu_ctx_t *vfu_ctx, 
vfu_reset_type_t type)
 return 0;
 }
 
-qdev_reset_all(DEVICE(o->pci_dev));
+device_cold_reset(DEVICE(o->pci_dev));
 
 return 0;
 }
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 2e64ffab45e..fab79045dd0 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -118,7 +118,7 @@ static void subsystem_reset(void)
 for (i = 0; i < ARRAY_SIZE(reset_dev_types); i++) {
 dev = DEVICE(object_resolve_path_type("", reset_dev_types[i], NULL));
 if (dev) {
-qdev_reset_all(dev);
+device_cold_reset(dev);
 }
 }
 }
diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c
index 5192b062d6f..88f99c05d53 100644
--- a/hw/usb/dev-uas.c
+++ b/hw/usb/dev-uas.c
@@ -791,7 +791,7 @@ static void usb_uas_task(UASDevice *uas, uas_iu *iu)
 
 case UAS_TMF_LOGICAL_UNIT_RESET:
 trace_usb_uas_tmf_logical_unit_reset(uas->dev.addr, tag, lun);
-qdev_reset_all(>qdev);
+device_cold_reset(>qdev);
 usb_uas_queue_response(uas, tag, UAS_RC_TMF_COMPLETE);
 break;
 
-- 
2.25.1

[PATCH 3/5] target/i386/ops_sse: Include missing "cpu.h" header

[Philippe Mathieu-Daudé]

'Reg' is defined as 'MMXReg', itself declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/i386/ops_sse.h| 1 +
 target/i386/ops_sse_header.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 3cbc36a59d..68c88c9ee3 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -19,6 +19,7 @@
  */
 
 #include "crypto/aes.h"
+#include "cpu.h"
 
 #if SHIFT == 0
 #define Reg MMXReg
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 8a7b2f4e2f..5631a6d1e1 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -16,6 +16,9 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see .
  */
+
+#include "cpu.h"
+
 #if SHIFT == 0
 #define Reg MMXReg
 #define SUFFIX _mmx
-- 
2.38.1

[PULL 17/36] target/loongarch: Convert to 3-phase reset

[Peter Maydell]

Convert the loongarch CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-8-peter.mayd...@linaro.org
---
 target/loongarch/cpu.h |  4 ++--
 target/loongarch/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index e15c633b0bf..e35cf655975 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -356,7 +356,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
 /**
  * LoongArchCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A LoongArch CPU model.
  */
@@ -366,7 +366,7 @@ struct LoongArchCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 /*
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index e7b0e12be6a..290ab4d526b 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -450,14 +450,16 @@ void loongarch_cpu_list(void)
 g_slist_free(list);
 }
 
-static void loongarch_cpu_reset(DeviceState *dev)
+static void loongarch_cpu_reset_hold(Object *obj)
 {
-CPUState *cs = CPU(dev);
+CPUState *cs = CPU(obj);
 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
 CPULoongArchState *env = >env;
 
-lacc->parent_reset(dev);
+if (lacc->parent_phases.hold) {
+lacc->parent_phases.hold(obj);
+}
 
 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
 env->fcsr0 = 0x0;
@@ -694,10 +696,12 @@ static void loongarch_cpu_class_init(ObjectClass *c, void 
*data)
 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
 CPUClass *cc = CPU_CLASS(c);
 DeviceClass *dc = DEVICE_CLASS(c);
+ResettableClass *rc = RESETTABLE_CLASS(c);
 
 device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
 >parent_realize);
-device_class_set_parent_reset(dc, loongarch_cpu_reset, 
>parent_reset);
+resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, 
NULL,
+   >parent_phases);
 
 cc->class_by_name = loongarch_cpu_class_by_name;
 cc->has_work = loongarch_cpu_has_work;
-- 
2.25.1

Re: [PULL v3 00/50] Block layer patches

[Peter Maydell]

On Thu, 15 Dec 2022 at 15:24, Kevin Wolf  wrote:
>
> The following changes since commit 48804eebd4a327e4b11f902ba80a00876ee53a43:
>
>   Merge tag 'pull-misc-2022-12-14' of https://repo.or.cz/qemu/armbru into 
> staging (2022-12-15 10:13:46 +)
>
> are available in the Git repository at:
>
>   https://repo.or.cz/qemu/kevin.git tags/for-upstream
>
> for you to fetch changes up to 1b3ff9feb942c2ad0b01ac931e99ad451ab0ef39:
>
>   block: GRAPH_RDLOCK for functions only called by co_wrappers (2022-12-15 
> 16:08:23 +0100)
>
> v3:
> - Dropped "configure: Enable -Wthread-safety if present" because FreeBSD
>   has TSA annotations in its pthread locking functions, so we would have
>   to annotate the use of every lock in QEMU first before we can enable
>   it.
>
> v2:
> - Changed TSA capability name to "mutex" to work with older clang
>   versions. The tsan-build CI job succeeds now.
>
> 
> Block layer patches
>
> - Code cleanups around block graph modification
> - Simplify drain
> - coroutine_fn correctness fixes, including splitting generated
>   coroutine wrappers into co_wrapper (to be called only from
>   non-coroutine context) and co_wrapper_mixed (both coroutine and
>   non-coroutine context)
> - Introduce a block graph rwlock


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM

[PATCH 07/10] target/ppc/internal: Restrict MMU declarations to sysemu

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/ppc/internal.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 337a362205..901bae6d39 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -242,9 +242,12 @@ static inline int prot_for_access_type(MMUAccessType 
access_type)
 g_assert_not_reached();
 }
 
+#ifndef CONFIG_USER_ONLY
+
 /* PowerPC MMU emulation */
 
 typedef struct mmu_ctx_t mmu_ctx_t;
+
 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
   hwaddr *raddrp, int *psizep, int *protp,
   int mmu_idx, bool guest_visible);
@@ -266,6 +269,8 @@ struct mmu_ctx_t {
 int nx;/* Non-execute area  */
 };
 
+#endif /* !CONFIG_USER_ONLY */
+
 /* Common routines used by software and hardware TLBs emulation */
 static inline int pte_is_valid(target_ulong pte0)
 {
-- 
2.38.1

[PULL 28/36] target/tricore: Convert to 3-phase reset

[Peter Maydell]

Convert the tricore CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Reviewed-by: Greg Kurz 
Reviewed-by: Mark Cave-Ayland 
Message-id: 20221124115023.2437291-19-peter.mayd...@linaro.org
---
 target/tricore/cpu-qom.h |  2 +-
 target/tricore/cpu.c | 12 
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index ee24e9fa76a..612731daa09 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -32,7 +32,7 @@ struct TriCoreCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 2c54a2825f8..594cd1efd5e 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -68,14 +68,16 @@ static void tricore_restore_state_to_opc(CPUState *cs,
 env->PC = data[0];
 }
 
-static void tricore_cpu_reset(DeviceState *dev)
+static void tricore_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 TriCoreCPU *cpu = TRICORE_CPU(s);
 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
 CPUTriCoreState *env = >env;
 
-tcc->parent_reset(dev);
+if (tcc->parent_phases.hold) {
+tcc->parent_phases.hold(obj);
+}
 
 cpu_state_reset(env);
 }
@@ -180,11 +182,13 @@ static void tricore_cpu_class_init(ObjectClass *c, void 
*data)
 TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
 CPUClass *cc = CPU_CLASS(c);
 DeviceClass *dc = DEVICE_CLASS(c);
+ResettableClass *rc = RESETTABLE_CLASS(c);
 
 device_class_set_parent_realize(dc, tricore_cpu_realizefn,
 >parent_realize);
 
-device_class_set_parent_reset(dc, tricore_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
+   >parent_phases);
 cc->class_by_name = tricore_cpu_class_by_name;
 cc->has_work = tricore_cpu_has_work;
 
-- 
2.25.1

[PATCH 08/10] target/riscv/cpu: Restrict sysemu-specific fields from CPUArchState

[Philippe Mathieu-Daudé]

The 'hwaddr' type is only available / meaningful on system emulation.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/riscv/cpu.h | 34 ++
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fc1f72e5c3..bd4e16d946 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -368,16 +368,6 @@ struct CPUArchState {
 uint64_t menvcfg;
 target_ulong senvcfg;
 uint64_t henvcfg;
-#endif
-target_ulong cur_pmmask;
-target_ulong cur_pmbase;
-
-float_status fp_status;
-
-/* Fields from here on are preserved across CPU reset. */
-QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
-QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
-bool vstime_irq;
 
 hwaddr kernel_addr;
 hwaddr fdt_addr;
@@ -388,6 +378,16 @@ struct CPUArchState {
 uint64_t kvm_timer_compare;
 uint64_t kvm_timer_state;
 uint64_t kvm_timer_frequency;
+#endif
+target_ulong cur_pmmask;
+target_ulong cur_pmbase;
+
+float_status fp_status;
+
+/* Fields from here on are preserved across CPU reset. */
+QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
+QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
+bool vstime_irq;
 };
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
@@ -553,12 +553,20 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 bool riscv_cpu_two_stage_lookup(int mmu_idx);
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
+#ifndef CONFIG_USER_ONLY
+hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int 
mmu_idx,
uintptr_t retaddr);
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 MMUAccessType access_type, int mmu_idx,
 bool probe, uintptr_t retaddr);
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+#endif
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(void);
 
@@ -566,12 +574,6 @@ void riscv_cpu_list(void);
 #define cpu_mmu_index riscv_cpu_mmu_index
 
 #ifndef CONFIG_USER_ONLY
-void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
-hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
-- 
2.38.1

[PATCH v3 5/5] target/cpu: Restrict do_transaction_failed() handlers to sysemu

[Philippe Mathieu-Daudé]

The 'hwaddr' type is only available / meaningful on system emulation.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/arm/internals.h |  2 ++
 target/m68k/cpu.h  |  2 ++
 target/riscv/cpu.h | 10 +-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 161e42d50f..14eb791226 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -624,6 +624,7 @@ G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, 
vaddr vaddr,
 MMUAccessType access_type,
 int mmu_idx, uintptr_t retaddr);
 
+#ifndef CONFIG_USER_ONLY
 /* arm_cpu_do_transaction_failed: handle a memory system error response
  * (eg "no device/memory present at address") by raising an external abort
  * exception
@@ -633,6 +634,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+#endif
 
 /* Call any registered EL change hooks */
 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 68ed531fc3..048d5aae2b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -581,10 +581,12 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool 
ifetch)
 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#ifndef CONFIG_USER_ONLY
 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
  unsigned size, MMUAccessType access_type,
  int mmu_idx, MemTxAttrs attrs,
  MemTxResult response, uintptr_t retaddr);
+#endif
 
 #include "exec/cpu-all.h"
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 758336295b..fc1f72e5c3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -559,11 +559,6 @@ G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState 
*cs, vaddr addr,
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 MMUAccessType access_type, int mmu_idx,
 bool probe, uintptr_t retaddr);
-void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(void);
 
@@ -571,6 +566,11 @@ void riscv_cpu_list(void);
 #define cpu_mmu_index riscv_cpu_mmu_index
 
 #ifndef CONFIG_USER_ONLY
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
-- 
2.38.1

[PATCH 4/5] target/i386: Remove x86_cpu_dump_local_apic_state() dead stub

[Philippe Mathieu-Daudé]

x86_cpu_dump_local_apic_state() is called from monitor.c which
is only compiled for system emulation since commit bf95728400
("monitor: remove target-specific code from monitor.c").

Interestingly this stub was added few weeks later in commit
1f871d49e3 ("hmp: added local apic dump state") and was not
necessary by that time.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/i386/cpu-dump.c | 5 +
 target/i386/cpu.h  | 4 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
index 08ac957e99..40697064d9 100644
--- a/target/i386/cpu-dump.c
+++ b/target/i386/cpu-dump.c
@@ -335,10 +335,7 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
 }
 qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
 }
-#else
-void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
-{
-}
+
 #endif /* !CONFIG_USER_ONLY */
 
 #define DUMP_CODE_BYTES_TOTAL50
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9824b7f8f2..32d048f326 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2355,12 +2355,16 @@ typedef int X86CPUVersion;
  */
 void x86_cpu_set_default_version(X86CPUVersion version);
 
+#ifndef CONFIG_USER_ONLY
+
 #define APIC_DEFAULT_ADDRESS 0xfee0
 #define APIC_SPACE_SIZE  0x10
 
 /* cpu-dump.c */
 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
 
+#endif
+
 /* cpu.c */
 bool cpu_is_bsp(X86CPU *cpu);
 
-- 
2.38.1

[PULL 19/36] target/microblaze: Convert to 3-phase reset

[Peter Maydell]

Convert the microblaze CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-10-peter.mayd...@linaro.org
---
 target/microblaze/cpu-qom.h |  4 ++--
 target/microblaze/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index 255b39a45df..cda9220fa99 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, 
MICROBLAZE_CPU)
 /**
  * MicroBlazeCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A MicroBlaze CPU model.
  */
@@ -40,7 +40,7 @@ struct MicroBlazeCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 89e493f3ff7..817681f9b21 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -162,14 +162,16 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, 
int level)
 }
 #endif
 
-static void mb_cpu_reset(DeviceState *dev)
+static void mb_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 CPUMBState *env = >env;
 
-mcc->parent_reset(dev);
+if (mcc->parent_phases.hold) {
+mcc->parent_phases.hold(obj);
+}
 
 memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 env->res_addr = RES_ADDR_NONE;
@@ -399,10 +401,12 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 DeviceClass *dc = DEVICE_CLASS(oc);
 CPUClass *cc = CPU_CLASS(oc);
 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, mb_cpu_realizefn,
 >parent_realize);
-device_class_set_parent_reset(dc, mb_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = mb_cpu_class_by_name;
 cc->has_work = mb_cpu_has_work;
-- 
2.25.1

[PULL 36/36] hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset

[Peter Maydell]

Convert the TYPE_PHB3_MSI class to 3-phase reset, so we can
avoid using the device_class_set_parent_reset() function.

Signed-off-by: Peter Maydell 
Tested-by: Daniel Henrique Barboza 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221125115240.3005559-8-peter.mayd...@linaro.org
---
 include/hw/ppc/xics.h  |  2 +-
 hw/pci-host/pnv_phb3_msi.c | 15 +--
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 00b80b08c27..95ead0dd7c9 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -95,7 +95,7 @@ struct ICSStateClass {
 DeviceClass parent_class;
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 
 void (*reject)(ICSState *s, uint32_t irq);
 void (*resend)(ICSState *s);
diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c
index ae908fd9e41..41e63b066f9 100644
--- a/hw/pci-host/pnv_phb3_msi.c
+++ b/hw/pci-host/pnv_phb3_msi.c
@@ -228,12 +228,14 @@ static void phb3_msi_resend(ICSState *ics)
 }
 }
 
-static void phb3_msi_reset(DeviceState *dev)
+static void phb3_msi_reset_hold(Object *obj)
 {
-Phb3MsiState *msi = PHB3_MSI(dev);
-ICSStateClass *icsc = ICS_GET_CLASS(dev);
+Phb3MsiState *msi = PHB3_MSI(obj);
+ICSStateClass *icsc = ICS_GET_CLASS(obj);
 
-icsc->parent_reset(dev);
+if (icsc->parent_phases.hold) {
+icsc->parent_phases.hold(obj);
+}
 
 memset(msi->rba, 0, sizeof(msi->rba));
 msi->rba_sum = 0;
@@ -287,11 +289,12 @@ static void phb3_msi_class_init(ObjectClass *klass, void 
*data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 ICSStateClass *isc = ICS_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 
 device_class_set_parent_realize(dc, phb3_msi_realize,
 >parent_realize);
-device_class_set_parent_reset(dc, phb3_msi_reset,
-  >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, phb3_msi_reset_hold, NULL,
+   >parent_phases);
 
 isc->reject = phb3_msi_reject;
 isc->resend = phb3_msi_resend;
-- 
2.25.1

[PATCH 0/2] sysemu/kvm: Header cleanups around "cpu.h"

[Philippe Mathieu-Daudé]

These patches are part of a big refactor cleanup
around "cpu.h". Most changes should be trivial IMHO.

Philippe Mathieu-Daudé (2):
  sysemu/kvm: Remove CONFIG_USER_ONLY guard
  sysemu/kvm: Reduce target-specific declarations

 include/sysemu/kvm.h | 27 ---
 1 file changed, 12 insertions(+), 15 deletions(-)

-- 
2.38.1

Re: [RFC PATCH-for-8.0] hw: Avoid using inlined functions with external linkage

[Philippe Mathieu-Daudé]

On 8/12/22 17:27, Peter Maydell wrote:

On Thu, 8 Dec 2022 at 16:11, Philippe Mathieu-Daudé  wrote:


When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
and building with -Wall we get:

   hw/arm/smmu-common.c:173:33: warning: static function 
'smmu_hash_remove_by_asid_iova' is used in an inline function with external 
linkage [-Wstatic-in-inline]
   hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 
'smmu_iotlb_inv_iova' internal linkage
 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
 ^
 static

None of our code base require / use inlined functions with external
linkage. Some places use internal inlining in the hot path. These
two functions are certainly not in any hot path and don't justify
any inlining.

Reported-by: Stefan Weil 
Signed-off-by: Philippe Mathieu-Daudé 
---
RFC: Any better justification?


I don't really understand what the warning is trying to warn
about, and googling didn't enlighten me. Does anybody understand it?

In any case, it does seem weird to define a function inline and
also have it be defined in a C file rather than as a 'static inline'
in a header file, so these are likely oversights rather than
intentional.


---
  hw/arm/smmu-common.c | 10 +-
  hw/i386/x86.c|  3 +--
  2 files changed, 6 insertions(+), 7 deletions(-)



diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 78cc131926..9ac1680180 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -64,8 +64,7 @@
  /* Physical Address of PVH entry point read from kernel ELF NOTE */
  static size_t pvh_start_addr;

-inline void init_topo_info(X86CPUTopoInfo *topo_info,
-   const X86MachineState *x86ms)
+void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms)
  {
  MachineState *ms = MACHINE(x86ms);


This function is not used anywhere outside this file, so we
can delete the prototype from include/hw/i386/x86.h and
make the function "static void".


Good idea.


With those changes,
Reviewed-by: Peter Maydell 


Thanks!

[PULL 18/36] target/m68k: Convert to 3-phase reset

[Peter Maydell]

Convert the m68k CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-9-peter.mayd...@linaro.org
---
 target/m68k/cpu-qom.h |  4 ++--
 target/m68k/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index cd9687192cd..0ec7750a926 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
 /*
  * M68kCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A Motorola 68k CPU model.
  */
@@ -40,7 +40,7 @@ struct M68kCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b67ddea2aee..99af1ab541a 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -66,16 +66,18 @@ static void m68k_unset_feature(CPUM68KState *env, int 
feature)
 env->features &= ~BIT_ULL(feature);
 }
 
-static void m68k_cpu_reset(DeviceState *dev)
+static void m68k_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 M68kCPU *cpu = M68K_CPU(s);
 M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);
 CPUM68KState *env = >env;
 floatx80 nan = floatx80_default_nan(NULL);
 int i;
 
-mcc->parent_reset(dev);
+if (mcc->parent_phases.hold) {
+mcc->parent_phases.hold(obj);
+}
 
 memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
 #ifdef CONFIG_SOFTMMU
@@ -552,10 +554,12 @@ static void m68k_cpu_class_init(ObjectClass *c, void 
*data)
 M68kCPUClass *mcc = M68K_CPU_CLASS(c);
 CPUClass *cc = CPU_CLASS(c);
 DeviceClass *dc = DEVICE_CLASS(c);
+ResettableClass *rc = RESETTABLE_CLASS(c);
 
 device_class_set_parent_realize(dc, m68k_cpu_realizefn,
 >parent_realize);
-device_class_set_parent_reset(dc, m68k_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, m68k_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = m68k_cpu_class_by_name;
 cc->has_work = m68k_cpu_has_work;
-- 
2.25.1

[PULL 10/36] hw/misc: Convert TYPE_MOS6522 subclasses to 3-phase reset

[Peter Maydell]

Convert the various subclasses of TYPE_MOS6522 to 3-phase reset.
This removes some uses of device_class_set_parent_reset(), which we
would eventually like to be able to get rid of.

Signed-off-by: Peter Maydell 
Acked-by: Mark Cave-Ayland 
Reviewed-by: Richard Henderson 
Reviewed-by: Philippe Mathieu-Daudé 
Message-id: 20221110143459.3833425-3-peter.mayd...@linaro.org
---
 include/hw/misc/mos6522.h |  2 +-
 hw/misc/mac_via.c | 26 --
 hw/misc/macio/cuda.c  | 14 --
 hw/misc/macio/pmu.c   | 14 --
 4 files changed, 33 insertions(+), 23 deletions(-)

diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h
index 0bc22a83957..05872fffc92 100644
--- a/include/hw/misc/mos6522.h
+++ b/include/hw/misc/mos6522.h
@@ -157,7 +157,7 @@ OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, 
MOS6522)
 struct MOS6522DeviceClass {
 DeviceClass parent_class;
 
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 void (*portB_write)(MOS6522State *dev);
 void (*portA_write)(MOS6522State *dev);
 /* These are used to influence the CUDA MacOS timebase calibration */
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index f42c12755a9..076d18e5fd9 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -975,14 +975,16 @@ static int via1_post_load(void *opaque, int version_id)
 }
 
 /* VIA 1 */
-static void mos6522_q800_via1_reset(DeviceState *dev)
+static void mos6522_q800_via1_reset_hold(Object *obj)
 {
-MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev);
+MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj);
 MOS6522State *ms = MOS6522(v1s);
 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
 ADBBusState *adb_bus = >adb_bus;
 
-mdc->parent_reset(dev);
+if (mdc->parent_phases.hold) {
+mdc->parent_phases.hold(obj);
+}
 
 ms->timers[0].frequency = VIA_TIMER_FREQ;
 ms->timers[1].frequency = VIA_TIMER_FREQ;
@@ -1097,11 +1099,12 @@ static Property mos6522_q800_via1_properties[] = {
 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
 
 dc->realize = mos6522_q800_via1_realize;
-device_class_set_parent_reset(dc, mos6522_q800_via1_reset,
-  >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via1_reset_hold,
+   NULL, >parent_phases);
 dc->vmsd = _q800_via1;
 device_class_set_props(dc, mos6522_q800_via1_properties);
 }
@@ -1123,12 +1126,14 @@ static void mos6522_q800_via2_portB_write(MOS6522State 
*s)
 }
 }
 
-static void mos6522_q800_via2_reset(DeviceState *dev)
+static void mos6522_q800_via2_reset_hold(Object *obj)
 {
-MOS6522State *ms = MOS6522(dev);
+MOS6522State *ms = MOS6522(obj);
 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
 
-mdc->parent_reset(dev);
+if (mdc->parent_phases.hold) {
+mdc->parent_phases.hold(obj);
+}
 
 ms->timers[0].frequency = VIA_TIMER_FREQ;
 ms->timers[1].frequency = VIA_TIMER_FREQ;
@@ -1183,10 +1188,11 @@ static const VMStateDescription vmstate_q800_via2 = {
 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
 
-device_class_set_parent_reset(dc, mos6522_q800_via2_reset,
-  >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via2_reset_hold,
+   NULL, >parent_phases);
 dc->vmsd = _q800_via2;
 mdc->portB_write = mos6522_q800_via2_portB_write;
 }
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 0d4c13319a8..853e88bfedd 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -589,12 +589,14 @@ static void mos6522_cuda_portB_write(MOS6522State *s)
 cuda_update(cs);
 }
 
-static void mos6522_cuda_reset(DeviceState *dev)
+static void mos6522_cuda_reset_hold(Object *obj)
 {
-MOS6522State *ms = MOS6522(dev);
+MOS6522State *ms = MOS6522(obj);
 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
 
-mdc->parent_reset(dev);
+if (mdc->parent_phases.hold) {
+mdc->parent_phases.hold(obj);
+}
 
 ms->timers[0].frequency = CUDA_TIMER_FREQ;
 ms->timers[1].frequency = (SCALE_US * 6000) / 4700;
@@ -602,11 +604,11 @@ static void mos6522_cuda_reset(DeviceState *dev)
 
 static void mos6522_cuda_class_init(ObjectClass *oc, void *data)
 {
-DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
 
-device_class_set_parent_reset(dc, mos6522_cuda_reset,
-  >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, 

[PATCH 06/10] target/ppc/helper: Include missing "cpu.h" header

[Philippe Mathieu-Daudé]

'dh_ctype_*' are defined as 'ppc_avr_t/ppc_vsr_t/ppc_acc_t',
themselves declared in "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/ppc/helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8dd22a35e4..a02db8d893 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -1,3 +1,5 @@
+#include "cpu.h"
+
 DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, noreturn, env, i32, 
i32)
 DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
 DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
-- 
2.38.1

[PULL 22/36] target/openrisc: Convert to 3-phase reset

[Peter Maydell]

Convert the openrisc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Message-id: 20221124115023.2437291-13-peter.mayd...@linaro.org
---
 target/openrisc/cpu.h |  4 ++--
 target/openrisc/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 1d5efa5ca2f..5f607497052 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, 
OPENRISC_CPU)
 /**
  * OpenRISCCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  *
  * A OpenRISC CPU model.
  */
@@ -44,7 +44,7 @@ struct OpenRISCCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 };
 
 #define TARGET_INSN_START_EXTRA_WORDS 1
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index de0176cd20c..4c11a1f7ada 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -70,13 +70,15 @@ static void openrisc_disas_set_info(CPUState *cpu, 
disassemble_info *info)
 info->print_insn = print_insn_or1k;
 }
 
-static void openrisc_cpu_reset(DeviceState *dev)
+static void openrisc_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 OpenRISCCPU *cpu = OPENRISC_CPU(s);
 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
 
-occ->parent_reset(dev);
+if (occ->parent_phases.hold) {
+occ->parent_phases.hold(obj);
+}
 
 memset(>env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
 
@@ -229,10 +231,12 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void 
*data)
 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 CPUClass *cc = CPU_CLASS(occ);
 DeviceClass *dc = DEVICE_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 >parent_realize);
-device_class_set_parent_reset(dc, openrisc_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = openrisc_cpu_class_by_name;
 cc->has_work = openrisc_cpu_has_work;
-- 
2.25.1

[PULL 26/36] target/sh4: Convert to 3-phase reset

[Peter Maydell]

Convert the sh4 CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Alistair Francis 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Taylor Simpson 
Reviewed-by: Greg Kurz 
Message-id: 20221124115023.2437291-17-peter.mayd...@linaro.org
---
 target/sh4/cpu-qom.h |  4 ++--
 target/sh4/cpu.c | 12 
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index d4192d10908..89785a90f02 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
 /**
  * SuperHCPUClass:
  * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
  * @pvr: Processor Version Register
  * @prr: Processor Revision Register
  * @cvr: Cache Version Register
@@ -47,7 +47,7 @@ struct SuperHCPUClass {
 /*< public >*/
 
 DeviceRealize parent_realize;
-DeviceReset parent_reset;
+ResettablePhases parent_phases;
 
 uint32_t pvr;
 uint32_t prr;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 453268392bf..951eb6b9c8d 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -87,14 +87,16 @@ static bool superh_cpu_has_work(CPUState *cs)
 return cs->interrupt_request & CPU_INTERRUPT_HARD;
 }
 
-static void superh_cpu_reset(DeviceState *dev)
+static void superh_cpu_reset_hold(Object *obj)
 {
-CPUState *s = CPU(dev);
+CPUState *s = CPU(obj);
 SuperHCPU *cpu = SUPERH_CPU(s);
 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
 CPUSH4State *env = >env;
 
-scc->parent_reset(dev);
+if (scc->parent_phases.hold) {
+scc->parent_phases.hold(obj);
+}
 
 memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
 
@@ -274,11 +276,13 @@ static void superh_cpu_class_init(ObjectClass *oc, void 
*data)
 DeviceClass *dc = DEVICE_CLASS(oc);
 CPUClass *cc = CPU_CLASS(oc);
 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+ResettableClass *rc = RESETTABLE_CLASS(oc);
 
 device_class_set_parent_realize(dc, superh_cpu_realizefn,
 >parent_realize);
 
-device_class_set_parent_reset(dc, superh_cpu_reset, >parent_reset);
+resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
+   >parent_phases);
 
 cc->class_by_name = superh_cpu_class_by_name;
 cc->has_work = superh_cpu_has_work;
-- 
2.25.1

[PULL 00/36] reset refactoring patches

[Peter Maydell]

This pull request collects up various reset-related patches
that I sent out and had reviewed during freeze. I've sent
them all here because they touch various devices across
the tree, and this seems more efficient than splitting them
across different submaintainer trees.

thanks
-- PMM

The following changes since commit 4208e6ae114ac8266dcacc9696a443ce5c37b04e:

  Merge tag 'pull-request-2022-12-15' of https://gitlab.com/thuth/qemu into 
staging (2022-12-15 21:39:56 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20221216

for you to fetch changes up to a0c2e80afc98a9771b109eb5ce0b47edd7c78155:

  hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset (2022-12-16 
15:59:07 +)


reset refactoring queue:
 * remove uses of qdev_reset_all(), qbus_reset_all(), device_legacy_reset()
 * convert various devices to 3-phase reset, so we can remove their
   uses of device_class_set_parent_reset()


Peter Maydell (36):
  hw/s390x/s390-pci-inst.c: Use device_cold_reset() to reset PCI devices
  pci: Use device_cold_reset() and bus_cold_reset()
  hw/hyperv/vmbus: Use device_cold_reset() and bus_cold_reset()
  Replace use of qdev_reset_all() with device_cold_reset()
  qdev: Remove qdev_reset_all() and qbus_reset_all()
  hw: Remove device_legacy_reset()
  hw/input/ps2: Convert TYPE_PS2_DEVICE to 3-phase reset
  hw/input/ps2.c: Convert TYPE_PS2_{KBD, MOUSE}_DEVICE to 3-phase reset
  hw/misc/mos6522: Convert TYPE_MOS6522 to 3-phase reset
  hw/misc: Convert TYPE_MOS6522 subclasses to 3-phase reset
  hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset
  target/arm: Convert to 3-phase reset
  target/avr: Convert to 3-phase reset
  target/cris: Convert to 3-phase reset
  target/hexagon: Convert to 3-phase reset
  target/i386: Convert to 3-phase reset
  target/loongarch: Convert to 3-phase reset
  target/m68k: Convert to 3-phase reset
  target/microblaze: Convert to 3-phase reset
  target/mips: Convert to 3-phase reset
  target/nios2: Convert to 3-phase reset
  target/openrisc: Convert to 3-phase reset
  target/ppc: Convert to 3-phase reset
  target/riscv: Convert to 3-phase reset
  target/rx: Convert to 3-phase reset
  target/sh4: Convert to 3-phase reset
  target/sparc: Convert to 3-phase reset
  target/tricore: Convert to 3-phase reset
  target/xtensa: Convert to 3-phase reset
  hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset
  hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset
  pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset
  pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset
  hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset()
  hw/intc/xics: Convert TYPE_ICS to 3-phase reset
  hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset

 hw/display/virtio-vga.h|  2 +-
 include/hw/input/ps2.h |  2 +-
 include/hw/misc/mos6522.h  |  2 +-
 include/hw/pci/pcie_port.h |  2 +-
 include/hw/ppc/xics.h  |  2 +-
 include/hw/qdev-core.h | 35 ---
 target/arm/cpu-qom.h   |  4 +--
 target/avr/cpu-qom.h   |  4 +--
 target/cris/cpu-qom.h  |  4 +--
 target/hexagon/cpu.h   |  2 +-
 target/i386/cpu-qom.h  |  4 +--
 target/loongarch/cpu.h |  4 +--
 target/m68k/cpu-qom.h  |  4 +--
 target/microblaze/cpu-qom.h|  4 +--
 target/mips/cpu-qom.h  |  4 +--
 target/nios2/cpu.h |  4 +--
 target/openrisc/cpu.h  |  4 +--
 target/ppc/cpu-qom.h   |  4 +--
 target/riscv/cpu.h |  4 +--
 target/rx/cpu-qom.h|  4 +--
 target/sh4/cpu-qom.h   |  4 +--
 target/sparc/cpu-qom.h |  4 +--
 target/tricore/cpu-qom.h   |  2 +-
 target/xtensa/cpu-qom.h|  4 +--
 hw/core/cpu-common.c   |  7 +++--
 hw/core/qdev.c | 64 --
 hw/display/virtio-vga.c| 15 ++
 hw/hyperv/vmbus.c  |  4 +--
 hw/i386/xen/xen_platform.c |  2 +-
 hw/input/adb.c |  2 +-
 hw/input/ps2.c | 45 -
 hw/intc/xics.c | 11 
 hw/misc/mac_via.c  | 26 ++---
 hw/misc/macio/cuda.c   | 14 +
 hw/misc/macio/pmu.c| 14 +
 hw/misc/mos6522.c  |  7 +++--
 hw/pci-bridge/cxl_root_port.c  | 14 +
 hw/pci-bridge/pcie_root_port.c |  8 --
 hw/pci-host/pnv_phb.c  | 18 ++--
 hw/pci-host/pnv_phb3_msi.c | 22 ++-
 hw/pci/pci.c   |  6 ++--
 hw/pci/pci_bridge.c|  2 +-
 hw/remote/vfio-user-obj.c

[PULL 02/36] pci: Use device_cold_reset() and bus_cold_reset()

[Peter Maydell]

In the PCI subsystem we currently use the legacy function
qdev_reset_all() and qbus_reset_all().  These perform a recursive
reset, starting from either a qbus or a qdev.  However they do not
permit any of the devices in the tree to use three-phase reset,
because device reset goes through the device_legacy_reset() function
that only calls the single DeviceClass::reset method.

Switch to using the device_cold_reset() and bus_cold_reset()
functions.  These also perform a recursive reset, where first the
children are reset and then finally the parent, but they use the new
(...in 2020...) Resettable mechanism, which supports both the old
style single-reset method and also the new 3-phase reset handling.

This should be a no-behaviour-change commit which just reduces the
use of a deprecated API.

Commit created with:
 sed -i -e 
's/qdev_reset_all/device_cold_reset/g;s/qbus_reset_all/bus_cold_reset/g' 
hw/pci/*.c

Signed-off-by: Peter Maydell 
---
 hw/pci/pci.c| 6 +++---
 hw/pci/pci_bridge.c | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index e6292d8060b..c61348dca01 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -378,14 +378,14 @@ static void pci_do_device_reset(PCIDevice *dev)
  */
 void pci_device_reset(PCIDevice *dev)
 {
-qdev_reset_all(>qdev);
+device_cold_reset(>qdev);
 pci_do_device_reset(dev);
 }
 
 /*
  * Trigger pci bus reset under a given bus.
- * Called via qbus_reset_all on RST# assert, after the devices
- * have been reset qdev_reset_all-ed already.
+ * Called via bus_cold_reset on RST# assert, after the devices
+ * have been reset device_cold_reset-ed already.
  */
 static void pcibus_reset(BusState *qbus)
 {
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index da34c8ebcd1..b2b180edd61 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -275,7 +275,7 @@ void pci_bridge_write_config(PCIDevice *d,
 newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
 /* Trigger hot reset on 0->1 transition. */
-qbus_reset_all(BUS(>sec_bus));
+bus_cold_reset(BUS(>sec_bus));
 }
 }
 
-- 
2.25.1