PING: [for-8.0 v2 00/11] Refactor cryptodev

Hi, Markus & Michael Could you please take a look at the changes of QAPI part? On 12/22/22 10:04, zhenwei pi wrote: On 12/20/22 23:36, Michael S. Tsirkin wrote: On Tue, Nov 22, 2022 at 10:07:45PM +0800, zhenwei pi wrote: v1 -> v2: - fix coding style and use 'g_strjoin()' instead of 'char

RE: [PATCH v10 2/9] KVM: Introduce per-page memory attributes

On Tuesday, January 3, 2023 9:40 AM, Chao Peng wrote: > > Because guest memory defaults to private, and now this patch stores > > the attributes with KVM_MEMORY_ATTRIBUTE_PRIVATE instead of > _SHARED, > > it would bring more KVM_EXIT_MEMORY_FAULT exits at the beginning of > > boot time. Maybe it

Re: [PATCH 0/6] Resolve TYPE_PIIX3_XEN_DEVICE

On 1/2/23 4:34 PM, Bernhard Beschow wrote: > This series first renders TYPE_PIIX3_XEN_DEVICE redundant and finally removes > it. The motivation is to 1/ decouple PIIX from Xen and 2/ to make Xen in the > PC > machine agnostic to the precise southbridge being used. 2/ will become > particularily

Re: [PATCH 0/6] target/i386: Support new Intel platform Instructions in CPUID enumeration

Kindly ping for any comments. BR, Jiaxi On 12/8/2022 3:19 PM, Jiaxi Chen wrote: > Latest Intel platform Granite Rapids/Sierra Forest has introduced below > new instructions and CPUIDs: > > - CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7] > - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21] > - AVX-IFMA

Re: [PATCH v10 2/9] KVM: Introduce per-page memory attributes

On Wed, Dec 28, 2022 at 04:28:01PM +0800, Chenyi Qiang wrote: ... > > +static int kvm_vm_ioctl_set_mem_attributes(struct kvm *kvm, > > + struct kvm_memory_attributes *attrs) > > +{ > > + gfn_t start, end; > > + unsigned long i; > > + void *entry; > > +

Re: [PATCH v4 1/2] tpm: convert tpmdev options processing to new visitor format

On 12/30/22 22:40, James Bottomley wrote: On Fri, 2022-12-30 at 12:01 -0500, Stefan Berger wrote: On 12/30/22 10:24, James Bottomley wrote: [...] @@ -2906,9 +2893,7 @@ void qemu_init(int argc, char **argv)   break;   #ifdef CONFIG_TPM   case

Re: [PATCH v6] xen/pt: reserve PCI slot 2 for Intel igd-passthru

On 1/2/23 12:46 PM, Michael S. Tsirkin wrote: > On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote: > > Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, > > as noted in docs/igd-assign.txt in the Qemu source code. > > > > Currently, when the xl toolstack is used

Re: [PATCH v3] tests/qtest: netdev: test stream and dgram backends

On 12/12/22 14:20, Thomas Huth wrote: On 09/11/2022 14.03, Laurent Vivier wrote: [...] diff --git a/tests/qtest/netdev-socket.c b/tests/qtest/netdev-socket.c new file mode 100644 index ..b6b59244a282 --- /dev/null +++ b/tests/qtest/netdev-socket.c @@ -0,0 +1,435 @@ +/* + * QTest

[PATCH 3/6] hw/isa/piix: Wire up Xen PCI IRQ handling outside of PIIX3

xen_intx_set_irq() doesn't depend on PIIX state. In order to resolve TYPE_PIIX3_XEN_DEVICE and in order to make Xen agnostic about the precise south bridge being used, set up Xen's PCI IRQ handling of PIIX3 in the board. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 12

[PATCH 4/6] hw/isa/piix: Avoid Xen-specific variant of piix_write_config()

Subscribe to pci_bus_fire_intx_routing_notifier() instead which allows for having a common piix_write_config() for all PIIX device models. While at it, move the subscription into machine code in order to resolve TYPE_PIIX3_XEN_DEVICE. In a possible future followup,

[PATCH 1/6] include/hw/xen/xen: Make xen_piix3_set_irq() generic and rename it

xen_piix3_set_irq() hardcoded the number of PCI IRQ lines. Get it from the PCI bus instead. Signed-off-by: Bernhard Beschow --- hw/i386/xen/xen-hvm.c | 9 ++--- hw/isa/piix.c | 2 +- include/hw/xen/xen.h | 2 +- stubs/xen-hw-stub.c | 2 +- 4 files changed, 9 insertions(+), 6

[PATCH 6/6] hw/isa/piix: Resolve redundant TYPE_PIIX3_XEN_DEVICE

During the last patches, TYPE_PIIX3_XEN_DEVICE turned into a clone of TYPE_PIIX3_DEVICE. Remove this redundancy. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 4 +--- hw/isa/piix.c | 20 include/hw/southbridge/piix.h | 1 - 3 files

[PATCH 2/6] hw/isa/piix: Reuse piix3_realize() in piix3_xen_realize()

This is a preparational patch for the next one to make the following more obvious: First, pci_bus_irqs() is now called twice in case of Xen where the second call overrides the pci_set_irq_fn with the Xen variant. Second, pci_bus_set_route_irq_fn() is now also called in Xen mode. Signed-off-by:

[PATCH 5/6] hw/isa/piix: Resolve redundant k->config_write assignments

The previous patch unified handling of piix_write_config() accross all PIIX device models which allows for assigning k->config_write once in the base class. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/isa/piix.c

[PATCH 0/6] Resolve TYPE_PIIX3_XEN_DEVICE

This series first renders TYPE_PIIX3_XEN_DEVICE redundant and finally removes it. The motivation is to 1/ decouple PIIX from Xen and 2/ to make Xen in the PC machine agnostic to the precise southbridge being used. 2/ will become particularily interesting once PIIX4 becomes usable in the PC

Re: [PATCH v3 04/26] configure: don't enable cross compilers unless in target_list

Stefan Weil writes: > Am 21.10.22 um 00:10 schrieb Richard Henderson: >> On 10/20/22 21:51, Alex Bennée wrote: >>> This avoids the unfortunate effect of always builds the pc-bios blobs >>> for targets the user isn't interested in. >>> >>> Suggested-by: Paolo Bonzini >>> Signed-off-by: Alex

Re: [PATCH v3 4/7] hw/misc: AXP209 PMU Emulation

Ping This is the only remaining patch from the series waiting for review. Thanks! Best regards, Strahinja On Mon, Dec 26, 2022 at 11:03 PM Strahinja Jankovic wrote: > > This patch adds minimal support for AXP-209 PMU. > Most important is chip ID since U-Boot SPL expects version 0x1. Besides >

Re: [PATCH] m25p80: Add the is25wp256 SFPD table

Am 2023-01-02 19:49, schrieb Guenter Roeck: On Mon, Jan 02, 2023 at 06:42:03PM +0100, Michael Walle wrote: Am 2023-01-02 17:23, schrieb Guenter Roeck: > On Mon, Jan 02, 2023 at 04:43:49PM +0100, Michael Walle wrote: > > Am 2023-01-02 14:53, schrieb Cédric Le Goater: > > > On 12/27/22 07:31,

[PATCH v5 0/2] hw/nvme: Support for Namespaces Management from guest OS

From: Michael Kropaczek Description: Currently namespaces could be configured as follows: 1. Legacy Namespace - just one namespace within Nvme controller's where the back-end was specified for nvme device by -drive parameter pointing directly to the image file. 2. Additional Namespaces -

[PATCH v5 1/2] hw/nvme: Support for Namespaces Management from guest OS - create-ns

From: Michael Kropaczek Added support for NVMEe NameSpaces Mangement allowing the guest OS to create namespaces by issuing nvme create-ns command. It is an extension to currently implemented Qemu nvme virtual device. Virtual devices representing namespaces will be created and/or deleted during

[PATCH v5 2/2] hw/nvme: Support for Namespaces Management from guest OS - delete-ns

From: Michael Kropaczek Added support for NVMEe NameSpaces Mangement allowing the guest OS to delete namespaces by issuing nvme delete-ns command. It is an extension to currently implemented Qemu nvme virtual device. Virtual devices representing namespaces will be created and/or deleted during

Re: [PATCH] m25p80: Add the is25wp256 SFPD table

On Mon, Jan 02, 2023 at 06:42:03PM +0100, Michael Walle wrote: > Am 2023-01-02 17:23, schrieb Guenter Roeck: > > On Mon, Jan 02, 2023 at 04:43:49PM +0100, Michael Walle wrote: > > > Am 2023-01-02 14:53, schrieb Cédric Le Goater: > > > > On 12/27/22 07:31, Tudor Ambarus wrote: > > > > > > > > > > >

Re: [PATCH v4 08/30] hw/i386/pc: Create RTC controllers in south bridges

Am 2. Januar 2023 17:03:29 UTC schrieb Thomas Huth : >On 21/12/2022 17.59, Bernhard Beschow wrote: >> Just like in the real hardware (and in PIIX4), create the RTC >> controllers in the south bridges. >> >> Signed-off-by: Bernhard Beschow >> Reviewed-by: Michael S. Tsirkin >> Message-Id:

[PATCH] target/arm: Allow users to set the number of VFP registers

Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support have 16 64-bit FPU registers and not 32 registers. Let users set the number of VFP registers with a CPU property. The primary use case of this property is for the Cortex A7 of the Aspeed AST2600 SoC. Signed-off-by: Cédric Le

Re: [PATCH v6] xen/pt: reserve PCI slot 2 for Intel igd-passthru

On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote: > Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, > as noted in docs/igd-assign.txt in the Qemu source code. > > Currently, when the xl toolstack is used to configure a Xen HVM guest with > Intel IGD

Re: [PATCH] m25p80: Add the is25wp256 SFPD table

Am 2023-01-02 17:23, schrieb Guenter Roeck: On Mon, Jan 02, 2023 at 04:43:49PM +0100, Michael Walle wrote: Am 2023-01-02 14:53, schrieb Cédric Le Goater: > On 12/27/22 07:31, Tudor Ambarus wrote: > > > > > > On 25.12.2022 14:18, Ben Dooks wrote: > > > On Wed, Dec 21, 2022 at 06:36:02PM +0100,

Re: [PATCH 2/4] target/m68k: pass sign directly into make_quotient()

On 1/2/23 02:10, Mark Cave-Ayland wrote: I think you need an "abs(floatx80_to_int32())" in both cases as you do in PATCH 4 Or in fact sign = extractFloatx80Sign(res); quot = floatx80_to_int32(floatx80_abs(res->d), status); make_quotient(env, sign, quot); Thanks for the

Re: [PATCH v4 08/30] hw/i386/pc: Create RTC controllers in south bridges

On 21/12/2022 17.59, Bernhard Beschow wrote: Just like in the real hardware (and in PIIX4), create the RTC controllers in the south bridges. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-11-shen...@gmail.com> --- hw/i386/pc.c

Re: [PATCH v4] hw/rtc/mc146818rtc: Make this rtc device target independent

On 02/01/2023 17.47, Bernhard Beschow wrote: Am 2. Januar 2023 16:09:08 UTC schrieb Thomas Huth : On 02/01/2023 14.36, Thomas Huth wrote: On 31/12/2022 00.45, Bernhard Beschow wrote: Am 29. Dezember 2022 10:58:48 UTC schrieb Thomas Huth : [...] static uint32_t

Re: [PATCH v4] hw/rtc/mc146818rtc: Make this rtc device target independent

Am 2. Januar 2023 16:09:08 UTC schrieb Thomas Huth : >On 02/01/2023 14.36, Thomas Huth wrote: >> On 31/12/2022 00.45, Bernhard Beschow wrote: >>> >>> Am 29. Dezember 2022 10:58:48 UTC schrieb Thomas Huth : >[...] static uint32_t rtc_periodic_clock_ticks(RTCState *s) { @@ -922,14

Re: [PATCH] m25p80: Add the is25wp256 SFPD table

On Mon, Jan 02, 2023 at 04:43:49PM +0100, Michael Walle wrote: > Am 2023-01-02 14:53, schrieb Cédric Le Goater: > > On 12/27/22 07:31, Tudor Ambarus wrote: > > > > > > > > > On 25.12.2022 14:18, Ben Dooks wrote: > > > > On Wed, Dec 21, 2022 at 06:36:02PM +0100, Cédric Le Goater wrote: > > > > >

[PATCH] meson: allow disablind the installation of keymaps

From: Carlos Santos There are situatuions in which the keyboard maps are not necessary (e.g. when building only tools or linux-user emulator). Add an option to avoid installing them, as already possible to do with firmware blobs. Signed-off-by: Carlos Santos --- configure

Re: [PATCH v4] hw/rtc/mc146818rtc: Make this rtc device target independent

On 02/01/2023 14.36, Thomas Huth wrote: On 31/12/2022 00.45, Bernhard Beschow wrote: Am 29. Dezember 2022 10:58:48 UTC schrieb Thomas Huth : [...] static uint32_t rtc_periodic_clock_ticks(RTCState *s) { @@ -922,14 +911,15 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)

[PATCH 1/1] hw/arm/sbsa-ref.c: Start APs powered off

For the SBSA-REF machine start all APs in the powered-off state. This reduces host CPU usage until PSCI_CPU_ON is called when the APs are needed. Signed-off-by: Rebecca Cran --- hw/arm/sbsa-ref.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c

Re: [PATCH] m25p80: Add the is25wp256 SFPD table

Am 2023-01-02 14:53, schrieb Cédric Le Goater: On 12/27/22 07:31, Tudor Ambarus wrote: On 25.12.2022 14:18, Ben Dooks wrote: On Wed, Dec 21, 2022 at 06:36:02PM +0100, Cédric Le Goater wrote: On 12/21/22 13:22, Guenter Roeck wrote: Generated from hardware using the following command and then

Re: [PATCH qemu] x86: don't let decompressed kernel image clobber setup_data

On Mon, 2 Jan 2023 at 14:37, Borislav Petkov wrote: > > On Mon, Jan 02, 2023 at 10:32:03AM +0100, Ard Biesheuvel wrote: > > So instead of appending data to the compressed image and assuming that > > it will stay in place, create or extend a memory reservation > > elsewhere, and refer to its

Re: [PATCH] ccid-card-emulated: fix cast warning

On Mon, Nov 14, 2022 at 5:22 PM wrote: > From: Marc-André Lureau > > ../hw/usb/ccid-card-emulated.c: In function 'handle_apdu_thread': > ../hw/usb/ccid-card-emulated.c:251:24: error: cast from pointer to integer > of different size [-Werror=pointer-to-int-cast] > 251 |

Re: [PATCH v2 09/11] hw/arm/aspeed_ast10x0: Map HACE peripheral

On 12/30/22 12:35, Philippe Mathieu-Daudé wrote: Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Before on Zephyr: uart:~$ hash test sha256_test tv[0]:hash_final error

Re: [PATCH] m25p80: Add the is25wp256 SFPD table

On 12/27/22 07:31, Tudor Ambarus wrote: On 25.12.2022 14:18, Ben Dooks wrote: On Wed, Dec 21, 2022 at 06:36:02PM +0100, Cédric Le Goater wrote: On 12/21/22 13:22, Guenter Roeck wrote: Generated from hardware using the following command and then padding with 0xff to fill out a power-of-2:    

Re: [PATCH v2 11/11] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board

On 12/30/22 12:35, Philippe Mathieu-Daudé wrote: Add a very quick test that runs some commands in a Zephyr shell: $ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado (2/2) tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07: console: ***

Re: [PATCH v2 10/11] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F

On 12/30/22 12:35, Philippe Mathieu-Daudé wrote: This SoC uses a Cortex-M4F. QEMU only implements a M4, which is good enough. Add a TODO note in case the M4F is added. How complex would it be to add the FPU version of the M4 ? I suppose we have all the instructions already implemented ?

Re: [PATCH v2 07/11] hw/arm/aspeed_ast10x0: Map I3C peripheral

On 12/30/22 12:35, Philippe Mathieu-Daudé wrote: Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Reviewed-by: Peter Delevoryas Signed-off-by: Philippe Mathieu-Daudé I3C is

Re: [PATCH v2 06/11] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals

On 12/30/22 12:34, Philippe Mathieu-Daudé wrote: Based on booting Zephyr demo from [1] running QEMU with '-d unimp' and checking missing devices in [2]. [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07 [2]

Re: [PATCH v2 05/11] hw/misc/aspeed_hace: Do not crash if address_space_map() failed

On 12/30/22 12:34, Philippe Mathieu-Daudé wrote: address_space_map() can fail: uart:~$ hash test sha256_test tv[0]: Segmentation fault: 11 Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault. gen_acc_mode_iov (req_len=0x718b7778, id=,

Re: [PATCH qemu] x86: don't let decompressed kernel image clobber setup_data

On Mon, Jan 02, 2023 at 10:32:03AM +0100, Ard Biesheuvel wrote: > So instead of appending data to the compressed image and assuming that > it will stay in place, create or extend a memory reservation > elsewhere, and refer to its absolute address in setup_data. >From my limited experience with

Re: [PATCH v2 04/11] hw/arm/aspeed: Use the IEC binary prefix definitions

On 12/30/22 12:34, Philippe Mathieu-Daudé wrote: IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed_ast10x0.c | 3 ++- hw/arm/aspeed_ast2600.c | 3

Re: [PATCH v4] hw/rtc/mc146818rtc: Make this rtc device target independent

On 31/12/2022 00.45, Bernhard Beschow wrote: Am 29. Dezember 2022 10:58:48 UTC schrieb Thomas Huth : The only reason for this code being target dependent is the apic-related code in rtc_policy_slew_deliver_irq(). Since these apic functions are rather simple, we can easily move them into a

Re: [PATCH v2 03/11] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level

On 12/30/22 12:34, Philippe Mathieu-Daudé wrote: Add more Aspeed watchdog registers from [*]. Since guests can righteously access them, log the access at 'unimplemented' level instead of 'guest-errors'. [*]

Re: [PATCH v2 02/11] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers

On 12/31/22 23:52, Dong, Eddie wrote: When booting the Zephyr demo in [1] we get: aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <-- aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03f1) This corresponds to this Zephyr code

Re: [PATCH v3 04/26] configure: don't enable cross compilers unless in target_list

Am 21.10.22 um 00:10 schrieb Richard Henderson: On 10/20/22 21:51, Alex Bennée wrote: This avoids the unfortunate effect of always builds the pc-bios blobs for targets the user isn't interested in. Suggested-by: Paolo Bonzini Signed-off-by: Alex Bennée ---   configure | 9 +   1 file

Re: [PATCH v2 08/11] hw/arm/aspeed_ast10x0: Map the secure SRAM

On 12/30/22 12:35, Philippe Mathieu-Daudé wrote: Some SRAM appears to be used by the Secure Boot unit and crypto accelerators. Name it 'secure sram'. Note, the SRAM base address was already present but unused (the 'SBC' index is used for the MMIO peripheral). Interestingly using

Re: [PATCH v2 01/11] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'

On 12/31/22 23:43, Dong, Eddie wrote: Avoid confusing two different things: - the WDT I/O region size ('iosize') - at which offset the SoC map the WDT ('offset') While it is often the same, we can map smaller region sizes at larger offsets. Here we are interested in the I/O region size, so

Re: [PATCH] chardev: clean up chardev-parallel.c

On Thu, Dec 22, 2022 at 11:42 AM Paolo Bonzini wrote: > > Replace HAVE_CHARDEV_PARPORT with a Meson conditional, remove unnecessary > defines, and close the file descriptor on FreeBSD/DragonFly. > > Signed-off-by: Paolo Bonzini > --- > chardev/char-parallel.c | 15 ++- >

[PATCH v5 11/11] hw/riscv/boot.c: make riscv_load_initrd() static

The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 80 - include/hw/riscv/boot.h | 1

[PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()

The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that

[PATCH v5 09/11] hw/riscv/boot.c: use MachineState in riscv_load_kernel()

All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c

[PATCH v5 07/11] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()

The sifive_u, spike and virt machines are writing the 'bootargs' FDT node during their respective create_fdt(). Given that bootargs is written only when '-append' is used, and this option is only allowed with the '-kernel' option, which in turn is already being check before executing

[PATCH v5 03/11] hw/riscv/sifive_u: use 'fdt' from MachineState

The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt instead. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza

[PATCH v5 05/11] hw/riscv/spike.c: load initrd right after riscv_load_kernel()

This will make the code more in line with what the other boards are doing. We'll also avoid an extra check to machine->kernel_filename since we already checked that before executing riscv_load_kernel(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by:

[PATCH v5 08/11] hw/riscv/boot.c: use MachineState in riscv_load_initrd()

'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be retrieved by the MachineState object for all callers. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c| 6 --

[PATCH v5 02/11] hw/riscv/spike: use 'fdt' from MachineState

The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SpikeState and use MachineState::fdt instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe

[PATCH v5 04/11] hw/riscv/boot.c: exit early if filename is NULL in load functions

riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works under the assumption that a 'filename' parameter is always not NULL. This is currently the case since all callers of these functions are checking for NULL before calling them. Add an g_assert() to make sure that a NULL value

[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups

Hi, This new version is still rebased on top of [1]: "[PATCH v2 00/12] hw/riscv: Improve Spike HTIF emulation fidelity" from Bin Meng. The change from v4 is on patch 9 where we added an extra flag in riscv_load_kernel() to allow for boards that don't load initrd (e.g. opentitan and sifive_e)

[PATCH v5 06/11] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()

riscv_load_initrd() returns the initrd end addr while also writing a 'start' var to mark the addr start. These informations are being used just to write the initrd FDT node. Every existing caller of riscv_load_initrd() is writing the FDT in the same manner. We can simplify things by writing the

[PATCH v5 01/11] tests/avocado: add RISC-V OpenSBI boot test

This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. The

Re: [PATCH RFC 3/4] vdagent: add live migration support

Hi On Fri, Dec 30, 2022 at 6:49 PM wrote: > > From: "dengp...@chinatelecom.cn" > > To support live migration, we made the following 2 modifications: > 1. save the caps field of VDAgentChardev. > 2. register vdagent to qemu-clipboard after >vm device state being reloaded during live

Re: [PATCH RFC 2/4] vdagent: refactor vdagent_chr_recv_caps function

On Fri, Dec 30, 2022 at 6:49 PM wrote: > > From: "dengp...@chinatelecom.cn" > > Abstract vdagent registry logic into > vdagent_register_to_qemu_clipboard. > > Note that trace log of vdagent_recv_caps also be added. > > Signed-off-by: dengp...@chinatelecom.cn > Signed-off-by:

[GIT PULL 0/4] Host Memory Backends and Memory devices queue 2023-01-02

The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b: Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +) are available in the Git repository at: https://github.com/davidhildenbrand/qemu.git tags/mem-2023-01-02

[GIT PULL 2/4] virtio-mem: Fix the iterator variable in a vmem->rdl_list loop

From: Chenyi Qiang It should be the variable rdl2 to revert the already-notified listeners. Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface") Signed-off-by: Chenyi Qiang Message-Id: <20221228090312.17276-1-chenyi.qi...@intel.com> Cc: qemu-sta...@nongnu.org Reviewed-by:

[GIT PULL 3/4] virtio-mem: Fix typo in function name

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221228130956.80515-1-phi...@linaro.org> Signed-off-by: David Hildenbrand --- hw/virtio/virtio-mem.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/virtio/virtio-mem.c

[GIT PULL 4/4] hostmem: Honor multiple preferred nodes if possible

From: Michal Privoznik If a memory-backend is configured with mode HOST_MEM_POLICY_PREFERRED then host_memory_backend_memory_complete() calls mbind() as: mbind(..., MPOL_PREFERRED, nodemask, ...); Here, 'nodemask' is a bitmap of host NUMA nodes and corresponds to the .host-nodes attribute.

Re: [PATCH RFC 1/4] vdagent: fix memory leak when vdagent_disconnect is called

Hi On Fri, Dec 30, 2022 at 6:48 PM wrote: > > From: "dengp...@chinatelecom.cn" > > Memory free should be done in vdagent_disconnect using > qemu_input_handler_unregister, replace qemu_input_handler_deactivate > with that. > > Signed-off-by: dengp...@chinatelecom.cn > Signed-off-by:

[GIT PULL 1/4] virtio-mem: Fix the bitmap index of the section offset

From: Chenyi Qiang vmem->bitmap indexes the memory region of the virtio-mem backend at a granularity of block_size. To calculate the index of target section offset, the block_size should be divided instead of the bitmap_size. Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager

Re: [PATCH v2] pflash: Only read non-zero parts of backend image

Hi, > > Moving away from pflash for efi variable storage would cause alot of > > churn through the whole stack. firmware, qemu, libvirt, upper > > management, all affected. Is that worth the trouble? Using pflash > > isn't that much of a problem IMHO. > > Agreed. pflash is a bit clunky but

Re: [PATCH 0/9] hw/arm/aspeed_ast10x0: Map more peripherals & few more fixes

On 12/29/22 16:23, Philippe Mathieu-Daudé wrote: Trying to fix some bugs triggered running Zephyr. Still 2 bugs: 1/ uart:~$ sensor get SYSCLK [00:00:23.592,000] os: * USAGE FAULT * [00:00:23.593,000] os: Illegal use of the EPSR [00:00:23.593,000] os: r0/a1: 0x00033448 r1/a2:

Re: [PATCH] usbredir: Do not detach usb if backend chardev disconnect

On Thu, Dec 22, 2022 at 09:21:25PM +0800, Minglei Liu wrote: > ping ! > please review this patch : [PATCH] usbredir: Do not detach usb if backend > chardev disconnect - minglei.liu (kernel.org) > > > minglei.liu

[PATCH] Update scripts/meson-buildoptions.sh

Note: `Makefile` relies on modification dates in the source tree to detect changes to `meson_options.txt`. However, git does not track those. Therefore, the following was necessary to regenerate `meson-buildoptions.sh`: touch meson_options.txt cd "$BUILD_DIR" make update-buildoptions

Re: [PATCH 1/9] hw/watchdog/wdt_aspeed: Map the whole MMIO range

On 12/30/22 08:32, Philippe Mathieu-Daudé wrote: On 29/12/22 21:42, Peter Delevoryas wrote: On Thu, Dec 29, 2022 at 04:23:17PM +0100, Philippe Mathieu-Daudé wrote: Avoid confusing two different things: - the WDT I/O region size ('iosize') - at which offset the SoC map the WDT ('offset') While

Re: [PATCH 1/9] hw/watchdog/wdt_aspeed: Map the whole MMIO range

On 12/29/22 16:23, Philippe Mathieu-Daudé wrote: Avoid confusing two different things: - the WDT I/O region size ('iosize') - at which offset the SoC map the WDT ('offset') While it is often the same, we can map smaller region sizes at larger offsets. Here we are interested in the I/O region

Re: [PATCH 2/4] target/m68k: pass sign directly into make_quotient()

On 01/01/2023 18:53, Richard Henderson wrote: On 1/1/23 09:26, Laurent Vivier wrote: Le 01/01/2023 à 15:43, Mark Cave-Ayland a écrit : This enables the quotient parameter to be changed from int32_t to uint32_t and also allows the extra sign logic in make_quotient() to be removed.

Re: [PATCH v2 02/11] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers

On 31/12/22 23:52, Dong, Eddie wrote: #define WDT_RELOAD_VAL_REG 0x0004 #define WDT_RESTART_REG 0x0008 #define WDT_CTRL_REG0x000C #define WDT_TIMEOUT_STATUS_REG 0x0010 #define WDT_TIMEOUT_STATUS_CLR_REG 0x0014 #define

Re: [PATCH 2/4] target/m68k: pass sign directly into make_quotient()

On 01/01/2023 17:26, Laurent Vivier wrote: Le 01/01/2023 à 15:43, Mark Cave-Ayland a écrit : This enables the quotient parameter to be changed from int32_t to uint32_t and also allows the extra sign logic in make_quotient() to be removed. Signed-off-by: Mark Cave-Ayland ---  

[PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64

On linux user mode, CPUX86State::idt::base and CPUX86State::gdt::base from Different CPUX86State Objects have same value, It is incorrect! Every CPUX86State::idt::base and Every CPUX86State::gdt::base Must points to independent memory space. Resolves:

[PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64

--- linux-user/i386/cpu_loop.c | 10 ++ linux-user/main.c | 11 +++ 2 files changed, 21 insertions(+) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 865413c08f..1f23bc5e3a 100644 --- a/linux-user/i386/cpu_loop.c +++

[PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64

On linux user mode, CPUX86State::idt::base and CPUX86State::gdt::base from Different CPUX86State Objects have same value, It is incorrect! Every CPUX86State::idt::base and Every CPUX86State::gdt::base Must points to independent memory space. Resolves:

Re: [PATCH qemu] x86: don't let decompressed kernel image clobber setup_data

On Mon, 2 Jan 2023 at 07:17, Borislav Petkov wrote: > > On Mon, Jan 02, 2023 at 07:01:50AM +0100, Borislav Petkov wrote: > > On Sat, Dec 31, 2022 at 07:31:21PM -0800, H. Peter Anvin wrote: > > > It would probably be a good idea to add a "maximum physical address for > > >

Re: [PATCH RESEND v3 00/10] migration: introduce dirtylimit capability

Ping, Hi, David, how about the commit about live migration: [PATCH RESEND v3 08/10] migration: Implement dirty-limit convergence algo. 在 2022/12/4 1:09, huang...@chinatelecom.cn 写道: From: Hyman Huang(黄勇) v3(resend): - fix the syntax error of the topic. v3: This version make some