On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote:
>
> Hi Frank,
>
> On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote:
> >
> > Hi Alexandre,
> >
> > Thanks for the contribution. This is really helpful.
> >
> > It seems like if we want to specify the SATP mode for the "named" CPUs,
> > we
From: Cédric Le Goater
If a secure kernel is started in a non-protected VM, the OS will hang
during boot without giving a proper error message to the user.
Perform the checks on Confidential Guest support at runtime with an
helper called from the service call switching the guest to protected
Hello,
Here is a little series improving error reporting of protected VMs.
Thanks,
C.
Changes in v2:
- dropped ConfidentialGuestSupportClass handler. The check is now
done from s390_pv_init() which is called after memory and CPU
initialization. This gives us a better chance to tune the
From: Cédric Le Goater
Support for protected VMs should have been enabled on the host with
the kernel parameter 'prot_virt=1'. If the hardware supports the
feature, it is reflected under sysfs.
Reviewed-by: Thomas Huth
Signed-off-by: Cédric Le Goater
---
hw/s390x/pv.c | 23
From: Cédric Le Goater
Such conditions on Protected Virtualization can now be checked at init
time.
Reviewed-by: Thomas Huth
Signed-off-by: Cédric Le Goater
---
hw/s390x/pv.c | 14 +-
target/s390x/diag.c | 7 ---
2 files changed, 13 insertions(+), 8 deletions(-)
diff
From: Cédric Le Goater
When a protected VM is started with the maximum number of CPUs (248),
the service call providing information on the CPUs requires more
buffer space than allocated and QEMU disgracefully aborts :
LOADPARM=[]
Using virtio-blk.
Using SCSI scheme.
On 5/1/23 22:48, Philippe Mathieu-Daudé wrote:
On 3/1/23 19:16, Richard Henderson wrote:
There was even a TODO comment that we ought to be using a cpu
property, but we failed to update when the property was added.
Use ARM_AFF1_SHIFT instead of the bare constant 8.
Signed-off-by: Richard
On 05/01/2023 22.42, Philippe Mathieu-Daudé wrote:
On 5/1/23 21:48, Thomas Huth wrote:
The qtests are not stable in the msys2-32bit job yet - especially
the test-hmp and the qom-test are failing randomly. Until this is
fixed,
Who is gonna look after this?
It certainly has to be someone
On 5/1/23 22:19, Evgeny Iakovlev wrote:
Windows open(2) implementations opens files in text mode by default and
needs a Windows-only O_BINARY flag to open files as binary. Qemu already
s/Qemu/QEMU/
knows about that flag in osdep.h, so we can just add it to the
host_flags for better
On 6/1/23 03:19, Richard Henderson wrote:
On 1/5/23 14:04, Philippe Mathieu-Daudé wrote:
On 3/1/23 19:16, Richard Henderson wrote:
Create a features member in ARMCPUClass and copy to the instance in
arm_cpu_init. Settings of this value will come in a future patch.
Signed-off-by: Richard
The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging
(2023-01-05 16:59:22 +)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git pull-loongarch-20230106
for
From: Tianrui Zhao
This patch adds irq number property for loongarch msi interrupt
controller, and remove hard coding irq number macro.
Signed-off-by: Tianrui Zhao
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230104020518.2564263-2-zhaotian...@loongson.cn>
Signed-off-by: Song Gao
---
From: Tianrui Zhao
Change the default irq number of pch pic to 32, so that the irq
number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM'
macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard
format.
Signed-off-by: Tianrui Zhao
Reviewed-by: Philippe Mathieu-Daudé
From: Tianrui Zhao
With loongarch 7A1000 manual, irq number supported can be set
in PCH_PIC_INT_ID_HI register. This patch adds irq number property
for loongarch_pch_pic, so that virt machine can set different
irq number when pch_pic intc is added.
Signed-off-by: Tianrui Zhao
Reviewed-by: Song
On Thu, Jan 05, 2023 at 12:38:30PM -0800, Vishal Annapurve wrote:
> On Thu, Dec 1, 2022 at 10:20 PM Chao Peng wrote:
> >
> > +#ifdef CONFIG_HAVE_KVM_RESTRICTED_MEM
> > +static bool restrictedmem_range_is_valid(struct kvm_memory_slot *slot,
> > +pgoff_t
From: Ilya Leoshkevich
Add a test that locklessly changes and exercises page protection bits
from various threads. This helps catch race conditions in the VMA
handling.
Acked-by: Alex Bennée
Signed-off-by: Ilya Leoshkevich
Message-Id: <20221223120252.513319-1-...@linux.ibm.com>
Signed-off-by:
From: Bin Meng
Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as
From: Bin Meng
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC
From: Bin Meng
The realize() callback has an errp for us to propagate the error up.
While we are here, correct the wrong multi-line comment format.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
of the MSYS2
jobs (2023-01-04 18:58:33 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230105
for you to fetch changes up to d4846c33ebe04d2141dcc613b5558d2f1d8077af:
tests/tcg/multiarch: add vma-pthread.c (2023-01-05 11:41:29 -0800
From: Christoph Muellner
This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore,
From: Bin Meng
At present the PLIC config parser can only handle legal config string
like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
given the parser won't get the correct configuration.
This commit improves the config parser to make it more robust.
Signed-off-by: Bin Meng
From: Jim Shu
If the number of interrupt is not multiple of 32, PLIC will have
out-of-bound access to source_priority array. Compute the number of
interrupt in the last word to avoid this out-of-bound access of array.
Signed-off-by: Jim Shu
Reviewed-by: Bin Meng
Message-Id:
From: Bin Meng
PLIC is not included in the 'spike' machine.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211030829.802437-5-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
hw/riscv/spike.c | 1 -
1 file changed, 1 deletion(-)
From: Richard Henderson
When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.
Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the
There are several instances where we need to be able to
allocate a pair of registers to related inputs/outputs.
Add 'p' and 'm' register constraints for this, in order to
be able to allocate the even/odd register first or second.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +
From: Bin Meng
There are 2 paths in helper_sret() and the same mstatus update codes
are replicated. Extract the common parts to simplify it a little bit.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20221207090037.281452-1-bm...@tinylab.org>
Signed-off-by: Alistair
From: Anup Patel
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id: <20221108125703.1463577-2-apa...@ventanamicro.com>
From: Bin Meng
At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:
s->bitfield_words = (s->num_sources + 31) >> 5;
if the we don't configure "num-sources" property its
From: Bin Meng
Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.
[1] PolarFire SoC MSS TRM:
From: Bin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().
Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.
Signed-off-by: Bin
From: Jim Shu
let tlb_fill() function also increments PMU counter when it is from
two-stage translation, so QEMU could also monitor these PMU events when
CPU runs in VS/VU mode (like running guest OS).
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Message-Id:
From: Bin Meng
At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id:
From: Richard Henderson
Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
From: Conor Dooley
The Fabric Interconnect Controllers provide interfaces between the FPGA
fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered
0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and
does not show up on the MSS memory map. FIC4 is dedicated to
From: Conor Dooley
The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usually connected to a flash chip, that is used for
From: Bin Meng
sstatus register dump is currently missing in riscv_cpu_dump_state().
As sstatus is a copy of mstatus, which is described in the priv spec,
it seems redundant to print the same information twice.
Add some comments for this to let people know this is intentional.
Signed-off-by:
From: Bin Meng
Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.
We use the value of G002 and G003, so it is 53 (including source 0).
[1] G000 manual:
From: LIU Zhiwei
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
is an pmp rule, valid
From: Bin Meng
At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.
Note
From: Conor Dooley
On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
Icicle Kit Reference Design v2022.09 or later this is/will
From: LIU Zhiwei
When QEMU is not in icount mode, execute instruction one by one. The
tdata1 can be read directly.
When QEMU is in icount mode, use a timer to simulate the itrigger. The
tdata1 may be not right because of lazy update of count in tdata1. Thus,
We should pack the adjusted count
From: Bin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().
Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
Signed-off-by:
From: Mayuresh Chitale
This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
From: Atish Patra
The imsic DT binding[1] has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.
Get rid of the unused dt property which may lead to confusion.
[1]
From: Bin Meng
"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211030829.802437-15-bm...@tinylab.org>
Signed-off-by: Alistair Francis
From: Bin Meng
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
the IBEX PLIC model was replaced with the SiFive PLIC model in the
'opentitan' machine but we forgot the add the dependency there.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by:
From: Bin Meng
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault
From: Bin Meng
Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
leaving M-mode.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20221207090037.281452-2-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
target/riscv/op_helper.c | 6 ++
1 file
From: Bin Meng
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Wilfred Mallawa
Message-Id: <20221211030829.802437-4-bm...@tinylab.org>
Signed-off-by: Alistair Francis
From: LIU Zhiwei
When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.
Translate the guest code in a way that each TB only has one instruction.
After executing the instruction, decrease the count by 1 until it reaches 0
where the itrigger fires.
Note
From: LIU Zhiwei
Avoid calling riscv_itrigger_enabled() when calculate the tbflags.
As the itrigger enable status can only be changed when write
tdata1, migration load or itrigger fire, update env->itrigger_enabled
at these places.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
From: Wilfred Mallawa
This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.
Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note:
From: Mayuresh Chitale
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id:
From: LIU Zhiwei
The max count in itrigger can be 0x3FFF, which will cause a no trivial
translation and execution overload.
When icount is enabled, QEMU provides API that can fetch guest
instruction number. Thus, we can set an timer for itrigger with
the count as deadline.
Only when timer
From: Richard Henderson
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-Id:
From: Bin Meng
H-mode has been removed since priv spec 1.10. Drop it.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211030829.802437-6-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
include/hw/intc/sifive_plic.h | 1 -
From: Frédéric Pétrot
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object
From: Richard Henderson
There was a typo using opc_addi instead of opc_add with the
two registers. While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.
Reported-by: LIU Zhiwei
Signed-off-by: Richard
From: Mayuresh Chitale
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
From: Wilfred Mallawa
Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
From: Alistair Francis
The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging
(2023-01-05 16:59:22 +)
are available in the Git repository at:
https://github.com/alistair23/qemu.git
On 1/5/23 14:08, Philippe Mathieu-Daudé wrote:
On 3/1/23 19:16, Richard Henderson wrote:
Since kvm32 was removed
Maybe add here:
(see commit 82bf7ae84c: "target/arm: Remove KVM support for 32-bit
Arm hosts")
, all kvm hosts support aarch64.
Signed-off-by: Richard Henderson
---
On 1/5/23 14:04, Philippe Mathieu-Daudé wrote:
On 3/1/23 19:16, Richard Henderson wrote:
Create a features member in ARMCPUClass and copy to the instance in
arm_cpu_init. Settings of this value will come in a future patch.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 18
Hi John,
Could you help me relay these fixes?
If I submit a pull request, I will go through company's internal review process
again.
Thanks a lot!
Dongdong
> -原始邮件-发件人:"John Snow" 发送时间:2023-01-06 07:25:43
> (星期五)收件人:"Dongdong Zhang"
> 抄送:qemu-devel@nongnu.org, cr...@redhat.com,
在 2023/1/4 上午10:05, Tianrui Zhao 写道:
With loongarch 7A1000 manual, irq number supported can be set
in PCH_PIC_INT_ID_HI register. This patch adds irq number property
for loongarch_pch_pic, so that virt machine can set different
irq number when pch_pic intc is added.
Signed-off-by: Tianrui
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, January 4, 2023 11:42 PM
> To: Sid Manning ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; Mark Burton
> Subject: Re: ARM: ptw.c:S1_ptw_translate
>
> WARNING: This email originated from outside of Qualcomm. Please be
On Sat, Dec 31, 2022 at 1:01 AM Felipe Balbi wrote:
>
> Olimex makes a series of low-cost STM32 boards. This commit introduces
> the minimum setup to support SMT32-H405. See [1] for details
>
> [1] https://www.olimex.com/Products/ARM/ST/STM32-H405/
>
> Signed-off-by: Felipe Balbi
Reviewed-by:
On Tue, Nov 29, 2022 at 6:08 PM Dongdong Zhang
wrote:
> diff --git a/python/qemu/machine/qtest.py b/python/qemu/machine/qtest.py
> index 1a1fc6c9b0..906bd13298 100644
> --- a/python/qemu/machine/qtest.py
> +++ b/python/qemu/machine/qtest.py
> @@ -42,7 +42,7 @@ class QEMUQtestProtocol:
>
On Thu, Dec 15, 2022 at 10:22 PM Dongdong Zhang
wrote:
>
> Hi all,
>
> I would like to ping a patch
>
> https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg04568.html
> https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg04570.html
>
>
> > -Original Messages-From:"Dongdong
Windows open(2) implementations opens files in text mode by default and
needs a Windows-only O_BINARY flag to open files as binary. Qemu already
knows about that flag in osdep.h, so we can just add it to the
host_flags for better compatibility when running qemu on Windows.
Signed-off-by: Evgeny
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Helps Hyper-V boot on aarch64-tcg because it context-switches DBGCLAIM
on EL2 entry/exit.
Signed-off-by: Evgeny Iakovlev
---
target/arm/cpu.h | 1 +
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX
Qemu doesn't implement Debug Communication Channel, however when running
Microsoft Hyper-V in software-emulated ARM64 as a guest, it tries to
access some of the DCM registers during an EL2 context switch.
Provide RAZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1
registers in the same way
Small series of changes to aarch64 emulation to better support running
Hyper-V as a TCG guest wtih EL3 firmware.
Evgeny Iakovlev (3):
target/arm: implement DBGCLAIM registers
target/arm: provide RAZ/WI stubs for more DCC registers
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX
Add control registers (c4, c5) to clobbers list
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/preg_alias.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/preg_alias.c
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/Makefile.target | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/Makefile.target
b/tests/tcg/hexagon/Makefile.target
index 9ee1faa1e1..adca8326bf
We create a new generator that creates an analyze_ function for
each instruction. Currently, these functions record the writes to
R, P, and C registers by calling ctx_log_reg_write[_pair] or
ctx_log_pred_write.
During gen_start_packet, we invoke the analyze_ function for
each instruction in the
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 14 --
target/hexagon/translate.c | 30 +
target/hexagon/gen_analyze_funcs.py | 17 +---
target/hexagon/gen_tcg_funcs.py | 18 -
4 files
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c | 513
Am 5. Januar 2023 13:10:38 UTC schrieb "Philippe Mathieu-Daudé"
:
>RC4030 declarations are not MIPS specific, no need to
>have them in all MIPS boards.
>
>Signed-off-by: Philippe Mathieu-Daudé
>---
>Based-on: <20230105130710.49264-1-phi...@linaro.org>
> "hw/pci-host/bonito:
On 3/1/23 19:16, Richard Henderson wrote:
Remove the cfgend variable entirely and reuse the property
accessor functions created for reset-hivecs. This removes
the last setting of cpu->reset_sctlr, to we can remove that
s/to/so/?
as well, using only the class value.
Signed-off-by: Richard
Add overrides for
SL2_jumpr31Unconditional
SL2_jumpr31_t Predicated true (old value)
SL2_jumpr31_f Predicated false (old value)
SL2_jumpr31_tnew Predicated true (new value)
SL2_jumpr31_fnew Predicated false (new value)
Signed-off-by:
On 3/1/23 19:16, Richard Henderson wrote:
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 -
hw/arm/xilinx_zynq.c | 9 ++---
hw/intc/armv7m_nvic.c | 2 +-
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
On 1/5/23 17:02, James Bottomley wrote:
On Thu, 2023-01-05 at 11:20 -0500, Stefan Berger wrote:
On 1/5/23 08:00, James Bottomley wrote:
[...]
+The mssim backend supports snapshotting and migration, but the
state
+of the Microsoft Simulator server must be preserved (or the server
+kept
On 3/1/23 19:16, Richard Henderson wrote:
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h| 3 +++
target/arm/cpu.h| 3 ---
hw/arm/aspeed_ast2600.c | 6 +++--
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 20
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git
The idef-parser skips the change-of-flow (COF) instructions, so add
overrides
Changes in v2
Add a new generator for analyze_ instructions. Pouplate the
DisasContext ahead of generating code.
Changes in v3
Cleanup of analysis code
Added test updates enabled by new toolchain
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4 ++
target/hexagon/genptr.c | 79
2 files changed, 83 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 9e8f3373ad..6267f51ccc 100644
---
Am 5. Januar 2023 17:37:02 UTC schrieb "Philippe Mathieu-Daudé"
:
>No need to document magic values when the definition names
>from "standard-headers/linux/pci_regs.h" are self-explicit.
>
>Signed-off-by: Philippe Mathieu-Daudé
>---
> hw/pci-host/grackle.c | 2 +-
> hw/pci-host/raven.c|
On 3/1/23 19:16, Richard Henderson wrote:
Use two intermediate functions to share code between
the 13 variants of pxa*_class_init.
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 81 +---
1 file changed, 23 insertions(+), 58 deletions(-)
On 3/1/23 19:16, Richard Henderson wrote:
Use an intermediate function to share code between
sa1100_class_init and sa1110_class_init.
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
Reviewed-by: Philippe
Le 05/01/2023 à 14:10, Philippe Mathieu-Daudé a écrit :
RC4030 declarations are not MIPS specific, no need to
have them in all MIPS boards.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20230105130710.49264-1-phi...@linaro.org>
"hw/pci-host/bonito: Housekeeping"
---
On 3/1/23 19:16, Richard Henderson wrote:
We can now store these values into ARMCPUClass instead of into
a temporary ARMHostCPUFeatures structure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5
target/arm/hvf_arm.h | 2 +-
target/arm/cpu.c | 13 --
On 3/1/23 19:16, Richard Henderson wrote:
Since kvm32 was removed
Maybe add here:
(see commit 82bf7ae84c: "target/arm: Remove KVM support for 32-bit
Arm hosts")
, all kvm hosts support aarch64.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 6 ++
1 file changed, 2
Am 5. Januar 2023 17:38:26 UTC schrieb "Philippe Mathieu-Daudé"
:
>This argument was added 9 years ago in commit 83d08f2673
>("pc: map PCI address space as catchall region for not mapped
>addresses") and has never been used since, so remove it.
>
>Signed-off-by: Philippe Mathieu-Daudé
On 3/1/23 19:16, Richard Henderson wrote:
Create a features member in ARMCPUClass and copy to the instance in
arm_cpu_init. Settings of this value will come in a future patch.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 18 ++
target/arm/cpu.c | 1 +
2
On Thu, 2023-01-05 at 11:20 -0500, Stefan Berger wrote:
>
>
> On 1/5/23 08:00, James Bottomley wrote:
[...]
> > +The mssim backend supports snapshotting and migration, but the
> > state
> > +of the Microsoft Simulator server must be preserved (or the server
> > +kept running) outside of QEMU for
On 3/1/23 19:16, Richard Henderson wrote:
Streamline new instances of this hook, so that we always go
through arm_cpu_leaf_class_init first, performing common tasks,
and have resolved the ARMCPUClass.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 2 +-
target/arm/cpu.c |
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