[PULL 14/18] bulk: Remove pointless QOM casts
From: Philippe Mathieu-Daudé
Mechanical change running Coccinelle spatch with content
generated from the qom-cast-macro-clean-cocci-gen.py added
in the previous commit.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230601093452.38972-3-phi...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off-by: Thomas Huth
---
block/nbd.c | 4 ++--
chardev/char-pty.c | 2 +-
hw/arm/musicpal.c | 2 +-
hw/arm/xlnx-versal.c| 2 +-
hw/display/vhost-user-gpu.c | 4 ++--
hw/intc/loongarch_extioi.c | 6 +++---
hw/m68k/q800.c | 2 +-
hw/pci-host/bonito.c| 2 +-
hw/ppc/pnv_lpc.c| 2 +-
hw/ppc/pnv_occ.c| 2 +-
hw/ppc/pnv_sbe.c| 2 +-
hw/riscv/virt.c | 10 +-
hw/rx/rx62n.c | 2 +-
hw/scsi/esp-pci.c | 18 +-
hw/sparc/sun4m.c| 4 ++--
hw/virtio/virtio-mem-pci.c | 6 +++---
hw/virtio/virtio-pmem-pci.c | 6 +++---
migration/fd.c | 4 ++--
migration/multifd.c | 2 +-
migration/yank_functions.c | 4 ++--
nbd/client-connection.c | 2 +-
nbd/server.c| 2 +-
softmmu/qdev-monitor.c | 2 +-
ui/vnc-ws.c | 6 +++---
24 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/block/nbd.c b/block/nbd.c
index a3f8f8a9d5..5aef5cb6bd 100644
--- a/block/nbd.c
+++ b/block/nbd.c
@@ -397,7 +397,7 @@ static void coroutine_fn GRAPH_RDLOCK
nbd_reconnect_attempt(BDRVNBDState *s)
/* Finalize previous connection if any */
if (s->ioc) {
-qio_channel_detach_aio_context(QIO_CHANNEL(s->ioc));
+qio_channel_detach_aio_context(s->ioc);
yank_unregister_function(BLOCKDEV_YANK_INSTANCE(s->bs->node_name),
nbd_yank, s->bs);
object_unref(OBJECT(s->ioc));
@@ -1455,7 +1455,7 @@ static void nbd_yank(void *opaque)
BDRVNBDState *s = (BDRVNBDState *)bs->opaque;
QEMU_LOCK_GUARD(>requests_lock);
-qio_channel_shutdown(QIO_CHANNEL(s->ioc), QIO_CHANNEL_SHUTDOWN_BOTH, NULL);
+qio_channel_shutdown(s->ioc, QIO_CHANNEL_SHUTDOWN_BOTH, NULL);
s->state = NBD_CLIENT_QUIT;
}
diff --git a/chardev/char-pty.c b/chardev/char-pty.c
index 92fd33c854..4e5deac18a 100644
--- a/chardev/char-pty.c
+++ b/chardev/char-pty.c
@@ -334,7 +334,7 @@ static void char_pty_open(Chardev *chr,
s = PTY_CHARDEV(chr);
s->ioc = QIO_CHANNEL(qio_channel_file_new_fd(master_fd));
name = g_strdup_printf("chardev-pty-%s", chr->label);
-qio_channel_set_name(QIO_CHANNEL(s->ioc), name);
+qio_channel_set_name(s->ioc, name);
g_free(name);
s->timer_src = NULL;
*be_opened = false;
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 58f3d30c9b..dc4e43e0ee 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1250,7 +1250,7 @@ static void musicpal_init(MachineState *machine)
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, _fatal);
qdev_realize_and_unref(uart_orgate, NULL, _fatal);
-qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
+qdev_connect_gpio_out(uart_orgate, 0,
qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 69b1b99e93..db1e0dee6e 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -327,7 +327,7 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
object_initialize_child(OBJECT(s), "rtc", >pmc.rtc,
TYPE_XLNX_ZYNQMP_RTC);
sbd = SYS_BUS_DEVICE(>pmc.rtc);
-sysbus_realize(SYS_BUS_DEVICE(sbd), _fatal);
+sysbus_realize(sbd, _fatal);
mr = sysbus_mmio_get_region(sbd, 0);
memory_region_add_subregion(>mr_ps, MM_PMC_RTC, mr);
diff --git a/hw/display/vhost-user-gpu.c b/hw/display/vhost-user-gpu.c
index 71dfd956b8..1386e869e5 100644
--- a/hw/display/vhost-user-gpu.c
+++ b/hw/display/vhost-user-gpu.c
@@ -364,11 +364,11 @@ vhost_user_gpu_gl_flushed(VirtIOGPUBase *b)
VhostUserGPU *g = VHOST_USER_GPU(b);
if (g->backend_blocked) {
-vhost_user_gpu_unblock(VHOST_USER_GPU(g));
+vhost_user_gpu_unblock(g);
g->backend_blocked = false;
}
-vhost_user_gpu_update_blocked(VHOST_USER_GPU(g), false);
+vhost_user_gpu_update_blocked(g, false);
}
static bool
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 0e7a3e32f3..af75460643 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -276,7 +276,7 @@ static void loongarch_extioi_instance_init(Object *obj)
int i, cpu, pin;
for (i = 0; i < EXTIOI_IRQS; i++) {
-sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq[i]);
+sysbus_init_irq(dev, >irq[i]);
}
qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
@@ -284,14
[PULL 10/18] tests/qtest: Run ipmi-bt-test only if CONFIG_IPMI_EXTERN is set
The ipmi-bt-test uses "-device ipmi-bmc-extern", thus it should
only be run if this device has been enabled in the configuration.
Message-Id: <20230524081024.1619273-1-th...@redhat.com>
Signed-off-by: Thomas Huth
---
tests/qtest/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 087f2dc9d7..1d8a53a669 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -49,7 +49,8 @@ qtests_i386 = \
(config_all_devices.has_key('CONFIG_SGA') ? ['boot-serial-test'] : []) +
\
(config_all_devices.has_key('CONFIG_ISA_IPMI_KCS') ? ['ipmi-kcs-test'] : [])
+\
(config_host.has_key('CONFIG_LINUX') and
\
- config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) +
\
+ config_all_devices.has_key('CONFIG_ISA_IPMI_BT') and
+ config_all_devices.has_key('CONFIG_IPMI_EXTERN') ? ['ipmi-bt-test'] : []) +
\
(config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) +
\
(config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) +
\
(config_all_devices.has_key('CONFIG_PVPANIC_PCI') ? ['pvpanic-pci-test'] :
[]) + \
--
2.31.1
[PULL 06/18] tests/tcg/s390x: Test single-stepping SVC
From: Ilya Leoshkevich
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
Acked-by: Alex Bennée
Message-Id: <20230510230213.330134-3-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/Makefile.target | 11 -
tests/tcg/s390x/gdbstub/test-svc.py | 64 +
tests/tcg/s390x/hello-s390x-asm.S | 20 +
3 files changed, 94 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/s390x/gdbstub/test-svc.py
create mode 100644 tests/tcg/s390x/hello-s390x-asm.S
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index b14c0bd84b..a2a15c4a23 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -77,7 +77,16 @@ run-gdbstub-signals-s390x: signals-s390x
--bin $< --test $(S390X_SRC)/gdbstub/test-signals-s390x.py, \
mixing signals and debugging)
-EXTRA_RUNS += run-gdbstub-signals-s390x
+hello-s390x-asm: CFLAGS+=-nostdlib
+
+run-gdbstub-svc: hello-s390x-asm
+ $(call run-test, $@, $(GDB_SCRIPT) \
+ --gdb $(HAVE_GDB_BIN) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(S390X_SRC)/gdbstub/test-svc.py, \
+ single-stepping svc)
+
+EXTRA_RUNS += run-gdbstub-signals-s390x run-gdbstub-svc
endif
# MVX versions of sha512
diff --git a/tests/tcg/s390x/gdbstub/test-svc.py
b/tests/tcg/s390x/gdbstub/test-svc.py
new file mode 100644
index 00..7851ca7284
--- /dev/null
+++ b/tests/tcg/s390x/gdbstub/test-svc.py
@@ -0,0 +1,64 @@
+"""Test single-stepping SVC.
+
+This runs as a sourced script (via -x, via run-test.py)."""
+from __future__ import print_function
+import gdb
+import sys
+
+
+n_failures = 0
+
+
+def report(cond, msg):
+"""Report success/fail of a test"""
+if cond:
+print("PASS: {}".format(msg))
+else:
+print("FAIL: {}".format(msg))
+global n_failures
+n_failures += 1
+
+
+def run_test():
+"""Run through the tests one by one"""
+report("lghi\t" in gdb.execute("x/i $pc", False, True), "insn #1")
+gdb.execute("si")
+report("larl\t" in gdb.execute("x/i $pc", False, True), "insn #2")
+gdb.execute("si")
+report("lghi\t" in gdb.execute("x/i $pc", False, True), "insn #3")
+gdb.execute("si")
+report("svc\t" in gdb.execute("x/i $pc", False, True), "insn #4")
+gdb.execute("si")
+report("xgr\t" in gdb.execute("x/i $pc", False, True), "insn #5")
+gdb.execute("si")
+report("svc\t" in gdb.execute("x/i $pc", False, True), "insn #6")
+gdb.execute("si")
+
+
+def main():
+"""Prepare the environment and run through the tests"""
+try:
+inferior = gdb.selected_inferior()
+print("ATTACHED: {}".format(inferior.architecture().name()))
+except (gdb.error, AttributeError):
+print("SKIPPING (not connected)")
+exit(0)
+
+if gdb.parse_and_eval('$pc') == 0:
+print("SKIP: PC not set")
+exit(0)
+
+try:
+# These are not very useful in scripts
+gdb.execute("set pagination off")
+gdb.execute("set confirm off")
+
+# Run the actual tests
+run_test()
+except gdb.error:
+report(False, "GDB Exception: {}".format(sys.exc_info()[0]))
+print("All tests complete: %d failures" % n_failures)
+exit(n_failures)
+
+
+main()
diff --git a/tests/tcg/s390x/hello-s390x-asm.S
b/tests/tcg/s390x/hello-s390x-asm.S
new file mode 100644
index 00..2e9faa1604
--- /dev/null
+++ b/tests/tcg/s390x/hello-s390x-asm.S
@@ -0,0 +1,20 @@
+/*
+ * Hello, World! in assembly.
+ */
+
+.globl _start
+_start:
+
+/* puts("Hello, World!"); */
+lghi %r2,1
+larl %r3,foo
+lghi %r4,foo_end-foo
+svc 4
+
+/* exit(0); */
+xgr %r2,%r2
+svc 1
+
+.align 2
+foo: .asciz "Hello, World!\n"
+foo_end:
--
2.31.1
[PULL 12/18] hw/mips/malta: Fix the malta machine on big endian hosts
Booting a Linux kernel with the malta machine is currently broken
on big endian hosts. The cpu_to_gt32 macro wants to byteswap a value
for little endian targets only, but uses the wrong way to do this:
cpu_to_[lb]e32 works the other way round on big endian hosts! Fix
it by using the same ways on both, big and little endian hosts.
Fixes: 0c8427baf0 ("hw/mips/malta: Use bootloader helper to set BAR registers")
Cc: qemu-sta...@nongnu.org
Message-Id: <20230330152613.232082-1-th...@redhat.com>
Reviewed-by: Peter Maydell
Signed-off-by: Thomas Huth
---
hw/mips/malta.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index e3be2eea56..47cb49f691 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -629,9 +629,9 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t
run_addr,
/* Bus endianess is always reversed */
#if TARGET_BIG_ENDIAN
-#define cpu_to_gt32 cpu_to_le32
+#define cpu_to_gt32(x) (x)
#else
-#define cpu_to_gt32 cpu_to_be32
+#define cpu_to_gt32(x) bswap32(x)
#endif
/* setup MEM-to-PCI0 mapping as done by YAMON */
--
2.31.1
[PULL 15/18] s390x/tcg: Fix CPU address returned by STIDP
From: Ilya Leoshkevich
In qemu-user-s390x, /proc/cpuinfo contains:
processor 0: version = 00, identification = 00, machine = 8561
processor 1: version = 00, identification = 40, machine = 8561
The highest nibble is supposed to contain the CPU address, but it's off
by 2 bits. Fix the shift value and provide a symbolic constant for it.
With the fix we get:
processor 0: version = 00, identification = 00, machine = 8561
processor 1: version = 00, identification = 10, machine = 8561
Fixes: 076d4d39b65f ("s390x/cpumodel: wire up cpu type + id for TCG")
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230605113950.1169228-2-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
target/s390x/cpu_models.h | 10 +-
target/s390x/cpu_models.c | 4 ++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
index fb1adc8b21..cc7305ec21 100644
--- a/target/s390x/cpu_models.h
+++ b/target/s390x/cpu_models.h
@@ -96,10 +96,18 @@ static inline bool s390_known_cpu_type(uint16_t type)
{
return s390_get_gen_for_cpu_type(type) != 0;
}
+#define CPU_ID_SHIFT 32
+#define CPU_ID_BITS 24
+/*
+ * When cpu_id_format is 0 (basic mode), the leftmost 4 bits of cpu_id contain
+ * the rightmost 4 bits of the physical CPU address.
+ */
+#define CPU_PHYS_ADDR_BITS 4
+#define CPU_PHYS_ADDR_SHIFT (CPU_ID_SHIFT + CPU_ID_BITS - CPU_PHYS_ADDR_BITS)
static inline uint64_t s390_cpuid_from_cpu_model(const S390CPUModel *model)
{
return ((uint64_t)model->cpu_ver << 56) |
- ((uint64_t)model->cpu_id << 32) |
+ ((uint64_t)model->cpu_id << CPU_ID_SHIFT) |
((uint64_t)model->def->type << 16) |
(model->def->gen == 7 ? 0 : (uint64_t)model->cpu_id_format << 15);
}
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 457b5cb10c..ae8880e81d 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -607,8 +607,8 @@ void s390_realize_cpu_model(CPUState *cs, Error **errp)
#if !defined(CONFIG_USER_ONLY)
cpu->env.cpuid = s390_cpuid_from_cpu_model(cpu->model);
if (tcg_enabled()) {
-/* basic mode, write the cpu address into the first 4 bit of the ID */
-cpu->env.cpuid = deposit64(cpu->env.cpuid, 54, 4, cpu->env.core_id);
+cpu->env.cpuid = deposit64(cpu->env.cpuid, CPU_PHYS_ADDR_SHIFT,
+ CPU_PHYS_ADDR_BITS, cpu->env.core_id);
}
#endif
}
--
2.31.1
[PULL 05/18] linux-user/s390x: Fix single-stepping SVC
From: Ilya Leoshkevich
Currently single-stepping SVC executes two instructions. The reason is
that EXCP_DEBUG for the SVC instruction itself is masked by EXCP_SVC.
Fix by re-raising EXCP_DEBUG.
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230510230213.330134-2-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
linux-user/s390x/cpu_loop.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c
index 285bc60071..8b7ac2879e 100644
--- a/linux-user/s390x/cpu_loop.c
+++ b/linux-user/s390x/cpu_loop.c
@@ -86,6 +86,15 @@ void cpu_loop(CPUS390XState *env)
} else if (ret != -QEMU_ESIGRETURN) {
env->regs[2] = ret;
}
+
+if (unlikely(cs->singlestep_enabled)) {
+/*
+ * cpu_tb_exec() did not raise EXCP_DEBUG, because it has seen
+ * that EXCP_SVC was already pending.
+ */
+cs->exception_index = EXCP_DEBUG;
+}
+
break;
case EXCP_DEBUG:
--
2.31.1
[PULL 01/18] target/s390x: Fix LCBB overwriting the top 32 bits
From: Ilya Leoshkevich
LCBB is supposed to overwrite only the bottom 32 bits, but QEMU
erroneously overwrites the entire register.
Fixes: 6d9303322ed9 ("s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230526181240.1425579-2-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Reviewed-by: David Hildenbrand
Signed-off-by: Thomas Huth
---
target/s390x/tcg/insn-data.h.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index bcc70d99ba..e41672684a 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -486,7 +486,7 @@
F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1_P, negf128, f128,
IF_BFP)
F(0xb373, LCDFR, RRE, FPSSH, 0, f2, new, f1, negf64, 0, IF_AFP1 |
IF_AFP2)
/* LOAD COUNT TO BLOCK BOUNDARY */
-C(0xe727, LCBB,RXE, V, la2, 0, r1, 0, lcbb, 0)
+C(0xe727, LCBB,RXE, V, la2, 0, new, r1_32, lcbb, 0)
/* LOAD HALFWORD */
C(0xb927, LHR, RRE, EI, 0, r2_16s, 0, r1_32, mov2, 0)
C(0xb907, LGHR,RRE, EI, 0, r2_16s, 0, r1, mov2, 0)
--
2.31.1
[PULL 09/18] tests/tcg/s390x: Test MXDB and MXDBR
From: Ilya Leoshkevich
Add a small test to prevent regressions.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230601223027.795501-3-...@linux.ibm.com>
Acked-by: David Hildenbrand
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/mxdb.c | 30 ++
tests/tcg/s390x/Makefile.target | 1 +
2 files changed, 31 insertions(+)
create mode 100644 tests/tcg/s390x/mxdb.c
diff --git a/tests/tcg/s390x/mxdb.c b/tests/tcg/s390x/mxdb.c
new file mode 100644
index 00..ae922559d3
--- /dev/null
+++ b/tests/tcg/s390x/mxdb.c
@@ -0,0 +1,30 @@
+/*
+ * Test the MXDB and MXDBR instructions.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include
+#include
+
+int main(void)
+{
+union {
+double d[2];
+long double ld;
+} a;
+double b;
+
+a.d[0] = 1.2345;
+a.d[1] = 999;
+b = 6.789;
+asm("mxdb %[a],%[b]" : [a] "+f" (a.ld) : [b] "R" (b));
+assert(a.ld > 8.38 && a.ld < 8.39);
+
+a.d[0] = 1.2345;
+a.d[1] = 999;
+b = 6.789;
+asm("mxdbr %[a],%[b]" : [a] "+f" (a.ld) : [b] "f" (b));
+assert(a.ld > 8.38 && a.ld < 8.39);
+
+return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index a2a15c4a23..85abfbb98c 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -35,6 +35,7 @@ TESTS+=chrl
TESTS+=rxsbg
TESTS+=ex-relative-long
TESTS+=ex-branch
+TESTS+=mxdb
cdsg: CFLAGS+=-pthread
cdsg: LDFLAGS+=-pthread
--
2.31.1
[PULL 16/18] linux-user/elfload: Expose get_elf_hwcap() on s390x
From: Ilya Leoshkevich
It is required for implementing /proc/cpuinfo emulation.
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230605113950.1169228-3-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
linux-user/loader.h | 4
linux-user/elfload.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-user/loader.h b/linux-user/loader.h
index f375ee0679..ad6ca9dbe3 100644
--- a/linux-user/loader.h
+++ b/linux-user/loader.h
@@ -56,4 +56,8 @@ abi_long memcpy_to_target(abi_ulong dest, const void *src,
extern unsigned long guest_stack_size;
+#ifdef TARGET_S390X
+uint32_t get_elf_hwcap(void);
+#endif
+
#endif /* LINUX_USER_LOADER_H */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 418ad92598..49ec9ccc94 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1583,7 +1583,7 @@ static inline void init_thread(struct target_pt_regs
*regs,
#define GET_FEATURE(_feat, _hwcap) \
do { if (s390_has_feat(_feat)) { hwcap |= _hwcap; } } while (0)
-static uint32_t get_elf_hwcap(void)
+uint32_t get_elf_hwcap(void)
{
/*
* Let's assume we always have esan3 and zarch.
--
2.31.1
[PULL 17/18] linux-user/elfload: Introduce elf_hwcap_str() on s390x
From: Ilya Leoshkevich
It is required for implementing /proc/cpuinfo emulation.
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230605113950.1169228-4-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
linux-user/loader.h | 1 +
linux-user/elfload.c | 27 +++
2 files changed, 28 insertions(+)
diff --git a/linux-user/loader.h b/linux-user/loader.h
index ad6ca9dbe3..59cbeacf24 100644
--- a/linux-user/loader.h
+++ b/linux-user/loader.h
@@ -58,6 +58,7 @@ extern unsigned long guest_stack_size;
#ifdef TARGET_S390X
uint32_t get_elf_hwcap(void);
+const char *elf_hwcap_str(uint32_t bit);
#endif
#endif /* LINUX_USER_LOADER_H */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 49ec9ccc94..d80d68484b 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1605,6 +1605,33 @@ uint32_t get_elf_hwcap(void)
return hwcap;
}
+const char *elf_hwcap_str(uint32_t bit)
+{
+static const char *hwcap_str[] = {
+[HWCAP_S390_ESAN3] = "esan3",
+[HWCAP_S390_ZARCH] = "zarch",
+[HWCAP_S390_STFLE] = "stfle",
+[HWCAP_S390_MSA] = "msa",
+[HWCAP_S390_LDISP] = "ldisp",
+[HWCAP_S390_EIMM] = "eimm",
+[HWCAP_S390_DFP] = "dfp",
+[HWCAP_S390_HPAGE] = "edat",
+[HWCAP_S390_ETF3EH]= "etf3eh",
+[HWCAP_S390_HIGH_GPRS] = "highgprs",
+[HWCAP_S390_TE]= "te",
+[HWCAP_S390_VXRS] = "vx",
+[HWCAP_S390_VXRS_BCD] = "vxd",
+[HWCAP_S390_VXRS_EXT] = "vxe",
+[HWCAP_S390_GS]= "gs",
+[HWCAP_S390_VXRS_EXT2] = "vxe2",
+[HWCAP_S390_VXRS_PDE] = "vxp",
+[HWCAP_S390_SORT] = "sort",
+[HWCAP_S390_DFLT] = "dflt",
+};
+
+return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
+}
+
static inline void init_thread(struct target_pt_regs *regs, struct image_info
*infop)
{
regs->psw.addr = infop->entry;
--
2.31.1
[PULL 02/18] tests/tcg/s390x: Test LCBB
From: Ilya Leoshkevich
Add a test to prevent regressions.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230526181240.1425579-3-...@linux.ibm.com>
Reviewed-by: David Hildenbrand
Acked-by: Richard Henderson
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/lcbb.c | 51 +
tests/tcg/s390x/Makefile.target | 1 +
2 files changed, 52 insertions(+)
create mode 100644 tests/tcg/s390x/lcbb.c
diff --git a/tests/tcg/s390x/lcbb.c b/tests/tcg/s390x/lcbb.c
new file mode 100644
index 00..8d368e0998
--- /dev/null
+++ b/tests/tcg/s390x/lcbb.c
@@ -0,0 +1,51 @@
+/*
+ * Test the LCBB instruction.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include
+#include
+
+static inline __attribute__((__always_inline__)) void
+lcbb(long *r1, void *dxb2, int m3, int *cc)
+{
+asm("lcbb %[r1],%[dxb2],%[m3]\n"
+"ipm %[cc]"
+: [r1] "+r" (*r1), [cc] "=r" (*cc)
+: [dxb2] "R" (*(char *)dxb2), [m3] "i" (m3)
+: "cc");
+*cc = (*cc >> 28) & 3;
+}
+
+static char buf[0x1000] __attribute__((aligned(0x1000)));
+
+static inline __attribute__((__always_inline__)) void
+test_lcbb(void *p, int m3, int exp_r1, int exp_cc)
+{
+long r1 = 0xfedcba9876543210;
+int cc;
+
+lcbb(, p, m3, );
+assert(r1 == (0xfedcba98 | exp_r1));
+assert(cc == exp_cc);
+}
+
+int main(void)
+{
+test_lcbb([0],0, 16, 0);
+test_lcbb([63], 0, 1, 3);
+test_lcbb([0],1, 16, 0);
+test_lcbb([127], 1, 1, 3);
+test_lcbb([0],2, 16, 0);
+test_lcbb([255], 2, 1, 3);
+test_lcbb([0],3, 16, 0);
+test_lcbb([511], 3, 1, 3);
+test_lcbb([0],4, 16, 0);
+test_lcbb([1023], 4, 1, 3);
+test_lcbb([0],5, 16, 0);
+test_lcbb([2047], 5, 1, 3);
+test_lcbb([0],6, 16, 0);
+test_lcbb([4095], 6, 1, 3);
+
+return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 23dc8b6a63..4ed07c6ab0 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -47,6 +47,7 @@ $(PGM_SPECIFICATION_TESTS): LDFLAGS+=pgm-specification-user.o
TESTS += $(PGM_SPECIFICATION_TESTS)
Z13_TESTS=vistr
+Z13_TESTS+=lcbb
$(Z13_TESTS): CFLAGS+=-march=z13 -O2
TESTS+=$(Z13_TESTS)
--
2.31.1
[PULL 07/18] Add conditional dependency for libkeyutils
From: Max Fritz
This modification enables better control over the inclusion of libkeyutils
based on the configuration, enhancing the flexibility of the build system.
Signed-off-by: Max Fritz
Message-Id: <168471463402.18155.357535902742993996...@git.sr.ht>
Reviewed-by: Daniel P. Berrangé
[thuth: Remove the "kwargs: static_kwargs" part - it's not necessary anymore]
Signed-off-by: Thomas Huth
---
meson.build | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index a61d3e9b06..576bc2fdbd 100644
--- a/meson.build
+++ b/meson.build
@@ -1781,8 +1781,10 @@ if gnutls.found()
tasn1 = dependency('libtasn1',
method: 'pkg-config')
endif
-keyutils = dependency('libkeyutils', required: false,
- method: 'pkg-config')
+keyutils = not_found
+if get_option('keyring').enabled()
+ keyutils = dependency('libkeyutils', required: false, method: 'pkg-config')
+endif
has_gettid = cc.has_function('gettid')
--
2.31.1
[PULL 13/18] scripts: Add qom-cast-macro-clean-cocci-gen.py
From: Philippe Mathieu-Daudé
Add a script to generate Coccinelle semantic patch
removing all pointless QOM cast macro uses.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230601093452.38972-2-phi...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
scripts/qom-cast-macro-clean-cocci-gen.py | 49 +++
2 files changed, 50 insertions(+)
create mode 100644 scripts/qom-cast-macro-clean-cocci-gen.py
diff --git a/MAINTAINERS b/MAINTAINERS
index 89f274f85e..b2137111f1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3045,6 +3045,7 @@ F: include/qom/
F: qapi/qom.json
F: qapi/qdev.json
F: scripts/coccinelle/qom-parent-type.cocci
+F: scripts/qom-cast-macro-clean-cocci-gen.py
F: softmmu/qdev-monitor.c
F: stubs/qdev.c
F: qom/
diff --git a/scripts/qom-cast-macro-clean-cocci-gen.py
b/scripts/qom-cast-macro-clean-cocci-gen.py
new file mode 100644
index 00..2fa8438a14
--- /dev/null
+++ b/scripts/qom-cast-macro-clean-cocci-gen.py
@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+#
+# Generate a Coccinelle semantic patch to remove pointless QOM cast.
+#
+# Usage:
+#
+# $ qom-cast-macro-clean-cocci-gen.py $(git ls-files) >
qom_pointless_cast.cocci
+# $ spatch \
+# --macro-file scripts/cocci-macro-file.h \
+# --sp-file qom_pointless_cast.cocci \
+# --keep-comments \
+# --use-gitgrep \
+# --in-place \
+# --dir .
+#
+# SPDX-FileContributor: Philippe Mathieu-Daudé
+# SPDX-FileCopyrightText: 2023 Linaro Ltd.
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import re
+import sys
+
+assert len(sys.argv) > 0
+
+def print_cocci_rule(qom_typedef, qom_cast_macro):
+print(f'''@@
+typedef {qom_typedef};
+{qom_typedef} *obj;
+@@
+-{qom_cast_macro}(obj)
++obj
+''')
+
+patterns = [
+r'DECLARE_INSTANCE_CHECKER\((\w+),\W*(\w+),\W*TYPE_\w+\)',
+r'DECLARE_OBJ_CHECKERS\((\w+),\W*\w+,\W*(\w+),\W*TYPE_\w+\)',
+r'OBJECT_DECLARE_TYPE\((\w+),\W*\w+,\W*(\w+)\)',
+r'OBJECT_DECLARE_SIMPLE_TYPE\((\w+),\W*(\w+)\)',
+r'INTERFACE_CHECK\((\w+),\W*\(\w+\),\W*TYPE_(\w+)\)',
+]
+
+for fn in sys.argv[1:]:
+try:
+content = open(fn, 'rt').read()
+except:
+continue
+for pattern in patterns:
+for match in re.findall(pattern, content):
+print_cocci_rule(match[0], match[1])
--
2.31.1
[PULL 04/18] tests/tcg/s390x: Test LOCFHR
From: Ilya Leoshkevich
Add a small test to prevent regressions.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230526181240.1425579-5-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Reviewed-by: David Hildenbrand
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/locfhr.c| 29 +
tests/tcg/s390x/Makefile.target | 1 +
2 files changed, 30 insertions(+)
create mode 100644 tests/tcg/s390x/locfhr.c
diff --git a/tests/tcg/s390x/locfhr.c b/tests/tcg/s390x/locfhr.c
new file mode 100644
index 00..ab9ff6e449
--- /dev/null
+++ b/tests/tcg/s390x/locfhr.c
@@ -0,0 +1,29 @@
+/*
+ * Test the LOCFHR instruction.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include
+#include
+
+static inline __attribute__((__always_inline__)) long
+locfhr(long r1, long r2, int m3, int cc)
+{
+cc <<= 28;
+asm("spm %[cc]\n"
+"locfhr %[r1],%[r2],%[m3]\n"
+: [r1] "+r" (r1)
+: [cc] "r" (cc), [r2] "r" (r2), [m3] "i" (m3)
+: "cc");
+return r1;
+}
+
+int main(void)
+{
+assert(locfhr(0x, 0x, 8, 0) ==
+ 0x);
+assert(locfhr(0x, 0x, 11, 1) ==
+ 0x);
+
+return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 4ed07c6ab0..b14c0bd84b 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -48,6 +48,7 @@ TESTS += $(PGM_SPECIFICATION_TESTS)
Z13_TESTS=vistr
Z13_TESTS+=lcbb
+Z13_TESTS+=locfhr
$(Z13_TESTS): CFLAGS+=-march=z13 -O2
TESTS+=$(Z13_TESTS)
--
2.31.1
[PULL 00/18] s390x and misc patches
Hi Richard! The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d: Merge tag 'migration-20230602-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700) are available in the Git repository at: https://gitlab.com/thuth/qemu.git tags/pull-request-2023-06-06 for you to fetch changes up to 1fb9bdaf59719c0d0c28043e58c8e3452fd6d7de: linux-user: Emulate /proc/cpuinfo on s390x (2023-06-05 20:48:34 +0200) * Fix emulated LCCB, LOCFHR, MXDB and MXDBR s390x instructions * Fix the malta machine on s390x (big endian) hosts * Emulate /proc/cpuinfo on s390x * Remove pointless QOM casts * Improve the inclusion logic for libkeyutils and ipmi-bt-test in meson.build Camilla Conte (1): gitlab-ci: Remove unused Python package Ilya Leoshkevich (12): target/s390x: Fix LCBB overwriting the top 32 bits tests/tcg/s390x: Test LCBB target/s390x: Fix LOCFHR taking the wrong half of R2 tests/tcg/s390x: Test LOCFHR linux-user/s390x: Fix single-stepping SVC tests/tcg/s390x: Test single-stepping SVC target/s390x: Fix MXDB and MXDBR tests/tcg/s390x: Test MXDB and MXDBR s390x/tcg: Fix CPU address returned by STIDP linux-user/elfload: Expose get_elf_hwcap() on s390x linux-user/elfload: Introduce elf_hwcap_str() on s390x linux-user: Emulate /proc/cpuinfo on s390x Max Fritz (1): Add conditional dependency for libkeyutils Philippe Mathieu-Daudé (2): scripts: Add qom-cast-macro-clean-cocci-gen.py bulk: Remove pointless QOM casts Thomas Huth (2): tests/qtest: Run ipmi-bt-test only if CONFIG_IPMI_EXTERN is set hw/mips/malta: Fix the malta machine on big endian hosts MAINTAINERS | 1 + meson.build | 6 +- linux-user/loader.h | 5 ++ target/s390x/cpu_models.h | 10 ++- target/s390x/helper.h | 2 +- target/s390x/tcg/insn-data.h.inc | 8 +-- block/nbd.c | 4 +- chardev/char-pty.c| 2 +- hw/arm/musicpal.c | 2 +- hw/arm/xlnx-versal.c | 2 +- hw/display/vhost-user-gpu.c | 4 +- hw/intc/loongarch_extioi.c| 6 +- hw/m68k/q800.c| 2 +- hw/mips/malta.c | 4 +- hw/pci-host/bonito.c | 2 +- hw/ppc/pnv_lpc.c | 2 +- hw/ppc/pnv_occ.c | 2 +- hw/ppc/pnv_sbe.c | 2 +- hw/riscv/virt.c | 10 +-- hw/rx/rx62n.c | 2 +- hw/scsi/esp-pci.c | 18 ++--- hw/sparc/sun4m.c | 4 +- hw/virtio/virtio-mem-pci.c| 6 +- hw/virtio/virtio-pmem-pci.c | 6 +- linux-user/elfload.c | 29 +++- linux-user/s390x/cpu_loop.c | 9 +++ linux-user/syscall.c | 106 +- migration/fd.c| 4 +- migration/multifd.c | 2 +- migration/yank_functions.c| 4 +- nbd/client-connection.c | 2 +- nbd/server.c | 2 +- softmmu/qdev-monitor.c| 2 +- target/s390x/cpu_models.c | 4 +- target/s390x/tcg/fpu_helper.c | 5 +- target/s390x/tcg/translate.c | 8 +-- tests/tcg/s390x/lcbb.c| 51 ++ tests/tcg/s390x/locfhr.c | 29 tests/tcg/s390x/mxdb.c| 30 + ui/vnc-ws.c | 6 +- .gitlab-ci.d/container-template.yml | 1 - scripts/qom-cast-macro-clean-cocci-gen.py | 49 ++ tests/qtest/meson.build | 3 +- tests/tcg/s390x/Makefile.target | 14 +++- tests/tcg/s390x/gdbstub/test-svc.py | 64 ++ tests/tcg/s390x/hello-s390x-asm.S | 20 ++ 46 files changed, 480 insertions(+), 76 deletions(-) create mode 100644 tests/tcg/s390x/lcbb.c create mode 100644 tests/tcg/s390x/locfhr.c create mode 100644 tests/tcg/s390x/mxdb.c create mode 100644 scripts/qom-cast-macro-clean-cocci-gen.py create mode 100644 tests/tcg/s390x/gdbstub/test-svc.py create mode 100644 tests/tcg/s390x/hello-s390x-asm.S
Re: [PATCH 01/10] sysemu/kvm: Remove unused headers
On 5/4/23 18:04, Philippe Mathieu-Daudé wrote: All types used are forward-declared in "qemu/typedefs.h". Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/kvm.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index cc6c678ed8..7902acdfd9 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -16,9 +16,6 @@ #ifndef QEMU_KVM_H #define QEMU_KVM_H -#include "qemu/queue.h" -#include "hw/core/cpu.h" -#include "exec/memattrs.h" Oops this is incorrect... MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run); MemTxAttrs is not: - forward-declared - used as pointer Since this is now merged as commit 1e05888ab5 I'll send a fix. #include "qemu/accel.h" #include "qom/object.h"
Re: [RFC v1 4/4] qemu: adjust queried bar size to power-of-2
On 6/6/23 01:50, ank...@nvidia.com wrote: From: Ankit Agrawal The GPU device memory is reported to the VM as a BAR. The device memory may not be aligned to the power-of-2, but the QEMU expects the PCI BAR to be. Align the reported device memory size to the next power-of-2 before QEMU does an mmap. Signed-off-by: Ankit Agrawal --- hw/vfio/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 4d01ea3515..bb49200458 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -2061,7 +2061,7 @@ int vfio_region_setup(Object *obj, VFIODevice *vbasedev, VFIORegion *region, region->vbasedev = vbasedev; region->flags = info->flags; -region->size = info->size; +region->size = info->size ? pow2ceil(info->size) : info->size; region->size = [REAL_]HOST_PAGE_ALIGN(info->size)? region->fd_offset = info->offset; region->nr = index;
Re: [RFC v1 2/4] qemu: patch guest SRAT for GPU memory
On 6/6/23 01:50, ank...@nvidia.com wrote: From: Ankit Agrawal The guest VM adds the GPU memory as (upto 8) separate memory-less NUMA nodes. ACPI SRAT need to thus insert proximity domains and tag them as MEM_AFFINITY_HOTPLUGGABLE. The VM kernel can then parse the SRAT and create NUMA nodes. Signed-off-by: Ankit Agrawal --- hw/arm/virt-acpi-build.c | 54 1 file changed, 54 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c /* * ACPI spec, Revision 5.1 * 5.2.16 System Resource Affinity Table (SRAT) @@ -568,6 +620,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) There is a x86 build_srat() equivalent. So some abstraction in hw/acpi/srat.c is possible. } +build_srat_devmem(table_data); + acpi_table_end(linker, ); }
RE: [PATCH v2 3/4] memory: Document update on replay()
>-Original Message-
>From: Peter Xu
>Sent: Tuesday, June 6, 2023 2:42 AM
>To: Duan, Zhenzhong
>Cc: qemu-devel@nongnu.org; m...@redhat.com; jasow...@redhat.com;
>pbonz...@redhat.com; richard.hender...@linaro.org; edua...@habkost.net;
>marcel.apfelb...@gmail.com; alex.william...@redhat.com;
>c...@redhat.com; da...@redhat.com; phi...@linaro.org;
>kwankh...@nvidia.com; c...@nvidia.com; Liu, Yi L ; Peng,
>Chao P
>Subject: Re: [PATCH v2 3/4] memory: Document update on replay()
>
>On Thu, Jun 01, 2023 at 02:33:19PM +0800, Zhenzhong Duan wrote:
>> diff --git a/include/exec/memory.h b/include/exec/memory.h index
>> eecc3eec6702..9a523ef62a94 100644
>> --- a/include/exec/memory.h
>> +++ b/include/exec/memory.h
>> @@ -441,9 +441,9 @@ struct IOMMUMemoryRegionClass {
>> * call the IOMMU translate method for every page in the address space
>> * with flag == IOMMU_NONE and then call the notifier if translate
>> * returns a valid mapping. If this method is implemented then it
>> - * overrides the default behaviour, and must provide the full semantics
>> - * of memory_region_iommu_replay(), by calling @notifier for every
>> - * translation present in the IOMMU.
>> + * overrides the default behavior, and must provide corresponding
>> + * semantics depending on notifier's type, e.g. IOMMU_NOTIFIER_MAP,
>> + * notify changed entries; IOMMU_NOTIFIER_FULL_MAP, notify full
>entries.
>
>IIUC it was always trying to notify all existing entries only, rather than
>changed
>entries. VT-d used to unmap all so it was also true.
Thanks for point out, I confused with invalidation path, I'll drop it.
Zhenzhong
RE: [PATCH v2 2/4] intel_iommu: Fix a potential issue in VFIO dirty page sync
>-Original Message-
>From: Peter Xu
>Sent: Tuesday, June 6, 2023 2:39 AM
>To: Duan, Zhenzhong
>Cc: qemu-devel@nongnu.org; m...@redhat.com; jasow...@redhat.com;
>pbonz...@redhat.com; richard.hender...@linaro.org; edua...@habkost.net;
>marcel.apfelb...@gmail.com; alex.william...@redhat.com;
>c...@redhat.com; da...@redhat.com; phi...@linaro.org;
>kwankh...@nvidia.com; c...@nvidia.com; Liu, Yi L ; Peng,
>Chao P
>Subject: Re: [PATCH v2 2/4] intel_iommu: Fix a potential issue in VFIO dirty
>page sync
>
>On Thu, Jun 01, 2023 at 02:33:18PM +0800, Zhenzhong Duan wrote:
>> Peter Xu found a potential issue:
>>
>> "The other thing is when I am looking at the new code I found that we
>> actually extended the replay() to be used also in dirty tracking of vfio,
>> in vfio_sync_dirty_bitmap(). For that maybe it's already broken if
>> unmap_all() because afaiu log_sync() can be called in migration thread
>> anytime during DMA so I think it means the device is prone to DMA with the
>> IOMMU pgtable quickly erased and rebuilt here, which means the DMA
>could
>> fail unexpectedly. Copy Alex, Kirti and Neo."
>>
>> To eliminate this small window with empty mapping, we should remove the
>> call to unmap_all(). Besides that, introduce a new notifier type called
>> IOMMU_NOTIFIER_FULL_MAP to get full mappings as intel_iommu only
>notifies
>> changed mappings while VFIO dirty page sync needs full mappings. Thanks
>> to current implementation of iova tree, we could pick mappings from iova
>> trees directly instead of walking through guest IOMMU page table.
>>
>> IOMMU_NOTIFIER_MAP is still used to get changed mappings for
>optimization
>> purpose. As long as notification for IOMMU_NOTIFIER_MAP could ensure
>shadow
>> page table in sync, then it's OK.
>>
>> Signed-off-by: Zhenzhong Duan
>> ---
>> hw/i386/intel_iommu.c | 49 +++--
>--
>> hw/vfio/common.c | 2 +-
>> include/exec/memory.h | 13
>> softmmu/memory.c | 4
>> 4 files changed, 58 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index 94d52f4205d2..061fcded0dfb 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -3819,6 +3819,41 @@ static int vtd_replay_hook(IOMMUTLBEvent
>*event, void *private)
>> return 0;
>> }
>>
>> +static gboolean vtd_replay_full_map(DMAMap *map, gpointer *private)
>> +{
>> +IOMMUTLBEvent event;
>> +
>> +event.type = IOMMU_NOTIFIER_MAP;
>> +event.entry.iova = map->iova;
>> +event.entry.addr_mask = map->size;
>> +event.entry.target_as = _space_memory;
>> +event.entry.perm = map->perm;
>> +event.entry.translated_addr = map->translated_addr;
>> +
>> +return vtd_replay_hook(, private);
>> +}
>> +
>> +/*
>> + * This is a fast path to notify the full mappings falling in the scope
>> + * of IOMMU notifier. The call site should ensure no iova tree update by
>> + * taking necessary locks(e.x. BQL).
>
>We should be accurate on the locking - I think it's the BQL so far.
Will update comments.
>
>> + */
>> +static int vtd_page_walk_full_map_fast_path(IOVATree *iova_tree,
>> +IOMMUNotifier *n)
>> +{
>> +DMAMap map;
>> +
>> +map.iova = n->start;
>> +map.size = n->end - n->start;
>> +if (!iova_tree_find(iova_tree, )) {
>> +return 0;
>> +}
>> +
>> +iova_tree_foreach_range_data(iova_tree, , vtd_replay_full_map,
>> + (gpointer *)n);
>> +return 0;
>> +}
>> +
>> static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr,
>IOMMUNotifier *n)
>> {
>> VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace,
>iommu);
>> @@ -3826,13 +3861,6 @@ static void
>vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
>> uint8_t bus_n = pci_bus_num(vtd_as->bus);
>> VTDContextEntry ce;
>>
>> -/*
>> - * The replay can be triggered by either a invalidation or a newly
>> - * created entry. No matter what, we release existing mappings
>> - * (it means flushing caches for UNMAP-only registers).
>> - */
>> -vtd_address_space_unmap(vtd_as, n);
>> -
>> if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, ) == 0) {
>> trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" :
>>"legacy mode",
>> @@ -3850,8 +3878,11 @@ static void
>vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
>> .as = vtd_as,
>> .domain_id = vtd_get_domain_id(s, , vtd_as->pasid),
>> };
>> -
>> -vtd_page_walk(s, , 0, ~0ULL, , vtd_as->pasid);
>> +if (n->notifier_flags & IOMMU_NOTIFIER_FULL_MAP) {
>> +vtd_page_walk_full_map_fast_path(vtd_as->iova_tree, n);
>> +} else {
>> +vtd_page_walk(s, , 0, ~0ULL, , vtd_as->pasid);
>> +}
>> }
>> } else {
>>
Re: [PATCH] virtio-net: correctly report maximum tx_queue_size value
On Mon, Jun 5, 2023 at 10:22 PM Laurent Vivier wrote:
>
> Maximum value for tx_queue_size depends on the backend type.
> 1024 for vDPA/vhost-user, 256 for all the others.
>
> The value is returned by virtio_net_max_tx_queue_size() to set the
> parameter:
>
> n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n),
> n->net_conf.tx_queue_size);
>
> But the parameter checking uses VIRTQUEUE_MAX_SIZE (1024).
>
> So the parameter is silently ignored and ethtool reports a different
> value than the one provided by the user.
>
>... -netdev tap,... -device virtio-net,tx_queue_size=1024
>
> # ethtool -g enp0s2
> Ring parameters for enp0s2:
> Pre-set maximums:
> RX: 256
> RX Mini:n/a
> RX Jumbo: n/a
> TX: 256
> Current hardware settings:
> RX: 256
> RX Mini:n/a
> RX Jumbo: n/a
> TX: 256
>
>... -netdev vhost-user,... -device virtio-net,tx_queue_size=2048
>
> Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024
>
> With this patch the correct maximum value is checked and displayed.
>
> For vDPA/vhost-user:
>
> Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024
>
> For all the others:
>
> Invalid tx_queue_size (= 512), must be a power of 2 between 256 and 256
>
> Fixes: 2eef278b9e63 ("virtio-net: fix tx queue size for !vhost-user")
> Cc: m...@redhat.com
> Signed-off-by: Laurent Vivier
Queued.
Thanks
> ---
> hw/net/virtio-net.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
> index 6df6b7329d25..e9905aac83ad 100644
> --- a/hw/net/virtio-net.c
> +++ b/hw/net/virtio-net.c
> @@ -3630,12 +3630,12 @@ static void virtio_net_device_realize(DeviceState
> *dev, Error **errp)
> }
>
> if (n->net_conf.tx_queue_size < VIRTIO_NET_TX_QUEUE_MIN_SIZE ||
> -n->net_conf.tx_queue_size > VIRTQUEUE_MAX_SIZE ||
> +n->net_conf.tx_queue_size > virtio_net_max_tx_queue_size(n) ||
> !is_power_of_2(n->net_conf.tx_queue_size)) {
> error_setg(errp, "Invalid tx_queue_size (= %" PRIu16 "), "
> "must be a power of 2 between %d and %d",
> n->net_conf.tx_queue_size, VIRTIO_NET_TX_QUEUE_MIN_SIZE,
> - VIRTQUEUE_MAX_SIZE);
> + virtio_net_max_tx_queue_size(n));
> virtio_cleanup(vdev);
> return;
> }
> --
> 2.39.2
>
>
Re: [PATCH] vdpa: mask _F_CTRL_GUEST_OFFLOADS for vhost vdpa devices
On Sat, Jun 3, 2023 at 1:33 AM Eugenio Pérez wrote:
>
> QEMU does not emulate it so it must be disabled as long as the backend
> does not support it.
>
> Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Thanks
> ---
> net/vhost-vdpa.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
> index 5360924ba0..427a57dd6f 100644
> --- a/net/vhost-vdpa.c
> +++ b/net/vhost-vdpa.c
> @@ -54,6 +54,7 @@ const int vdpa_feature_bits[] = {
> VIRTIO_F_VERSION_1,
> VIRTIO_NET_F_CSUM,
> VIRTIO_NET_F_GUEST_CSUM,
> +VIRTIO_NET_F_CTRL_GUEST_OFFLOADS,
> VIRTIO_NET_F_GSO,
> VIRTIO_NET_F_GUEST_TSO4,
> VIRTIO_NET_F_GUEST_TSO6,
> --
> 2.31.1
>
Re: [PATCH] vdpa: fix not using CVQ buffer in case of error
On Sat, Jun 3, 2023 at 1:35 AM Eugenio Pérez wrote:
>
> Bug introducing when refactoring. Otherway, the guest never received
> the used buffer.
>
> Fixes: be4278b65fc1 ("vdpa: extract vhost_vdpa_net_cvq_add from
> vhost_vdpa_net_handle_ctrl_avail")
> Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Thanks
> ---
> net/vhost-vdpa.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
> index 16d47f7b3c..5360924ba0 100644
> --- a/net/vhost-vdpa.c
> +++ b/net/vhost-vdpa.c
> @@ -807,7 +807,7 @@ static int
> vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
> }
>
> if (*s->status != VIRTIO_NET_OK) {
> -return VIRTIO_NET_ERR;
> +goto out;
> }
>
> status = VIRTIO_NET_ERR;
> --
> 2.31.1
>
[RFC v1 3/4] qemu: patch guest DSDT for GPU memory
From: Ankit Agrawal
To add the memory in the guest as NUMA nodes, it needs the PXM node index
and the total count of nodes associated with the memory. The range of
proximity domains are communicated to the VM as part of the guest ACPI
using the nvidia,gpu-mem-pxm-start and nvidia,gpu-mem-pxm-count DSD
properties. These value respectively represent the staring proximity
domain id and the count. Kernel modules can then fetch this information
and determine the numa node ID using pxm_to_node().
Signed-off-by: Ankit Agrawal
---
hw/pci-host/gpex-acpi.c | 71 +
1 file changed, 71 insertions(+)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 7c7316bc96..36873889c1 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -49,6 +49,74 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t
irq)
}
}
+static void acpi_dsdt_add_gpu(Aml *dev, int32_t devfn,
+ uint64_t gpu_mem_pxm_start,
+ uint64_t gpu_mem_pxm_count)
+{
+Aml *dev_gpu = aml_device("GPU%X", PCI_SLOT(devfn));
+Aml *pkg = aml_package(2);
+Aml *pkg1 = aml_package(2);
+Aml *pkg2 = aml_package(2);
+Aml *dev_pkg = aml_package(2);
+Aml *UUID;
+
+aml_append(dev_gpu, aml_name_decl("_ADR", aml_int(PCI_SLOT(devfn) << 16)));
+
+aml_append(pkg1, aml_string("nvidia,gpu-mem-pxm-start"));
+aml_append(pkg1, aml_int(gpu_mem_pxm_start));
+
+aml_append(pkg2, aml_string("nvidia,gpu-mem-pxm-count"));
+aml_append(pkg2, aml_int(gpu_mem_pxm_count));
+
+aml_append(pkg, pkg1);
+aml_append(pkg, pkg2);
+
+UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+aml_append(dev_pkg, UUID);
+aml_append(dev_pkg, pkg);
+
+aml_append(dev_gpu, aml_name_decl("_DSD", dev_pkg));
+aml_append(dev, dev_gpu);
+}
+
+static void find_hbm_device(PCIBus *bus, PCIDevice *pdev,
+void *opaque)
+{
+Aml *dev = (Aml *)opaque;
+uint32_t vendor_id = pci_default_read_config(pdev, PCI_VENDOR_ID, 2);
+
+if (bus == NULL) {
+return;
+}
+
+if (vendor_id == PCI_VENDOR_ID_NVIDIA &&
+pdev->has_coherent_memory) {
+Object *po = OBJECT(pdev);
+
+if (po == NULL) {
+return;
+}
+
+uint64_t pxm_start
+ = object_property_get_uint(po, "gpu_mem_pxm_start", NULL);
+uint64_t pxm_count
+ = object_property_get_uint(po, "gpu_mem_pxm_count", NULL);
+
+acpi_dsdt_add_gpu(dev, pdev->devfn, pxm_start, pxm_count);
+}
+}
+
+static void acpi_dsdt_find_and_add_gpu(PCIBus *bus, Aml *dev)
+{
+if (bus == NULL) {
+return;
+}
+
+pci_for_each_device_reverse(bus, pci_bus_num(bus),
+find_hbm_device, dev);
+
+}
+
static void acpi_dsdt_add_pci_osc(Aml *dev)
{
Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
@@ -207,7 +275,10 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
acpi_dsdt_add_pci_route_table(dev, cfg->irq);
+acpi_dsdt_find_and_add_gpu(cfg->bus, dev);
+
method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
+
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
aml_append(dev, method);
--
2.17.1
[RFC v1 2/4] qemu: patch guest SRAT for GPU memory
From: Ankit Agrawal
The guest VM adds the GPU memory as (upto 8) separate memory-less NUMA
nodes. ACPI SRAT need to thus insert proximity domains and tag them as
MEM_AFFINITY_HOTPLUGGABLE. The VM kernel can then parse the SRAT and
create NUMA nodes.
Signed-off-by: Ankit Agrawal
---
hw/arm/virt-acpi-build.c | 54
1 file changed, 54 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 4156111d49..42f76752b4 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -45,6 +45,7 @@
#include "hw/acpi/hmat.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci.h"
+#include "hw/vfio/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/gpex.h"
#include "hw/arm/virt.h"
@@ -514,6 +515,57 @@ build_spcr(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
acpi_table_end(linker, );
}
+static int devmem_device_list(Object *obj, void *opaque)
+{
+GSList **list = opaque;
+
+if (object_dynamic_cast(obj, TYPE_VFIO_PCI)) {
+*list = g_slist_append(*list, DEVICE(obj));
+}
+
+object_child_foreach(obj, devmem_device_list, opaque);
+return 0;
+}
+
+static GSList *devmem_get_device_list(void)
+{
+GSList *list = NULL;
+
+object_child_foreach(qdev_get_machine(), devmem_device_list, );
+return list;
+}
+
+static void build_srat_devmem(GArray *table_data)
+{
+GSList *device_list, *list = devmem_get_device_list();
+
+for (device_list = list; device_list; device_list = device_list->next) {
+DeviceState *dev = device_list->data;
+Object *obj = OBJECT(dev);
+VFIOPCIDevice *pcidev
+= ((VFIOPCIDevice *)object_dynamic_cast(OBJECT(obj),
+ TYPE_VFIO_PCI));
+
+if (pcidev->pdev.has_coherent_memory) {
+uint64_t start_node = object_property_get_uint(obj,
+ "gpu_mem_pxm_start", _abort);
+uint64_t node_count = object_property_get_uint(obj,
+ "gpu_mem_pxm_count", _abort);
+uint64_t node_index;
+
+/*
+ * Add the node_count PXM domains starting from start_node as
+ * hot pluggable. The VM kernel parse the PXM domains and
+ * creates NUMA nodes.
+ */
+for (node_index = 0; node_index < node_count; node_index++)
+build_srat_memory(table_data, 0, 0, start_node + node_index,
+MEM_AFFINITY_ENABLED | MEM_AFFINITY_HOTPLUGGABLE);
+}
+}
+g_slist_free(list);
+}
+
/*
* ACPI spec, Revision 5.1
* 5.2.16 System Resource Affinity Table (SRAT)
@@ -568,6 +620,8 @@ build_srat(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
}
+build_srat_devmem(table_data);
+
acpi_table_end(linker, );
}
--
2.17.1
[RFC v1 4/4] qemu: adjust queried bar size to power-of-2
From: Ankit Agrawal The GPU device memory is reported to the VM as a BAR. The device memory may not be aligned to the power-of-2, but the QEMU expects the PCI BAR to be. Align the reported device memory size to the next power-of-2 before QEMU does an mmap. Signed-off-by: Ankit Agrawal --- hw/vfio/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 4d01ea3515..bb49200458 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -2061,7 +2061,7 @@ int vfio_region_setup(Object *obj, VFIODevice *vbasedev, VFIORegion *region, region->vbasedev = vbasedev; region->flags = info->flags; -region->size = info->size; +region->size = info->size ? pow2ceil(info->size) : info->size; region->fd_offset = info->offset; region->nr = index; -- 2.17.1
[RFC v1 0/4] Expose GPU memory as coherently CPU accessible
From: Ankit Agrawal NVIDIA is building systems which allows the CPU to coherently access GPU memory. This GPU device memory can be added and managed by the kernel memory manager. The patch holds the required changes in QEMU to expose this memory to the device assigned VMs. The GPU device memory region is exposed as device BAR1 and QEMU mmaps to it. It then adds new proximity domains to represent the memory in the VM ACPI SRAT. This allows the device memory to be added as separate NUMA nodes inside the VM. The proximity domains (PXM) are passed to the VM using ACPI DSD properties to help VM kernel modules add the memory. Current Linux cannot create NUMA nodes on the fly, hence creating enough NUMA nodes in ACPI is needed so that they are available at the VM bootup time. The physical platform firwmare provides 8 NUMA nodes, which QEMU is emulating here. A new vfio-pci variant driver is added to manage the device memory and report as a BAR. Ongoing review of the corresponding kernel side changes along with the new vfio-pci variant driver. Ref: https://lore.kernel.org/lkml/20230405180134.16932-1-ank...@nvidia.com/ Applied over v8.0.2. Ankit Agrawal (4): qemu: add GPU memory information as object qemu: patch guest SRAT for GPU memory qemu: patch guest DSDT for GPU memory qemu: adjust queried bar size to power-of-2 hw/arm/virt-acpi-build.c| 54 hw/pci-host/gpex-acpi.c | 71 hw/vfio/common.c| 2 +- hw/vfio/pci-quirks.c| 13 +++ hw/vfio/pci.c | 72 + hw/vfio/pci.h | 1 + include/hw/pci/pci_device.h | 3 ++ 7 files changed, 215 insertions(+), 1 deletion(-) -- 2.17.1
[RFC v1 1/4] qemu: add GPU memory information as object
From: Ankit Agrawal
The GPU memory is exposed as device BAR1 to the VM and is discovered
by QEMU through the VFIO_DEVICE_GET_REGION_INFO ioctl. QEMU performs
the mapping to it.
The GPU memory can be added in the VM as (upto 8) separate NUMA nodes.
To achieve this, QEMU inserts a series of the PXM domains in the SRAT
and communicate this range of nodes to the VM through DSD properties.
These PXM start and count are added as object properties and pushed to
the SRAT and DST builder code.
The code is activated only for a set of NVIDIA devices supporting the
feature.
Signed-off-by: Ankit Agrawal
---
hw/vfio/pci-quirks.c| 13 +++
hw/vfio/pci.c | 72 +
hw/vfio/pci.h | 1 +
include/hw/pci/pci_device.h | 3 ++
4 files changed, 89 insertions(+)
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index f0147a050a..b7334ccd1d 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1751,3 +1751,16 @@ int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp)
return 0;
}
+
+bool vfio_has_cpu_coherent_devmem(VFIOPCIDevice *vdev)
+{
+switch (vdev->device_id) {
+/* Nvidia */
+case 0x2342:
+case 0x2343:
+case 0x2345:
+return true;
+}
+
+return false;
+}
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index ec9a854361..403516ffb3 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -42,6 +42,8 @@
#include "qapi/error.h"
#include "migration/blocker.h"
#include "migration/qemu-file.h"
+#include "qapi/visitor.h"
+#include "include/hw/boards.h"
#define TYPE_VFIO_PCI_NOHOTPLUG "vfio-pci-nohotplug"
@@ -2824,6 +2826,22 @@ static void vfio_register_req_notifier(VFIOPCIDevice
*vdev)
}
}
+static void vfio_pci_get_gpu_mem_pxm_start(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+uint64_t pxm_start = (uintptr_t) opaque;
+visit_type_uint64(v, name, _start, errp);
+}
+
+static void vfio_pci_get_gpu_mem_pxm_count(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+uint64_t pxm_count = (uintptr_t) opaque;
+visit_type_uint64(v, name, _count, errp);
+}
+
static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev)
{
Error *err = NULL;
@@ -2843,6 +2861,53 @@ static void vfio_unregister_req_notifier(VFIOPCIDevice
*vdev)
vdev->req_enabled = false;
}
+static int vfio_pci_nvidia_dev_mem_probe(VFIOPCIDevice *vPciDev,
+ Error **errp)
+{
+unsigned int num_nodes;
+MemoryRegion *nv2mr = g_malloc0(sizeof(*nv2mr));
+Object *obj = NULL;
+VFIODevice *vdev = >vbasedev;
+MachineState *ms = MACHINE(qdev_get_machine());
+
+if (!vfio_has_cpu_coherent_devmem(vPciDev)) {
+return -ENODEV;
+}
+
+if (vdev->type == VFIO_DEVICE_TYPE_PCI) {
+obj = vfio_pci_get_object(vdev);
+}
+
+if (!obj) {
+return -EINVAL;
+}
+
+/*
+ * This device has memory that is coherently accessible from the CPU.
+ * The memory can be represented by upto 8 seperate memory-only
+ * NUMA nodes.
+ */
+vPciDev->pdev.has_coherent_memory = true;
+num_nodes = 8;
+
+/*
+ * To have 8 unique nodes in the VM, a series of PXM nodes are
+ * required to be added to VM's SRAT. Send the information about
+ * the starting PXM ID and the count to the ACPI builder code.
+ */
+object_property_add(OBJECT(vPciDev), "gpu_mem_pxm_start", "uint64",
+vfio_pci_get_gpu_mem_pxm_start, NULL, NULL,
+(void *) (uintptr_t) ms->numa_state->num_nodes);
+
+object_property_add(OBJECT(vPciDev), "gpu_mem_pxm_count", "uint64",
+vfio_pci_get_gpu_mem_pxm_count, NULL, NULL,
+(void *) (uintptr_t) num_nodes);
+
+ms->numa_state->num_nodes += num_nodes;
+
+return 0;
+}
+
static void vfio_realize(PCIDevice *pdev, Error **errp)
{
VFIOPCIDevice *vdev = VFIO_PCI(pdev);
@@ -3151,6 +3216,13 @@ static void vfio_realize(PCIDevice *pdev, Error **errp)
}
}
+if (vdev->vendor_id == PCI_VENDOR_ID_NVIDIA) {
+ret = vfio_pci_nvidia_dev_mem_probe(vdev, errp);
+if (ret && ret != -ENODEV) {
+error_report("Failed to setup NVIDIA dev_mem with error %d", ret);
+}
+}
+
vfio_register_err_notifier(vdev);
vfio_register_req_notifier(vdev);
vfio_setup_resetfn_quirk(vdev);
diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h
index 177abcc8fb..d8791f8f1f 100644
--- a/hw/vfio/pci.h
+++ b/hw/vfio/pci.h
@@ -226,4 +226,5 @@ void vfio_display_reset(VFIOPCIDevice *vdev);
int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
void vfio_display_finalize(VFIOPCIDevice *vdev);
+bool vfio_has_cpu_coherent_devmem(VFIOPCIDevice *vdev);
Re: [PATCH v3] target/riscv: Smepmp: Return error when access permission not allowed in PMP
On 2023/6/6 00:45, Himanshu Chauhan wrote:
On an address match, skip checking for default permissions and return error
based on access defined in PMP configuration.
v3 Changes:
o Removed explicit return of boolean value from comparision
of priv/allowed_priv
v2 Changes:
o Removed goto to return in place when address matches
o Call pmp_hart_has_privs_default at the end of the loop
Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when address
matches")
Signed-off-by: Himanshu Chauhan
---
Reviewed-by: Weiwei Li
Weiwei Li
target/riscv/pmp.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 418738afd8..9d8db493e6 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -291,7 +291,6 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
pmp_priv_t *allowed_privs, target_ulong mode)
{
int i = 0;
-bool ret = false;
int pmp_size = 0;
target_ulong s = 0;
target_ulong e = 0;
@@ -435,17 +434,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
* defined with PMP must be used. We shouldn't fallback on
* finding default privileges.
*/
-ret = true;
-break;
+return (privs & *allowed_privs) == privs;
}
}
/* No rule matched */
-if (!ret) {
-ret = pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
-}
-
-return ret;
+return pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
}
/*
Re: [PATCH v2 5/8] hw/ide/ahci: PxCI should not get cleared when ERR_STAT is set
On Thu, Jun 1, 2023 at 9:46 AM Niklas Cassel wrote:
>
> From: Niklas Cassel
>
> For NCQ, PxCI is cleared on command queued successfully.
> For non-NCQ, PxCI is cleared on command completed successfully.
> Successfully means ERR_STAT, BUSY and DRQ are all cleared.
>
> A command that has ERR_STAT set, does not get to clear PxCI.
> See AHCI 1.3.1, section 5.3.8, states RegFIS:Entry and RegFIS:ClearCI,
> and 5.3.16.5 ERR:FatalTaskfile.
>
> In the case of non-NCQ commands, not clearing PxCI is needed in order
> for host software to be able to see which command slot that failed.
>
> Signed-off-by: Niklas Cassel
This patch causes the ahci test suite to hang. You might just need to
update the AHCI test suite.
"make check" will hang on the ahci-test as of this patch.
--js
> ---
> hw/ide/ahci.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 3deaf01add..1237f94ddc 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -1518,7 +1518,8 @@ static void ahci_clear_cmd_issue(AHCIDevice *ad,
> uint8_t slot)
> {
> IDEState *ide_state = >port.ifs[0];
>
> -if (!(ide_state->status & (BUSY_STAT | DRQ_STAT))) {
> +if (!(ide_state->status & ERR_STAT) &&
> +!(ide_state->status & (BUSY_STAT | DRQ_STAT))) {
> ad->port_regs.cmd_issue &= ~(1 << slot);
> }
> }
> @@ -1527,6 +1528,7 @@ static void ahci_clear_cmd_issue(AHCIDevice *ad,
> uint8_t slot)
> static void ahci_cmd_done(const IDEDMA *dma)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
> +IDEState *ide_state = >port.ifs[0];
>
> trace_ahci_cmd_done(ad->hba, ad->port_no);
>
> @@ -1543,7 +1545,8 @@ static void ahci_cmd_done(const IDEDMA *dma)
> */
> ahci_write_fis_d2h(ad, true);
>
> -if (ad->port_regs.cmd_issue && !ad->check_bh) {
> +if (!(ide_state->status & ERR_STAT) &&
> +ad->port_regs.cmd_issue && !ad->check_bh) {
> ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad,
> >mem_reentrancy_guard);
> qemu_bh_schedule(ad->check_bh);
> --
> 2.40.1
>
[RFC PATCH] exec/cpu-defs: Check for SOFTMMU instead of !USER_ONLY
We want to check the softmmu tlb availability, not
if we are targetting system emulation. Besides, this
code could be used by user emulation in the future.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20230605222420.14776-1-phi...@linaro.org>
See also
https://lore.kernel.org/qemu-devel/7913570a-8bf6-2ac9-6869-fab872737...@linaro.org/
---
include/exec/cpu-defs.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 0d418a0384..4cb77c8dec 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -60,7 +60,7 @@
*/
#define NB_MMU_MODES 16
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
#include "exec/tlb-common.h"
/* use a fully associative victim tlb of 8 entries */
@@ -89,9 +89,9 @@
# endif
# endif
-#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
-#if !defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_SOFTMMU)
/*
* The full TLB entry, which is not accessed by generated TCG code,
* so the layout is not as critical as that of CPUTLBEntry. This is
@@ -133,9 +133,9 @@ typedef struct CPUTLBEntryFull {
TARGET_PAGE_ENTRY_EXTRA
#endif
} CPUTLBEntryFull;
-#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_SOFTMMU */
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
/*
* Data elements that are per MMU mode, minus the bits accessed by
* the TCG fast path.
@@ -201,7 +201,7 @@ typedef struct CPUTLB {
typedef struct CPUTLB { } CPUTLB;
-#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
/*
* This structure must be placed in ArchCPU immediately
--
2.38.1
Re: [PATCH v4 2/2] hw/vfio: Add number of dirty pages to vfio_get_dirty_bitmap tracepoint
On Tue, 30 May 2023 19:05:56 +0100
Joao Martins wrote:
> Include the number of dirty pages on the vfio_get_dirty_bitmap tracepoint.
> These are fetched from the newly added return value in
> cpu_physical_memory_set_dirty_lebitmap().
>
> Signed-off-by: Joao Martins
> Reviewed-by: Cédric Le Goater
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/vfio/common.c | 7 ---
> hw/vfio/trace-events | 2 +-
> 2 files changed, 5 insertions(+), 4 deletions(-)
Acked-by: Alex Williamson
> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
> index 78358ede2764..fa8fd949b1cf 100644
> --- a/hw/vfio/common.c
> +++ b/hw/vfio/common.c
> @@ -1747,6 +1747,7 @@ static int vfio_get_dirty_bitmap(VFIOContainer
> *container, uint64_t iova,
> {
> bool all_device_dirty_tracking =
> vfio_devices_all_device_dirty_tracking(container);
> +uint64_t dirty_pages;
> VFIOBitmap vbmap;
> int ret;
>
> @@ -1772,11 +1773,11 @@ static int vfio_get_dirty_bitmap(VFIOContainer
> *container, uint64_t iova,
> goto out;
> }
>
> -cpu_physical_memory_set_dirty_lebitmap(vbmap.bitmap, ram_addr,
> - vbmap.pages);
> +dirty_pages = cpu_physical_memory_set_dirty_lebitmap(vbmap.bitmap,
> ram_addr,
> + vbmap.pages);
>
> trace_vfio_get_dirty_bitmap(container->fd, iova, size, vbmap.size,
> -ram_addr);
> +ram_addr, dirty_pages);
> out:
> g_free(vbmap.bitmap);
>
> diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
> index 646e42fd27f9..cfb60c354de3 100644
> --- a/hw/vfio/trace-events
> +++ b/hw/vfio/trace-events
> @@ -120,7 +120,7 @@ vfio_region_sparse_mmap_header(const char *name, int
> index, int nr_areas) "Devic
> vfio_region_sparse_mmap_entry(int i, unsigned long start, unsigned long end)
> "sparse entry %d [0x%lx - 0x%lx]"
> vfio_get_dev_region(const char *name, int index, uint32_t type, uint32_t
> subtype) "%s index %d, %08x/%08x"
> vfio_dma_unmap_overflow_workaround(void) ""
> -vfio_get_dirty_bitmap(int fd, uint64_t iova, uint64_t size, uint64_t
> bitmap_size, uint64_t start) "container fd=%d, iova=0x%"PRIx64" size=
> 0x%"PRIx64" bitmap_size=0x%"PRIx64" start=0x%"PRIx64
> +vfio_get_dirty_bitmap(int fd, uint64_t iova, uint64_t size, uint64_t
> bitmap_size, uint64_t start, uint64_t dirty_pages) "container fd=%d,
> iova=0x%"PRIx64" size= 0x%"PRIx64" bitmap_size=0x%"PRIx64" start=0x%"PRIx64"
> dirty_pages=%"PRIu64
> vfio_iommu_map_dirty_notify(uint64_t iova_start, uint64_t iova_end) "iommu
> dirty @ 0x%"PRIx64" - 0x%"PRIx64
>
> # platform.c
Re: [PATCH] util/cacheflush: Avoid flushing dcache twice when not necessary
On 5/6/23 23:56, BALATON Zoltan wrote:
On Mon, 5 Jun 2023, Philippe Mathieu-Daudé wrote:
describes sys_icache_invalidate() as
"equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)",
having kCacheFunctionPrepareForExecution defined as:
/* Prepare memory for execution. This should be called
* after writing machine instructions to memory, before
* executing them. It syncs the dcache and icache. [...]
*/
Since the dcache is also sync'd, we can avoid the sys_dcache_flush()
call when both rx/rw pointers are equal.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20230605175647.88395-2-phi...@linaro.org>
---
util/cacheflush.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/util/cacheflush.c b/util/cacheflush.c
index de35616718..a08906155a 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -241,7 +241,14 @@ static void __attribute__((constructor))
init_cache_info(void)
void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
{
- sys_dcache_flush((void *)rw, len);
+ if (rx == rw) {
Isn't it more straight forward to use rx != rw and drop the else branch
than having an empty if branch? You can still keep the comment above the
if to explain it if needed.
I tried that first but found it was not obvious, so chose this
form because it seemed clearer to me.
Re: [RFC PATCH v2 0/9] bulk: Replace CONFIG_SOFTMMU by !CONFIG_USER_ONLY/CONFIG_SYSTEM_ONLY
On 6/6/23 00:24, Philippe Mathieu-Daudé wrote: Richard clarified my confusion with CONFIG_SOFTMMU from v1: https://lore.kernel.org/qemu-devel/7913570a-8bf6-2ac9-6869-fab872737...@linaro.org/ This series tries to make it a bit more explicit by removing mentions of CONFIG_SOFTMMU in non-TCG code. We replace CONFIG_SOFTMMU by !CONFIG_USER_ONLY in C code and by CONFIG_SYSTEM_ONLY in meson config files. Now we could poison CONFIG_SOFTMMU on non-TCG files (to force the use of CONFIG_USER_ONLY), as the definition is only used here: - accel/tcg/ - include/tcg/tcg.h - plugins/api.c - tcg/
[RFC PATCH v2 0/9] bulk: Replace CONFIG_SOFTMMU by !CONFIG_USER_ONLY/CONFIG_SYSTEM_ONLY
Richard clarified my confusion with CONFIG_SOFTMMU from v1: https://lore.kernel.org/qemu-devel/7913570a-8bf6-2ac9-6869-fab872737...@linaro.org/ This series tries to make it a bit more explicit by removing mentions of CONFIG_SOFTMMU in non-TCG code. We replace CONFIG_SOFTMMU by !CONFIG_USER_ONLY in C code and by CONFIG_SYSTEM_ONLY in meson config files. Philippe Mathieu-Daudé (9): target/tricore: Remove pointless CONFIG_SOFTMMU guard target/i386: Check for USER_ONLY definition instead of SOFTMMU one target/m68k: Check for USER_ONLY definition instead of SOFTMMU one target/ppc: Check for USER_ONLY definition instead of SOFTMMU one hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU one accel/tcg: Check for USER_ONLY definition instead of SOFTMMU one meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY meson: Replace softmmu_ss -> system_ss docs/devel/build-system.rst| 14 +-- meson.build| 15 +-- accel/tcg/internal.h | 6 +- include/hw/core/cpu.h | 4 +- include/hw/core/tcg-cpu-ops.h | 102 ++--- target/m68k/helper.h | 2 +- accel/tcg/cpu-exec.c | 4 +- target/i386/tcg/translate.c| 2 +- target/m68k/cpu.c | 14 ++- target/m68k/helper.c | 4 +- target/m68k/translate.c| 28 +++--- target/ppc/cpu_init.c | 20 ++-- target/ppc/helper_regs.c | 6 +- target/tricore/helper.c| 2 - accel/meson.build | 4 +- accel/qtest/meson.build| 2 +- accel/stubs/meson.build| 2 +- accel/tcg/meson.build | 6 +- audio/meson.build | 8 +- backends/meson.build | 20 ++-- backends/tpm/meson.build | 8 +- block/meson.build | 6 +- block/monitor/meson.build | 2 +- chardev/meson.build| 2 +- disas/meson.build | 2 +- dump/meson.build | 4 +- ebpf/meson.build | 2 +- fsdev/meson.build | 4 +- gdbstub/meson.build| 10 +- hw/9pfs/meson.build| 2 +- hw/acpi/meson.build| 10 +- hw/adc/meson.build | 10 +- hw/arm/meson.build | 8 +- hw/audio/meson.build | 28 +++--- hw/block/meson.build | 28 +++--- hw/char/meson.build| 70 +++--- hw/core/meson.build| 22 ++--- hw/cpu/meson.build | 6 +- hw/cxl/meson.build | 4 +- hw/display/meson.build | 76 +++ hw/dma/meson.build | 32 +++ hw/gpio/meson.build| 26 +++--- hw/i2c/meson.build | 2 +- hw/i386/kvm/meson.build| 2 +- hw/ide/meson.build | 28 +++--- hw/input/meson.build | 32 +++ hw/intc/meson.build| 44 - hw/ipack/meson.build | 2 +- hw/ipmi/meson.build| 2 +- hw/isa/meson.build | 18 ++-- hw/mem/meson.build | 8 +- hw/misc/macio/meson.build | 2 +- hw/misc/meson.build| 142 ++--- hw/net/can/meson.build | 14 +-- hw/net/meson.build | 96 +-- hw/nubus/meson.build | 2 +- hw/nvme/meson.build| 2 +- hw/nvram/meson.build | 26 +++--- hw/pci-bridge/meson.build | 4 +- hw/pci-host/meson.build| 2 +- hw/pci/meson.build | 8 +- hw/pcmcia/meson.build | 4 +- hw/rdma/meson.build| 2 +- hw/remote/meson.build | 2 +- hw/rtc/meson.build | 28 +++--- hw/scsi/meson.build| 2 +- hw/sd/meson.build | 24 ++--- hw/sensor/meson.build | 18 ++-- hw/smbios/meson.build | 6 +- hw/ssi/meson.build | 26 +++--- hw/timer/meson.build | 74 +++ hw/tpm/meson.build | 14 +-- hw/usb/meson.build | 74 +++ hw/virtio/meson.build | 12 +-- hw/watchdog/meson.build| 18 ++-- hw/xen/meson.build | 4 +- migration/meson.build | 12 +-- monitor/meson.build| 6 +- net/can/meson.build| 2 +- net/meson.build| 38 qapi/meson.build | 2 +- qom/meson.build| 2 +- replay/meson.build | 2 +- semihosting/meson.build| 2 +- softmmu/meson.build| 12 +-- stats/meson.build | 2 +-
[RFC PATCH v2 1/9] target/tricore: Remove pointless CONFIG_SOFTMMU guard
We don't build any user emulation target for Tricore,
only the system emulation. No need to check for it as
it is always defined.
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 114685cce4..cd34b34133 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -30,7 +30,6 @@ enum {
TLBRET_MATCH = 0
};
-#if defined(CONFIG_SOFTMMU)
static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
@@ -56,7 +55,6 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
}
return phys_addr;
}
-#endif
/* TODO: Add exeption support*/
static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
--
2.38.1
[RFC PATCH v2 3/9] target/m68k: Check for USER_ONLY definition instead of SOFTMMU one
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Invert some if() ladders for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/helper.h| 2 +-
target/m68k/cpu.c | 14 ++
target/m68k/helper.c| 4 ++--
target/m68k/translate.c | 28 ++--
4 files changed, 23 insertions(+), 25 deletions(-)
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index c9bed2b884..2bbe0dc032 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -124,7 +124,7 @@ DEF_HELPER_FLAGS_4(bfffo_mem, TCG_CALL_NO_WG, i64, env,
i32, s32, i32)
DEF_HELPER_3(chk, void, env, s32, s32)
DEF_HELPER_4(chk2, void, env, s32, s32, s32)
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_3(ptest, void, env, i32, i32)
DEF_HELPER_3(pflush, void, env, i32, i32)
DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 99af1ab541..70d58471dc 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -80,10 +80,10 @@ static void m68k_cpu_reset_hold(Object *obj)
}
memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
-#ifdef CONFIG_SOFTMMU
-cpu_m68k_set_sr(env, SR_S | SR_I);
-#else
+#ifdef CONFIG_USER_ONLY
cpu_m68k_set_sr(env, 0);
+#else
+cpu_m68k_set_sr(env, SR_S | SR_I);
#endif
for (i = 0; i < 8; i++) {
env->fregs[i].d = nan;
@@ -334,7 +334,7 @@ static void m68k_cpu_initfn(Object *obj)
cpu_set_cpustate_pointers(cpu);
}
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
static bool fpu_needed(void *opaque)
{
M68kCPU *s = opaque;
@@ -525,15 +525,13 @@ static const VMStateDescription vmstate_m68k_cpu = {
NULL
},
};
-#endif
-#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps m68k_sysemu_ops = {
.get_phys_page_debug = m68k_cpu_get_phys_page_debug,
};
-#endif
+#endif /* !CONFIG_USER_ONLY */
#include "hw/core/tcg-cpu-ops.h"
@@ -568,7 +566,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->get_pc = m68k_cpu_get_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
dc->vmsd = _m68k_cpu;
cc->sysemu_ops = _sysemu_ops;
#endif
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 3b3a6ea8bd..01c18a7c59 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -1480,7 +1480,7 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t
val, uint32_t acc)
env->macc[acc + 1] = res;
}
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
{
hwaddr physical;
@@ -1534,4 +1534,4 @@ void HELPER(reset)(CPUM68KState *env)
{
/* FIXME: reset all except CPU */
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 551ef9e52a..e07161d76f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2637,10 +2637,10 @@ DISAS_INSN(swap)
DISAS_INSN(bkpt)
{
-#if defined(CONFIG_SOFTMMU)
-gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
-#else
+#if defined(CONFIG_USER_ONLY)
gen_exception(s, s->base.pc_next, EXCP_DEBUG);
+#else
+gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
#endif
}
@@ -2838,7 +2838,7 @@ DISAS_INSN(unlk)
tcg_gen_addi_i32(QREG_SP, src, 4);
}
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
DISAS_INSN(reset)
{
if (IS_USER(s)) {
@@ -4398,7 +4398,7 @@ DISAS_INSN(move_from_sr)
DEST_EA(env, insn, OS_WORD, sr, NULL);
}
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
DISAS_INSN(moves)
{
int opsize;
@@ -4605,7 +4605,7 @@ DISAS_INSN(cinv)
/* Invalidate cache line. Implement as no-op. */
}
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
DISAS_INSN(pflush)
{
TCGv opmode;
@@ -5352,7 +5352,7 @@ DISAS_INSN(ftrapcc)
do_trapcc(s, );
}
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
DISAS_INSN(frestore)
{
TCGv addr;
@@ -5795,7 +5795,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(bitop_im, 08c0, ffc0);
INSN(arith_im, 0a80, fff8, CF_ISA_A);
INSN(arith_im, 0a00, ff00, M68K);
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
INSN(moves, 0e00, ff00, M68K);
#endif
INSN(cas, 0ac0, ffc0, CAS);
@@ -5824,7 +5824,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(move_to_ccr, 44c0, ffc0);
INSN(not, 4680, fff8, CF_ISA_A);
INSN(not, 4600, ff00, M68K);
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
BASE(move_to_sr, 46c0, ffc0);
#endif
INSN(nbcd, 4800, ffc0, M68K);
@@ -5841,7 +5841,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(tst, 4a00, ff00);
[RFC PATCH v2 6/9] accel/tcg: Check for USER_ONLY definition instead of SOFTMMU one
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Invert some if() ladders for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal.h | 6 +++---
accel/tcg/cpu-exec.c | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
index 24f225cac7..65380ccb42 100644
--- a/accel/tcg/internal.h
+++ b/accel/tcg/internal.h
@@ -17,10 +17,10 @@
* memory related structures are protected with mmap_lock.
* In !user-mode we use per-page locks.
*/
-#ifdef CONFIG_SOFTMMU
-#define assert_memory_lock()
-#else
+#ifdef CONFIG_USER_ONLY
#define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
+#else
+#define assert_memory_lock()
#endif
#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 1cf4f1fa22..cf07e6740f 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -563,7 +563,7 @@ void cpu_exec_step_atomic(CPUState *cpu)
cpu_tb_exec(cpu, tb, _exit);
cpu_exec_exit(cpu);
} else {
-#ifndef CONFIG_SOFTMMU
+#ifdef CONFIG_USER_ONLY
clear_helper_retaddr();
if (have_mmap_lock()) {
mmap_unlock();
@@ -1020,7 +1020,7 @@ static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc)
/* Non-buggy compilers preserve this; assert the correct value. */
g_assert(cpu == current_cpu);
-#ifndef CONFIG_SOFTMMU
+#ifdef CONFIG_USER_ONLY
clear_helper_retaddr();
if (have_mmap_lock()) {
mmap_unlock();
--
2.38.1
[RFC PATCH v2 8/9] meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY
Since we *might* have user emulation with softmmu,
use the clearer 'CONFIG_SYSTEM_ONLY' key to check
for system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build| 4 ++--
accel/qtest/meson.build| 2 +-
accel/stubs/meson.build| 2 +-
accel/tcg/meson.build | 6 +++---
dump/meson.build | 2 +-
hw/i386/kvm/meson.build| 2 +-
migration/meson.build | 2 +-
monitor/meson.build| 2 +-
qapi/meson.build | 2 +-
semihosting/meson.build| 2 +-
softmmu/meson.build| 4 ++--
target/i386/tcg/sysemu/meson.build | 2 +-
ui/meson.build | 4 ++--
13 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/meson.build b/meson.build
index ce3fec7276..b1fa9ca5b9 100644
--- a/meson.build
+++ b/meson.build
@@ -3015,7 +3015,7 @@ config_all += config_host
config_all += config_all_disas
config_all += {
'CONFIG_XEN': xen.found(),
- 'CONFIG_SOFTMMU': have_system,
+ 'CONFIG_SYSTEM_ONLY': have_system,
'CONFIG_USER_ONLY': have_user,
'CONFIG_ALL': true,
}
@@ -3702,7 +3702,7 @@ endif
softmmu_ss.add(authz, blockdev, chardev, crypto, io, qmp)
common_ss.add(qom, qemuutil)
-common_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: [softmmu_ss])
+common_ss.add_all(when: 'CONFIG_SYSTEM_ONLY', if_true: [softmmu_ss])
common_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: user_ss)
common_all = common_ss.apply(config_all, strict: false)
diff --git a/accel/qtest/meson.build b/accel/qtest/meson.build
index 176d990ae1..2018de8a05 100644
--- a/accel/qtest/meson.build
+++ b/accel/qtest/meson.build
@@ -1 +1 @@
-qtest_module_ss.add(when: ['CONFIG_SOFTMMU'], if_true: files('qtest.c'))
+qtest_module_ss.add(when: ['CONFIG_SYSTEM_ONLY'], if_true: files('qtest.c'))
diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build
index 0249b9258f..f7a9486e06 100644
--- a/accel/stubs/meson.build
+++ b/accel/stubs/meson.build
@@ -4,4 +4,4 @@ sysemu_stubs_ss.add(when: 'CONFIG_XEN', if_false:
files('xen-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
-specific_ss.add_all(when: ['CONFIG_SOFTMMU'], if_true: sysemu_stubs_ss)
+specific_ss.add_all(when: ['CONFIG_SYSTEM_ONLY'], if_true: sysemu_stubs_ss)
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index aeb20a6ef0..166bef173b 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -10,18 +10,18 @@ tcg_ss.add(files(
'translator.c',
))
tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
-tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user-exec-stub.c'))
+tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c')])
tcg_ss.add(when: libdw, if_true: files('debuginfo.c'))
tcg_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c'))
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
-specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
+specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
'monitor.c',
))
-tcg_module_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
+tcg_module_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'tcg-accel-ops.c',
'tcg-accel-ops-mttcg.c',
'tcg-accel-ops-icount.c',
diff --git a/dump/meson.build b/dump/meson.build
index df52ee4268..3ef1f7ce00 100644
--- a/dump/meson.build
+++ b/dump/meson.build
@@ -1,2 +1,2 @@
softmmu_ss.add([files('dump.c', 'dump-hmp-cmds.c'), snappy, lzo])
-specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files('win_dump.c'))
+specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: files('win_dump.c'))
diff --git a/hw/i386/kvm/meson.build b/hw/i386/kvm/meson.build
index 6621ba5cd7..ab143d6474 100644
--- a/hw/i386/kvm/meson.build
+++ b/hw/i386/kvm/meson.build
@@ -19,4 +19,4 @@ xen_stubs_ss.add(when: 'CONFIG_XEN_EMU', if_false: files(
'xen-stubs.c',
))
-specific_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: xen_stubs_ss)
+specific_ss.add_all(when: 'CONFIG_SYSTEM_ONLY', if_true: xen_stubs_ss)
diff --git a/migration/meson.build b/migration/meson.build
index 8ba6e420fe..9975407cd0 100644
--- a/migration/meson.build
+++ b/migration/meson.build
@@ -40,6 +40,6 @@ if get_option('live_block_migration').allowed()
endif
softmmu_ss.add(when: zstd, if_true: files('multifd-zstd.c'))
-specific_ss.add(when: 'CONFIG_SOFTMMU',
+specific_ss.add(when: 'CONFIG_SYSTEM_ONLY',
if_true: files('ram.c',
'target.c'))
diff --git a/monitor/meson.build b/monitor/meson.build
index ccb4d1a8e6..4c0a33ae65 100644
--- a/monitor/meson.build
+++ b/monitor/meson.build
@@ -7,5 +7,5 @@ softmmu_ss.add(files(
))
softmmu_ss.add([spice_headers, files('qmp-cmds.c')])
-specific_ss.add(when:
[RFC PATCH v2 7/9] meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY
We use the CONFIG_USER_ONLY key to describe user emulation,
and the CONFIG_SOFTMMU key to describe system emulation. Alias
it as 'CONFIG_SYSTEM_ONLY' for parity with user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
index a61d3e9b06..ce3fec7276 100644
--- a/meson.build
+++ b/meson.build
@@ -2888,6 +2888,7 @@ foreach target : target_dirs
endif
config_target += { 'CONFIG_BSD_USER': 'y' }
elif target.endswith('softmmu')
+config_target += { 'CONFIG_SYSTEM_ONLY': 'y' }
config_target += { 'CONFIG_SOFTMMU': 'y' }
endif
if target.endswith('-user')
--
2.38.1
[RFC PATCH v2 4/9] target/ppc: Check for USER_ONLY definition instead of SOFTMMU one
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c| 20 ++--
target/ppc/helper_regs.c | 6 ++
2 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 05bf73296b..a1b0bb2905 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5840,7 +5840,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI);
pcc->mmu_model = POWERPC_MMU_64B;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
pcc->hash64_opts = _hash64_opts_basic;
#endif
pcc->excp_model = POWERPC_EXCP_970;
@@ -5919,7 +5919,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
LPCR_RMI | LPCR_HDICE;
pcc->mmu_model = POWERPC_MMU_2_03;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
pcc->hash64_opts = _hash64_opts_basic;
pcc->lrg_decr_bits = 32;
#endif
@@ -6036,7 +6036,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
pcc->mmu_model = POWERPC_MMU_2_06;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
pcc->hash64_opts = _hash64_opts_POWER7;
pcc->lrg_decr_bits = 32;
#endif
@@ -6180,7 +6180,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
LPCR_P8_PECE3 | LPCR_P8_PECE4;
pcc->mmu_model = POWERPC_MMU_2_07;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
pcc->hash64_opts = _hash64_opts_POWER7;
pcc->lrg_decr_bits = 32;
pcc->n_host_threads = 8;
@@ -6196,7 +6196,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
}
-#ifdef CONFIG_SOFTMMU
+#ifndef CONFIG_USER_ONLY
/*
* Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
* Encoded as array of int_32s in the form:
@@ -6213,7 +6213,7 @@ static struct ppc_radix_page_info POWER9_radix_page_info
= {
0x401e /* 1G - enc: 0x2 */
}
};
-#endif /* CONFIG_SOFTMMU */
+#endif /* CONFIG_USER_ONLY */
static void init_proc_POWER9(CPUPPCState *env)
{
@@ -6370,7 +6370,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
/* segment page size remain the same */
pcc->hash64_opts = _hash64_opts_POWER7;
pcc->radix_page_info = _radix_page_info;
@@ -6388,7 +6388,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
}
-#ifdef CONFIG_SOFTMMU
+#ifndef CONFIG_USER_ONLY
/*
* Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
* Encoded as array of int_32s in the form:
@@ -6405,7 +6405,7 @@ static struct ppc_radix_page_info POWER10_radix_page_info
= {
0x401e /* 1G - enc: 0x2 */
}
};
-#endif /* CONFIG_SOFTMMU */
+#endif /* !CONFIG_USER_ONLY */
static void init_proc_POWER10(CPUPPCState *env)
{
@@ -6546,7 +6546,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
-#if defined(CONFIG_SOFTMMU)
+#if !defined(CONFIG_USER_ONLY)
/* segment page size remain the same */
pcc->hash64_opts = _hash64_opts_POWER7;
pcc->radix_page_info = _radix_page_info;
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index fb351c303f..537e835360 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -273,7 +273,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value,
int alter_hv)
return excp;
}
-#ifdef CONFIG_SOFTMMU
+#ifndef CONFIG_USER_ONLY
void store_40x_sler(CPUPPCState *env, uint32_t val)
{
/* XXX: TO BE FIXED */
@@ -283,9 +283,7 @@ void store_40x_sler(CPUPPCState *env, uint32_t val)
}
env->spr[SPR_405_SLER] = val;
}
-#endif /* CONFIG_SOFTMMU */
-#ifndef CONFIG_USER_ONLY
void check_tlb_flush(CPUPPCState *env, bool global)
{
CPUState *cs = env_cpu(env);
@@ -304,7 +302,7 @@ void check_tlb_flush(CPUPPCState *env, bool global)
tlb_flush(cs);
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
/**
* _spr_register
--
2.38.1
[RFC PATCH v2 9/9] meson: Replace softmmu_ss -> system_ss
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/build-system.rst| 14 +-- meson.build| 12 +-- accel/meson.build | 4 +- audio/meson.build | 8 +- backends/meson.build | 20 ++-- backends/tpm/meson.build | 8 +- block/meson.build | 6 +- block/monitor/meson.build | 2 +- chardev/meson.build| 2 +- disas/meson.build | 2 +- dump/meson.build | 2 +- ebpf/meson.build | 2 +- fsdev/meson.build | 4 +- gdbstub/meson.build| 10 +- hw/9pfs/meson.build| 2 +- hw/acpi/meson.build| 10 +- hw/adc/meson.build | 10 +- hw/arm/meson.build | 8 +- hw/audio/meson.build | 28 +++--- hw/block/meson.build | 28 +++--- hw/char/meson.build| 70 +++--- hw/core/meson.build| 22 ++--- hw/cpu/meson.build | 6 +- hw/cxl/meson.build | 4 +- hw/display/meson.build | 76 +++ hw/dma/meson.build | 32 +++ hw/gpio/meson.build| 26 +++--- hw/i2c/meson.build | 2 +- hw/ide/meson.build | 28 +++--- hw/input/meson.build | 32 +++ hw/intc/meson.build| 44 - hw/ipack/meson.build | 2 +- hw/ipmi/meson.build| 2 +- hw/isa/meson.build | 18 ++-- hw/mem/meson.build | 8 +- hw/misc/macio/meson.build | 2 +- hw/misc/meson.build| 142 ++--- hw/net/can/meson.build | 14 +-- hw/net/meson.build | 96 +-- hw/nubus/meson.build | 2 +- hw/nvme/meson.build| 2 +- hw/nvram/meson.build | 26 +++--- hw/pci-bridge/meson.build | 4 +- hw/pci-host/meson.build| 2 +- hw/pci/meson.build | 8 +- hw/pcmcia/meson.build | 4 +- hw/rdma/meson.build| 2 +- hw/remote/meson.build | 2 +- hw/rtc/meson.build | 28 +++--- hw/scsi/meson.build| 2 +- hw/sd/meson.build | 24 ++--- hw/sensor/meson.build | 18 ++-- hw/smbios/meson.build | 6 +- hw/ssi/meson.build | 26 +++--- hw/timer/meson.build | 74 +++ hw/tpm/meson.build | 14 +-- hw/usb/meson.build | 74 +++ hw/virtio/meson.build | 12 +-- hw/watchdog/meson.build| 18 ++-- hw/xen/meson.build | 4 +- migration/meson.build | 10 +- monitor/meson.build| 4 +- net/can/meson.build| 2 +- net/meson.build| 38 qom/meson.build| 2 +- replay/meson.build | 2 +- softmmu/meson.build| 8 +- stats/meson.build | 2 +- target/alpha/meson.build | 6 +- target/arm/hvf/meson.build | 2 +- target/arm/meson.build | 6 +- target/arm/tcg/meson.build | 2 +- target/avr/meson.build | 6 +- target/cris/meson.build| 6 +- target/hppa/meson.build| 6 +- target/i386/hax/meson.build| 6 +- target/i386/hvf/meson.build| 2 +- target/i386/kvm/meson.build| 4 +- target/i386/meson.build| 8 +- target/i386/nvmm/meson.build | 4 +- target/i386/tcg/sysemu/meson.build | 2 +- target/i386/whpx/meson.build | 2 +- target/loongarch/meson.build | 6 +- target/m68k/meson.build| 6 +- target/microblaze/meson.build | 6 +- target/mips/meson.build| 4 +- target/mips/sysemu/meson.build | 2 +- target/mips/tcg/sysemu/meson.build | 2 +- target/nios2/meson.build | 6 +- target/openrisc/meson.build| 6 +- target/ppc/meson.build | 10 +- target/riscv/meson.build | 6 +- target/s390x/kvm/meson.build | 2 +- target/s390x/meson.build | 6 +- target/sh4/meson.build | 6 +- target/sparc/meson.build | 6 +- target/tricore/meson.build | 4 +- target/xtensa/meson.build | 6 +- tcg/meson.build| 2 +- trace/meson.build | 2
[RFC PATCH v2 5/9] hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU one
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Invert the #ifdef'ry in TCGCPUOps structure for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 4 +-
include/hw/core/tcg-cpu-ops.h | 102 +-
2 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 383456d1b3..f41b0c56f7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1014,7 +1014,7 @@ void page_size_init(void);
#ifdef NEED_CPU_H
-#ifdef CONFIG_SOFTMMU
+#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_cpu_common;
@@ -1025,7 +1025,7 @@ extern const VMStateDescription vmstate_cpu_common;
.flags = VMS_STRUCT,\
.offset = 0,\
}
-#endif /* CONFIG_SOFTMMU */
+#endif /* !CONFIG_USER_ONLY */
#endif /* NEED_CPU_H */
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 0ae08df47e..3e8b1b737a 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -64,7 +64,56 @@ struct TCGCPUOps {
*/
void (*do_interrupt)(CPUState *cpu);
#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
-#ifdef CONFIG_SOFTMMU
+#ifdef CONFIG_USER_ONLY
+/**
+ * record_sigsegv:
+ * @cpu: cpu context
+ * @addr: faulting guest address
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGSEGV with si_code set for @maperr,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide anything to the signal
+ * handler with anything besides the user context registers, and
+ * the siginfo_t, then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
+ * so that a "normal" cpu exception can be raised. In this case,
+ * the signal must be raised by the architecture cpu_loop.
+ */
+void (*record_sigsegv)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+/**
+ * record_sigbus:
+ * @cpu: cpu context
+ * @addr: misaligned guest address
+ * @access_type: access was read/write/execute
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGBUS with si_code BUS_ADRALN,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide the signal handler with
+ * anything besides the user context registers, and the siginfo_t,
+ * then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu do_unaligned_access code,
+ * @ra is provided so that a "normal" cpu exception can be raised.
+ * In this case, the signal must be raised by the architecture cpu_loop.
+ */
+void (*record_sigbus)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, uintptr_t ra);
+#else
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
/**
@@ -121,56 +170,7 @@ struct TCGCPUOps {
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
-#else
-/**
- * record_sigsegv:
- * @cpu: cpu context
- * @addr: faulting guest address
- * @access_type: access was read/write/execute
- * @maperr: true for invalid page, false for permission fault
- * @ra: host pc for unwinding
- *
- * We are about to raise SIGSEGV with si_code set for @maperr,
- * and si_addr set for @addr. Record anything further needed
- * for the signal ucontext_t.
- *
- * If the emulated kernel does not provide anything to the signal
- * handler with anything besides the user context registers, and
- * the siginfo_t, then this hook need do nothing and may be omitted.
- * Otherwise, record the data and return; the caller will raise
- * the signal, unwind the cpu state, and return to the main loop.
- *
- * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
- * so that a "normal" cpu exception can be raised. In this case,
- * the signal must be raised by the
[RFC PATCH v2 2/9] target/i386: Check for USER_ONLY definition instead of SOFTMMU one
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5cf14311a6..750253e679 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6915,7 +6915,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; -#ifdef CONFIG_SOFTMMU +#ifndef CONFIG_USER_ONLY dc->mem_index = cpu_mmu_index(env, false); #endif dc->cpuid_features = env->features[FEAT_1_EDX]; -- 2.38.1
Re: [PATCH] bitops.h: Compile out asserts without --enable-debug
On Tue, 23 May 2023, Alex Bennée wrote: Richard Henderson writes: On 5/22/23 15:26, BALATON Zoltan wrote: On Mon, 22 May 2023, Alex Bennée wrote: (ajb: add Richard for his compiler-fu) BALATON Zoltan writes: On Mon, 22 May 2023, Alex Bennée wrote: BALATON Zoltan writes: The low level extract and deposit funtions provided by bitops.h are used in performance critical places. It crept into target/ppc via FIELD_EX64 and also used by softfloat so PPC code using a lot of FPU where hardfloat is also disabled is doubly affected. Most of these asserts compile out to nothing if the compiler is able to verify the constants are in the range. For example examining the start of float64_add: I don't see any check and abort steps because all the shift and mask values are known at compile time. The softfloat compilation certainly does have some assert points though: readelf -s ./libqemu-ppc64-softmmu.fa.p/fpu_softfloat.c.o |grep assert 136: 0 NOTYPE GLOBAL DEFAULT UND g_assertion_mess[...] 138: 0 NOTYPE GLOBAL DEFAULT UND __assert_fail but the references are for the ISRA segments so its tricky to know if they get used or are just there for LTO purposes. If there are hot-paths that show up the extract/deposit functions I suspect a better approach would be to implement _nocheck variants (or maybe _noassert?) and use them where required rather than turning off the assert checking for these utility functions. Just to clarify again, the asserts are still there when compiled with --enable-debug. The patch only turns them off for optimised release builds which I think makes sense if these asserts are to catch programming errors. Well as Peter said the general policy is to keep asserts in but I appreciate this is a hotpath case. I think I've also suggested adding noassert versions of these but that wasn't a popular idea and it may also not be easy to convert all places to use that like for example the register fields related usage in target/ppc as that would also affect other places. Is code generation or device emulation really on the hot-path. Generally a well predicted assert is in the noise for those operations. They aren't in code generation but in helpers as you can also see in the profile below and so they can be on hot path. Also I've noticed that extract8 and extract16 just call extract32 after adding another assert on their own in addition to the one in extract32 which is double overhead for really no reason. I'd delete all these asserts as the likelhood of bugs these could catch is very low anyway (how often do you expect somebody to call these with out of bound values that would not be obvious from the results otherwise?) but leaving them in non-debug builds is totally useless in my opinion. So this seems to be the simplest and most effective approach. The softfloat related usage in these tests I've done seem to mostly come from unpacking and repacking floats in softfloat which is done for every operation, e.g. muladd which mp3 encoding mostly uses does 3 unpacks and 1 pack for each call and each unpack is 3 extracts so even small overheads add app quickly. Just 1 muladd will result in 9 extracts and 2 deposits at least plus updating PPC flags for each FPU op adds a bunch more. I did some profiling with perf to find these. After some messing about trying to get lame to cross compile to a static binary I was able to replicate what you've seen: 11.44% qemu-ppc64 qemu-ppc64 [.] unpack_raw64.isra.0 11.03% qemu-ppc64 qemu-ppc64 [.] parts64_uncanon_normal 8.26% qemu-ppc64 qemu-ppc64 [.] helper_compute_fprf_float64 6.75% qemu-ppc64 qemu-ppc64 [.] do_float_check_status 5.34% qemu-ppc64 qemu-ppc64 [.] parts64_muladd 4.75% qemu-ppc64 qemu-ppc64 [.] pack_raw64.isra.0 4.38% qemu-ppc64 qemu-ppc64 [.] parts64_canonicalize 3.62% qemu-ppc64 qemu-ppc64 [.] float64r32_round_pack_canonical 3.32% qemu-ppc64 qemu-ppc64 [.] helper_todouble 2.68% qemu-ppc64 qemu-ppc64 [.] float64_add 2.51% qemu-ppc64 qemu-ppc64 [.] float64_hs_compare 2.30% qemu-ppc64 qemu-ppc64 [.] float64r32_muladd 1.80% qemu-ppc64 qemu-ppc64 [.] float64r32_mul 1.40% qemu-ppc64 qemu-ppc64 [.] float64r32_add 1.34% qemu-ppc64 qemu-ppc64 [.] parts64_mul 1.16% qemu-ppc64 qemu-ppc64 [.] parts64_addsub 1.14% qemu-ppc64 qemu-ppc64 [.] helper_reset_fpstatus 1.06% qemu-ppc64 qemu-ppc64 [.] helper_float_check_status 1.04% qemu-ppc64 qemu-ppc64 [.] float64_muladd I've run 32 bit PPC version in qemu-system-ppc so the profile is a bit different (has more system related overhead that I plan to look at separately) but this part is similar to the above. I also wonder
Re: [PATCH v5 2/9] migration: Implement switchover ack logic
On Tue, 30 May 2023 17:48:14 +0300
Avihai Horon wrote:
> Implement switchover ack logic. This prevents the source from stopping
> the VM and completing the migration until an ACK is received from the
> destination that it's OK to do so.
>
> To achieve this, a new SaveVMHandlers handler switchover_ack_needed()
> and a new return path message MIG_RP_MSG_SWITCHOVER_ACK are added.
>
> The switchover_ack_needed() handler is called during migration setup in
> the destination to check if switchover ack is used by the migrated
> device.
>
> When switchover is approved by all migrated devices in the destination
> that support this capability, the MIG_RP_MSG_SWITCHOVER_ACK return path
> message is sent to the source to notify it that it's OK to do
> switchover.
>
> Signed-off-by: Avihai Horon
> Reviewed-by: Peter Xu
> ---
> include/migration/register.h | 2 ++
> migration/migration.h| 14 ++
> migration/savevm.h | 1 +
> migration/migration.c| 32 +++--
> migration/savevm.c | 54
> migration/trace-events | 3 ++
> 6 files changed, 104 insertions(+), 2 deletions(-)
>
> diff --git a/include/migration/register.h b/include/migration/register.h
> index a8dfd8fefd..90914f32f5 100644
> --- a/include/migration/register.h
> +++ b/include/migration/register.h
> @@ -71,6 +71,8 @@ typedef struct SaveVMHandlers {
> int (*load_cleanup)(void *opaque);
> /* Called when postcopy migration wants to resume from failure */
> int (*resume_prepare)(MigrationState *s, void *opaque);
> +/* Checks if switchover ack should be used. Called only in dest */
> +bool (*switchover_ack_needed)(void *opaque);
> } SaveVMHandlers;
>
> int register_savevm_live(const char *idstr,
> diff --git a/migration/migration.h b/migration/migration.h
> index 48a46123a0..1e92ba7b1d 100644
> --- a/migration/migration.h
> +++ b/migration/migration.h
> @@ -209,6 +209,13 @@ struct MigrationIncomingState {
> * contains valid information.
> */
> QemuMutex page_request_mutex;
> +
> +/*
> + * Number of devices that have yet to approve switchover. When this
> reaches
> + * zero an ACK that it's OK to do switchover is sent to the source. No
> lock
> + * is needed as this field is updated serially.
> + */
> +unsigned int switchover_ack_pending_num;
> };
>
> MigrationIncomingState *migration_incoming_get_current(void);
> @@ -437,6 +444,12 @@ struct MigrationState {
>
> /* QEMU_VM_VMDESCRIPTION content filled for all non-iterable devices. */
> JSONWriter *vmdesc;
> +
> +/*
> + * Indicates whether an ACK from the destination that it's OK to do
> + * switchover has been received.
> + */
> +bool switchover_acked;
> };
>
> void migrate_set_state(int *state, int old_state, int new_state);
> @@ -477,6 +490,7 @@ int
> migrate_send_rp_message_req_pages(MigrationIncomingState *mis,
> void migrate_send_rp_recv_bitmap(MigrationIncomingState *mis,
> char *block_name);
> void migrate_send_rp_resume_ack(MigrationIncomingState *mis, uint32_t value);
> +int migrate_send_rp_switchover_ack(MigrationIncomingState *mis);
>
> void dirty_bitmap_mig_before_vm_start(void);
> void dirty_bitmap_mig_cancel_outgoing(void);
> diff --git a/migration/savevm.h b/migration/savevm.h
> index fb636735f0..e894bbc143 100644
> --- a/migration/savevm.h
> +++ b/migration/savevm.h
> @@ -65,6 +65,7 @@ int qemu_loadvm_state(QEMUFile *f);
> void qemu_loadvm_state_cleanup(void);
> int qemu_loadvm_state_main(QEMUFile *f, MigrationIncomingState *mis);
> int qemu_load_device_state(QEMUFile *f);
> +int qemu_loadvm_approve_switchover(void);
> int qemu_savevm_state_complete_precopy_non_iterable(QEMUFile *f,
> bool in_postcopy, bool inactivate_disks);
>
> diff --git a/migration/migration.c b/migration/migration.c
> index 5de7f734b9..c73261118c 100644
> --- a/migration/migration.c
> +++ b/migration/migration.c
> @@ -78,6 +78,7 @@ enum mig_rp_message_type {
> MIG_RP_MSG_REQ_PAGES,/* data (start: be64, len: be32) */
> MIG_RP_MSG_RECV_BITMAP, /* send recved_bitmap back to source */
> MIG_RP_MSG_RESUME_ACK, /* tell source that we are ready to resume */
> +MIG_RP_MSG_SWITCHOVER_ACK, /* Tell source it's OK to do switchover */
>
> MIG_RP_MSG_MAX
> };
> @@ -760,6 +761,11 @@ bool migration_has_all_channels(void)
> return true;
> }
>
> +int migrate_send_rp_switchover_ack(MigrationIncomingState *mis)
> +{
> +return migrate_send_rp_message(mis, MIG_RP_MSG_SWITCHOVER_ACK, 0, NULL);
> +}
> +
> /*
> * Send a 'SHUT' message on the return channel with the given value
> * to indicate that we've finished with the RP. Non-0 value indicates
> @@ -1405,6 +1411,7 @@ void migrate_init(MigrationState *s)
> s->vm_was_running = false;
> s->iteration_initial_bytes = 0;
> s->threshold_size = 0;
> +
Re: [PATCH] hw/acpi: Fix PM control register access
n Sun, 28 May 2023, BALATON Zoltan wrote:
On pegasos2 which has ACPI as part of VT8231 south bridge the board
firmware writes PM control register by accessing the second byte so
addr will be 1. This wasn't handled correctly and the write went to
addr 0 instead. This fixes ACPI shutdown with pegasos2 firmware.
Signed-off-by: BALATON Zoltan
---
This is replacing the previous attempt which changed enduanness to
NATIVE_ENDIAN that was found to be wrong. I'm still not sure what's
happening as these functions are called with addr = 1 and size = 2 but
maybe the guest really does word access to addr 1 when wanting to
write 1 byte. This fixes the problem and should not break anything
else but please review.
Ping?
Regards,
BALATON Zoltan
hw/acpi/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/core.c b/hw/acpi/core.c
index 6da275c599..bbc599a252 100644
--- a/hw/acpi/core.c
+++ b/hw/acpi/core.c
@@ -593,13 +593,13 @@ void acpi_pm1_cnt_update(ACPIREGS *ar,
static uint64_t acpi_pm_cnt_read(void *opaque, hwaddr addr, unsigned width)
{
ACPIREGS *ar = opaque;
-return ar->pm1.cnt.cnt;
+return ar->pm1.cnt.cnt >> addr * 8;
}
static void acpi_pm_cnt_write(void *opaque, hwaddr addr, uint64_t val,
unsigned width)
{
-acpi_pm1_cnt_write(opaque, val);
+acpi_pm1_cnt_write(opaque, val << addr * 8);
}
static const MemoryRegionOps acpi_pm_cnt_ops = {
Re: [PATCH] util/cacheflush: Avoid flushing dcache twice when not necessary
On Mon, 5 Jun 2023, Philippe Mathieu-Daudé wrote:
describes sys_icache_invalidate() as
"equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)",
having kCacheFunctionPrepareForExecution defined as:
/* Prepare memory for execution. This should be called
* after writing machine instructions to memory, before
* executing them. It syncs the dcache and icache. [...]
*/
Since the dcache is also sync'd, we can avoid the sys_dcache_flush()
call when both rx/rw pointers are equal.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20230605175647.88395-2-phi...@linaro.org>
---
util/cacheflush.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/util/cacheflush.c b/util/cacheflush.c
index de35616718..a08906155a 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -241,7 +241,14 @@ static void __attribute__((constructor))
init_cache_info(void)
void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
{
-sys_dcache_flush((void *)rw, len);
+if (rx == rw) {
Isn't it more straight forward to use rx != rw and drop the else branch
than having an empty if branch? You can still keep the comment above the
if to explain it if needed.
Regards,
BALATON Zoltan
+/*
+ * sys_icache_invalidate() syncs the dcache and icache,
+ * so no need to call sys_dcache_flush().
+ */
+} else {
+sys_dcache_flush((void *)rw, len);
+}
sys_icache_invalidate((void *)rx, len);
}
#else
[PATCH] mv64361: Add dummy gigabit ethernet PHY access registers
We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some valid looking result otherwise it hangs. Add some minimal dummy implementation to avoid rhis. Signed-off-by: BALATON Zoltan --- This is only used by MorphOS on pegasos2 so most likely could go via the ppc queue. hw/pci-host/mv64361.c | 6 ++ hw/pci-host/mv643xx.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 19e8031a3f..01bd8c887f 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size) } } break; +case MV64340_ETH_PHY_ADDR: +ret = 0x98; +break; +case MV64340_ETH_SMI: +ret = BIT(27); +break; case MV64340_CUNIT_ARBITER_CONTROL_REG: ret = 0x11ff | (s->gpp_int_level << 10); break; diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h index cd26a43f18..f2e1baea88 100644 --- a/hw/pci-host/mv643xx.h +++ b/hw/pci-host/mv643xx.h @@ -656,6 +656,9 @@ /*Ethernet Unit Registers */ // +#define MV64340_ETH_PHY_ADDR0x2000 +#define MV64340_ETH_SMI 0x2004 + /***/ /* CUNIT Registers */ /***/ -- 2.30.9
[PATCH v4 1/3] hw/i386/pc: Refactor logic to set SMBIOS set defaults
In preparation for subsequent code to upgrade default SMBIOS
entry point type. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
hw/i386/pc.c | 12
hw/i386/pc_piix.c | 9 -
hw/i386/pc_q35.c | 8
3 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index bb62c994fa..8fc34f5454 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -781,6 +781,18 @@ void pc_machine_done(Notifier *notifier, void *data)
acpi_setup();
if (x86ms->fw_cfg) {
+PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+
+if (pcmc->smbios_defaults) {
+MachineClass *mc = MACHINE_GET_CLASS(pcms);
+
+/* These values are guest ABI, do not change */
+smbios_set_defaults("QEMU", mc->desc,
+mc->name, pcmc->smbios_legacy_mode,
+pcmc->smbios_uuid_encoded,
+pcms->smbios_entry_point_type);
+}
+
fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
/* update FW_CFG_NB_CPUS to account for -device added CPUs */
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index d5b0dcd1fe..da6ba4eeb4 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -198,15 +198,6 @@ static void pc_init1(MachineState *machine,
pc_guest_info_init(pcms);
-if (pcmc->smbios_defaults) {
-MachineClass *mc = MACHINE_GET_CLASS(machine);
-/* These values are guest ABI, do not change */
-smbios_set_defaults("QEMU", mc->desc,
-mc->name, pcmc->smbios_legacy_mode,
-pcmc->smbios_uuid_encoded,
-pcms->smbios_entry_point_type);
-}
-
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(pcms, system_memory, rom_memory, hole64_size);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 6155427e48..a58cd1d3ea 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -198,14 +198,6 @@ static void pc_q35_init(MachineState *machine)
pc_guest_info_init(pcms);
-if (pcmc->smbios_defaults) {
-/* These values are guest ABI, do not change */
-smbios_set_defaults("QEMU", mc->desc,
-mc->name, pcmc->smbios_legacy_mode,
-pcmc->smbios_uuid_encoded,
-pcms->smbios_entry_point_type);
-}
-
/* create pci host bus */
q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
--
2.34.1
[PATCH v4 0/3] hw/i386/pc: Update max_cpus and default to SMBIOS
In order to support large number of vcpus, a newer 64-bit SMBIOS entry point type is needed. Therefore, upgrade the default SMBIOS version for PC machines to SMBIOS 3.0 for newer systems. Then increase the maximum number of vCPUs for Q35 models to 1024, which is the limit for KVM. Changes from V3: (https://lore.kernel.org/qemu-devel/20230603032255.517970-1-suravee.suthikulpa...@amd.com/T/#t ) * Patch 1: Refactor the code to setup SMBIOS defaults to pc_machine_done(). * Patch 2: Minor typo fixes in comment. Changes from V2: (https://lore.kernel.org/qemu-devel/20230531225127.331998-1-suravee.suthikulpa...@amd.com/) * Add patch 1. Changes from V1: (https://lore.kernel.org/all/ynkdgsii1vfvx...@redhat.com/T/) * Bump from 512 to KVM_MAX_VCPUS (per Igor's suggestion) Thank you, Suravee Suravee Suthikulpanit (3): hw/i386/pc: Refactor logic to set SMBIOS set defaults hw/i386/pc: Default to use SMBIOS 3.0 for newer machine models pc: q35: Bump max_cpus to 1024 hw/i386/pc.c | 26 +- hw/i386/pc_piix.c| 14 +- hw/i386/pc_q35.c | 15 ++- include/hw/i386/pc.h | 2 ++ 4 files changed, 38 insertions(+), 19 deletions(-) -- 2.34.1
Re: [PATCH v3 1/2] hw/i386/pc: Default to use SMBIOS 3.0 for newer machine models
Michael,
On 6/4/2023 7:55 PM, Michael S. Tsirkin wrote:
On Fri, Jun 02, 2023 at 10:22:54PM -0500, Suravee Suthikulpanit wrote:
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -199,6 +199,14 @@ static void pc_q35_init(MachineState *machine)
pc_guest_info_init(pcms);
if (pcmc->smbios_defaults) {
+/*
+ * Check if user has specified command line option to override
+ * the default SMBIOS default entry point type.
+ */
+if (!pcms->smbios_use_cmdline_ep_type) {
+pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
+}
+
/* These values are guest ABI, do not change */
smbios_set_defaults("QEMU", mc->desc,
mc->name, pcmc->smbios_legacy_mode,
@@ -359,6 +367,7 @@ static void pc_q35_machine_options(MachineClass *m)
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pcmc->pci_root_uid = 0;
pcmc->default_cpu_version = 1;
+pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
m->family = "pc_q35";
m->desc = "Standard PC (Q35 + ICH9, 2009)";
@@ -387,10 +396,15 @@ DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL,
static void pc_q35_8_0_machine_options(MachineClass *m)
{
+PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+
pc_q35_8_1_machine_options(m);
m->alias = NULL;
compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
+
+/* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */
+pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
}
DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c661e9cc80..f754da5a38 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -50,6 +50,7 @@ typedef struct PCMachineState {
bool i8042_enabled;
bool default_bus_bypass_iommu;
uint64_t max_fw_size;
+bool smbios_use_cmdline_ep_type;
/* ACPI Memory hotplug IO base address */
hwaddr memhp_io_base;
@@ -110,6 +111,7 @@ struct PCMachineClass {
bool smbios_defaults;
bool smbios_legacy_mode;
bool smbios_uuid_encoded;
+SmbiosEntryPointType default_smbios_ep_type;
/* RAM / address space compat: */
bool gigabyte_align;
Can't we avoid this code duplication?
E.g. can't we use the pc_compat_8_0 machinery?
I think we can. I have just submitted v4 with some code refactoring to
avoid duplication when set up SMBIOS defaults.
Thanks,
Suravee
[PATCH v4 2/3] hw/i386/pc: Default to use SMBIOS 3.0 for newer machine models
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
models. This is necessary to avoid the following message when launching
a VM with large number of vcpus.
"SMBIOS 2.1 table length 66822 exceeds 65535"
Note that user can still override the entry point tyme w/ QEMU option
"-M ..., smbios-entry-point-type=[32|64].
Signed-off-by: Suravee Suthikulpanit
---
hw/i386/pc.c | 14 +-
hw/i386/pc_piix.c| 5 +
hw/i386/pc_q35.c | 5 +
include/hw/i386/pc.h | 2 ++
4 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 8fc34f5454..5a87b82185 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -786,6 +786,14 @@ void pc_machine_done(Notifier *notifier, void *data)
if (pcmc->smbios_defaults) {
MachineClass *mc = MACHINE_GET_CLASS(pcms);
+/*
+ * Check if user has specified a command line option
+ * to override the SMBIOS default entry point type.
+ */
+if (!pcms->smbios_use_cmdline_ep_type) {
+pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
+}
+
/* These values are guest ABI, do not change */
smbios_set_defaults("QEMU", mc->desc,
mc->name, pcmc->smbios_legacy_mode,
@@ -1782,7 +1790,10 @@ static void pc_machine_set_smbios_ep(Object *obj,
Visitor *v, const char *name,
{
PCMachineState *pcms = PC_MACHINE(obj);
-visit_type_SmbiosEntryPointType(v, name, >smbios_entry_point_type,
errp);
+pcms->smbios_use_cmdline_ep_type =
+visit_type_SmbiosEntryPointType(v, name,
+>smbios_entry_point_type,
+errp);
}
static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
@@ -1992,6 +2003,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
*data)
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
mc->default_ram_id = "pc.ram";
+pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index da6ba4eeb4..1a2bb25c75 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -467,11 +467,16 @@ DEFINE_I440FX_MACHINE(v8_1, "pc-i440fx-8.1", NULL,
static void pc_i440fx_8_0_machine_options(MachineClass *m)
{
+PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+
pc_i440fx_8_1_machine_options(m);
m->alias = NULL;
m->is_default = false;
compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
+
+/* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */
+pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
}
DEFINE_I440FX_MACHINE(v8_0, "pc-i440fx-8.0", NULL,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index a58cd1d3ea..371cca7484 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -379,10 +379,15 @@ DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL,
static void pc_q35_8_0_machine_options(MachineClass *m)
{
+PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+
pc_q35_8_1_machine_options(m);
m->alias = NULL;
compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
+
+/* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */
+pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
}
DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c661e9cc80..f754da5a38 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -50,6 +50,7 @@ typedef struct PCMachineState {
bool i8042_enabled;
bool default_bus_bypass_iommu;
uint64_t max_fw_size;
+bool smbios_use_cmdline_ep_type;
/* ACPI Memory hotplug IO base address */
hwaddr memhp_io_base;
@@ -110,6 +111,7 @@ struct PCMachineClass {
bool smbios_defaults;
bool smbios_legacy_mode;
bool smbios_uuid_encoded;
+SmbiosEntryPointType default_smbios_ep_type;
/* RAM / address space compat: */
bool gigabyte_align;
--
2.34.1
[PATCH v4 3/3] pc: q35: Bump max_cpus to 1024
Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number. In case KVM could not support the specified number of vcpus, QEMU would return the following error message: qemu-system-x86_64: kvm_init_vcpu: kvm_get_vcpu failed (xxx): Invalid argument Cc: Igor Mammedov Cc: Daniel P. Berrangé Cc: Michael S. Tsirkin Cc: Julia Suvorova Signed-off-by: Suravee Suthikulpanit --- hw/i386/pc_q35.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 371cca7484..bd862add94 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -365,7 +365,7 @@ static void pc_q35_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); -m->max_cpus = 288; +m->max_cpus = 1024; } static void pc_q35_8_1_machine_options(MachineClass *m) -- 2.34.1
Re: [RFC PATCH 1/2] bulk: Replace !CONFIG_SOFTMMU -> CONFIG_USER_ONLY
On 6/5/23 13:29, Philippe Mathieu-Daudé wrote:
On 3/6/23 05:49, Richard Henderson wrote:
On 6/2/23 15:58, Philippe Mathieu-Daudé wrote:
CONFIG_USER_ONLY is the opposite of CONFIG_SOFTMMU.
Replace !CONFIG_SOFTMMU negation by the positive form
which is clearer when reviewing code.
CONFIG_SOFTMMU should be reserved for the actual softmmu tlb, which we *should* be able
to enable for user-only. It is the only way to handle some of our host/guest page size
problems. Further, CONFIG_SOFTMMU should go away as a #define and become a runtime test
(forced to true for system mode). Pie in the sky stuff.
This would be:
bool has_softmmu(void)
{
#ifdef CONFIG_USER_ONLY
/* TODO: implement */
return false;
#else
return true;
#endif
}
?
Yes, something like that.
r~
Re: [PULL 00/52] tcg patch queue
On 6/5/23 13:14, Richard Henderson wrote: The following changes since commit b52daaf2c868f2bab102eb5acbf55b2917f46aea: Merge tag 'pull-block-2023-06-05' ofhttps://gitlab.com/hreitz/qemu into staging (2023-06-05 10:27:31 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230605 for you to fetch changes up to a7f6911c127b1dd1b8764e03b0ebcf0a227a15e4: tcg/tcg-op-vec: Remove left over _link_error() definitions (2023-06-05 12:20:16 -0700) Build tcg/ once for system and once for user. Unmap perf_marker. Remove left over _link_error() definitions. Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~
Re: [RFC PATCH 1/2] bulk: Replace !CONFIG_SOFTMMU -> CONFIG_USER_ONLY
On 3/6/23 05:49, Richard Henderson wrote:
On 6/2/23 15:58, Philippe Mathieu-Daudé wrote:
CONFIG_USER_ONLY is the opposite of CONFIG_SOFTMMU.
Replace !CONFIG_SOFTMMU negation by the positive form
which is clearer when reviewing code.
CONFIG_SOFTMMU should be reserved for the actual softmmu tlb, which we
*should* be able to enable for user-only. It is the only way to handle
some of our host/guest page size problems. Further, CONFIG_SOFTMMU
should go away as a #define and become a runtime test (forced to true
for system mode). Pie in the sky stuff.
This would be:
bool has_softmmu(void)
{
#ifdef CONFIG_USER_ONLY
/* TODO: implement */
return false;
#else
return true;
#endif
}
?
It is quite likely that all uses of CONFIG_SOFTMMU outside of tcg/,
accel/tcg/, and random bits of include/ should only be using
CONFIG_USER_ONLY.
I see.
Thanks,
Phil.
[PULL 51/52] accel/tcg: Unmap perf_marker
From: Ilya Leoshkevich
Coverity complains that perf_marker is never unmapped.
Fix by unmapping it in perf_exit().
Fixes: Coverity CID 1507929
Fixes: 5584e2dbe8c9 ("tcg: add perfmap and jitdump")
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230605114134.1169974-1-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
accel/tcg/perf.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c
index f5a1eda39f..cd1aa99a7e 100644
--- a/accel/tcg/perf.c
+++ b/accel/tcg/perf.c
@@ -111,6 +111,8 @@ static void write_perfmap_entry(const void *start, size_t
insn,
}
static FILE *jitdump;
+static size_t perf_marker_size;
+static void *perf_marker = MAP_FAILED;
#define JITHEADER_MAGIC 0x4A695444
#define JITHEADER_VERSION 1
@@ -190,7 +192,6 @@ void perf_enable_jitdump(void)
{
struct jitheader header;
char jitdump_file[32];
-void *perf_marker;
if (!use_rt_clock) {
warn_report("CLOCK_MONOTONIC is not available, proceeding without
jitdump");
@@ -210,7 +211,8 @@ void perf_enable_jitdump(void)
* PERF_RECORD_MMAP or PERF_RECORD_MMAP2 event is of the form jit-%d.dump
* and will process it as a jitdump file.
*/
-perf_marker = mmap(NULL, qemu_real_host_page_size(), PROT_READ | PROT_EXEC,
+perf_marker_size = qemu_real_host_page_size();
+perf_marker = mmap(NULL, perf_marker_size, PROT_READ | PROT_EXEC,
MAP_PRIVATE, fileno(jitdump), 0);
if (perf_marker == MAP_FAILED) {
warn_report("Could not map %s: %s, proceeding without jitdump",
@@ -372,6 +374,11 @@ void perf_exit(void)
perfmap = NULL;
}
+if (perf_marker != MAP_FAILED) {
+munmap(perf_marker, perf_marker_size);
+perf_marker = MAP_FAILED;
+}
+
if (jitdump) {
fclose(jitdump);
jitdump = NULL;
--
2.34.1
[PULL 23/52] tcg: Split helper-gen.h
Create helper-gen-common.h without the target specific portion.
Use that in tcg-op-common.h. Reorg headers in target/arm to
ensure that helper-gen.h is included before helper-info.c.inc.
All other targets are already correct in this regard.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
MAINTAINERS | 1 +
include/exec/helper-gen-common.h | 18 ++
include/exec/helper-gen.h| 101 ++
include/tcg/tcg-op-common.h | 2 +-
include/exec/helper-gen.h.inc| 102 +++
target/arm/tcg/translate.c | 8 +--
6 files changed, 129 insertions(+), 103 deletions(-)
create mode 100644 include/exec/helper-gen-common.h
create mode 100644 include/exec/helper-gen.h.inc
diff --git a/MAINTAINERS b/MAINTAINERS
index a1b8376f4c..2366f64d3d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -154,6 +154,7 @@ F: include/exec/exec-all.h
F: include/exec/tb-flush.h
F: include/exec/target_long.h
F: include/exec/helper*.h
+F: include/exec/helper*.h.inc
F: include/exec/helper-info.c.inc
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
diff --git a/include/exec/helper-gen-common.h b/include/exec/helper-gen-common.h
new file mode 100644
index 00..5d6d78a625
--- /dev/null
+++ b/include/exec/helper-gen-common.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Helper file for declaring TCG helper functions.
+ * This one expands generation functions for tcg opcodes.
+ */
+
+#ifndef HELPER_GEN_COMMON_H
+#define HELPER_GEN_COMMON_H
+
+#define HELPER_H "accel/tcg/tcg-runtime.h"
+#include "exec/helper-gen.h.inc"
+#undef HELPER_H
+
+#define HELPER_H "accel/tcg/plugin-helpers.h"
+#include "exec/helper-gen.h.inc"
+#undef HELPER_H
+
+#endif /* HELPER_GEN_COMMON_H */
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index 784dd24ae2..f7ec155699 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -2,108 +2,15 @@
/*
* Helper file for declaring TCG helper functions.
* This one expands generation functions for tcg opcodes.
- * Define HELPER_H for the header file to be expanded,
- * and static inline to change from global file scope.
*/
#ifndef HELPER_GEN_H
#define HELPER_GEN_H
-#include "tcg/tcg.h"
-#include "tcg/helper-info.h"
-#include "exec/helper-head.h"
+#include "exec/helper-gen-common.h"
-#define DEF_HELPER_FLAGS_0(name, flags, ret)\
-extern TCGHelperInfo glue(helper_info_, name); \
-static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret))\
-{ \
-tcg_gen_call0((helper_info_, name), dh_retvar(ret)); \
-}
-
-#define DEF_HELPER_FLAGS_1(name, flags, ret, t1)\
-extern TCGHelperInfo glue(helper_info_, name); \
-static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
-dh_arg_decl(t1, 1)) \
-{ \
-tcg_gen_call1((helper_info_, name), dh_retvar(ret),\
- dh_arg(t1, 1)); \
-}
-
-#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2)\
-extern TCGHelperInfo glue(helper_info_, name); \
-static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
-dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \
-{ \
-tcg_gen_call2((helper_info_, name), dh_retvar(ret),\
- dh_arg(t1, 1), dh_arg(t2, 2));\
-}
-
-#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3)\
-extern TCGHelperInfo glue(helper_info_, name); \
-static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
-dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \
-{ \
-tcg_gen_call3((helper_info_, name), dh_retvar(ret),\
- dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \
-}
-
-#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4)\
-extern TCGHelperInfo glue(helper_info_, name); \
-static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
-dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \
-dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \
-{ \
-tcg_gen_call4((helper_info_, name), dh_retvar(ret),\
- dh_arg(t1, 1), dh_arg(t2, 2), \
- dh_arg(t3, 3), dh_arg(t4,
[PULL 22/52] tcg: Split tcg_gen_callN
Make tcg_gen_callN a static function. Create tcg_gen_call[0-7]
functions for use by helper-gen.h.inc.
Removes a multiplicty of calls to __stack_chk_fail, saving up
to 143kiB of .text space as measured on an x86_64 host.
Old New Less%Change
680 8741816 146864 1.65% qemu-system-aarch64
5911832 5856152 55680 0.94% qemu-system-riscv64
5816728 5767512 49216 0.85% qemu-system-mips64
6707832 6659144 48688 0.73% qemu-system-ppc64
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/helper-gen.h | 40 ++---
include/tcg/tcg.h | 14 +-
tcg/tcg.c | 54 ++-
3 files changed, 86 insertions(+), 22 deletions(-)
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index 248cff3351..784dd24ae2 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -17,7 +17,7 @@
extern TCGHelperInfo glue(helper_info_, name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret))\
{ \
-tcg_gen_callN((helper_info_, name), dh_retvar(ret), 0, NULL); \
+tcg_gen_call0((helper_info_, name), dh_retvar(ret)); \
}
#define DEF_HELPER_FLAGS_1(name, flags, ret, t1)\
@@ -25,8 +25,8 @@ extern TCGHelperInfo glue(helper_info_, name);
\
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1)) \
{ \
-TCGTemp *args[1] = { dh_arg(t1, 1) }; \
-tcg_gen_callN((helper_info_, name), dh_retvar(ret), 1, args); \
+tcg_gen_call1((helper_info_, name), dh_retvar(ret),\
+ dh_arg(t1, 1)); \
}
#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2)\
@@ -34,8 +34,8 @@ extern TCGHelperInfo glue(helper_info_, name);
\
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \
{ \
-TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) };\
-tcg_gen_callN((helper_info_, name), dh_retvar(ret), 2, args); \
+tcg_gen_call2((helper_info_, name), dh_retvar(ret),\
+ dh_arg(t1, 1), dh_arg(t2, 2));\
}
#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3)\
@@ -43,8 +43,8 @@ extern TCGHelperInfo glue(helper_info_, name);
\
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \
{ \
-TCGTemp *args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \
-tcg_gen_callN((helper_info_, name), dh_retvar(ret), 3, args); \
+tcg_gen_call3((helper_info_, name), dh_retvar(ret),\
+ dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \
}
#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4)\
@@ -53,9 +53,9 @@ static inline void glue(gen_helper_,
name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \
dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \
{ \
-TCGTemp *args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \
- dh_arg(t3, 3), dh_arg(t4, 4) };\
-tcg_gen_callN((helper_info_, name), dh_retvar(ret), 4, args); \
+tcg_gen_call4((helper_info_, name), dh_retvar(ret),\
+ dh_arg(t1, 1), dh_arg(t2, 2), \
+ dh_arg(t3, 3), dh_arg(t4, 4));\
}
#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5)\
@@ -64,9 +64,9 @@ static inline void glue(gen_helper_,
name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \
{ \
-TCGTemp *args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
- dh_arg(t4, 4), dh_arg(t5, 5) };\
-tcg_gen_callN((helper_info_, name), dh_retvar(ret), 5, args); \
+tcg_gen_call5((helper_info_, name), dh_retvar(ret),\
+ dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
+
[PULL 04/52] tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses replaced with TCGContext.addr_type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index d2d0f604c2..48efd83817 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -1027,6 +1027,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
TCGReg addr_reg, MemOpIdx oi,
bool is_ld)
{
+TCGType addr_type = s->addr_type;
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
@@ -1063,7 +1064,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD);
/* Load the tlb comparator and the addend. */
-tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_T2, TCG_REG_T1, cmp_off);
+tcg_out_ld(s, addr_type, TCG_REG_T2, TCG_REG_T1, cmp_off);
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off);
h->base = TCG_REG_T1;
@@ -1084,7 +1085,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
ldst->label_ptr[0] = s->code_ptr;
/* bne,pn %[xi]cc, label0 */
-cc = TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC;
+cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC;
tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0);
#else
/*
@@ -1110,7 +,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
#endif
/* If the guest address must be zero-extended, do in the delay slot. */
-if (TARGET_LONG_BITS == 32) {
+if (addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_REG_T2, addr_reg);
h->index = TCG_REG_T2;
} else {
--
2.34.1
[PULL 35/52] accel/tcg: Move most of gen-icount.h into translator.c
The only usage of gen_tb_start and gen_tb_end are here.
Move the static icount_start_insn variable into a local
within translator_loop. Simplify the two subroutines
by passing in the existing local cflags variable.
Leave only the declaration of gen_io_start in gen-icount.h.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 79 +
accel/tcg/translator.c| 83 ++-
2 files changed, 82 insertions(+), 80 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index f6de79a6b4..6006af4c06 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -1,83 +1,6 @@
#ifndef GEN_ICOUNT_H
#define GEN_ICOUNT_H
-#include "exec/exec-all.h"
-
-/* Helpers for instruction counting code generation. */
-
-static TCGOp *icount_start_insn;
-
-static inline void gen_io_start(void)
-{
-tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
- offsetof(ArchCPU, parent_obj.can_do_io) -
- offsetof(ArchCPU, env));
-}
-
-static inline void gen_tb_start(const TranslationBlock *tb)
-{
-TCGv_i32 count = tcg_temp_new_i32();
-
-tcg_gen_ld_i32(count, cpu_env,
- offsetof(ArchCPU, neg.icount_decr.u32) -
- offsetof(ArchCPU, env));
-
-if (tb_cflags(tb) & CF_USE_ICOUNT) {
-/*
- * We emit a sub with a dummy immediate argument. Keep the insn index
- * of the sub so that we later (when we know the actual insn count)
- * can update the argument with the actual insn count.
- */
-tcg_gen_sub_i32(count, count, tcg_constant_i32(0));
-icount_start_insn = tcg_last_op();
-}
-
-/*
- * Emit the check against icount_decr.u32 to see if we should exit
- * unless we suppress the check with CF_NOIRQ. If we are using
- * icount and have suppressed interruption the higher level code
- * should have ensured we don't run more instructions than the
- * budget.
- */
-if (tb_cflags(tb) & CF_NOIRQ) {
-tcg_ctx->exitreq_label = NULL;
-} else {
-tcg_ctx->exitreq_label = gen_new_label();
-tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
-}
-
-if (tb_cflags(tb) & CF_USE_ICOUNT) {
-tcg_gen_st16_i32(count, cpu_env,
- offsetof(ArchCPU, neg.icount_decr.u16.low) -
- offsetof(ArchCPU, env));
-/*
- * cpu->can_do_io is cleared automatically here at the beginning of
- * each translation block. The cost is minimal and only paid for
- * -icount, plus it would be very easy to forget doing it in the
- * translator. Doing it here means we don't need a gen_io_end() to
- * go with gen_io_start().
- */
-tcg_gen_st_i32(tcg_constant_i32(0), cpu_env,
- offsetof(ArchCPU, parent_obj.can_do_io) -
- offsetof(ArchCPU, env));
-}
-}
-
-static inline void gen_tb_end(const TranslationBlock *tb, int num_insns)
-{
-if (tb_cflags(tb) & CF_USE_ICOUNT) {
-/*
- * Update the num_insn immediate parameter now that we know
- * the actual insn count.
- */
-tcg_set_insn_param(icount_start_insn, 2,
- tcgv_i32_arg(tcg_constant_i32(num_insns)));
-}
-
-if (tcg_ctx->exitreq_label) {
-gen_set_label(tcg_ctx->exitreq_label);
-tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED);
-}
-}
+void gen_io_start(void);
#endif
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 6120ef2a92..b0d0015c70 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -18,6 +18,84 @@
#include "exec/plugin-gen.h"
#include "exec/replay-core.h"
+
+void gen_io_start(void)
+{
+tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ offsetof(ArchCPU, parent_obj.can_do_io) -
+ offsetof(ArchCPU, env));
+}
+
+static TCGOp *gen_tb_start(uint32_t cflags)
+{
+TCGv_i32 count = tcg_temp_new_i32();
+TCGOp *icount_start_insn = NULL;
+
+tcg_gen_ld_i32(count, cpu_env,
+ offsetof(ArchCPU, neg.icount_decr.u32) -
+ offsetof(ArchCPU, env));
+
+if (cflags & CF_USE_ICOUNT) {
+/*
+ * We emit a sub with a dummy immediate argument. Keep the insn index
+ * of the sub so that we later (when we know the actual insn count)
+ * can update the argument with the actual insn count.
+ */
+tcg_gen_sub_i32(count, count, tcg_constant_i32(0));
+icount_start_insn = tcg_last_op();
+}
+
+/*
+ * Emit the check against icount_decr.u32 to see if we should exit
+ * unless we suppress the check with CF_NOIRQ. If we are using
+ * icount and have suppressed interruption the higher level code
+ * should have ensured we don't run more instructions than the
+ *
[PULL 15/52] tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h
Create tcg/tcg-op-common.h, moving everything that does not concern
TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header
instead of tcg-op.h, in preparation for compiling tcg/ only once.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 996 ++
include/tcg/tcg-op.h| 1004 +--
tcg/optimize.c |2 +-
tcg/tcg-op-gvec.c |2 +-
tcg/tcg-op-ldst.c |2 +-
tcg/tcg-op-vec.c|2 +-
tcg/tcg-op.c|2 +-
tcg/tcg.c |2 +-
tcg/tci.c |3 +-
9 files changed, 1007 insertions(+), 1008 deletions(-)
create mode 100644 include/tcg/tcg-op-common.h
diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
new file mode 100644
index 00..04a9ca1fc6
--- /dev/null
+++ b/include/tcg/tcg-op-common.h
@@ -0,0 +1,996 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Target independent opcode generation functions.
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ */
+
+#ifndef TCG_TCG_OP_COMMON_H
+#define TCG_TCG_OP_COMMON_H
+
+#include "tcg/tcg.h"
+#include "exec/helper-proto.h"
+#include "exec/helper-gen.h"
+
+/* Basic output routines. Not for general consumption. */
+
+void tcg_gen_op1(TCGOpcode, TCGArg);
+void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
+void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+
+void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
+void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
+void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
+
+static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
+{
+tcg_gen_op1(opc, tcgv_i32_arg(a1));
+}
+
+static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
+{
+tcg_gen_op1(opc, tcgv_i64_arg(a1));
+}
+
+static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
+{
+tcg_gen_op1(opc, a1);
+}
+
+static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
+{
+tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
+}
+
+static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
+{
+tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
+}
+
+static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
+{
+tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
+}
+
+static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
+{
+tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
+}
+
+static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
+{
+tcg_gen_op2(opc, a1, a2);
+}
+
+static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
+ TCGv_i32 a2, TCGv_i32 a3)
+{
+tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
+}
+
+static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
+ TCGv_i64 a2, TCGv_i64 a3)
+{
+tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
+}
+
+static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
+TCGv_i32 a2, TCGArg a3)
+{
+tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
+}
+
+static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
+TCGv_i64 a2, TCGArg a3)
+{
+tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
+}
+
+static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
+ TCGv_ptr base, TCGArg offset)
+{
+tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
+}
+
+static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
+ TCGv_ptr base, TCGArg offset)
+{
+tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
+}
+
+static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
+ TCGv_i32 a3, TCGv_i32 a4)
+{
+tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+tcgv_i32_arg(a3), tcgv_i32_arg(a4));
+}
+
+static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
+ TCGv_i64 a3, TCGv_i64 a4)
+{
+tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+tcgv_i64_arg(a3), tcgv_i64_arg(a4));
+}
+
+static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
+TCGv_i32 a3, TCGArg a4)
+{
+tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+tcgv_i32_arg(a3), a4);
+}
+
+static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
+
[PULL 27/52] tcg: Add guest_mo to TCGContext
This replaces of TCG_GUEST_DEFAULT_MO in tcg-op-ldst.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
accel/tcg/translate-all.c | 5 +
tcg/tcg-op-ldst.c | 4 +---
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 813c733910..9f607e2664 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -521,6 +521,7 @@ struct TCGContext {
uint8_t tlb_dyn_max_bits;
#endif
uint8_t insn_start_words;
+TCGBar guest_mo;
TCGRegSet reserved_regs;
intptr_t current_frame_offset;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 67b838e16b..200de2793c 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -364,6 +364,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
(int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env);
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
+#ifdef TCG_GUEST_DEFAULT_MO
+tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
+#else
+tcg_ctx->guest_mo = TCG_MO_ALL;
+#endif
tb_overflow:
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index 3c00bf0c95..9bcf63b041 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -104,9 +104,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 v, TCGTemp
*addr, MemOpIdx oi)
static void tcg_gen_req_mo(TCGBar type)
{
-#ifdef TCG_GUEST_DEFAULT_MO
-type &= TCG_GUEST_DEFAULT_MO;
-#endif
+type &= tcg_ctx->guest_mo;
type &= ~TCG_TARGET_DEFAULT_MO;
if (type) {
tcg_gen_mb(type | TCG_BAR_SC);
--
2.34.1
[PULL 34/52] include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE
The last use was removed with 2ac01d6dafab.
Fixes: 2ac01d6dafab ("translate-all: use a binary search tree to track TBs in
TBContext")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f01c7d57e8..698943d58f 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -467,16 +467,6 @@ int probe_access_full(CPUArchState *env, target_ulong
addr, int size,
CPUTLBEntryFull **pfull, uintptr_t retaddr);
#endif
-/* Estimated block size for TB allocation. */
-/* ??? The following is based on a 2015 survey of x86_64 host output.
- Better would seem to be some sort of dynamically sized TB array,
- adapting to the block sizes actually being produced. */
-#if defined(CONFIG_SOFTMMU)
-#define CODE_GEN_AVG_BLOCK_SIZE 400
-#else
-#define CODE_GEN_AVG_BLOCK_SIZE 150
-#endif
-
/* Hide the qatomic_read to make code a little easier on the eyes */
static inline uint32_t tb_cflags(const TranslationBlock *tb)
{
--
2.34.1
[PULL 47/52] plugins: Move plugin_insn_append to translator.c
This function is only used in translator.c, and uses a
target-specific typedef: abi_ptr.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/plugin-gen.h | 22 --
accel/tcg/translator.c| 21 +
2 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h
index 3af0168e65..e9a976f815 100644
--- a/include/exec/plugin-gen.h
+++ b/include/exec/plugin-gen.h
@@ -29,25 +29,6 @@ void plugin_gen_insn_end(void);
void plugin_gen_disable_mem_helpers(void);
void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info);
-static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t
size)
-{
-struct qemu_plugin_insn *insn = tcg_ctx->plugin_insn;
-abi_ptr off;
-
-if (insn == NULL) {
-return;
-}
-off = pc - insn->vaddr;
-if (off < insn->data->len) {
-g_byte_array_set_size(insn->data, off);
-} else if (off > insn->data->len) {
-/* we have an unexpected gap */
-g_assert_not_reached();
-}
-
-insn->data = g_byte_array_append(insn->data, from, size);
-}
-
#else /* !CONFIG_PLUGIN */
static inline bool
@@ -72,9 +53,6 @@ static inline void plugin_gen_disable_mem_helpers(void)
static inline void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info)
{ }
-static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t
size)
-{ }
-
#endif /* CONFIG_PLUGIN */
#endif /* QEMU_PLUGIN_GEN_H */
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index fda4e7f637..918a455e73 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -285,6 +285,27 @@ static void *translator_access(CPUArchState *env,
DisasContextBase *db,
return host + (pc - base);
}
+static void plugin_insn_append(abi_ptr pc, const void *from, size_t size)
+{
+#ifdef CONFIG_PLUGIN
+struct qemu_plugin_insn *insn = tcg_ctx->plugin_insn;
+abi_ptr off;
+
+if (insn == NULL) {
+return;
+}
+off = pc - insn->vaddr;
+if (off < insn->data->len) {
+g_byte_array_set_size(insn->data, off);
+} else if (off > insn->data->len) {
+/* we have an unexpected gap */
+g_assert_not_reached();
+}
+
+insn->data = g_byte_array_append(insn->data, from, size);
+#endif
+}
+
uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
{
uint8_t ret;
--
2.34.1
[PULL 45/52] tcg: Move env defines out of NEED_CPU_H in helper-head.h
Since the change to CPUArchState, we have a common typedef that can always be used. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index a355ef8ebe..28ceab0a46 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -22,6 +22,7 @@ #define dh_alias_f64 i64 #define dh_alias_ptr ptr #define dh_alias_cptr ptr +#define dh_alias_env ptr #define dh_alias_void void #define dh_alias_noreturn noreturn #define dh_alias(t) glue(dh_alias_, t) @@ -37,6 +38,7 @@ #define dh_ctype_f64 float64 #define dh_ctype_ptr void * #define dh_ctype_cptr const void * +#define dh_ctype_env CPUArchState * #define dh_ctype_void void #define dh_ctype_noreturn G_NORETURN void #define dh_ctype(t) dh_ctype_##t @@ -52,9 +54,6 @@ # endif # endif # define dh_ctype_tl target_ulong -# define dh_alias_env ptr -# define dh_ctype_env CPUArchState * -# define dh_typecode_env dh_typecode_ptr #endif /* We can't use glue() here because it falls foul of C preprocessor @@ -96,6 +95,7 @@ #define dh_typecode_f32 dh_typecode_i32 #define dh_typecode_f64 dh_typecode_i64 #define dh_typecode_cptr dh_typecode_ptr +#define dh_typecode_env dh_typecode_ptr #define dh_typecode(t) dh_typecode_##t #define dh_callflag_i32 0 -- 2.34.1
[PULL 52/52] tcg/tcg-op-vec: Remove left over _link_error() definitions
From: Philippe Mathieu-Daudé
In commit d56fea79f9 ("tcg: Move TCG_{LOW,HIGH} to tcg-internal.h")
we replaced the "_link_error" definitions with modern QEMU_ERROR()
attribute markup. We covered tcg-op.c but forgot to completely
clean tcg-op-vec.c. Do it now.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230605175647.88395-3-phi...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
tcg/tcg-op-vec.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 35d67eeda0..64bc8a2156 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -24,17 +24,6 @@
#include "tcg/tcg-mo.h"
#include "tcg-internal.h"
-
-/* Reduce the number of ifdefs below. This assumes that all uses of
- TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
- the compiler can eliminate. */
-#if TCG_TARGET_REG_BITS == 64
-extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);
-extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
-#define TCGV_LOW TCGV_LOW_link_error
-#define TCGV_HIGH TCGV_HIGH_link_error
-#endif
-
/*
* Vector optional opcode tracking.
* Except for the basic logical operations (and, or, xor), and
--
2.34.1
[PULL 33/52] tcg: Spit out exec/translation-block.h
This is all that is required by tcg/ from exec-all.h.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 132 +--
include/exec/translation-block.h | 149 +++
tcg/tcg-op-ldst.c| 2 +-
3 files changed, 151 insertions(+), 132 deletions(-)
create mode 100644 include/exec/translation-block.h
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index dec17b1e62..f01c7d57e8 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -24,20 +24,9 @@
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#endif
-#include "qemu/interval-tree.h"
+#include "exec/translation-block.h"
#include "qemu/clang-tsa.h"
-/* Page tracking code uses ram addresses in system mode, and virtual
- addresses in userspace mode. Define tb_page_addr_t to be an appropriate
- type. */
-#if defined(CONFIG_USER_ONLY)
-typedef vaddr tb_page_addr_t;
-#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx
-#else
-typedef ram_addr_t tb_page_addr_t;
-#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
-#endif
-
/**
* cpu_unwind_state_data:
* @cpu: the cpu context
@@ -478,8 +467,6 @@ int probe_access_full(CPUArchState *env, target_ulong addr,
int size,
CPUTLBEntryFull **pfull, uintptr_t retaddr);
#endif
-#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line
*/
-
/* Estimated block size for TB allocation. */
/* ??? The following is based on a 2015 survey of x86_64 host output.
Better would seem to be some sort of dynamically sized TB array,
@@ -490,123 +477,6 @@ int probe_access_full(CPUArchState *env, target_ulong
addr, int size,
#define CODE_GEN_AVG_BLOCK_SIZE 150
#endif
-/*
- * Translation Cache-related fields of a TB.
- * This struct exists just for convenience; we keep track of TB's in a binary
- * search tree, and the only fields needed to compare TB's in the tree are
- * @ptr and @size.
- * Note: the address of search data can be obtained by adding @size to @ptr.
- */
-struct tb_tc {
-const void *ptr;/* pointer to the translated code */
-size_t size;
-};
-
-struct TranslationBlock {
-/*
- * Guest PC corresponding to this block. This must be the true
- * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and
- * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
- * privilege, must store those bits elsewhere.
- *
- * If CF_PCREL, the opcodes for the TranslationBlock are written
- * such that the TB is associated only with the physical page and
- * may be run in any virtual address context. In this case, PC
- * must always be taken from ENV in a target-specific manner.
- * Unwind information is taken as offsets from the page, to be
- * deposited into the "current" PC.
- */
-vaddr pc;
-
-/*
- * Target-specific data associated with the TranslationBlock, e.g.:
- * x86: the original user, the Code Segment virtual base,
- * arm: an extension of tb->flags,
- * s390x: instruction data for EXECUTE,
- * sparc: the next pc of the instruction queue (for delay slots).
- */
-uint64_t cs_base;
-
-uint32_t flags; /* flags defining in which context the code was generated
*/
-uint32_t cflags;/* compile flags */
-
-/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
-#define CF_COUNT_MASK0x01ff
-#define CF_NO_GOTO_TB0x0200 /* Do not chain with goto_tb */
-#define CF_NO_GOTO_PTR 0x0400 /* Do not chain with goto_ptr */
-#define CF_SINGLE_STEP 0x0800 /* gdbstub single-step in effect */
-#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
-#define CF_MEMI_ONLY 0x0001 /* Only instrument memory ops */
-#define CF_USE_ICOUNT0x0002
-#define CF_INVALID 0x0004 /* TB is stale. Set with @jmp_lock held */
-#define CF_PARALLEL 0x0008 /* Generate code for a parallel context */
-#define CF_NOIRQ 0x0010 /* Generate an uninterruptible TB */
-#define CF_PCREL 0x0020 /* Opcodes in TB are PC-relative */
-#define CF_CLUSTER_MASK 0xff00 /* Top 8 bits are cluster ID */
-#define CF_CLUSTER_SHIFT 24
-
-/*
- * Above fields used for comparing
- */
-
-/* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */
-uint16_t size;
-uint16_t icount;
-
-struct tb_tc tc;
-
-/*
- * Track tb_page_addr_t intervals that intersect this TB.
- * For user-only, the virtual addresses are always contiguous,
- * and we use a unified interval tree. For system, we use a
- * linked list headed in each PageDesc. Within the list, the lsb
- * of the previous pointer tells the index of page_next[], and the
- * list is protected by the PageDesc lock(s).
- */
-#ifdef CONFIG_USER_ONLY
-IntervalTreeNode itree;
-#else
-uintptr_t page_next[2];
-tb_page_addr_t page_addr[2];
[PULL 32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits
This makes TranslationBlock agnostic to the address size of the guest.
Use vaddr for pc, since that's always a virtual address.
Use uint64_t for cs_base, since usage varies between guests.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 4 ++--
accel/tcg/cpu-exec.c| 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ec0902c532..dec17b1e62 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -516,7 +516,7 @@ struct TranslationBlock {
* Unwind information is taken as offsets from the page, to be
* deposited into the "current" PC.
*/
-target_ulong pc;
+vaddr pc;
/*
* Target-specific data associated with the TranslationBlock, e.g.:
@@ -525,7 +525,7 @@ struct TranslationBlock {
* s390x: instruction data for EXECUTE,
* sparc: the next pc of the instruction queue (for delay slots).
*/
-target_ulong cs_base;
+uint64_t cs_base;
uint32_t flags; /* flags defining in which context the code was generated
*/
uint32_t cflags;/* compile flags */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 60ca9e229e..1cf4f1fa22 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -297,7 +297,7 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu,
{
if (qemu_log_in_addr_range(pc)) {
qemu_log_mask(CPU_LOG_EXEC,
- "Trace %d: %p [" TARGET_FMT_lx
+ "Trace %d: %p [%08" PRIx64
"/" TARGET_FMT_lx "/%08x/%08x] %s\n",
cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
tb->flags, tb->cflags, lookup_symbol(pc));
--
2.34.1
[PULL 43/52] accel/tcg: Tidy includes for translator.[ch]
Reduce the header to only bswap.h and cpu_ldst.h.
Move exec/translate-all.h to translator.c.
Reduce tcg.h and tcg-op.h to tcg-op-common.h.
Remove otherwise unused headers.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 6 +-
accel/tcg/translator.c| 8 +++-
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 228002a623..224ae14aa7 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -18,12 +18,8 @@
* member in your target-specific DisasContext.
*/
-
#include "qemu/bswap.h"
-#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
-#include "exec/translate-all.h"
-#include "tcg/tcg.h"
+#include "exec/cpu_ldst.h" /* for abi_ptr */
/**
* gen_intermediate_code
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 60a613c99d..fda4e7f637 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -8,15 +8,13 @@
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "qemu/error-report.h"
-#include "tcg/tcg.h"
-#include "tcg/tcg-op.h"
#include "exec/exec-all.h"
-#include "exec/log.h"
#include "exec/translator.h"
+#include "exec/translate-all.h"
#include "exec/plugin-gen.h"
-#include "exec/replay-core.h"
-
+#include "tcg/tcg-op-common.h"
static void gen_io_start(void)
{
--
2.34.1
[PULL 16/52] target/arm: Include helper-gen.h in translator.h
This had been included via tcg-op-common.h via tcg-op.h, but that is going away. It is needed for inlines within translator.h, so we might as well do it there and not individually in each translator c file. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 1 + target/arm/tcg/translate-a64.c | 2 -- target/arm/tcg/translate-sme.c | 1 - target/arm/tcg/translate-sve.c | 2 -- target/arm/tcg/translate.c | 2 -- 5 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index a9d1f4adc2..868a3abd0d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -2,6 +2,7 @@ #define TARGET_ARM_TRANSLATE_H #include "exec/translator.h" +#include "exec/helper-gen.h" #include "internals.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 741a608739..bc0cb98955 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -29,8 +29,6 @@ #include "qemu/host-utils.h" #include "semihosting/semihost.h" #include "exec/gen-icount.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "cpregs.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e3adba314e..b0812d9dd6 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -23,7 +23,6 @@ #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" #include "translate.h" -#include "exec/helper-gen.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 92ab290106..106baf311f 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -27,8 +27,6 @@ #include "arm_ldst.h" #include "translate.h" #include "internals.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7468476724..c89825ad6a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -30,8 +30,6 @@ #include "qemu/bitops.h" #include "arm_ldst.h" #include "semihosting/semihost.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "cpregs.h" -- 2.34.1
Re: [PATCH RESEND v2] hw/i2c: Enable an id for the pca954x devices
Hi Patrick,
On 31/5/23 18:34, Patrick Venture wrote:
On Wed, Mar 22, 2023 at 2:40 PM Philippe Mathieu-Daudé
mailto:phi...@linaro.org>> wrote:
On 22/3/23 22:19, Corey Minyard wrote:
> On Wed, Mar 22, 2023 at 10:21:36AM -0700, Patrick Venture wrote:
>> This allows the devices to be more readily found and specified.
>> Without setting the name field, they can only be found by device
type
>> name, which doesn't let you specify the second of the same
device type
>> behind a bus.
>>
>> Tested: Verified that by default the device was findable with
the name
>> 'pca954x[77]', for an instance attached at that address.
>
> This looks good to me.
>
> Acked-by: Corey Minyard mailto:cminy...@mvista.com>>
>
> if you are taking this in through another tree. Or do you want me to
> take this?
Since I have to send a MIPS PR, I'll take this one;
to alleviate you and the CI minutes.
I don't see this patch yet, did it got lost in the shuffle?
I quickly tried to test the patch before sending the PR and it was not
working, so I dropped it; but since it was a busy day I neglected to
post an update on the list. I apologize for that.
Revisiting the patch, the problem is trivial, a simple typo:
+static Property pca954x_props[] = {
+DEFINE_PROP_STRING("nane", Pca954xState, name),
+DEFINE_PROP_END_OF_LIST()
+};
I'm queuing this patch again with s/nane/name/.
Regards,
Phil.
[PULL 17/52] target/hexagon: Include helper-gen.h where needed
This had been included via tcg-op-common.h via tcg-op.h,
but that is going away. In idef-parser.y, shuffle some
tcg related includes into a more logical order.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hexagon/genptr.c | 1 +
target/hexagon/translate.c | 1 +
target/hexagon/idef-parser/idef-parser.y | 3 ++-
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index bcb287dd8b..217bc7bb5a 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -20,6 +20,7 @@
#include "internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
+#include "exec/helper-gen.h"
#include "insn.h"
#include "opcodes.h"
#include "translate.h"
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 8838ab2364..42a7697fc9 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -20,6 +20,7 @@
#include "cpu.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
+#include "exec/helper-gen.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "internal.h"
diff --git a/target/hexagon/idef-parser/idef-parser.y
b/target/hexagon/idef-parser/idef-parser.y
index 5c983954ed..cd2612eb8c 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -843,13 +843,14 @@ int main(int argc, char **argv)
fputs("#include \"qemu/log.h\"\n", output_file);
fputs("#include \"cpu.h\"\n", output_file);
fputs("#include \"internal.h\"\n", output_file);
+fputs("#include \"tcg/tcg.h\"\n", output_file);
fputs("#include \"tcg/tcg-op.h\"\n", output_file);
+fputs("#include \"exec/helper-gen.h\"\n", output_file);
fputs("#include \"insn.h\"\n", output_file);
fputs("#include \"opcodes.h\"\n", output_file);
fputs("#include \"translate.h\"\n", output_file);
fputs("#define QEMU_GENERATE\n", output_file);
fputs("#include \"genptr.h\"\n", output_file);
-fputs("#include \"tcg/tcg.h\"\n", output_file);
fputs("#include \"macros.h\"\n", output_file);
fprintf(output_file, "#include \"%s\"\n", argv[ARG_INDEX_EMITTER_H]);
--
2.34.1
[PULL 40/52] target/mips: Tidy helpers for translation
Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/translate.h| 6 -- target/mips/tcg/msa_translate.c| 3 --- target/mips/tcg/mxu_translate.c| 2 -- target/mips/tcg/octeon_translate.c | 4 +--- target/mips/tcg/rel6_translate.c | 2 -- target/mips/tcg/translate.c| 18 ++ target/mips/tcg/translate_addr_const.c | 1 - target/mips/tcg/tx79_translate.c | 4 +--- target/mips/tcg/vr54xx_translate.c | 3 --- 9 files changed, 12 insertions(+), 31 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index fa8bf55209..3b0498a47a 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -8,9 +8,11 @@ #ifndef TARGET_MIPS_TRANSLATE_H #define TARGET_MIPS_TRANSLATE_H -#include "qemu/log.h" -#include "exec/translator.h" +#include "cpu.h" #include "tcg/tcg-op.h" +#include "exec/translator.h" +#include "exec/helper-gen.h" +#include "qemu/log.h" #define MIPS_DEBUG_DISAS 0 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 220cd3b048..b5b66fb38a 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -11,11 +11,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" #include "fpu_helper.h" -#include "internal.h" static int elm_n(DisasContext *ctx, int x); static int elm_df(DisasContext *ctx, int x); diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index be038b5f07..39348b3a91 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -16,8 +16,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" /* diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 103c304d10..e25c4cbaa0 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -7,10 +7,8 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/helper-gen.h" #include "translate.h" +#include "tcg/tcg-op-gvec.h" /* Include the auto-generated decoder. */ #include "decode-octeon.c.inc" diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index d631851258..59f237ba3b 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -9,8 +9,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" /* Include the auto-generated decoders. */ diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 312ed66989..f3da05ba3b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -23,19 +23,13 @@ */ #include "qemu/osdep.h" -#include "cpu.h" -#include "internal.h" -#include "tcg/tcg-op.h" -#include "exec/translator.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" -#include "semihosting/semihost.h" - -#include "trace.h" -#include "exec/log.h" -#include "qemu/qemu-print.h" -#include "fpu_helper.h" #include "translate.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "semihosting/semihost.h" +#include "trace.h" +#include "disas/disas.h" +#include "fpu_helper.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c index a510da406c..6f4b39f715 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" #include "translate.h" bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index 3a45a1bfea..dd6fb8a7bd 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -8,10 +8,8 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/helper-gen.h" #include "translate.h" +#include "tcg/tcg-op-gvec.h" /* Include the auto-generated decoder. */ #include "decode-tx79.c.inc" diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c index 804672f84c..2c1f6cc527 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -10,10 +10,7 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" -#include "internal.h" /* Include the auto-generated decoder. */ #include
[PULL 42/52] target/arm: Add missing include of exec/exec-all.h
This had been pulled in via exec/translator.h, but the include of exec-all.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 5b53b6215d..4d88197715 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -4,6 +4,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" #include "exec/translator.h" #include "exec/helper-gen.h" #include "internals.h" -- 2.34.1
[PULL 49/52] exec/poison: Do not poison CONFIG_SOFTMMU
If CONFIG_USER_ONLY is ok generically, so is CONFIG_SOFTMMU,
because they are exactly opposite.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/poison.h | 1 -
scripts/make-config-poison.sh | 5 +++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 256736e11a..e94ee8dfef 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -85,7 +85,6 @@
#pragma GCC poison CONFIG_HVF
#pragma GCC poison CONFIG_LINUX_USER
#pragma GCC poison CONFIG_KVM
-#pragma GCC poison CONFIG_SOFTMMU
#pragma GCC poison CONFIG_WHPX
#pragma GCC poison CONFIG_XEN
diff --git a/scripts/make-config-poison.sh b/scripts/make-config-poison.sh
index 1892854261..2b36907e23 100755
--- a/scripts/make-config-poison.sh
+++ b/scripts/make-config-poison.sh
@@ -4,11 +4,12 @@ if test $# = 0; then
exit 0
fi
-# Create list of config switches that should be poisoned in common code...
-# but filter out CONFIG_TCG and CONFIG_USER_ONLY which are special.
+# Create list of config switches that should be poisoned in common code,
+# but filter out several which are handled manually.
exec sed -n \
-e' /CONFIG_TCG/d' \
-e '/CONFIG_USER_ONLY/d' \
+ -e '/CONFIG_SOFTMMU/d' \
-e '/^#define / {' \
-e's///' \
-e's/ .*//' \
--
2.34.1
[PULL 38/52] accel/tcg: Move translator_fake_ldb out of line
This is used by exactly one host in extraordinary circumstances.
This means that translator.h need not include plugin-gen.h;
translator.c already includes plugin-gen.h.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 8 +---
accel/tcg/translator.c| 5 +
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index c1a1203789..228002a623 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -22,7 +22,6 @@
#include "qemu/bswap.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-#include "exec/plugin-gen.h"
#include "exec/translate-all.h"
#include "tcg/tcg.h"
@@ -229,12 +228,7 @@ translator_ldq_swap(CPUArchState *env, DisasContextBase
*db,
* re-synthesised for s390x "ex"). It ensures we update other areas of
* the translator with details of the executed instruction.
*/
-
-static inline void translator_fake_ldb(uint8_t insn8, abi_ptr pc)
-{
-plugin_insn_append(pc, , sizeof(insn8));
-}
-
+void translator_fake_ldb(uint8_t insn8, abi_ptr pc);
/*
* Return whether addr is on the same page as where disassembly started.
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 7a130e706e..60a613c99d 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -345,3 +345,8 @@ uint64_t translator_ldq(CPUArchState *env, DisasContextBase
*db, abi_ptr pc)
plugin_insn_append(pc, , sizeof(ret));
return ret;
}
+
+void translator_fake_ldb(uint8_t insn8, abi_ptr pc)
+{
+plugin_insn_append(pc, , sizeof(insn8));
+}
--
2.34.1
[PULL 24/52] tcg: Split helper-proto.h
Create helper-proto-common.h without the target specific portion. Use that in tcg-op-common.h. Include helper-proto.h in target/arm and target/hexagon before helper-info.c.inc; all other targets are already correct in this regard. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-proto-common.h | 18 include/exec/helper-proto.h| 73 -- include/tcg/tcg-op-common.h| 2 +- include/exec/helper-proto.h.inc| 68 accel/tcg/cputlb.c | 3 +- accel/tcg/plugin-gen.c | 2 +- accel/tcg/tcg-runtime-gvec.c | 2 +- accel/tcg/tcg-runtime.c| 2 +- target/arm/tcg/translate.c | 1 + target/hexagon/translate.c | 1 + 10 files changed, 102 insertions(+), 70 deletions(-) create mode 100644 include/exec/helper-proto-common.h create mode 100644 include/exec/helper-proto.h.inc diff --git a/include/exec/helper-proto-common.h b/include/exec/helper-proto-common.h new file mode 100644 index 00..4d4b022668 --- /dev/null +++ b/include/exec/helper-proto-common.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + */ + +#ifndef HELPER_PROTO_COMMON_H +#define HELPER_PROTO_COMMON_H + +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + +#endif /* HELPER_PROTO_COMMON_H */ diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 7a3f04b58c..6935cb4f16 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -1,71 +1,16 @@ -/* Helper file for declaring TCG helper functions. - This one expands prototypes for the helper functions. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + */ #ifndef HELPER_PROTO_H #define HELPER_PROTO_H -#include "exec/helper-head.h" +#include "exec/helper-proto-common.h" -/* - * Work around an issue with --enable-lto, in which GCC's ipa-split pass - * decides to split out the noreturn code paths that raise an exception, - * taking the __builtin_return_address() along into the new function, - * where it no longer computes a value that returns to TCG generated code. - * Despite the name, the noinline attribute affects splitter, so this - * prevents the optimization in question. Given that helpers should not - * otherwise be called directly, this should have any other visible effect. - * - * See https://gitlab.com/qemu-project/qemu/-/issues/1454 - */ -#define DEF_HELPER_ATTR __attribute__((noinline)) - -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -dh_ctype(ret) HELPER(name) (void) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), \ -dh_ctype(t3)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ -dh_ctype(t4)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ -dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ -dh_ctype(t4), dh_ctype(t5), \ -dh_ctype(t6)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ -dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \ -dh_ctype(t7)) DEF_HELPER_ATTR; - -#define IN_HELPER_PROTO - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef IN_HELPER_PROTO - -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 -#undef DEF_HELPER_ATTR +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H #endif /* HELPER_PROTO_H */ diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f6f05469c5..be382bbf77 100644
[PULL 48/52] plugins: Drop unused headers from exec/plugin-gen.h
Two headers are not required for the rest of the contents of plugin-gen.h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index e9a976f815..52828781bc 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -12,8 +12,6 @@ #ifndef QEMU_PLUGIN_GEN_H #define QEMU_PLUGIN_GEN_H -#include "exec/cpu_ldst.h" -#include "qemu/plugin.h" #include "tcg/tcg.h" struct DisasContextBase; -- 2.34.1
[PULL 46/52] tcg: Remove target-specific headers from tcg.[ch]
This finally paves the way for tcg/ to be built once per mode. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - accel/tcg/plugin-gen.c | 1 + tcg/region.c | 2 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 635fa53fdb..a498f31967 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -25,7 +25,6 @@ #ifndef TCG_H #define TCG_H -#include "cpu.h" #include "exec/memop.h" #include "exec/memopidx.h" #include "qemu/bitops.h" diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3e528f191d..5c13615112 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -43,6 +43,7 @@ * CPU's index into a TCG temp, since the first callback did it already. */ #include "qemu/osdep.h" +#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" diff --git a/tcg/region.c b/tcg/region.c index f8410ba5db..2b28ed3556 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -30,8 +30,8 @@ #include "qemu/cacheinfo.h" #include "qemu/qtree.h" #include "qapi/error.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" +#include "exec/translation-block.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8c1ad49c4e..c07de5d9f8 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -23,10 +23,10 @@ */ #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" +#include "exec/translation-block.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 41186f540f..3fcd0d9f32 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -34,7 +34,7 @@ #include "qemu/cacheflush.h" #include "qemu/cacheinfo.h" #include "qemu/timer.h" -#include "exec/exec-all.h" +#include "exec/translation-block.h" #include "exec/tlb-common.h" #include "tcg/tcg-op-common.h" -- 2.34.1
[PULL 50/52] tcg: Build once for system and once for user-only
Create two static libraries for use by each execution mode.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/meson.build | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/tcg/meson.build b/tcg/meson.build
index bdc185a485..565c60bc96 100644
--- a/tcg/meson.build
+++ b/tcg/meson.build
@@ -1,3 +1,7 @@
+if not get_option('tcg').allowed()
+ subdir_done()
+endif
+
tcg_ss = ss.source_set()
tcg_ss.add(files(
@@ -14,8 +18,28 @@ tcg_ss.add(files(
if get_option('tcg_interpreter')
libffi = dependency('libffi', version: '>=3.0', required: true,
method: 'pkg-config')
- specific_ss.add(libffi)
- specific_ss.add(files('tci.c'))
+ tcg_ss.add(libffi)
+ tcg_ss.add(files('tci.c'))
endif
-specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
+tcg_ss = tcg_ss.apply(config_host, strict: false)
+
+libtcg_user = static_library('tcg_user',
+ tcg_ss.sources() + genh,
+ name_suffix: 'fa',
+ c_args: '-DCONFIG_USER_ONLY',
+ build_by_default: have_user)
+
+tcg_user = declare_dependency(link_with: libtcg_user,
+ dependencies: tcg_ss.dependencies())
+user_ss.add(tcg_user)
+
+libtcg_softmmu = static_library('tcg_softmmu',
+tcg_ss.sources() + genh,
+name_suffix: 'fa',
+c_args: '-DCONFIG_SOFTMMU',
+build_by_default: have_system)
+
+tcg_softmmu = declare_dependency(link_with: libtcg_softmmu,
+ dependencies: tcg_ss.dependencies())
+softmmu_ss.add(tcg_softmmu)
--
2.34.1
[PULL 10/52] *: Add missing includes of tcg/tcg.h
This had been pulled in from exec/cpu_ldst.h, via exec/exec-all.h,
but the include of tcg.h will be removed.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/monitor.c | 1 +
accel/tcg/tcg-accel-ops-mttcg.c | 2 +-
accel/tcg/tcg-accel-ops-rr.c| 2 +-
target/i386/helper.c| 3 +++
target/openrisc/sys_helper.c| 1 +
5 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c
index 92fce580f1..f171bc6f5e 100644
--- a/accel/tcg/monitor.c
+++ b/accel/tcg/monitor.c
@@ -15,6 +15,7 @@
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/tcg.h"
+#include "tcg/tcg.h"
#include "internal.h"
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
index d50239e0e2..5d72c9b1bd 100644
--- a/accel/tcg/tcg-accel-ops-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -32,7 +32,7 @@
#include "qemu/guest-random.h"
#include "exec/exec-all.h"
#include "hw/boards.h"
-
+#include "tcg/tcg.h"
#include "tcg-accel-ops.h"
#include "tcg-accel-ops-mttcg.h"
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
index b6d10fa9a2..70b9b89073 100644
--- a/accel/tcg/tcg-accel-ops-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -32,7 +32,7 @@
#include "qemu/notify.h"
#include "qemu/guest-random.h"
#include "exec/exec-all.h"
-
+#include "tcg/tcg.h"
#include "tcg-accel-ops.h"
#include "tcg-accel-ops-rr.h"
#include "tcg-accel-ops-icount.h"
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 8857444819..682d10d98a 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -28,6 +28,9 @@
#include "monitor/monitor.h"
#endif
#include "qemu/log.h"
+#ifdef CONFIG_TCG
+#include "tcg/tcg.h"
+#endif
void cpu_sync_avx_hflag(CPUX86State *env)
{
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index ccdee3b8be..110f157601 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -26,6 +26,7 @@
#ifndef CONFIG_USER_ONLY
#include "hw/boards.h"
#endif
+#include "tcg/tcg.h"
#define TO_SPR(group, number) (((group) << 11) + (number))
--
2.34.1
[PULL 21/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line
Removes a multiplicity of calls to __assert_fail, saving up
to 360kiB of .text space as measured on an x86_64 host.
Old New Less%Change
9257272 680 368592 3.98% qemu-system-aarch64
6100968 5911832 189136 3.10% qemu-system-riscv64
5839112 5707032 132080 2.26% qemu-system-mips
4447608 4341752 105856 2.38% qemu-system-s390x
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 30 --
tcg/tcg.c | 19 +++
2 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 34035dab81..64c10a63f3 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -630,13 +630,6 @@ static inline void *tcg_splitwx_to_rw(const void *rx)
}
#endif
-static inline size_t temp_idx(TCGTemp *ts)
-{
-ptrdiff_t n = ts - tcg_ctx->temps;
-tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
-return n;
-}
-
static inline TCGArg temp_arg(TCGTemp *ts)
{
return (uintptr_t)ts;
@@ -647,16 +640,25 @@ static inline TCGTemp *arg_temp(TCGArg a)
return (TCGTemp *)(uintptr_t)a;
}
-/* Using the offset of a temporary, relative to TCGContext, rather than
- its index means that we don't use 0. That leaves offset 0 free for
- a NULL representation without having to leave index 0 unused. */
+#ifdef CONFIG_DEBUG_TCG
+size_t temp_idx(TCGTemp *ts);
+TCGTemp *tcgv_i32_temp(TCGv_i32 v);
+#else
+static inline size_t temp_idx(TCGTemp *ts)
+{
+return ts - tcg_ctx->temps;
+}
+
+/*
+ * Using the offset of a temporary, relative to TCGContext, rather than
+ * its index means that we don't use 0. That leaves offset 0 free for
+ * a NULL representation without having to leave index 0 unused.
+ */
static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
{
-uintptr_t o = (uintptr_t)v;
-TCGTemp *t = (void *)tcg_ctx + o;
-tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
-return t;
+return (void *)tcg_ctx + (uintptr_t)v;
}
+#endif
static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
{
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ffd3ccaff7..59624fceec 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1800,6 +1800,25 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match,
unsigned vece, int64_t val)
return tcg_constant_vec(t->base_type, vece, val);
}
+#ifdef CONFIG_DEBUG_TCG
+size_t temp_idx(TCGTemp *ts)
+{
+ptrdiff_t n = ts - tcg_ctx->temps;
+assert(n >= 0 && n < tcg_ctx->nb_temps);
+return n;
+}
+
+TCGTemp *tcgv_i32_temp(TCGv_i32 v)
+{
+uintptr_t o = (uintptr_t)v - offsetof(TCGContext, temps);
+
+assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps);
+assert(o % sizeof(TCGTemp) == 0);
+
+return (void *)tcg_ctx + (uintptr_t)v;
+}
+#endif /* CONFIG_DEBUG_TCG */
+
/* Return true if OP may appear in the opcode stream.
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)
--
2.34.1
[PULL 25/52] target/sh4: Emit insn_start for each insn in gUSA region
Fixes an assert in tcg_gen_code that we don't accidentally
eliminate an insn_start during optimization.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/translate.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 9d2c7a3337..76f46d268b 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2146,9 +2146,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State
*env)
/* The entire region has been translated. */
ctx->envflags &= ~TB_FLAG_GUSA_MASK;
-ctx->base.pc_next = pc_end;
-ctx->base.num_insns += max_insns - 1;
-return;
+goto done;
fail:
qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n",
@@ -2165,8 +2163,19 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State
*env)
purposes of accounting within the TB. We might as well report the
entire region consumed via ctx->base.pc_next so that it's immediately
available in the disassembly dump. */
+
+ done:
ctx->base.pc_next = pc_end;
ctx->base.num_insns += max_insns - 1;
+
+/*
+ * Emit insn_start to cover each of the insns in the region.
+ * This matches an assert in tcg.c making sure that we have
+ * tb->icount * insn_start.
+ */
+for (i = 1; i < max_insns; ++i) {
+tcg_gen_insn_start(pc + i * 2, ctx->envflags);
+}
}
#endif
--
2.34.1
[PULL 12/52] target/arm: Fix test of TCG_OVERSIZED_GUEST
The symbol is always defined, even if to 0. We wanted to test for
TCG_OVERSIZED_GUEST == 0.
This fixed, the #error is reached while building arm-softmmu, because
TCG_OVERSIZED_GUEST is not true (nor supposed to be true) for arm32
guest on a 32-bit host. But that's ok, because this feature doesn't
apply to arm32. Add an #ifdef for TARGET_AARCH64.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 69c05cd9da..b0d2a05403 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -418,6 +418,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t
old_val,
uint64_t new_val, S1Translate *ptw,
ARMMMUFaultInfo *fi)
{
+#ifdef TARGET_AARCH64
uint64_t cur_val;
void *host = ptw->out_host;
@@ -473,7 +474,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t
old_val,
* we know that TCG_OVERSIZED_GUEST is set, which means that we are
* running in round-robin mode and could only race with dma i/o.
*/
-#ifndef TCG_OVERSIZED_GUEST
+#if !TCG_OVERSIZED_GUEST
# error "Unexpected configuration"
#endif
bool locked = qemu_mutex_iothread_locked();
@@ -497,6 +498,10 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t
old_val,
#endif
return cur_val;
+#else
+/* AArch32 does not have FEAT_HADFS. */
+g_assert_not_reached();
+#endif
}
static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
--
2.34.1
[PULL 36/52] accel/tcg: Introduce translator_io_start
New wrapper around gen_io_start which takes care of the USE_ICOUNT
check, as well as marking the DisasContext to end the TB.
Remove exec/gen-icount.h.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
MAINTAINERS | 1 -
include/exec/gen-icount.h | 6 --
include/exec/translator.h | 10 +++
target/arm/cpregs.h | 4 +-
accel/tcg/translator.c| 27 ++-
target/alpha/translate.c | 15 +---
target/arm/tcg/translate-a64.c| 23 +++---
target/arm/tcg/translate-mve.c| 1 -
target/arm/tcg/translate-neon.c | 1 -
target/arm/tcg/translate-vfp.c| 4 +-
target/arm/tcg/translate.c| 20 ++---
target/avr/translate.c| 1 -
target/cris/translate.c | 2 -
target/hppa/translate.c | 5 +-
target/i386/tcg/translate.c | 52 +++--
target/loongarch/translate.c | 2 -
target/m68k/translate.c | 2 -
target/microblaze/translate.c | 2 -
target/mips/tcg/translate.c | 29 +++
target/nios2/translate.c | 1 -
target/openrisc/translate.c | 9 +--
target/ppc/translate.c| 13 +---
target/riscv/translate.c | 2 -
target/rx/translate.c | 2 -
target/s390x/tcg/translate.c | 6 +-
target/sh4/translate.c| 2 -
target/sparc/translate.c | 75 +--
target/tricore/translate.c| 2 -
target/xtensa/translate.c | 27 ++-
target/loongarch/insn_trans/trans_extra.c.inc | 4 +-
.../insn_trans/trans_privileged.c.inc | 4 +-
.../riscv/insn_trans/trans_privileged.c.inc | 8 +-
target/riscv/insn_trans/trans_rvi.c.inc | 24 ++
33 files changed, 117 insertions(+), 269 deletions(-)
delete mode 100644 include/exec/gen-icount.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2366f64d3d..55668d6336 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2867,7 +2867,6 @@ F: ui/cocoa.m
Main loop
M: Paolo Bonzini
S: Maintained
-F: include/exec/gen-icount.h
F: include/qemu/main-loop.h
F: include/sysemu/runstate.h
F: include/sysemu/runstate-action.h
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
deleted file mode 100644
index 6006af4c06..00
--- a/include/exec/gen-icount.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef GEN_ICOUNT_H
-#define GEN_ICOUNT_H
-
-void gen_io_start(void);
-
-#endif
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 797fef7515..c1a1203789 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -160,6 +160,16 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,
int *max_insns,
*/
bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
+/**
+ * translator_io_start
+ * @db: Disassembly context
+ *
+ * If icount is enabled, set cpu->can_to_io, adjust db->is_jmp to
+ * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true.
+ * Otherwise return false.
+ */
+bool translator_io_start(DisasContextBase *db);
+
/*
* Translator Load Functions
*
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index b04d344a9f..14785686f6 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -67,8 +67,8 @@ enum {
ARM_CP_ALIAS = 1 << 8,
/*
* Flag: Register does I/O and therefore its accesses need to be marked
- * with gen_io_start() and also end the TB. In particular, registers which
- * implement clocks or timers require this.
+ * with translator_io_start() and also end the TB. In particular,
+ * registers which implement clocks or timers require this.
*/
ARM_CP_IO= 1 << 9,
/*
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index b0d0015c70..7a130e706e 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -12,20 +12,43 @@
#include "tcg/tcg.h"
#include "tcg/tcg-op.h"
#include "exec/exec-all.h"
-#include "exec/gen-icount.h"
#include "exec/log.h"
#include "exec/translator.h"
#include "exec/plugin-gen.h"
#include "exec/replay-core.h"
-void gen_io_start(void)
+static void gen_io_start(void)
{
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
offsetof(ArchCPU, parent_obj.can_do_io) -
offsetof(ArchCPU, env));
}
+bool translator_io_start(DisasContextBase *db)
+{
+uint32_t cflags = tb_cflags(db->tb);
+
+if (!(cflags & CF_USE_ICOUNT)) {
+return false;
+}
+if (db->num_insns == db->max_insns && (cflags & CF_LAST_IO)) {
+/* Already started in translator_loop. */
+return true;
+}
+
+
[PULL 08/52] target/avr: Add missing includes of qemu/error-report.h
This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/avr/helper.c b/target/avr/helper.c index 156dde4e92..2bad242a66 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" -- 2.34.1
[PULL 18/52] tcg: Remove outdated comments in helper-head.h
Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index f863a6ef5d..a355ef8ebe 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -1,18 +1,6 @@ -/* Helper file for declaring TCG helper functions. - Used by other helper files. - - Targets should use DEF_HELPER_N and DEF_HELPER_FLAGS_N to declare helper - functions. Names should be specified without the helper_ prefix, and - the return and argument types specified. 3 basic types are understood - (i32, i64 and ptr). Additional aliases are provided for convenience and - to match the types used by the C helper implementation. - - The target helper.h should be included in all files that use/define - helper functions. THis will ensure that function prototypes are - consistent. In addition it should be included an extra two times for - helper.c, defining: -GEN_HELPER 1 to produce op generation functions (gen_helper_*) -GEN_HELPER 2 to do runtime registration helper functions. +/* + * Helper file for declaring TCG helper functions. + * Used by other helper files. */ #ifndef EXEC_HELPER_HEAD_H -- 2.34.1
[PULL 31/52] exec-all: Widen tb_page_addr_t for user-only
This is a step toward making TranslationBlock agnostic to the address size of the guest. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 3b1b57f6ad..ec0902c532 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,8 @@ addresses in userspace mode. Define tb_page_addr_t to be an appropriate type. */ #if defined(CONFIG_USER_ONLY) -typedef abi_ulong tb_page_addr_t; -#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx +typedef vaddr tb_page_addr_t; +#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx #else typedef ram_addr_t tb_page_addr_t; #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT -- 2.34.1
[PULL 41/52] target/*: Add missing includes of exec/translation-block.h
This had been pulled in via exec/exec-all.h, via exec/translator.h, but the include of exec-all.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/translate.c | 1 + target/loongarch/translate.c | 3 +-- target/mips/tcg/translate.c | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 770de58647..708339198e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -22,6 +22,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 1cf27a4611..3146a2d4ac 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -9,11 +9,10 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" - +#include "exec/translation-block.h" #include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu/softfloat.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index f3da05ba3b..74af91e4f5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -26,6 +26,7 @@ #include "translate.h" #include "internal.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "semihosting/semihost.h" #include "trace.h" #include "disas/disas.h" -- 2.34.1
[PULL 00/52] tcg patch queue
The following changes since commit b52daaf2c868f2bab102eb5acbf55b2917f46aea: Merge tag 'pull-block-2023-06-05' of https://gitlab.com/hreitz/qemu into staging (2023-06-05 10:27:31 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230605 for you to fetch changes up to a7f6911c127b1dd1b8764e03b0ebcf0a227a15e4: tcg/tcg-op-vec: Remove left over _link_error() definitions (2023-06-05 12:20:16 -0700) Build tcg/ once for system and once for user. Unmap perf_marker. Remove left over _link_error() definitions. Ilya Leoshkevich (1): accel/tcg: Unmap perf_marker Philippe Mathieu-Daudé (2): target/ppc: Inline gen_icount_io_start() tcg/tcg-op-vec: Remove left over _link_error() definitions Richard Henderson (49): tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h tcg: Widen CPUTLBEntry comparators to 64-bits tcg: Add tlb_fast_offset to TCGContext target/avr: Add missing includes of qemu/error-report.h target/*: Add missing includes of tcg/debug-assert.h *: Add missing includes of tcg/tcg.h tcg: Split out tcg-target-reg-bits.h target/arm: Fix test of TCG_OVERSIZED_GUEST tcg: Split out tcg/oversized-guest.h tcg: Move TCGv, dup_const_tl definitions to tcg-op.h tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h target/arm: Include helper-gen.h in translator.h target/hexagon: Include helper-gen.h where needed tcg: Remove outdated comments in helper-head.h tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h tcg: Pass TCGHelperInfo to tcg_gen_callN tcg: Move temp_idx and tcgv_i32_temp debug out of line tcg: Split tcg_gen_callN tcg: Split helper-gen.h tcg: Split helper-proto.h target/sh4: Emit insn_start for each insn in gUSA region tcg: Add insn_start_words to TCGContext tcg: Add guest_mo to TCGContext tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits tcg: Split tcg/tcg-op-gvec.h tcg: Remove NO_CPU_IO_DEFS exec-all: Widen tb_page_addr_t for user-only exec-all: Widen TranslationBlock pc and cs_base to 64-bits tcg: Spit out exec/translation-block.h include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE accel/tcg: Move most of gen-icount.h into translator.c accel/tcg: Introduce translator_io_start accel/tcg: Move translator_fake_ldb out of line target/arm: Tidy helpers for translation target/mips: Tidy helpers for translation target/*: Add missing includes of exec/translation-block.h target/arm: Add missing include of exec/exec-all.h accel/tcg: Tidy includes for translator.[ch] tcg: Fix PAGE/PROT confusion tcg: Move env defines out of NEED_CPU_H in helper-head.h tcg: Remove target-specific headers from tcg.[ch] plugins: Move plugin_insn_append to translator.c plugins: Drop unused headers from exec/plugin-gen.h exec/poison: Do not poison CONFIG_SOFTMMU tcg: Build once for system and once for user-only MAINTAINERS|3 +- include/exec/cpu-all.h |3 + include/exec/cpu-defs.h| 50 +- include/exec/cpu_ldst.h| 22 +- include/exec/exec-all.h| 142 +-- include/exec/gen-icount.h | 83 -- include/exec/helper-gen-common.h | 18 + include/exec/helper-gen.h | 97 +- include/exec/helper-head.h | 24 +- include/exec/helper-proto-common.h | 18 + include/exec/helper-proto.h| 73 +- include/exec/helper-tcg.h | 75 -- include/exec/plugin-gen.h | 24 - include/exec/poison.h |1 - include/exec/tlb-common.h | 56 ++ include/exec/translation-block.h | 149 +++ include/exec/translator.h | 24 +- include/qemu/typedefs.h|1 + include/tcg/helper-info.h | 64 ++ include/tcg/insn-start-words.h | 17 + include/tcg/oversized-guest.h | 23 + include/tcg/tcg-op-common.h| 996 +++ include/tcg/tcg-op-gvec-common.h | 426 include/tcg/tcg-op-gvec.h | 444 + include/tcg/tcg-op.h | 1033
[PULL 29/52] tcg: Split tcg/tcg-op-gvec.h
Create tcg/tcg-op-gvec-common.h, moving everything that does not
concern TARGET_LONG_BITS. Adjust tcg-op-gvec.c to use the new header.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 426 +
include/tcg/tcg-op-gvec.h| 444 +--
tcg/tcg-op-gvec.c| 2 +-
3 files changed, 437 insertions(+), 435 deletions(-)
create mode 100644 include/tcg/tcg-op-gvec-common.h
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h
new file mode 100644
index 00..e2683d487f
--- /dev/null
+++ b/include/tcg/tcg-op-gvec-common.h
@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Target independent generic vector operation expansion
+ *
+ * Copyright (c) 2018 Linaro
+ */
+
+#ifndef TCG_TCG_OP_GVEC_COMMON_H
+#define TCG_TCG_OP_GVEC_COMMON_H
+
+/*
+ * "Generic" vectors. All operands are given as offsets from ENV,
+ * and therefore cannot also be allocated via tcg_global_mem_new_*.
+ * OPRSZ is the byte size of the vector upon which the operation is performed.
+ * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
+ *
+ * All sizes must be 8 or any multiple of 16.
+ * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
+ * Operands may completely, but not partially, overlap.
+ */
+
+/* Expand a call to a gvec-style helper, with pointers to two vector
+ operands, and a descriptor (see tcg-gvec-desc.h). */
+typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
+uint32_t oprsz, uint32_t maxsz, int32_t data,
+gen_helper_gvec_2 *fn);
+
+/* Similarly, passing an extra data value. */
+typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32);
+void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2i *fn);
+
+/* Similarly, passing an extra pointer (e.g. env or float_status). */
+typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
+TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+int32_t data, gen_helper_gvec_2_ptr *fn);
+
+/* Similarly, with three vector operands. */
+typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+uint32_t oprsz, uint32_t maxsz, int32_t data,
+gen_helper_gvec_3 *fn);
+
+/* Similarly, with four vector operands. */
+typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
+int32_t data, gen_helper_gvec_4 *fn);
+
+/* Similarly, with five vector operands. */
+typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+uint32_t cofs, uint32_t xofs, uint32_t oprsz,
+uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
+
+typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+int32_t data, gen_helper_gvec_3_ptr *fn);
+
+typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
+uint32_t maxsz, int32_t data,
+gen_helper_gvec_4_ptr *fn);
+
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
+uint32_t oprsz, uint32_t maxsz, int32_t data,
+gen_helper_gvec_5_ptr *fn);
+
+/* Expand a gvec operation. Either inline or out-of-line depending on
+ the actual vector size and the operations supported by the host. */
+typedef struct {
+/* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+void (*fni8)(TCGv_i64, TCGv_i64);
+void (*fni4)(TCGv_i32, TCGv_i32);
+/* Expand inline
[PULL 03/52] tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses replaced with TCGContext.addr_type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 503126cd66..2795242b60 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -1745,6 +1745,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
TCGReg addr_reg, MemOpIdx oi,
bool is_ld)
{
+TCGType addr_type = s->addr_type;
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
@@ -1786,7 +1787,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask);
} else {
tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off);
-tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask);
+tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask);
}
if (is_ld) {
@@ -1794,7 +1795,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
} else {
ofs = offsetof(CPUTLBEntry, addr_write);
}
-if (TARGET_LONG_BITS == 32) {
+if (addr_type == TCG_TYPE_I32) {
tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
} else {
tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
@@ -1807,7 +1808,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE,
offsetof(CPUTLBEntry, addend));
-if (TARGET_LONG_BITS == 32) {
+if (addr_type == TCG_TYPE_I32) {
tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg);
h->base = TCG_REG_NONE;
} else {
@@ -1830,7 +1831,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
}
h->base = addr_reg;
-if (TARGET_LONG_BITS == 32) {
+if (addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_TMP0, addr_reg);
h->base = TCG_TMP0;
}
--
2.34.1
[PULL 26/52] tcg: Add insn_start_words to TCGContext
This will enable replacement of TARGET_INSN_START_WORDS in tcg.c.
Split out "tcg/insn-start-words.h" and use it in target/.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/tcg/insn-start-words.h | 17 +
include/tcg/tcg-op.h | 8
include/tcg/tcg-opc.h | 6 +++---
include/tcg/tcg.h | 9 ++---
accel/tcg/perf.c | 8 ++--
accel/tcg/translate-all.c | 20 +---
target/i386/helper.c | 2 +-
target/openrisc/sys_helper.c | 2 +-
tcg/tcg.c | 16 +++-
9 files changed, 58 insertions(+), 30 deletions(-)
create mode 100644 include/tcg/insn-start-words.h
diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
new file mode 100644
index 00..50c18bd326
--- /dev/null
+++ b/include/tcg/insn-start-words.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define TARGET_INSN_START_WORDS
+ * Copyright (c) 2008 Fabrice Bellard
+ */
+
+#ifndef TARGET_INSN_START_WORDS
+
+#include "cpu.h"
+
+#ifndef TARGET_INSN_START_EXTRA_WORDS
+# define TARGET_INSN_START_WORDS 1
+#else
+# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
+#endif
+
+#endif /* TARGET_INSN_START_WORDS */
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 47f1dce816..d63683c47b 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -22,20 +22,20 @@
# error
#endif
-#if TARGET_INSN_START_WORDS == 1
+#ifndef TARGET_INSN_START_EXTRA_WORDS
static inline void tcg_gen_insn_start(target_ulong pc)
{
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
tcg_set_insn_start_param(op, 0, pc);
}
-#elif TARGET_INSN_START_WORDS == 2
+#elif TARGET_INSN_START_EXTRA_WORDS == 1
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
{
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS);
tcg_set_insn_start_param(op, 0, pc);
tcg_set_insn_start_param(op, 1, a1);
}
-#elif TARGET_INSN_START_WORDS == 3
+#elif TARGET_INSN_START_EXTRA_WORDS == 2
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
target_ulong a2)
{
@@ -45,7 +45,7 @@ static inline void tcg_gen_insn_start(target_ulong pc,
target_ulong a1,
tcg_set_insn_start_param(op, 2, a2);
}
#else
-# error "Unhandled number of operands to insn_start"
+#error Unhandled TARGET_INSN_START_EXTRA_WORDS value
#endif
#if TARGET_LONG_BITS == 32
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 21594c1590..acfa5ba753 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -188,9 +188,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 |
IMPL(TCG_TARGET_HAS_mulsh_i64))
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
-/* QEMU specific */
-DEF(insn_start, 0, 0, DATA64_ARGS * TARGET_INSN_START_WORDS,
-TCG_OPF_NOT_PRESENT)
+/* There are tcg_ctx->insn_start_words here, not just one. */
+DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT)
+
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 7c1bbba673..813c733910 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -173,12 +173,6 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_v256 0
#endif
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
-# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
-
typedef enum TCGOpcode {
#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
#include "tcg/tcg-opc.h"
@@ -526,6 +520,7 @@ struct TCGContext {
uint8_t page_bits;
uint8_t tlb_dyn_max_bits;
#endif
+uint8_t insn_start_words;
TCGRegSet reserved_regs;
intptr_t current_frame_offset;
@@ -597,7 +592,7 @@ struct TCGContext {
TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
uint16_t gen_insn_end_off[TCG_MAX_INSNS];
-uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
+uint64_t *gen_insn_data;
/* Exit to translator on overflow. */
sigjmp_buf jmp_trans;
diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c
index 65e35ea3b9..f5a1eda39f 100644
--- a/accel/tcg/perf.c
+++ b/accel/tcg/perf.c
@@ -311,7 +311,8 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock
*tb,
const void *start)
{
struct debuginfo_query *q;
-size_t insn;
+size_t insn, start_words;
+uint64_t *gen_insn_data;
if (!perfmap && !jitdump) {
return;
@@ -325,9 +326,12 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock
*tb,
debuginfo_lock();
/* Query debuginfo for each guest instruction. */
+gen_insn_data = tcg_ctx->gen_insn_data;
+start_words = tcg_ctx->insn_start_words;
+
for (insn = 0; insn <
[PULL 44/52] tcg: Fix PAGE/PROT confusion
The bug was hidden because they happen to have the same values.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/region.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index bef4c4756f..f8410ba5db 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -505,6 +505,14 @@ static int alloc_code_gen_buffer(size_t tb_size, int
splitwx, Error **errp)
return PROT_READ | PROT_WRITE;
}
#elif defined(_WIN32)
+/*
+ * Local source-level compatibility with Unix.
+ * Used by tcg_region_init below.
+ */
+#define PROT_READ 1
+#define PROT_WRITE 2
+#define PROT_EXEC 4
+
static int alloc_code_gen_buffer(size_t size, int splitwx, Error **errp)
{
void *buf;
@@ -525,7 +533,7 @@ static int alloc_code_gen_buffer(size_t size, int splitwx,
Error **errp)
region.start_aligned = buf;
region.total_size = size;
-return PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+return PROT_READ | PROT_WRITE | PROT_EXEC;
}
#else
static int alloc_code_gen_buffer_anon(size_t size, int prot,
@@ -794,10 +802,10 @@ void tcg_region_init(size_t tb_size, int splitwx,
unsigned max_cpus)
* buffer -- let that one use hugepages throughout.
* Work with the page protections set up with the initial mapping.
*/
-need_prot = PAGE_READ | PAGE_WRITE;
+need_prot = PROT_READ | PROT_WRITE;
#ifndef CONFIG_TCG_INTERPRETER
if (tcg_splitwx_diff == 0) {
-need_prot |= PAGE_EXEC;
+need_prot |= PROT_EXEC;
}
#endif
for (size_t i = 0, n = region.n; i < n; i++) {
@@ -807,9 +815,9 @@ void tcg_region_init(size_t tb_size, int splitwx, unsigned
max_cpus)
if (have_prot != need_prot) {
int rc;
-if (need_prot == (PAGE_READ | PAGE_WRITE | PAGE_EXEC)) {
+if (need_prot == (PROT_READ | PROT_WRITE | PROT_EXEC)) {
rc = qemu_mprotect_rwx(start, end - start);
-} else if (need_prot == (PAGE_READ | PAGE_WRITE)) {
+} else if (need_prot == (PROT_READ | PROT_WRITE)) {
rc = qemu_mprotect_rw(start, end - start);
} else {
g_assert_not_reached();
--
2.34.1
[PULL 20/52] tcg: Pass TCGHelperInfo to tcg_gen_callN
In preparation for compiling tcg/ only once, eliminate
the all_helpers array. Instantiate the info structs for
the generic helpers in accel/tcg/, and the structs for
the target-specific helpers in each translate.c.
Since we don't see all of the info structs at startup,
initialize at first use, using g_once_init_* to make
sure we don't race while doing so.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
MAINTAINERS| 1 +
include/exec/helper-gen.h | 66
include/exec/helper-tcg.h | 75 ---
include/qemu/typedefs.h| 1 +
include/tcg/helper-info.h | 9 ++-
include/tcg/tcg.h | 2 +-
accel/tcg/plugin-gen.c | 5 ++
accel/tcg/tcg-runtime.c| 4 ++
target/alpha/translate.c | 3 +
target/arm/tcg/translate.c | 3 +
target/avr/translate.c | 5 ++
target/cris/translate.c| 6 +-
target/hexagon/translate.c | 4 ++
target/hppa/translate.c| 5 ++
target/i386/tcg/translate.c| 5 ++
target/loongarch/translate.c | 4 ++
target/m68k/translate.c| 3 +
target/microblaze/translate.c | 4 ++
target/mips/tcg/translate.c| 5 ++
target/nios2/translate.c | 5 ++
target/openrisc/translate.c| 5 ++
target/ppc/translate.c | 4 ++
target/riscv/translate.c | 4 ++
target/rx/translate.c | 5 ++
target/s390x/tcg/translate.c | 4 ++
target/sh4/translate.c | 4 ++
target/sparc/translate.c | 3 +
target/tricore/translate.c | 5 ++
target/xtensa/translate.c | 4 ++
tcg/tcg.c | 108 -
include/exec/helper-info.c.inc | 96 +
31 files changed, 282 insertions(+), 175 deletions(-)
delete mode 100644 include/exec/helper-tcg.h
create mode 100644 include/exec/helper-info.c.inc
diff --git a/MAINTAINERS b/MAINTAINERS
index 89f274f85e..a1b8376f4c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -154,6 +154,7 @@ F: include/exec/exec-all.h
F: include/exec/tb-flush.h
F: include/exec/target_long.h
F: include/exec/helper*.h
+F: include/exec/helper-info.c.inc
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
F: include/hw/core/tcg-cpu-ops.h
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index 7b6ca975ef..248cff3351 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -1,81 +1,96 @@
-/* Helper file for declaring TCG helper functions.
- This one expands generation functions for tcg opcodes. */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Helper file for declaring TCG helper functions.
+ * This one expands generation functions for tcg opcodes.
+ * Define HELPER_H for the header file to be expanded,
+ * and static inline to change from global file scope.
+ */
#ifndef HELPER_GEN_H
#define HELPER_GEN_H
+#include "tcg/tcg.h"
+#include "tcg/helper-info.h"
#include "exec/helper-head.h"
#define DEF_HELPER_FLAGS_0(name, flags, ret)\
+extern TCGHelperInfo glue(helper_info_, name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret))\
{ \
- tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \
+tcg_gen_callN((helper_info_, name), dh_retvar(ret), 0, NULL); \
}
#define DEF_HELPER_FLAGS_1(name, flags, ret, t1)\
+extern TCGHelperInfo glue(helper_info_, name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1)) \
{ \
- TCGTemp *args[1] = { dh_arg(t1, 1) }; \
- tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \
+TCGTemp *args[1] = { dh_arg(t1, 1) }; \
+tcg_gen_callN((helper_info_, name), dh_retvar(ret), 1, args); \
}
#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2)\
+extern TCGHelperInfo glue(helper_info_, name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \
{ \
- TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \
- tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \
+TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) };\
+tcg_gen_callN((helper_info_, name), dh_retvar(ret), 2, args); \
}
#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3)\
+extern TCGHelperInfo glue(helper_info_, name); \
static inline void
[PULL 07/52] tcg: Add tlb_fast_offset to TCGContext
Disconnect the layout of ArchCPU from TCG compilation.
Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 39 +-
include/exec/tlb-common.h| 56
include/tcg/tcg.h| 1 +
accel/tcg/translate-all.c| 2 ++
tcg/tcg.c| 13
tcg/aarch64/tcg-target.c.inc | 7 ++--
tcg/arm/tcg-target.c.inc | 7 ++--
tcg/i386/tcg-target.c.inc| 9 ++---
tcg/loongarch64/tcg-target.c.inc | 7 ++--
tcg/mips/tcg-target.c.inc| 7 ++--
tcg/ppc/tcg-target.c.inc | 7 ++--
tcg/riscv/tcg-target.c.inc | 7 ++--
tcg/s390x/tcg-target.c.inc | 7 ++--
tcg/sparc64/tcg-target.c.inc | 7 ++--
14 files changed, 110 insertions(+), 66 deletions(-)
create mode 100644 include/exec/tlb-common.h
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index b757d37966..0d418a0384 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -61,12 +61,11 @@
#define NB_MMU_MODES 16
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#include "exec/tlb-common.h"
/* use a fully associative victim tlb of 8 entries */
#define CPU_VTLB_SIZE 8
-#define CPU_TLB_ENTRY_BITS 5
-
#define CPU_TLB_DYN_MIN_BITS 6
#define CPU_TLB_DYN_DEFAULT_BITS 8
@@ -90,27 +89,6 @@
# endif
# endif
-/* Minimalized TLB entry for use by TCG fast path. */
-typedef union CPUTLBEntry {
-struct {
-uint64_t addr_read;
-uint64_t addr_write;
-uint64_t addr_code;
-/*
- * Addend to virtual address to get host address. IO accesses
- * use the corresponding iotlb value.
- */
-uintptr_t addend;
-};
-/*
- * Padding to get a power of two size, as well as index
- * access to addr_{read,write,code}.
- */
-uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
-} CPUTLBEntry;
-
-QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
-
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
#if !defined(CONFIG_USER_ONLY)
@@ -184,17 +162,6 @@ typedef struct CPUTLBDesc {
CPUTLBEntryFull *fulltlb;
} CPUTLBDesc;
-/*
- * Data elements that are per MMU mode, accessed by the fast path.
- * The structure is aligned to aid loading the pair with one insn.
- */
-typedef struct CPUTLBDescFast {
-/* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
-uintptr_t mask;
-/* The array of tlb entries itself. */
-CPUTLBEntry *table;
-} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
-
/*
* Data elements that are shared between all MMU modes.
*/
@@ -230,10 +197,6 @@ typedef struct CPUTLB {
CPUTLBDescFast f[NB_MMU_MODES];
} CPUTLB;
-/* This will be used by TCG backends to compute offsets. */
-#define TLB_MASK_TABLE_OFS(IDX) \
-((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env))
-
#else
typedef struct CPUTLB { } CPUTLB;
diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h
new file mode 100644
index 00..dc5a5faa0b
--- /dev/null
+++ b/include/exec/tlb-common.h
@@ -0,0 +1,56 @@
+/*
+ * Common definitions for the softmmu tlb
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
[PULL 28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits
The replacement isn't ideal, as the raw count of bits
is not easily synced with exec/cpu-all.h, but it does
remove from tcg.h the target dependency on TARGET_PAGE_BITS_MIN
which is built into TLB_FLAGS_MASK.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 3 +++
include/tcg/tcg.h | 4
tcg/tcg-op-ldst.c | 18 --
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 78d258af44..09bf4c0cc6 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -314,6 +314,9 @@ CPUArchState *cpu_copy(CPUArchState *env);
*
* Use TARGET_PAGE_BITS_MIN so that these bits are constant
* when TARGET_PAGE_BITS_VARY is in effect.
+ *
+ * The count, if not the placement of these bits is known
+ * to tcg/tcg-op-ldst.c, check_max_alignment().
*/
/* Zero if TLB entry is valid. */
#define TLB_INVALID_MASK(1 << (TARGET_PAGE_BITS_MIN - 1))
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 9f607e2664..635fa53fdb 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -305,10 +305,6 @@ static inline unsigned get_alignment_bits(MemOp memop)
/* A specific alignment requirement. */
a = a >> MO_ASHIFT;
}
-#if defined(CONFIG_SOFTMMU)
-/* The requested alignment cannot overlap the TLB flags. */
-tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
-#endif
return a;
}
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index 9bcf63b041..46a5977b35 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -32,11 +32,23 @@
#include "tcg-internal.h"
-static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
+static void check_max_alignment(unsigned a_bits)
+{
+#if defined(CONFIG_SOFTMMU)
+/*
+ * The requested alignment cannot overlap the TLB flags.
+ * FIXME: Must keep the count up-to-date with "exec/cpu-all.h".
+ */
+tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits);
+#endif
+}
+
+static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
{
-/* Trigger the asserts within as early as possible. */
unsigned a_bits = get_alignment_bits(op);
+check_max_alignment(a_bits);
+
/* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */
if (a_bits == (op & MO_SIZE)) {
op = (op & ~MO_AMASK) | MO_ALIGN;
@@ -491,6 +503,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp
*addr,
TCGv_i64 ext_addr = NULL;
TCGOpcode opc;
+check_max_alignment(get_alignment_bits(memop));
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
/* TODO: For now, force 32-bit hosts to use the helper. */
@@ -599,6 +612,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp
*addr,
TCGv_i64 ext_addr = NULL;
TCGOpcode opc;
+check_max_alignment(get_alignment_bits(memop));
tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST);
/* TODO: For now, force 32-bit hosts to use the helper. */
--
2.34.1
[PULL 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits
This makes CPUTLBEntry agnostic to the address size of the guest.
When 32-bit addresses are in effect, we can simply read the low
32 bits of the 64-bit field. Similarly when we need to update
the field for setting TLB_NOTDIRTY.
For TCG backends that could in theory be big-endian, but in
practice are not (arm, loongarch, riscv), use QEMU_BUILD_BUG_ON
to document and ensure this is not accidentally missed.
For s390x, which is always big-endian, use HOST_BIG_ENDIAN anyway,
to document the reason for the adjustment.
For sparc64 and ppc64, always perform a 64-bit load, and rely on
the following 32-bit comparison to ignore the high bits.
Rearrange mips and ppc if ladders for clarity.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 37 +++-
include/exec/cpu_ldst.h | 19 ++--
accel/tcg/cputlb.c | 8 +--
tcg/aarch64/tcg-target.c.inc | 1 +
tcg/arm/tcg-target.c.inc | 1 +
tcg/loongarch64/tcg-target.c.inc | 1 +
tcg/mips/tcg-target.c.inc| 13 ++-
tcg/ppc/tcg-target.c.inc | 28 +---
tcg/riscv/tcg-target.c.inc | 1 +
tcg/s390x/tcg-target.c.inc | 1 +
tcg/sparc64/tcg-target.c.inc | 8 +--
11 files changed, 67 insertions(+), 51 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index a6e0cf1812..b757d37966 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -65,11 +65,7 @@
/* use a fully associative victim tlb of 8 entries */
#define CPU_VTLB_SIZE 8
-#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
-#define CPU_TLB_ENTRY_BITS 4
-#else
#define CPU_TLB_ENTRY_BITS 5
-#endif
#define CPU_TLB_DYN_MIN_BITS 6
#define CPU_TLB_DYN_DEFAULT_BITS 8
@@ -95,33 +91,26 @@
# endif
/* Minimalized TLB entry for use by TCG fast path. */
-typedef struct CPUTLBEntry {
-/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
- bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
-go directly to ram.
- bit 3 : indicates that the entry is invalid
- bit 2..0 : zero
-*/
-union {
-struct {
-target_ulong addr_read;
-target_ulong addr_write;
-target_ulong addr_code;
-/* Addend to virtual address to get host address. IO accesses
- use the corresponding iotlb value. */
-uintptr_t addend;
-};
+typedef union CPUTLBEntry {
+struct {
+uint64_t addr_read;
+uint64_t addr_write;
+uint64_t addr_code;
/*
- * Padding to get a power of two size, as well as index
- * access to addr_{read,write,code}.
+ * Addend to virtual address to get host address. IO accesses
+ * use the corresponding iotlb value.
*/
-target_ulong addr_idx[(1 << CPU_TLB_ENTRY_BITS) / TARGET_LONG_SIZE];
+uintptr_t addend;
};
+/*
+ * Padding to get a power of two size, as well as index
+ * access to addr_{read,write,code}.
+ */
+uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
} CPUTLBEntry;
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
-
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
#if !defined(CONFIG_USER_ONLY)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 5939688f69..a43b34e46b 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -334,18 +334,25 @@ static inline target_ulong tlb_read_idx(const CPUTLBEntry
*entry,
{
/* Do not rearrange the CPUTLBEntry structure members. */
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
- MMU_DATA_LOAD * TARGET_LONG_SIZE);
+ MMU_DATA_LOAD * sizeof(uint64_t));
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
- MMU_DATA_STORE * TARGET_LONG_SIZE);
+ MMU_DATA_STORE * sizeof(uint64_t));
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
- MMU_INST_FETCH * TARGET_LONG_SIZE);
+ MMU_INST_FETCH * sizeof(uint64_t));
-const target_ulong *ptr = >addr_idx[access_type];
-#if TCG_OVERSIZED_GUEST
-return *ptr;
+#if TARGET_LONG_BITS == 32
+/* Use qatomic_read, in case of addr_write; only care about low bits. */
+const uint32_t *ptr = (uint32_t *)>addr_idx[access_type];
+ptr += HOST_BIG_ENDIAN;
+return qatomic_read(ptr);
#else
+const uint64_t *ptr = >addr_idx[access_type];
+# if TCG_OVERSIZED_GUEST
+return *ptr;
+# else
/* ofs might correspond to .addr_write, so use qatomic_read */
return qatomic_read(ptr);
+# endif
#endif
}
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 90c72c9940..6beaeb0a81 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1000,11 +1000,15 @@
