From: Hyman Huang(黄勇)
Implement dirty-limit convergence algo for live migration,
which is kind of like auto-converge algo but using dirty-limit
instead of cpu throttle to make migration convergent.
Enable dirty page limit if dirty_rate_high_cnt greater than 2
when dirty-limit capability
From: Hyman Huang(黄勇)
dirty_rate paraemter of hmp command "set_vcpu_dirty_limit" is invalid
if less than 0, so add parameter check for it.
Note that this patch also delete the unsolicited help message and
clean up the code.
Signed-off-by: Hyman Huang(黄勇)
Reviewed-by: Markus Armbruster
From: Hyman Huang(黄勇)
Add migration dirty-limit capability test if kernel support
dirty ring.
Migration dirty-limit capability introduce dirty limit
capability, two parameters: x-vcpu-dirty-limit-period and
vcpu-dirty-limit are introduced to implement the live
migration with dirty limit.
The
Hi, Juan, this version maybe the last version,
i rebase on master and fix the conflicts with
the switchover-ack capability. Please be free
to the take this version to make PR or the
previous version if you already fixed conflicts.
v7:
1. Rebase on master and fix conflicts
v6:
1. Rebase on
From: Hyman Huang(黄勇)
Introduce "vcpu-dirty-limit" migration parameter used
to limit dirty page rate during live migration.
"vcpu-dirty-limit" and "x-vcpu-dirty-limit-period" are
two dirty-limit-related migration parameters, which can
be set before and during live migration by qmp
From: Hyman Huang(黄勇)
Introduce migration dirty-limit capability, which can
be turned on before live migration and limit dirty
page rate durty live migration.
Introduce migrate_dirty_limit function to help check
if dirty-limit capability enabled during live migration.
Meanwhile, refactor
From: Hyman Huang(黄勇)
Check if block migration is running before throttling
guest down in auto-converge way.
Note that this modification is kind of like code clean,
because block migration does not depend on auto-converge
capability, so the order of checks can be adjusted.
Signed-off-by: Hyman
From: Hyman Huang(黄勇)
Extend query-migrate to provide throttle time and estimated
ring full time with dirty-limit capability enabled, through which
we can observe if dirty limit take effect during live migration.
Signed-off-by: Hyman Huang(黄勇)
Reviewed-by: Markus Armbruster
Reviewed-by: Juan
From: Hyman Huang(黄勇)
This commit is prepared for the implementation of dirty-limit
convergence algo.
The detection logic of throttling condition can apply to both
auto-converge and dirty-limit algo, putting it's position
before the checking logic for auto-converge feature.
Signed-off-by:
From: Hyman Huang(黄勇)
Introduce "x-vcpu-dirty-limit-period" migration experimental
parameter, which is in the range of 1 to 1000ms and used to
make dirtyrate calculation period configurable.
Currently with the "x-vcpu-dirty-limit-period" varies, the
total time of live migration changes, test
> On 05-Jul-2023, at 7:09 AM, Akihiko Odaki wrote:
>
>
>
> On 2023/07/05 0:07, Ani Sinha wrote:
>>> On 04-Jul-2023, at 7:58 PM, Igor Mammedov wrote:
>>>
>>> On Tue, 4 Jul 2023 19:20:00 +0530
>>> Ani Sinha wrote:
>>>
> On 04-Jul-2023, at 6:18 PM, Igor Mammedov wrote:
>
> On
Reviewed-by: Frank Chang
On Tue, Jul 4, 2023 at 4:41 PM Jason Chien wrote:
> RVA23 Profiles states:
> The RVA23 profiles are intended to be used for 64-bit application
> processors that will run rich OS stacks from standard binary OS
> distributions and with a substantial number of third-party
On 7/4/23 18:20, Peter Maydell wrote:
If you build QEMU with the clang UB sanitizer and do a
'make check-tcg' run, it can fail like this:
TESTvma-pthread-with-libinsn.so on aarch64
../../util/interval-tree.c:751:32: runtime error: member access within
null pointer of type
On 7/5/23 06:57, Richard Henderson wrote:
On 7/4/23 18:36, Peter Maydell wrote:
docs/system/arm/sbsa.rst | 5 +-
hw/arm/sbsa-ref.c | 23 +++--
hw/misc/allwinner-sramc.c | 1 +
target/arm/cpu.c | 65 -
target/arm/gdbstub.c
On 7/4/23 18:36, Peter Maydell wrote:
docs/system/arm/sbsa.rst | 5 +-
hw/arm/sbsa-ref.c | 23 +++--
hw/misc/allwinner-sramc.c | 1 +
target/arm/cpu.c | 65 -
target/arm/gdbstub.c | 4 +
target/arm/helper.c
>-Original Message-
>From: Eric Auger
>Sent: Tuesday, July 4, 2023 7:15 PM
>To: eric.auger@gmail.com; eric.au...@redhat.com; qemu-
>de...@nongnu.org; qemu-...@nongnu.org; m...@redhat.com; jean-
>phili...@linaro.org; Duan, Zhenzhong
>Cc: alex.william...@redhat.com; c...@redhap.com;
On 7/4/23 18:36, Peter Maydell wrote:
+int main(int argc, char **argv)
+{
+const char *shm_name = "qemu-test-tcg-aarch64-icivau";
+int fd;
+
+fd = shm_open(shm_name, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR);
Build failures:
https://gitlab.com/qemu-project/qemu/-/jobs/4592433393#L3958
Hi Eric,
>-Original Message-
>From: Eric Auger
>Sent: Tuesday, July 4, 2023 7:15 PM
>Subject: [PATCH 1/2] virtio-iommu: Fix 64kB host page size VFIO device
>assignment
>
>When running on a 64kB page size host and protecting a VFIO device
>with the virtio-iommu, qemu crashes with this
On Tue Jul 4, 2023 at 1:06 AM AEST, BALATON Zoltan wrote:
> On Mon, 3 Jul 2023, Nicholas Piggin wrote:
> > On Mon Jul 3, 2023 at 10:26 PM AEST, BALATON Zoltan wrote:
> >> On Mon, 3 Jul 2023, Nicholas Piggin wrote:
> >>> checkstop state does not halt the system, interrupts continue to be
> >>>
On 2023/07/04 23:03, Ani Sinha wrote:
On 04-Jul-2023, at 5:20 PM, Akihiko Odaki wrote:
On 2023/07/04 20:38, Igor Mammedov wrote:
On Sat, 1 Jul 2023 16:28:30 +0900
Akihiko Odaki wrote:
On 2023/07/01 0:29, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki
The current implementers of ARI are all SR-IOV devices. The ARI next
function number field is undefined for VF according to PCI Express Base
Specification Revision 5.0 Version 1.0 section 9.3.7.7. The PF should
end the linked list formed with the field by specifying 0 according to
section 7.8.7.2.
Currently the only implementers of ARI is SR-IOV devices, and they
behave similar. Share the ARI next function number.
Signed-off-by: Akihiko Odaki
---
docs/pcie_sriov.txt | 4 ++--
include/hw/pci/pcie.h | 2 +-
hw/net/igb.c | 2 +-
hw/net/igbvf.c| 2 +-
hw/nvme/ctrl.c
The ARI next function number field is undefined for VF. The PF should
end the linked list formed with the field by specifying 0.
Supersedes: <20230701070133.24877-1-akihiko.od...@daynix.com>
("[PATCH 0/4] pci: Compare function number and ARI next function number")
V4 -> V5:
Added references to
On 2023/7/4 23:39, Eugenio Perez Martin wrote:
> On Thu, Jun 29, 2023 at 5:26 PM Hawkins Jiawei wrote:
>>
>> This patch introduces vhost_vdpa_net_load_rx_mode()
>> and vhost_vdpa_net_load_rx() to restore the packet
>> receive filtering state in relation to
>> VIRTIO_NET_F_CTRL_RX feature at
On Wed, 5 Jul 2023 at 01:27, Nicholas Piggin wrote:
>
> The P10 core xscom memory regions overlap because the size is wrong.
> The P10 core+L2 xscom region size is allocated as 0x1000 (with some
> unused ranges). "EC" is used as a closer match, as "EX" includes L3
> which has a disjoint xscom
On 2023/7/4 22:53, Eugenio Perez Martin wrote:
> On Thu, Jun 29, 2023 at 5:26 PM Hawkins Jiawei wrote:
>>
>> This patch refactors vhost_vdpa_net_load_mac() to
>> restore the MAC address filtering state at device's startup.
>>
>> Signed-off-by: Hawkins Jiawei
>> ---
>> v2:
>>- use iovec
On 2023/07/05 0:07, Ani Sinha wrote:
On 04-Jul-2023, at 7:58 PM, Igor Mammedov wrote:
On Tue, 4 Jul 2023 19:20:00 +0530
Ani Sinha wrote:
On 04-Jul-2023, at 6:18 PM, Igor Mammedov wrote:
On Tue, 4 Jul 2023 21:02:09 +0900
Akihiko Odaki wrote:
On 2023/07/04 20:59, Ani Sinha wrote:
The P10 core xscom memory regions overlap because the size is wrong.
The P10 core+L2 xscom region size is allocated as 0x1000 (with some
unused ranges). "EC" is used as a closer match, as "EX" includes L3
which has a disjoint xscom range that would require a different
region if it were
On Tue Jul 4, 2023 at 3:41 PM AEST, Joel Stanley wrote:
> The quad model implements the EC xscoms for the p9 machine, reusing the
> same model for p10 which isn't quite correct. This series adds a PnvQuad
> class and subclasses it for P9 and P10.
>
> I mistakenly thought we needed the quad model
On 2023/7/4 22:17, Eugenio Perez Martin wrote:
> On Thu, Jun 29, 2023 at 5:25 PM Hawkins Jiawei wrote:
>>
>> According to VirtIO standard, "The driver MUST follow
>> the VIRTIO_NET_CTRL_MAC_TABLE_SET command by a le32 number,
>> followed by that number of non-multicast MAC addresses,
>> followed
-Original Message-
From: Matheus Tavares Bernardino
Sent: Monday, July 3, 2023 3:50 PM
To: qemu-devel@nongnu.org
Cc: bc...@quicinc.com; quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com
Subject: [PATCH] Hexagon: move GETPC() calls to top level helpers
As docs/devel/loads-stores.rst
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/4/23 11:48, Frederic Barrat wrote:
We currently only allow 64-bit operations on the ESB CI pages. There's
no real reason for that limitation, skiboot/linux didn't need
more. However the hardware supports any size, so this
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/4/23 02:41, Joel Stanley wrote:
The quad model implements the EC xscoms for the p9 machine, reusing the
same model for p10 which isn't quite correct. This series adds a PnvQuad
class and subclasses it for P9 and P10.
I
> Matheus Tavares Bernardino wrote:
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index 5451b061ee..efb8013912 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -173,14 +173,20 @@
> #define MEM_STORE8(VA, DATA, SLOT) \
>
04.07.2023 14:06, ~ssinprem wrote:
From: Sittisak Sinprem
- I2C list follow I2C Tree v1.6 20230320
- fru eeprom data use FB FRU format version 4
Signed-off-by: Sittisak Sinprem
Once again, this has nothing to do with qemu-stable@, it is not a fix
suitable for stable releases.
Thanks,
On Fri, Jun 30, 2023 at 01:37:49AM +0200, BALATON Zoltan wrote:
> Hello,
>
> Some devices have bits that allow the guest to change endianness of memory
> mapped resources, e.g. ati-vga should allow switching the regs BAR into big
> endian on writing a bit. What's the best way to emulate this?
>
On Tue, 4 Jul 2023, BALATON Zoltan wrote:
Forgot to add commit message here:
This also changes type of sz local variable to ssize_t because it is used
to store return value of load_elf() and load_image_targphys() that return
ssize_t.
Should I resend for this or you can ammend on commit?
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index af5489de26..9c9944188b 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -44,6 +44,8 @@
On Tue, 4 Jul 2023 at 18:19, Anthony PERARD wrote:
>
> From: Anthony PERARD
>
> Commit 189829399070 ("xen-block: Use specific blockdev driver")
> introduced a new error path, without taking care of allocated
> resources.
>
> So only allocate the qdicts after the error check, and free both
>
* Daniel P. Berrangé:
> On Mon, Jul 03, 2023 at 06:03:08PM +0200, Pierrick Bouvier wrote:
>> Hi everyone,
>>
>> Recently (in d135f781 [1], between v7.0.0 and v8.0.0), qemu-user default cpu
>> was updated to "max" instead of qemu32/qemu64.
>>
>> This change "broke" qemu self emulation if this
Thanks for this deep analysis.
Even if the bug is potentially on glibc side, would that be worth to
change something in qemu CPU description to avoid it (like changing cpuid)?
On 7/3/23 23:05, Daniel P. Berrangé wrote:
On Mon, Jul 03, 2023 at 06:03:08PM +0200, Pierrick Bouvier wrote:
Hi
On 7/3/23 19:29, Michael Tokarev wrote:
03.07.2023 18:48, Pierrick Bouvier пишет:
Support for execveat syscall was implemented in 55bbe4 and is available
since QEMU 8.0.0. It relies on host execveat, which is widely available
on most of Linux kernels today.
However, this change breaks
On Fri, 2023-06-23 at 14:27 +0100, Peter Maydell wrote:
> On Thu, 6 Apr 2023 at 17:25, Woodhouse, David wrote:
> >
> > On Thu, 2023-04-06 at 16:48 +0100, Peter Maydell wrote:
> > > On Thu, 2 Mar 2023 at 12:37, Paolo Bonzini wrote:
> > > >
> > > > From: David Woodhouse
> > > >
> > > > The way
From: Anthony PERARD
Commit 189829399070 ("xen-block: Use specific blockdev driver")
introduced a new error path, without taking care of allocated
resources.
So only allocate the qdicts after the error check, and free both
`filename` and `driver` when we are about to return and thus taking
care
On 7/4/23 16:48, Frederic Barrat wrote:
We currently only allow 64-bit operations on the ESB CI pages. There's
no real reason for that limitation, skiboot/linux didn't need
more. However the hardware supports any size, so this patch relaxes
that restriction. It impacts both the ESB pages for
On 7/4/23 18:20, Frederic Barrat wrote:
On 04/07/2023 15:49, Cédric Le Goater wrote:
Hello,
Here are changes improving multisocket support of the XIVE models
(POWER9 only). When a source has an END target on another chip, the
XIVE IC will use an MMIO store to forward the notification to the
On Wed, Jun 21, 2023 at 02:54:56PM +, Yong-Xuan Wang wrote:
> Select KVM AIA when the host kernel has in-kernel AIA chip support.
> Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
> devices to KVM APLIC.
> We also extend virt machine to specify the KVM AIA mode. The "kvm-aia"
From: Yuquan Wang
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
We bump the platform version to 0.3 with this change.
From: John Högberg
https://gitlab.com/qemu-project/qemu/-/issues/1034
Signed-off-by: John Högberg
Message-id: 168778890374.24232.340213885153806878...@git.sr.ht
Reviewed-by: Peter Maydell
[PMM: fixed typo in comment]
Signed-off-by: Peter Maydell
---
tests/tcg/aarch64/icivau.c| 189
From: Richard Henderson
Always print each matrix row whole, one per line, so that we
get the entire matrix in the proper shape.
Signed-off-by: Richard Henderson
Message-id: 20230622151201.1578522-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
From: Vikram Garhwal
Following are done to fix the coverity issues:
1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
3. Replace rand() in generate_random_data() with g_rand_int()
Signed-off-by:
From: Akihiko Odaki
AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
advertised accordingly.
Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for
R40")
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard
From: Richard Henderson
Allow the line length to extend to 548 columns. While annoyingly wide,
it's still less confusing than the continuations we print. Also, the
default VL used by Linux (and max for A64FX) uses only 140 columns.
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
For the outer product set of insns, which take an entire matrix
tile as output, the argument is not a combined tile+column.
Therefore using get_tile_rowcol was incorrect, as we extracted
the tile number from itself.
The test case relies only on assembler support for SME,
repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230704
for you to fetch changes up to 86a78272f094857b4eda79d721c116e93942aa9a:
target/xtensa: Assert that interrupt level is within bounds (2023-07-04
14:27:08 +0100
From: Fabiano Rosas
This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:
$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg
--enable-xen
$ make -j$(nproc)
...
From: John Högberg
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, requiring an instruction synchronization
barrier on every core that will execute the new code, and on many
models also the
From: Eric Auger
Some registers whose 'cooked' writefns induce TLB maintenance do
not have raw_writefn ops defined. If only the writefn ops is set
(ie. no raw_writefn is provided), it is assumed the cooked also
work as the raw one. For those registers it is not obvious the
tlb_flush works on KVM
In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
If you build QEMU with the clang UB sanitizer and do a
'make check-tcg' run, it can fail like this:
TESTvma-pthread-with-libinsn.so on aarch64
../../util/interval-tree.c:751:32: runtime error: member access within
null pointer of type 'IntervalTreeNode' (aka 'struct
IntervalTreeNode')
On 04/07/2023 15:49, Cédric Le Goater wrote:
Hello,
Here are changes improving multisocket support of the XIVE models
(POWER9 only). When a source has an END target on another chip, the
XIVE IC will use an MMIO store to forward the notification to the
remote chip. The long term plan is to
On Wed, Jun 21, 2023 at 02:54:55PM +, Yong-Xuan Wang wrote:
> KVM AIA can't emulate APLIC only.
I think you mean "KVM AIA can't emulate the APLIC alone." ?
> When "aia=aplic" parameter is passed,
> APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
> mmio operations of
Hi
On Mon, Jun 26, 2023 at 9:49 PM Kim, Dongwon wrote:
> Hi Marc-André Lureau,
>
> On 6/26/2023 4:56 AM, Marc-André Lureau wrote:
> > Hi
> >
> > On Wed, Jun 21, 2023 at 11:53 PM Dongwon Kim
> > wrote:
> >
> > x and y offsets and width and height of the scanout texture
> > is not
On Wed, Jun 28, 2023 at 1:05 AM Dongwon Kim wrote:
> The primary guest scanout shows the booting screen right after reboot
> but additional guest displays (i.e. max_ouptuts > 1) will keep displaying
> the old frames until the guest virtio gpu driver gets initialized, which
> could cause some
Peter Maydell writes:
> If you build QEMU with the clang sanitizer enabled, you can see it
> fire when running the arm-cpu-features test:
>
> $ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64
> ./build/arm-clang/tests/qtest/arm-cpu-features
> [...]
> ../../target/arm/cpu64.c:125:19:
On Tue, 4 Jul 2023 at 16:52, Philippe Mathieu-Daudé wrote:
>
> On 4/7/23 17:43, Peter Maydell wrote:
> > If you build QEMU with the clang sanitizer enabled, you can see it
> > fire when running the arm-cpu-features test:
> >
> > $ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64
> >
On 4/7/23 17:44, Peter Maydell wrote:
On Tue, 4 Jul 2023 at 16:21, Philippe Mathieu-Daudé wrote:
On 28/6/23 18:48, Fabiano Rosas wrote:
This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:
$ ../configure
Hi
On Wed, Jun 28, 2023 at 9:12 PM Dongwon Kim wrote:
> Skip refresh if a new dmabuf (guest scanout frame) is submitted
> and ready to be drawn because the scanout will be refreshed with
> new frame anyway.
>
> Also, setting scanout mode is better to be done right before
> a draw event is
Hello Avihai
On 7/4/23 15:39, Avihai Horon wrote:
vfio_realize() has the following flow:
1. vfio_bars_prepare() -- sets VFIOBAR->size.
2. msix_early_setup().
3. vfio_bars_register() -- allocates VFIOBAR->mr.
After vfio_bars_prepare() is called msix_early_setup() can fail. If it
does fail,
On 4/7/23 17:43, Peter Maydell wrote:
If you build QEMU with the clang sanitizer enabled, you can see it
fire when running the arm-cpu-features test:
$ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64
./build/arm-clang/tests/qtest/arm-cpu-features
[...]
../../target/arm/cpu64.c:125:19:
From: David Woodhouse
Coverity points out (CID 1507534, 1507968) that we sometimes access
env->xen_singleshot_timer_ns under the protection of
env->xen_timers_lock and sometimes not.
This isn't always an issue. There are two modes for the timers; if the
kernel supports the EVTCHN_SEND
On Fri, 2023-06-02 at 17:58 +0100, Peter Maydell wrote:
> On Mon, 22 May 2023 at 19:52, David Woodhouse wrote:
> >
> > From: David Woodhouse
> >
> > Coverity points out (CID 1507534) that we sometimes access
> > env->xen_singleshot_timer_ns under the protection of
> > env->xen_timers_lock (eg
On Tue, 4 Jul 2023 at 16:21, Philippe Mathieu-Daudé wrote:
>
> On 28/6/23 18:48, Fabiano Rosas wrote:
> > This code is only relevant when TCG is present in the build. Building
> > with --disable-tcg --enable-xen on an x86 host we get:
> >
> > $ ../configure
If you build QEMU with the clang sanitizer enabled, you can see it
fire when running the arm-cpu-features test:
$ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64
./build/arm-clang/tests/qtest/arm-cpu-features
[...]
../../target/arm/cpu64.c:125:19: runtime error: shift exponent 64 is too
On Thu, Jun 29, 2023 at 5:26 PM Hawkins Jiawei wrote:
>
> This patch introduces vhost_vdpa_net_load_rx_mode()
> and vhost_vdpa_net_load_rx() to restore the packet
> receive filtering state in relation to
> VIRTIO_NET_F_CTRL_RX feature at device's startup.
>
> Signed-off-by: Hawkins Jiawei
> ---
When QEMU is built with --enable-modules, the module_block.py script
parses block/*.c to find block drivers that are built as modules. The
script generates a table of block drivers called block_driver_modules[].
This table is used for block driver module loading.
The blkio.c driver uses macros to
The following changes since commit d145c0da22cde391d8c6672d33146ce306e8bf75:
Merge tag 'pull-tcg-20230701' of https://gitlab.com/rth7680/qemu into staging
(2023-07-01 08:55:37 +0200)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-pull-request
for
Stefano Garzarella writes:
> On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote:
>>Currently QEMU has to know some details about the back-end to be able
>>to setup the guest. While various parts of the setup can be delegated
>>to the backend (for example config handling) this is a
On 28/6/23 18:48, Fabiano Rosas wrote:
This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:
$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg
--enable-xen
$ make -j$(nproc)
...
On Wed, Jun 28, 2023 at 9:36 PM Dongwon Kim wrote:
> Observed a wrong context is bound when changing the scanout mode.
> To prevent problem, it is needed to make sure to bind the right
> context in gtk_egl_set_scanout_mode/gtk_gl_area_set_scanout_mode
> as well as unbind one in the end of
The main loop thread can consume 100% CPU when using --device
virtio-blk-pci,iothread=. ppoll() constantly returns but
reading virtqueue host notifiers fails with EAGAIN. The file descriptors
are stale and remain registered with the AioContext because of bugs in
the virtio-blk dataplane start/stop
On Wed, Jun 21, 2023 at 02:54:54PM +, Yong-Xuan Wang wrote:
> implement a function to create an KVM AIA chip
This is a bit too terse. We should at least summarize the KVM API this
uses.
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
> ---
> target/riscv/kvm.c | 163
Coverity points out (CID 1508128) a bounds checking error. We need to check
for gsi >= IOAPIC_NUM_PINS, not just greater-than.
Also fix up an assert() that has the same problem, that Coverity didn't see.
Signed-off-by: David Woodhouse
---
hw/i386/kvm/xen_evtchn.c | 4 ++--
1 file changed, 2
Hi
On Wed, Jun 28, 2023 at 12:32 AM Dongwon Kim wrote:
> Surface is replaced with a place holder whenever the surface res
> is unreferenced by the guest message. With this logic, there is
> very frequent switching between guest display and the place holder
> image, which is looking like a
On 4/7/23 16:49, Philippe Mathieu-Daudé wrote:
This series converts the ARM_TIMER model to QOM.
Doing so we also correct an abuse of SysBus IRQ in
the ICP PIT model.
Since v1:
- Added pm215's R-b tags
- Addressed Mark/Peter review comments
- Drop '*State' suffix from structure names
-
> On 04-Jul-2023, at 7:58 PM, Igor Mammedov wrote:
>
> On Tue, 4 Jul 2023 19:20:00 +0530
> Ani Sinha wrote:
>
>>> On 04-Jul-2023, at 6:18 PM, Igor Mammedov wrote:
>>>
>>> On Tue, 4 Jul 2023 21:02:09 +0900
>>> Akihiko Odaki wrote:
>>>
On 2023/07/04 20:59, Ani Sinha wrote:
>
On 4/7/23 17:00, Marcin Juszkiewicz wrote:
W dniu 4.07.2023 o 16:54, Philippe Mathieu-Daudé pisze:
On 4/7/23 15:35, Marcin Juszkiewicz wrote:
W dniu 4.07.2023 o 15:06, Peter Maydell pisze:
This patchset implements the Cortex Neoverse-V1 CPU type, as a
representative Armv8.3 (+ some extras
On Fri, 9 Jun 2023 at 18:23, Aaron Lindsay wrote:
>
> Changes from v2 of this patchset [0]:
> - Remove properties for EPAC, Pauth2, FPAC, FPACCombined
> - Separate out aa64isar2 addition into its own patch
> - Comment clarifications
> - Several code formatting/simplifications
> - Rebase on top of
W dniu 4.07.2023 o 16:54, Philippe Mathieu-Daudé pisze:
On 4/7/23 15:35, Marcin Juszkiewicz wrote:
W dniu 4.07.2023 o 15:06, Peter Maydell pisze:
This patchset implements the Cortex Neoverse-V1 CPU type, as a
representative Armv8.3 (+ some extras from 8.4) CPU matching real
hardware. The
Peter Maydell writes:
> Now that we have implemented support for FEAT_LSE2, we can define
> a CPU model for the Neoverse-V1, and enable it for the virt and
> sbsa-ref boards.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote:
Currently QEMU has to know some details about the back-end to be able
to setup the guest. While various parts of the setup can be delegated
to the backend (for example config handling) this is a very piecemeal
approach.
This patch
On 4/7/23 15:35, Marcin Juszkiewicz wrote:
W dniu 4.07.2023 o 15:06, Peter Maydell pisze:
This patchset implements the Cortex Neoverse-V1 CPU type, as a
representative Armv8.3 (+ some extras from 8.4) CPU matching real
hardware. The main thing we were waiting for to be able to define
this was
On Thu, Jun 29, 2023 at 5:26 PM Hawkins Jiawei wrote:
>
> This patch refactors vhost_vdpa_net_load_mac() to
> restore the MAC address filtering state at device's startup.
>
> Signed-off-by: Hawkins Jiawei
> ---
> v2:
> - use iovec suggested by Eugenio
> - avoid sending CVQ command in default
Both SP804Timer/IntegratorPIT peek at ArmTimer internal state.
This is fine so far but we want to convert ArmTimer to QOM
where peeking at QOM state internal should be avoided.
ArmTimer's IRQ is just a pointer, so we can pass/set it via
argument, avoiding accessing ArmTimer internal state except
Introduce the ARM_TIMER sysbus device, exposing one output IRQ
and a single MMIO region.
arm_timer_new() is converted as QOM instance init()/finalize()
handlers. Note in arm_timer_finalize() we release a ptimer handle
which was previously leaked.
ArmTimer is directly embedded into
SysBus IRQ are *output* IRQs. As some sort of simplification
to avoid to forward it, IntegratorPIT misuses it as ARM timer
input IRQ. Fix that by using a simple IRQ forwarder handler.
Note: sysbus_pass_irq() forwards GPIOs and IRQs from a container
to an inner device but only work with an entire
To make the next commit easier to digest, extract icp_pit_realize()
from icp_pit_init() as a preliminary step.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/timer/arm_timer.c
Extract arm_timer_reset_hold() before converting this model to
QOM/QDev in few commits. This will become our ResettableHoldPhase
handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
Having a QOM object using its device type as suffix is
often helpful.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
index 41045de8ed..8dae845998 100644
---
QDev models often use foo_new() as the combination of
foo_init() + foo_realize(). Here arm_timer_init() is
a such combination, so rename it as arm_timer_new() to
emphasis the returned device is already realized.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
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