[PATCH v6 5/5] default-configs: Add TARGET_XML_FILES definition

[Akihiko Odaki]

loongarch64-linux-user has references to XML files so include them.

Fixes: d32688ecdb ("default-configs: Add loongarch linux-user support")
Signed-off-by: Akihiko Odaki 
---
 configs/targets/loongarch64-linux-user.mak | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/targets/loongarch64-linux-user.mak 
b/configs/targets/loongarch64-linux-user.mak
index 7d1b964020..43b8a2160f 100644
--- a/configs/targets/loongarch64-linux-user.mak
+++ b/configs/targets/loongarch64-linux-user.mak
@@ -1,3 +1,4 @@
 # Default configuration for loongarch64-linux-user
 TARGET_ARCH=loongarch64
 TARGET_BASE_ARCH=loongarch
+TARGET_XML_FILES=gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml 
gdb-xml/loongarch-fpu.xml
-- 
2.42.0

[PATCH v6 1/5] hw/riscv: Use misa_mxl instead of misa_mxl_max

[Akihiko Odaki]

The effective MXL value matters when booting.

Signed-off-by: Akihiko Odaki 
---
 hw/riscv/boot.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 52bf8e67de..dad3f6e7b1 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -36,7 +36,7 @@
 
 bool riscv_is_32bit(RISCVHartArrayState *harts)
 {
-return harts->harts[0].env.misa_mxl_max == MXL_RV32;
+return harts->harts[0].env.misa_mxl == MXL_RV32;
 }
 
 /*
-- 
2.42.0

[PATCH v6 3/5] target/riscv: Move misa_mxl_max to class

[Akihiko Odaki]

misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.

Signed-off-by: Akihiko Odaki 
---
 target/riscv/cpu-qom.h |   1 +
 target/riscv/cpu.h |   3 +-
 target/riscv/cpu.c | 118 +++--
 target/riscv/gdbstub.c |  12 ++--
 target/riscv/kvm/kvm-cpu.c |  10 ++--
 target/riscv/machine.c |   7 +--
 target/riscv/tcg/tcg-cpu.c |  12 ++--
 target/riscv/translate.c   |   3 +-
 8 files changed, 87 insertions(+), 79 deletions(-)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index f3fbe37a2c..33b6d52c90 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -68,5 +68,6 @@ struct RISCVCPUClass {
 /*< public >*/
 DeviceRealize parent_realize;
 ResettablePhases parent_phases;
+uint32_t misa_mxl_max;  /* max mxl for this cpu */
 };
 #endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f8ffa5ee38..ef10efd1e7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -159,7 +159,6 @@ struct CPUArchState {
 
 /* RISCVMXL, but uint32_t for vmstate migration */
 uint32_t misa_mxl;  /* current mxl */
-uint32_t misa_mxl_max;  /* max mxl for this cpu */
 uint32_t misa_ext;  /* current extensions */
 uint32_t misa_ext_mask; /* max ext for this cpu */
 uint32_t xl;/* current xlen */
@@ -711,7 +710,7 @@ enum riscv_pmu_event_idx {
 /* used by tcg/tcg-cpu.c*/
 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
-void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
+void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext);
 
 typedef struct RISCVCPUMultiExtConfig {
 const char *name;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac4a6c7eec..1fb5747f00 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -263,9 +263,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, 
bool async)
 }
 }
 
-void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
 {
-env->misa_mxl_max = env->misa_mxl = mxl;
 env->misa_ext_mask = env->misa_ext = ext;
 }
 
@@ -367,11 +366,7 @@ static void riscv_any_cpu_init(Object *obj)
 {
 RISCVCPU *cpu = RISCV_CPU(obj);
 CPURISCVState *env = >env;
-#if defined(TARGET_RISCV32)
-riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-#elif defined(TARGET_RISCV64)
-riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-#endif
+riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 
 #ifndef CONFIG_USER_ONLY
 set_satp_mode_max_supported(RISCV_CPU(obj),
@@ -392,16 +387,14 @@ static void riscv_max_cpu_init(Object *obj)
 {
 RISCVCPU *cpu = RISCV_CPU(obj);
 CPURISCVState *env = >env;
-RISCVMXL mlx = MXL_RV64;
 
-#ifdef TARGET_RISCV32
-mlx = MXL_RV32;
-#endif
-riscv_cpu_set_misa(env, mlx, 0);
 env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
-set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
-VM_1_10_SV32 : VM_1_10_SV57);
+#ifdef TARGET_RISCV32
+set_satp_mode_max_supported(cpu, VM_1_10_SV32);
+#else
+set_satp_mode_max_supported(cpu, VM_1_10_SV57);
+#endif
 #endif
 }
 
@@ -409,8 +402,6 @@ static void riscv_max_cpu_init(Object *obj)
 static void rv64_base_cpu_init(Object *obj)
 {
 CPURISCVState *env = _CPU(obj)->env;
-/* We set this in the realise function */
-riscv_cpu_set_misa(env, MXL_RV64, 0);
 /* Set latest version of privileged specification */
 env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -422,8 +413,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
 {
 RISCVCPU *cpu = RISCV_CPU(obj);
 CPURISCVState *env = >env;
-riscv_cpu_set_misa(env, MXL_RV64,
-   RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -441,7 +431,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 RISCVCPU *cpu = RISCV_CPU(obj);
 
-riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
 env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -458,7 +448,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
 CPURISCVState *env = _CPU(obj)->env;
 RISCVCPU *cpu = RISCV_CPU(obj);
 
-riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
 env->priv_ver = PRIV_VERSION_1_11_0;
 
 

[PATCH v6 4/5] target/riscv: Validate misa_mxl_max only once

[Akihiko Odaki]

misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.

Signed-off-by: Akihiko Odaki 
---
 target/riscv/cpu.c | 21 +
 target/riscv/tcg/tcg-cpu.c | 23 ---
 2 files changed, 21 insertions(+), 23 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1fb5747f00..72124e57fd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1193,6 +1193,26 @@ static const MISAExtInfo misa_ext_info_arr[] = {
 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
 };
 
+static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
+{
+CPUClass *cc = CPU_CLASS(mcc);
+
+/* Validate that MISA_MXL is set properly. */
+switch (mcc->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+case MXL_RV64:
+case MXL_RV128:
+cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+break;
+#endif
+case MXL_RV32:
+cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+break;
+default:
+g_assert_not_reached();
+}
+}
+
 static int riscv_validate_misa_info_idx(uint32_t bit)
 {
 int idx;
@@ -1593,6 +1613,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void 
*data)
 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 
 mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+riscv_cpu_validate_misa_mxl(mcc);
 }
 
 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 5bf9d31f7c..a82c49ef67 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -148,27 +148,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState 
*env, Error **errp)
 }
 }
 
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
-{
-RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-CPUClass *cc = CPU_CLASS(mcc);
-
-/* Validate that MISA_MXL is set properly. */
-switch (mcc->misa_mxl_max) {
-#ifdef TARGET_RISCV64
-case MXL_RV64:
-case MXL_RV128:
-cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-break;
-#endif
-case MXL_RV32:
-cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
-break;
-default:
-g_assert_not_reached();
-}
-}
-
 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
 {
 CPURISCVState *env = >env;
@@ -568,8 +547,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
 return false;
 }
 
-riscv_cpu_validate_misa_mxl(cpu);
-
 riscv_cpu_validate_priv_spec(cpu, _err);
 if (local_err != NULL) {
 error_propagate(errp, local_err);
-- 
2.42.0

[PATCH v6 2/5] target/riscv: Remove misa_mxl validation

[Akihiko Odaki]

It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.

Signed-off-by: Akihiko Odaki 
Acked-by: LIU Zhiwei 
Reviewed-by: Daniel Henrique Barboza 
---
 target/riscv/tcg/tcg-cpu.c | 13 ++---
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a28918ab30..7f45e42000 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -148,7 +148,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState 
*env, Error **errp)
 }
 }
 
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
 {
 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 CPUClass *cc = CPU_CLASS(mcc);
@@ -168,11 +168,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, 
Error **errp)
 default:
 g_assert_not_reached();
 }
-
-if (env->misa_mxl_max != env->misa_mxl) {
-error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
-return;
-}
 }
 
 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
@@ -573,11 +568,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
 return false;
 }
 
-riscv_cpu_validate_misa_mxl(cpu, _err);
-if (local_err != NULL) {
-error_propagate(errp, local_err);
-return false;
-}
+riscv_cpu_validate_misa_mxl(cpu);
 
 riscv_cpu_validate_priv_spec(cpu, _err);
 if (local_err != NULL) {
-- 
2.42.0

[PATCH v6 0/5] gdbstub and TCG plugin improvements

[Akihiko Odaki]

Based-on: <20231029145033.592566-1-alex.ben...@linaro.org>
("[PATCH v2 00/19] Maintainer updates for testing, gdb, semihosting and
plugins (pre-PR)")

This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".

The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different misa_ext_mask.

V5 -> V6:
  Added patch "default-configs: Add TARGET_XML_FILES definition".
  Rebased.

V4 -> V5:
  Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max".

V3 -> V4:
  Added patch "gdbstub: Check if gdb_regs is NULL".

V2 -> V3:
  Restored patch sets from the previous version.
  Rebased to commit 800485762e6564e04e2ab315132d477069562d91.

V1 -> V2:
  Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64".
  Added patch "target/riscv: Initialize gdb_core_xml_file only once".
  Dropped patch "target/riscv: Remove misa_mxl validation".
  Dropped patch "target/riscv: Move misa_mxl_max to class".
  Dropped patch "target/riscv: Validate misa_mxl_max only once".

Akihiko Odaki (5):
  hw/riscv: Use misa_mxl instead of misa_mxl_max
  target/riscv: Remove misa_mxl validation
  target/riscv: Move misa_mxl_max to class
  target/riscv: Validate misa_mxl_max only once
  default-configs: Add TARGET_XML_FILES definition

 configs/targets/loongarch64-linux-user.mak |   1 +
 target/riscv/cpu-qom.h |   1 +
 target/riscv/cpu.h |   3 +-
 hw/riscv/boot.c|   2 +-
 target/riscv/cpu.c | 139 -
 target/riscv/gdbstub.c |  12 +-
 target/riscv/kvm/kvm-cpu.c |  10 +-
 target/riscv/machine.c |   7 +-
 target/riscv/tcg/tcg-cpu.c |  42 +--
 target/riscv/translate.c   |   3 +-
 10 files changed, 109 insertions(+), 111 deletions(-)

-- 
2.42.0

[PATCH v6 06/21] net: Remove flag propagation

[Akihiko Odaki]

There is no defined flag now.

Signed-off-by: Akihiko Odaki 
---
 include/net/filter.h|  3 ---
 include/net/queue.h |  6 --
 include/sysemu/replay.h |  2 +-
 net/dump.c  |  4 ++--
 net/filter-buffer.c |  4 +---
 net/filter-mirror.c |  6 ++
 net/filter-replay.c |  3 +--
 net/filter-rewriter.c   |  5 ++---
 net/filter.c|  8 +++-
 net/net.c   | 43 ++---
 replay/replay-net.c |  8 ++--
 11 files changed, 28 insertions(+), 64 deletions(-)

diff --git a/include/net/filter.h b/include/net/filter.h
index 27ffc630df..e523771e72 100644
--- a/include/net/filter.h
+++ b/include/net/filter.h
@@ -26,7 +26,6 @@ typedef void (FilterCleanup) (NetFilterState *nf);
  */
 typedef ssize_t (FilterReceiveIOV)(NetFilterState *nc,
NetClientState *sender,
-   unsigned flags,
const struct iovec *iov,
int iovcnt,
NetPacketSent *sent_cb);
@@ -65,14 +64,12 @@ struct NetFilterState {
 ssize_t qemu_netfilter_receive(NetFilterState *nf,
NetFilterDirection direction,
NetClientState *sender,
-   unsigned flags,
const struct iovec *iov,
int iovcnt,
NetPacketSent *sent_cb);
 
 /* pass the packet to the next filter */
 ssize_t qemu_netfilter_pass_to_next(NetClientState *sender,
-unsigned flags,
 const struct iovec *iov,
 int iovcnt,
 void *opaque);
diff --git a/include/net/queue.h b/include/net/queue.h
index 7a43863be2..571f4e1436 100644
--- a/include/net/queue.h
+++ b/include/net/queue.h
@@ -30,15 +30,12 @@ typedef struct NetQueue NetQueue;
 
 typedef void (NetPacketSent) (NetClientState *sender, ssize_t ret);
 
-#define QEMU_NET_PACKET_FLAG_NONE  0
-
 /* Returns:
  *   >0 - success
  *0 - queue packet for future redelivery
  *   <0 - failure (discard packet)
  */
 typedef ssize_t (NetQueueDeliverFunc)(NetClientState *sender,
-  unsigned flags,
   const struct iovec *iov,
   int iovcnt,
   void *opaque);
@@ -47,7 +44,6 @@ NetQueue *qemu_new_net_queue(NetQueueDeliverFunc *deliver, 
void *opaque);
 
 void qemu_net_queue_append_iov(NetQueue *queue,
NetClientState *sender,
-   unsigned flags,
const struct iovec *iov,
int iovcnt,
NetPacketSent *sent_cb);
@@ -64,14 +60,12 @@ ssize_t qemu_net_queue_receive_iov(NetQueue *queue,
 
 ssize_t qemu_net_queue_send(NetQueue *queue,
 NetClientState *sender,
-unsigned flags,
 const uint8_t *data,
 size_t size,
 NetPacketSent *sent_cb);
 
 ssize_t qemu_net_queue_send_iov(NetQueue *queue,
 NetClientState *sender,
-unsigned flags,
 const struct iovec *iov,
 int iovcnt,
 NetPacketSent *sent_cb);
diff --git a/include/sysemu/replay.h b/include/sysemu/replay.h
index 08aae5869f..67b2d3ac73 100644
--- a/include/sysemu/replay.h
+++ b/include/sysemu/replay.h
@@ -158,7 +158,7 @@ ReplayNetState *replay_register_net(NetFilterState *nfs);
 /*! Unregisters replay network filter. */
 void replay_unregister_net(ReplayNetState *rns);
 /*! Called to write network packet to the replay log. */
-void replay_net_packet_event(ReplayNetState *rns, unsigned flags,
+void replay_net_packet_event(ReplayNetState *rns,
  const struct iovec *iov, int iovcnt);
 
 /* Audio */
diff --git a/net/dump.c b/net/dump.c
index 956e34a123..dd8ada9b5e 100644
--- a/net/dump.c
+++ b/net/dump.c
@@ -150,8 +150,8 @@ struct NetFilterDumpState {
 };
 
 static ssize_t filter_dump_receive_iov(NetFilterState *nf, NetClientState 
*sndr,
-   unsigned flags, const struct iovec *iov,
-   int iovcnt, NetPacketSent *sent_cb)
+   const struct iovec *iov, int iovcnt,
+   NetPacketSent *sent_cb)
 {
 NetFilterDumpState *nfds = FILTER_DUMP(nf);
 
diff --git a/net/filter-buffer.c b/net/filter-buffer.c
index 283dc9cbe6..6d8b581cd8 100644
--- a/net/filter-buffer.c
+++ b/net/filter-buffer.c
@@ -58,7 +58,6 

[PATCH v6 21/21] ebpf: Add a separate target for skeleton

[Akihiko Odaki]

This generalizes the rule to generate the skeleton and allows to add
another.

Signed-off-by: Akihiko Odaki 
---
 tools/ebpf/Makefile.ebpf | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/tools/ebpf/Makefile.ebpf b/tools/ebpf/Makefile.ebpf
index 3391e7ce08..572ca5987a 100755
--- a/tools/ebpf/Makefile.ebpf
+++ b/tools/ebpf/Makefile.ebpf
@@ -1,23 +1,24 @@
-OBJS = rss.bpf.o
+SKELETONS = rss.bpf.skeleton.h
 
 LLVM_STRIP ?= llvm-strip
 CLANG ?= clang
 INC_FLAGS = `$(CLANG) -print-file-name=include`
 EXTRA_CFLAGS ?= -O2 -g -target bpf
 
-all: $(OBJS)
+all: $(SKELETONS)
 
 .PHONY: clean
 
 clean:
-   rm -f $(OBJS)
-   rm -f rss.bpf.skeleton.h
+   rm -f $(SKELETONS) $(SKELETONS:%.skeleton.h=%.o)
 
-$(OBJS):  %.o:%.c
+%.o: %.c
$(CLANG) $(INC_FLAGS) \
 -D__KERNEL__ -D__ASM_SYSREG_H \
 -I../include $(LINUXINCLUDE) \
 $(EXTRA_CFLAGS) -c $< -o $@
$(LLVM_STRIP) -g $@
-   bpftool gen skeleton rss.bpf.o > rss.bpf.skeleton.h
-   cp rss.bpf.skeleton.h ../../ebpf/
+
+%.skeleton.h: %.o
+   bpftool gen skeleton $< > $@
+   cp $@ ../../ebpf/
-- 
2.42.0

[PATCH v6 15/21] virtio-net: Do not clear VIRTIO_NET_F_HASH_REPORT

[Akihiko Odaki]

virtio-net can report hash values even if the peer does not have a
virtio-net header.

Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index e30105884c..bdb4579f98 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -774,8 +774,6 @@ static uint64_t virtio_net_get_features(VirtIODevice *vdev, 
uint64_t features,
 virtio_clear_feature(, VIRTIO_NET_F_HOST_USO);
 virtio_clear_feature(, VIRTIO_NET_F_GUEST_USO4);
 virtio_clear_feature(, VIRTIO_NET_F_GUEST_USO6);
-
-virtio_clear_feature(, VIRTIO_NET_F_HASH_REPORT);
 }
 
 if (!peer_has_vnet_hdr(n) || !peer_has_ufo(n)) {
-- 
2.42.0

[PATCH v6 11/21] virtio-net: Return an error when vhost cannot enable RSS

[Akihiko Odaki]

vhost requires eBPF for RSS. When eBPF is not available, virtio-net
implicitly disables RSS even if the user explicitly requests it. Return
an error instead of implicitly disabling RSS if RSS is requested but not
available.

Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 97 ++---
 1 file changed, 48 insertions(+), 49 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 5d4afd12b2..7bb91617d0 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -792,9 +792,6 @@ static uint64_t virtio_net_get_features(VirtIODevice *vdev, 
uint64_t features,
 return features;
 }
 
-if (!ebpf_rss_is_loaded(>ebpf_rss)) {
-virtio_clear_feature(, VIRTIO_NET_F_RSS);
-}
 features = vhost_net_get_features(get_vhost_net(nc->peer), features);
 vdev->backend_features = features;
 
@@ -3533,6 +3530,50 @@ static bool failover_hide_primary_device(DeviceListener 
*listener,
 return qatomic_read(>failover_primary_hidden);
 }
 
+static void virtio_net_device_unrealize(DeviceState *dev)
+{
+VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+VirtIONet *n = VIRTIO_NET(dev);
+int i, max_queue_pairs;
+
+if (virtio_has_feature(n->host_features, VIRTIO_NET_F_RSS)) {
+virtio_net_unload_ebpf(n);
+}
+
+/* This will stop vhost backend if appropriate. */
+virtio_net_set_status(vdev, 0);
+
+g_free(n->netclient_name);
+n->netclient_name = NULL;
+g_free(n->netclient_type);
+n->netclient_type = NULL;
+
+g_free(n->mac_table.macs);
+g_free(n->vlans);
+
+if (n->failover) {
+qobject_unref(n->primary_opts);
+device_listener_unregister(>primary_listener);
+migration_remove_notifier(>migration_state);
+} else {
+assert(n->primary_opts == NULL);
+}
+
+max_queue_pairs = n->multiqueue ? n->max_queue_pairs : 1;
+for (i = 0; i < max_queue_pairs; i++) {
+virtio_net_del_queue(n, i);
+}
+/* delete also control vq */
+virtio_del_queue(vdev, max_queue_pairs * 2);
+qemu_announce_timer_del(>announce_timer, false);
+g_free(n->vqs);
+qemu_del_nic(n->nic);
+virtio_net_rsc_cleanup(n);
+g_free(n->rss_data.indirections_table);
+net_rx_pkt_uninit(n->rx_pkt);
+virtio_cleanup(vdev);
+}
+
 static void virtio_net_device_realize(DeviceState *dev, Error **errp)
 {
 VirtIODevice *vdev = VIRTIO_DEVICE(dev);
@@ -3704,53 +3745,11 @@ static void virtio_net_device_realize(DeviceState *dev, 
Error **errp)
 
 net_rx_pkt_init(>rx_pkt);
 
-if (virtio_has_feature(n->host_features, VIRTIO_NET_F_RSS)) {
-virtio_net_load_ebpf(n);
-}
-}
-
-static void virtio_net_device_unrealize(DeviceState *dev)
-{
-VirtIODevice *vdev = VIRTIO_DEVICE(dev);
-VirtIONet *n = VIRTIO_NET(dev);
-int i, max_queue_pairs;
-
-if (virtio_has_feature(n->host_features, VIRTIO_NET_F_RSS)) {
-virtio_net_unload_ebpf(n);
+if (virtio_has_feature(n->host_features, VIRTIO_NET_F_RSS) &&
+!virtio_net_load_ebpf(n)) {
+error_setg(errp, "Can't load eBPF RSS");
+virtio_net_device_unrealize(dev);
 }
-
-/* This will stop vhost backend if appropriate. */
-virtio_net_set_status(vdev, 0);
-
-g_free(n->netclient_name);
-n->netclient_name = NULL;
-g_free(n->netclient_type);
-n->netclient_type = NULL;
-
-g_free(n->mac_table.macs);
-g_free(n->vlans);
-
-if (n->failover) {
-qobject_unref(n->primary_opts);
-device_listener_unregister(>primary_listener);
-migration_remove_notifier(>migration_state);
-} else {
-assert(n->primary_opts == NULL);
-}
-
-max_queue_pairs = n->multiqueue ? n->max_queue_pairs : 1;
-for (i = 0; i < max_queue_pairs; i++) {
-virtio_net_del_queue(n, i);
-}
-/* delete also control vq */
-virtio_del_queue(vdev, max_queue_pairs * 2);
-qemu_announce_timer_del(>announce_timer, false);
-g_free(n->vqs);
-qemu_del_nic(n->nic);
-virtio_net_rsc_cleanup(n);
-g_free(n->rss_data.indirections_table);
-net_rx_pkt_uninit(n->rx_pkt);
-virtio_cleanup(vdev);
 }
 
 static void virtio_net_reset(VirtIODevice *vdev)
-- 
2.42.0

[PATCH v6 14/21] virtio-net: Do not write hashes to peer buffer

[Akihiko Odaki]

The peer buffer is qualified with const and not meant to be modified.
It also prevents enabling VIRTIO_NET_F_HASH_REPORT for peers without
virtio-net header support.

Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 36 +---
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 0fe75b3c08..e30105884c 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -1786,16 +1786,9 @@ static uint8_t virtio_net_get_hash_type(bool hasip4,
 return 0xff;
 }
 
-static void virtio_set_packet_hash(const uint8_t *buf, uint8_t report,
-   uint32_t hash)
-{
-struct virtio_net_hdr_v1_hash *hdr = (void *)buf;
-hdr->hash_value = hash;
-hdr->hash_report = report;
-}
-
 static int virtio_net_process_rss(NetClientState *nc, const uint8_t *buf,
-  size_t size)
+  size_t size,
+  struct virtio_net_hdr_v1_hash *hdr)
 {
 VirtIONet *n = qemu_get_nic_opaque(nc);
 unsigned int index = nc->queue_index, new_index = index;
@@ -1826,7 +1819,8 @@ static int virtio_net_process_rss(NetClientState *nc, 
const uint8_t *buf,
  n->rss_data.hash_types);
 if (net_hash_type > NetPktRssIpV6UdpEx) {
 if (n->rss_data.populate_hash) {
-virtio_set_packet_hash(buf, VIRTIO_NET_HASH_REPORT_NONE, 0);
+hdr->hash_value = VIRTIO_NET_HASH_REPORT_NONE;
+hdr->hash_report = 0;
 }
 return n->rss_data.redirect ? n->rss_data.default_queue : -1;
 }
@@ -1834,7 +1828,8 @@ static int virtio_net_process_rss(NetClientState *nc, 
const uint8_t *buf,
 hash = net_rx_pkt_calc_rss_hash(pkt, net_hash_type, n->rss_data.key);
 
 if (n->rss_data.populate_hash) {
-virtio_set_packet_hash(buf, reports[net_hash_type], hash);
+hdr->hash_value = hash;
+hdr->hash_report = reports[net_hash_type];
 }
 
 if (n->rss_data.redirect) {
@@ -1854,7 +1849,7 @@ static ssize_t virtio_net_receive_rcu(NetClientState *nc, 
const uint8_t *buf,
 VirtQueueElement *elems[VIRTQUEUE_MAX_SIZE];
 size_t lens[VIRTQUEUE_MAX_SIZE];
 struct iovec mhdr_sg[VIRTQUEUE_MAX_SIZE];
-struct virtio_net_hdr_mrg_rxbuf mhdr;
+struct virtio_net_hdr_v1_hash extra_hdr;
 unsigned mhdr_cnt = 0;
 size_t offset, i, guest_offset, j;
 ssize_t err;
@@ -1864,7 +1859,7 @@ static ssize_t virtio_net_receive_rcu(NetClientState *nc, 
const uint8_t *buf,
 }
 
 if (!no_rss && n->rss_data.enabled && n->rss_data.enabled_software_rss) {
-int index = virtio_net_process_rss(nc, buf, size);
+int index = virtio_net_process_rss(nc, buf, size, _hdr);
 if (index >= 0) {
 NetClientState *nc2 = qemu_get_subqueue(n->nic, index);
 return virtio_net_receive_rcu(nc2, buf, size, true);
@@ -1924,15 +1919,17 @@ static ssize_t virtio_net_receive_rcu(NetClientState 
*nc, const uint8_t *buf,
 if (n->mergeable_rx_bufs) {
 mhdr_cnt = iov_copy(mhdr_sg, ARRAY_SIZE(mhdr_sg),
 sg, elem->in_num,
-offsetof(typeof(mhdr), num_buffers),
-sizeof(mhdr.num_buffers));
+offsetof(typeof(extra_hdr), 
hdr.num_buffers),
+sizeof(extra_hdr.hdr.num_buffers));
 }
 
 receive_header(n, sg, elem->in_num, buf, size);
 if (n->rss_data.populate_hash) {
-offset = sizeof(mhdr);
+offset = offsetof(typeof(extra_hdr), hash_value);
 iov_from_buf(sg, elem->in_num, offset,
- buf + offset, n->host_hdr_len - sizeof(mhdr));
+ (char *)_hdr + offset,
+ sizeof(extra_hdr.hash_value) +
+ sizeof(extra_hdr.hash_report));
 }
 offset = n->host_hdr_len;
 total += n->guest_hdr_len;
@@ -1962,10 +1959,11 @@ static ssize_t virtio_net_receive_rcu(NetClientState 
*nc, const uint8_t *buf,
 }
 
 if (mhdr_cnt) {
-virtio_stw_p(vdev, _buffers, i);
+virtio_stw_p(vdev, _hdr.hdr.num_buffers, i);
 iov_from_buf(mhdr_sg, mhdr_cnt,
  0,
- _buffers, sizeof mhdr.num_buffers);
+ _hdr.hdr.num_buffers,
+ sizeof extra_hdr.hdr.num_buffers);
 }
 
 for (j = 0; j < i; j++) {
-- 
2.42.0

[PATCH v6 10/21] virtio-net: Unify the logic to update NIC state for RSS

[Akihiko Odaki]

The code to attach or detach the eBPF program to RSS were duplicated so
unify them into one function to save some code.

Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 90 ++---
 1 file changed, 36 insertions(+), 54 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 4c528baad9..5d4afd12b2 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -1231,18 +1231,6 @@ static int virtio_net_handle_announce(VirtIONet *n, 
uint8_t cmd,
 }
 }
 
-static void virtio_net_detach_epbf_rss(VirtIONet *n);
-
-static void virtio_net_disable_rss(VirtIONet *n)
-{
-if (n->rss_data.enabled) {
-trace_virtio_net_rss_disable();
-}
-n->rss_data.enabled = false;
-
-virtio_net_detach_epbf_rss(n);
-}
-
 static bool virtio_net_attach_ebpf_to_backend(NICState *nic, int prog_fd)
 {
 NetClientState *nc = qemu_get_peer(qemu_get_queue(nic), 0);
@@ -1290,6 +1278,40 @@ static void virtio_net_detach_epbf_rss(VirtIONet *n)
 virtio_net_attach_ebpf_to_backend(n->nic, -1);
 }
 
+static void virtio_net_commit_rss_config(VirtIONet *n)
+{
+if (n->rss_data.enabled) {
+n->rss_data.enabled_software_rss = n->rss_data.populate_hash;
+if (n->rss_data.populate_hash) {
+virtio_net_detach_epbf_rss(n);
+} else if (!virtio_net_attach_epbf_rss(n)) {
+if (get_vhost_net(qemu_get_queue(n->nic)->peer)) {
+warn_report("Can't load eBPF RSS for vhost");
+} else {
+warn_report("Can't load eBPF RSS - fallback to software RSS");
+n->rss_data.enabled_software_rss = true;
+}
+}
+
+trace_virtio_net_rss_enable(n->rss_data.hash_types,
+n->rss_data.indirections_len,
+sizeof(n->rss_data.key));
+} else {
+virtio_net_detach_epbf_rss(n);
+trace_virtio_net_rss_disable();
+}
+}
+
+static void virtio_net_disable_rss(VirtIONet *n)
+{
+if (!n->rss_data.enabled) {
+return;
+}
+
+n->rss_data.enabled = false;
+virtio_net_commit_rss_config(n);
+}
+
 static bool virtio_net_load_ebpf(VirtIONet *n)
 {
 if (!virtio_net_attach_ebpf_to_backend(n->nic, -1)) {
@@ -1418,28 +1440,7 @@ static uint16_t virtio_net_handle_rss(VirtIONet *n,
 goto error;
 }
 n->rss_data.enabled = true;
-
-if (!n->rss_data.populate_hash) {
-if (!virtio_net_attach_epbf_rss(n)) {
-/* EBPF must be loaded for vhost */
-if (get_vhost_net(qemu_get_queue(n->nic)->peer)) {
-warn_report("Can't load eBPF RSS for vhost");
-goto error;
-}
-/* fallback to software RSS */
-warn_report("Can't load eBPF RSS - fallback to software RSS");
-n->rss_data.enabled_software_rss = true;
-}
-} else {
-/* use software RSS for hash populating */
-/* and detach eBPF if was loaded before */
-virtio_net_detach_epbf_rss(n);
-n->rss_data.enabled_software_rss = true;
-}
-
-trace_virtio_net_rss_enable(n->rss_data.hash_types,
-n->rss_data.indirections_len,
-temp.b);
+virtio_net_commit_rss_config(n);
 return queue_pairs;
 error:
 trace_virtio_net_rss_error(err_msg, err_value);
@@ -3035,26 +3036,7 @@ static int virtio_net_post_load_device(void *opaque, int 
version_id)
 }
 }
 
-if (n->rss_data.enabled) {
-n->rss_data.enabled_software_rss = n->rss_data.populate_hash;
-if (!n->rss_data.populate_hash) {
-if (!virtio_net_attach_epbf_rss(n)) {
-if (get_vhost_net(qemu_get_queue(n->nic)->peer)) {
-warn_report("Can't post-load eBPF RSS for vhost");
-} else {
-warn_report("Can't post-load eBPF RSS - "
-"fallback to software RSS");
-n->rss_data.enabled_software_rss = true;
-}
-}
-}
-
-trace_virtio_net_rss_enable(n->rss_data.hash_types,
-n->rss_data.indirections_len,
-sizeof(n->rss_data.key));
-} else {
-trace_virtio_net_rss_disable();
-}
+virtio_net_commit_rss_config(n);
 return 0;
 }
 
-- 
2.42.0

[PATCH v6 04/21] net: Remove receive_raw()

[Akihiko Odaki]

While netmap implements virtio-net header, it does not implement
receive_raw(). Instead of implementing receive_raw for netmap, add
virtio-net headers in the common code and use receive_iov()/receive()
instead. This also fixes the buffer size for the virtio-net header.

Fixes: fbbdbddec0 ("tap: allow extended virtio header with hash info")
Signed-off-by: Akihiko Odaki 
---
 include/net/net.h   |  1 -
 include/net/queue.h |  1 -
 net/net.c   | 17 +
 net/queue.c | 30 ++
 net/tap.c   |  1 -
 5 files changed, 19 insertions(+), 31 deletions(-)

diff --git a/include/net/net.h b/include/net/net.h
index d98a2b136a..5bc1f82550 100644
--- a/include/net/net.h
+++ b/include/net/net.h
@@ -72,7 +72,6 @@ typedef struct NetClientInfo {
 NetClientDriver type;
 size_t size;
 NetReceive *receive;
-NetReceive *receive_raw;
 NetReceiveIOV *receive_iov;
 NetCanReceive *can_receive;
 NetStart *start;
diff --git a/include/net/queue.h b/include/net/queue.h
index 9f2f289d77..7a43863be2 100644
--- a/include/net/queue.h
+++ b/include/net/queue.h
@@ -31,7 +31,6 @@ typedef struct NetQueue NetQueue;
 typedef void (NetPacketSent) (NetClientState *sender, ssize_t ret);
 
 #define QEMU_NET_PACKET_FLAG_NONE  0
-#define QEMU_NET_PACKET_FLAG_RAW  (1<<0)
 
 /* Returns:
  *   >0 - success
diff --git a/net/net.c b/net/net.c
index 717d48ce15..ad8ecce5d6 100644
--- a/net/net.c
+++ b/net/net.c
@@ -761,8 +761,13 @@ ssize_t qemu_receive_packet_iov(NetClientState *nc, const 
struct iovec *iov,
 
 ssize_t qemu_send_packet_raw(NetClientState *nc, const uint8_t *buf, int size)
 {
-return qemu_send_packet_async_with_flags(nc, QEMU_NET_PACKET_FLAG_RAW,
- buf, size, NULL);
+struct virtio_net_hdr_v1_hash vnet_hdr = { };
+struct iovec iov[] = {
+{ .iov_base = _hdr, .iov_len = nc->vnet_hdr_len },
+{ .iov_base = (void *)buf, .iov_len = size }
+};
+
+return qemu_sendv_packet_async(nc, iov, ARRAY_SIZE(iov), NULL);
 }
 
 static ssize_t nc_sendv_compat(NetClientState *nc, const struct iovec *iov,
@@ -786,11 +791,7 @@ static ssize_t nc_sendv_compat(NetClientState *nc, const 
struct iovec *iov,
 offset = iov_to_buf(iov, iovcnt, 0, buf, offset);
 }
 
-if (flags & QEMU_NET_PACKET_FLAG_RAW && nc->info->receive_raw) {
-ret = nc->info->receive_raw(nc, buffer, offset);
-} else {
-ret = nc->info->receive(nc, buffer, offset);
-}
+ret = nc->info->receive(nc, buffer, offset);
 
 g_free(buf);
 return ret;
@@ -823,7 +824,7 @@ static ssize_t qemu_deliver_packet_iov(NetClientState 
*sender,
 owned_reentrancy_guard->engaged_in_io = true;
 }
 
-if (nc->info->receive_iov && !(flags & QEMU_NET_PACKET_FLAG_RAW)) {
+if (nc->info->receive_iov) {
 ret = nc->info->receive_iov(nc, iov, iovcnt);
 } else {
 ret = nc_sendv_compat(nc, iov, iovcnt, flags);
diff --git a/net/queue.c b/net/queue.c
index c872d51df8..70d29d7ac0 100644
--- a/net/queue.c
+++ b/net/queue.c
@@ -43,7 +43,6 @@
 struct NetPacket {
 QTAILQ_ENTRY(NetPacket) entry;
 NetClientState *sender;
-unsigned flags;
 int size;
 NetPacketSent *sent_cb;
 uint8_t data[];
@@ -92,7 +91,6 @@ void qemu_del_net_queue(NetQueue *queue)
 
 static void qemu_net_queue_append(NetQueue *queue,
   NetClientState *sender,
-  unsigned flags,
   const uint8_t *buf,
   size_t size,
   NetPacketSent *sent_cb)
@@ -104,7 +102,6 @@ static void qemu_net_queue_append(NetQueue *queue,
 }
 packet = g_malloc(sizeof(NetPacket) + size);
 packet->sender = sender;
-packet->flags = flags;
 packet->size = size;
 packet->sent_cb = sent_cb;
 memcpy(packet->data, buf, size);
@@ -115,7 +112,6 @@ static void qemu_net_queue_append(NetQueue *queue,
 
 void qemu_net_queue_append_iov(NetQueue *queue,
NetClientState *sender,
-   unsigned flags,
const struct iovec *iov,
int iovcnt,
NetPacketSent *sent_cb)
@@ -134,7 +130,6 @@ void qemu_net_queue_append_iov(NetQueue *queue,
 packet = g_malloc(sizeof(NetPacket) + max_len);
 packet->sender = sender;
 packet->sent_cb = sent_cb;
-packet->flags = flags;
 packet->size = 0;
 
 for (i = 0; i < iovcnt; i++) {
@@ -150,7 +145,6 @@ void qemu_net_queue_append_iov(NetQueue *queue,
 
 static ssize_t qemu_net_queue_deliver(NetQueue *queue,
   NetClientState *sender,
-  unsigned flags,
   const uint8_t *data,
   size_t size)
 {
@@ -161,7 +155,7 @@ static 

[PATCH v6 08/21] virtio-net: Copy header only when necessary

[Akihiko Odaki]

It is necessary to copy the header only for byte swapping. Worse, when
byte swapping is not needed, the header can be larger than the buffer
due to VIRTIO_NET_F_HASH_REPORT, which results in buffer overflow.

Copy the header only when byte swapping is needed.

Fixes: e22f0603fb ("virtio-net: reference implementation of hash report")
Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 26 --
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index e12176acb1..b6223031e1 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -359,7 +359,8 @@ static void virtio_net_vnet_endian_status(VirtIONet *n, 
uint8_t status)
  * can't do it, we fallback onto fixing the headers in the core
  * virtio-net code.
  */
-n->needs_vnet_hdr_swap = virtio_net_set_vnet_endian(vdev, n->nic->ncs,
+n->needs_vnet_hdr_swap = n->has_vnet_hdr &&
+ virtio_net_set_vnet_endian(vdev, n->nic->ncs,
 queue_pairs, true);
 } else if (virtio_net_started(n, vdev->status)) {
 /* After using the device, we need to reset the network backend to
@@ -2709,7 +2710,7 @@ static int32_t virtio_net_flush_tx(VirtIONetQueue *q)
 return -EINVAL;
 }
 
-if (n->has_vnet_hdr) {
+if (n->needs_vnet_hdr_swap) {
 if (iov_to_buf(out_sg, out_num, 0, , n->guest_hdr_len) <
 n->guest_hdr_len) {
 virtio_error(vdev, "virtio-net header incorrect");
@@ -2717,19 +2718,16 @@ static int32_t virtio_net_flush_tx(VirtIONetQueue *q)
 g_free(elem);
 return -EINVAL;
 }
-if (n->needs_vnet_hdr_swap) {
-virtio_net_hdr_swap(vdev, (void *) );
-sg2[0].iov_base = 
-sg2[0].iov_len = n->guest_hdr_len;
-out_num = iov_copy([1], ARRAY_SIZE(sg2) - 1,
-   out_sg, out_num,
-   n->guest_hdr_len, -1);
-if (out_num == VIRTQUEUE_MAX_SIZE) {
-goto drop;
-}
-out_num += 1;
-out_sg = sg2;
+virtio_net_hdr_swap(vdev, (void *) );
+sg2[0].iov_base = 
+sg2[0].iov_len = n->guest_hdr_len;
+out_num = iov_copy([1], ARRAY_SIZE(sg2) - 1, out_sg, out_num,
+   n->guest_hdr_len, -1);
+if (out_num == VIRTQUEUE_MAX_SIZE) {
+goto drop;
 }
+out_num += 1;
+out_sg = sg2;
 }
 /*
  * If host wants to see the guest header as is, we can
-- 
2.42.0

[PATCH v6 00/21] virtio-net RSS/hash report fixes and improvements

[Akihiko Odaki]

Based-on: <20230524064704.47711-1-akihiko.od...@daynix.com>
("[PATCH 0/2] net: Update MemReentrancyGuard for NIC")

This series contains fixes and improvements for virtio-net RSS and hash
reporting feature.

V5 -> V6:
  Corrected the message for patch "virtio-net: Return an error when vhost
  cannot enable RSS".
  Removed changes to introduce asserts from "virtio-net: Return an error
  when vhost cannot enable RSS".
  Reorganized patches "virtio-net: Return an error when vhost cannot enable
  RSS" and "virtio-net: Do not clear VIRTIO_NET_F_RSS". This version now
  contains patches "virtio-net: Return an error when vhost cannot enable
  RSS" and "virtio-net: Enable software RSS".
  Rebased.

V4 -> V5:
  Added patch "virtio-net: Do not write hashes to peer buffer".

V3 -> V4:
  Extract patches "tap: Remove tap_receive()" and  "net: Remove flag
  propagation" from "net: Remove receive_raw()".
  Added patch "virtio-net: Always set populate_hash".
  Added patch "virtio-net: Do not clear VIRTIO_NET_F_HASH_REPORT".
  Added patch "ebpf: Use standard section name".
  Added patch "ebpf: Simplify error handling".
  Added patch "ebpf: Return 0 when configuration fails".
  Added patch "ebpf: Refactor tun_rss_steering_prog()".
  Added patch "ebpf: Add a separate target for skeleton".

V2 -> V3:
  Added patch "tap: Remove tap_probe_vnet_hdr_len()".
  Added patch "tap: Remove qemu_using_vnet_hdr()".
  Added patch "net: Move virtio-net header length assertion".
  Added patch "net: Remove receive_raw()".
  Added patch "tap: Shrink zeroed virtio-net header".
  Dropped patch "tap: Fix virtio-net header buffer size".

V1 -> V2:
  Added patch "ebpf: Fix RSS error handling".

Akihiko Odaki (21):
  tap: Remove tap_probe_vnet_hdr_len()
  tap: Remove qemu_using_vnet_hdr()
  net: Move virtio-net header length assertion
  net: Remove receive_raw()
  tap: Remove tap_receive()
  net: Remove flag propagation
  tap: Shrink zeroed virtio-net header
  virtio-net: Copy header only when necessary
  virtio-net: Disable RSS on reset
  virtio-net: Unify the logic to update NIC state for RSS
  virtio-net: Return an error when vhost cannot enable RSS
  virtio-net: Enable software RSS
  virtio-net: Always set populate_hash
  virtio-net: Do not write hashes to peer buffer
  virtio-net: Do not clear VIRTIO_NET_F_HASH_REPORT
  ebpf: Fix RSS error handling
  ebpf: Use standard section name
  ebpf: Simplify error handling
  ebpf: Return 0 when configuration fails
  ebpf: Refactor tun_rss_steering_prog()
  ebpf: Add a separate target for skeleton

 ebpf/rss.bpf.skeleton.h  | 1557 +++---
 include/net/filter.h |3 -
 include/net/net.h|7 -
 include/net/queue.h  |7 -
 include/sysemu/replay.h  |2 +-
 net/tap_int.h|1 -
 ebpf/ebpf_rss.c  |   12 +-
 hw/net/e1000e.c  |1 -
 hw/net/igb.c |1 -
 hw/net/net_tx_pkt.c  |4 +-
 hw/net/virtio-net.c  |  310 
 hw/net/vmxnet3.c |2 -
 net/dump.c   |8 +-
 net/filter-buffer.c  |4 +-
 net/filter-mirror.c  |6 +-
 net/filter-replay.c  |3 +-
 net/filter-rewriter.c|5 +-
 net/filter.c |8 +-
 net/net.c|   83 +-
 net/netmap.c |5 -
 net/queue.c  |   30 +-
 net/tap-bsd.c|5 -
 net/tap-linux.c  |   20 -
 net/tap-solaris.c|5 -
 net/tap-stub.c   |5 -
 net/tap.c|   74 +-
 replay/replay-net.c  |8 +-
 tools/ebpf/rss.bpf.c |   46 +-
 tools/ebpf/Makefile.ebpf |   15 +-
 29 files changed, 1016 insertions(+), 1221 deletions(-)

-- 
2.42.0

[PATCH v6 19/21] ebpf: Return 0 when configuration fails

[Akihiko Odaki]

The kernel interprets the returned value as an unsigned 32-bit so -1
will mean queue 4294967295, which is awkward. Return 0 instead.

Signed-off-by: Akihiko Odaki 
---
 ebpf/rss.bpf.skeleton.h | 1339 +++
 tools/ebpf/rss.bpf.c|2 +-
 2 files changed, 670 insertions(+), 671 deletions(-)

diff --git a/ebpf/rss.bpf.skeleton.h b/ebpf/rss.bpf.skeleton.h
index f011c3258e..3e33786799 100644
--- a/ebpf/rss.bpf.skeleton.h
+++ b/ebpf/rss.bpf.skeleton.h
@@ -176,643 +176,642 @@ err:
 
 static inline const void *rss_bpf__elf_bytes(size_t *sz)
 {
-   *sz = 20520;
+   *sz = 20480;
return (const void *)"\
 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\xe8\x4c\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\
-\x01\0\xbf\x19\0\0\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\x4c\xff\0\0\0\0\xbf\xa7\
-\0\0\0\0\0\0\x07\x07\0\0\x4c\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
-\xbf\x72\0\0\0\0\0\0\x85\0\0\0\x01\0\0\0\xbf\x06\0\0\0\0\0\0\x18\x01\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\xbf\x72\0\0\0\0\0\0\x85\0\0\0\x01\0\0\0\xbf\x08\0\0\0\0\0\0\
-\x18\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\x15\x06\x62\x02\0\0\0\0\xbf\x87\0\0\
-\0\0\0\0\x15\x07\x60\x02\0\0\0\0\x71\x61\0\0\0\0\0\0\x55\x01\x01\0\0\0\0\0\x05\
-\0\x59\x02\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xc0\xff\0\0\0\0\x7b\x1a\xb8\xff\
-\0\0\0\0\x7b\x1a\xb0\xff\0\0\0\0\x7b\x1a\xa8\xff\0\0\0\0\x7b\x1a\xa0\xff\0\0\0\
-\0\x63\x1a\x98\xff\0\0\0\0\x7b\x1a\x90\xff\0\0\0\0\x7b\x1a\x88\xff\0\0\0\0\x7b\
-\x1a\x80\xff\0\0\0\0\x7b\x1a\x78\xff\0\0\0\0\x7b\x1a\x70\xff\0\0\0\0\x7b\x1a\
-\x68\xff\0\0\0\0\x7b\x1a\x60\xff\0\0\0\0\x7b\x1a\x58\xff\0\0\0\0\x7b\x1a\x50\
-\xff\0\0\0\0\x15\x09\x48\x02\0\0\0\0\x6b\x1a\xc8\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\
-\0\x07\x03\0\0\xc8\xff\xff\xff\xbf\x91\0\0\0\0\0\0\xb7\x02\0\0\x0c\0\0\0\xb7\
-\x04\0\0\x02\0\0\0\xb7\x05\0\0\0\0\0\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\
-\x77\0\0\0\x20\0\0\0\x55\0\x3d\x02\0\0\0\0\xb7\x02\0\0\x10\0\0\0\x69\xa1\xc8\
-\xff\0\0\0\0\xbf\x13\0\0\0\0\0\0\xdc\x03\0\0\x10\0\0\0\x15\x03\x02\0\0\x81\0\0\
-\x55\x03\x0b\0\xa8\x88\0\0\xb7\x02\0\0\x14\0\0\0\xbf\xa3\0\0\0\0\0\0\x07\x03\0\
-\0\xc8\xff\xff\xff\xbf\x91\0\0\0\0\0\0\xb7\x04\0\0\x02\0\0\0\xb7\x05\0\0\0\0\0\
-\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\x77\0\0\0\x20\0\0\0\x55\0\x2d\x02\0\
-\0\0\0\x69\xa1\xc8\xff\0\0\0\0\x15\x01\x2b\x02\0\0\0\0\x7b\x7a\x30\xff\0\0\0\0\
-\x7b\x9a\x38\xff\0\0\0\0\x15\x01\x55\0\x86\xdd\0\0\x55\x01\x39\0\x08\0\0\0\xb7\
-\x07\0\0\x01\0\0\0\x73\x7a\x50\xff\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xd8\xff\
-\0\0\0\0\x7b\x1a\xd0\xff\0\0\0\0\x7b\x1a\xc8\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\0\
-\x07\x03\0\0\xc8\xff\xff\xff\x79\xa1\x38\xff\0\0\0\0\xb7\x02\0\0\0\0\0\0\xb7\
-\x04\0\0\x14\0\0\0\xb7\x05\0\0\x01\0\0\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\
-\0\x77\0\0\0\x20\0\0\0\x55\0\x17\x02\0\0\0\0\x69\xa1\xce\xff\0\0\0\0\x55\x01\
-\x01\0\0\0\0\0\xb7\x07\0\0\0\0\0\0\x61\xa1\xd4\xff\0\0\0\0\x63\x1a\x5c\xff\0\0\
-\0\0\x61\xa1\xd8\xff\0\0\0\0\x63\x1a\x60\xff\0\0\0\0\x71\xa9\xd1\xff\0\0\0\0\
-\x73\x7a\x56\xff\0\0\0\0\x71\xa1\xc8\xff\0\0\0\0\x67\x01\0\0\x02\0\0\0\x57\x01\
-\0\0\x3c\0\0\0\x7b\x1a\x40\xff\0\0\0\0\xbf\x91\0\0\0\0\0\0\x57\x01\0\0\xff\0\0\
-\0\x15\x01\x19\0\0\0\0\0\x57\x07\0\0\xff\0\0\0\x55\x07\x17\0\0\0\0\0\x57\x09\0\
-\0\xff\0\0\0\x15\x09\x5a\x01\x11\0\0\0\x55\x09\x14\0\x06\0\0\0\xb7\x01\0\0\x01\
-\0\0\0\x73\x1a\x53\xff\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xd8\xff\0\0\0\0\x7b\
-\x1a\xd0\xff\0\0\0\0\x7b\x1a\xc8\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\0\x07\x03\0\0\
-\xc8\xff\xff\xff\x79\xa1\x38\xff\0\0\0\0\x79\xa2\x40\xff\0\0\0\0\xb7\x04\0\0\
-\x14\0\0\0\xb7\x05\0\0\x01\0\0\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\x77\0\
-\0\0\x20\0\0\0\x55\0\xf2\x01\0\0\0\0\x69\xa1\xc8\xff\0\0\0\0\x6b\x1a\x58\xff\0\
-\0\0\0\x69\xa1\xca\xff\0\0\0\0\x6b\x1a\x5a\xff\0\0\0\0\x71\xa1\x50\xff\0\0\0\0\
-\x15\x01\xdb\0\0\0\0\0\x71\x62\x03\0\0\0\0\0\x67\x02\0\0\x08\0\0\0\x71\x61\x02\
-\0\0\0\0\0\x4f\x12\0\0\0\0\0\0\x71\x63\x04\0\0\0\0\0\x67\x03\0\0\x10\0\0\0\x71\
-\x61\x05\0\0\0\0\0\x67\x01\0\0\x18\0\0\0\x4f\x31\0\0\0\0\0\0\x4f\x21\0\0\0\0\0\
-\0\x71\xa2\x53\xff\0\0\0\0\x79\xa0\x30\xff\0\0\0\0\x15\x02\x0c\x01\0\0\0\0\xbf\
-\x12\0\0\0\0\0\0\x57\x02\0\0\x02\0\0\0\x15\x02\x09\x01\0\0\0\0\x61\xa1\x5c\xff\
-\0\0\0\0\x63\x1a\xa0\xff\0\0\0\0\x61\xa1\x60\xff\0\0\0\0\x63\x1a\xa4\xff\0\0\0\
-\0\x69\xa1\x58\xff\0\0\0\0\x6b\x1a\xa8\xff\0\0\0\0\x69\xa1\x5a\xff\0\0\0\0\x6b\
-\x1a\xaa\xff\0\0\0\0\x05\0\x6a\x01\0\0\0\0\xb7\x01\0\0\x01\0\0\0\x73\x1a\x51\
-\xff\0\0\0\0\xb7\x01\0\0\0\0\0\0\x7b\x1a\xe8\xff\0\0\0\0\x7b\x1a\xe0\xff\0\0\0\
-\0\x7b\x1a\xd8\xff\0\0\0\0\x7b\x1a\xd0\xff\0\0\0\0\x7b\x1a\xc8\xff\0\0\0\0\xbf\
-\xa3\0\0\0\0\0\0\x07\x03\0\0\xc8\xff\xff\xff\xb7\x01\0\0\x28\0\0\0\x7b\x1a\x40\
-\xff\0\0\0\0\xbf\x91\0\0\0\0\0\0\xb7\x02\0\0\0\0\0\0\xb7\x04\0\0\x28\0\0\0\xb7\
-\x05\0\0\x01\0\0\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\x77\0\0\0\x20\0\0\0\

[PATCH v6 03/21] net: Move virtio-net header length assertion

[Akihiko Odaki]

The virtio-net header length assertion should happen for any clients.

Signed-off-by: Akihiko Odaki 
---
 net/net.c | 5 +
 net/tap.c | 3 ---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/net/net.c b/net/net.c
index fda9a8f994..717d48ce15 100644
--- a/net/net.c
+++ b/net/net.c
@@ -56,6 +56,7 @@
 #include "net/filter.h"
 #include "qapi/string-output-visitor.h"
 #include "qapi/qobject-input-visitor.h"
+#include "standard-headers/linux/virtio_net.h"
 
 /* Net bridge is currently not supported for W32. */
 #if !defined(_WIN32)
@@ -549,6 +550,10 @@ void qemu_set_vnet_hdr_len(NetClientState *nc, int len)
 return;
 }
 
+assert(len == sizeof(struct virtio_net_hdr_mrg_rxbuf) ||
+   len == sizeof(struct virtio_net_hdr) ||
+   len == sizeof(struct virtio_net_hdr_v1_hash));
+
 nc->vnet_hdr_len = len;
 nc->info->set_vnet_hdr_len(nc, len);
 }
diff --git a/net/tap.c b/net/tap.c
index 0e031ee9fa..d94731b2fa 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -274,9 +274,6 @@ static void tap_set_vnet_hdr_len(NetClientState *nc, int 
len)
 TAPState *s = DO_UPCAST(TAPState, nc, nc);
 
 assert(nc->info->type == NET_CLIENT_DRIVER_TAP);
-assert(len == sizeof(struct virtio_net_hdr_mrg_rxbuf) ||
-   len == sizeof(struct virtio_net_hdr) ||
-   len == sizeof(struct virtio_net_hdr_v1_hash));
 
 tap_fd_set_vnet_hdr_len(s->fd, len);
 s->host_vnet_hdr_len = len;
-- 
2.42.0

[PATCH v6 09/21] virtio-net: Disable RSS on reset

[Akihiko Odaki]

RSS is disabled by default.

Fixes: 590790297c ("virtio-net: implement RSS configuration command")
Signed-off-by: Akihiko Odaki 
Reviewed-by: Michael Tokarev 
---
 hw/net/virtio-net.c | 70 +++--
 1 file changed, 36 insertions(+), 34 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index b6223031e1..4c528baad9 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -599,40 +599,6 @@ static void virtio_net_queue_enable(VirtIODevice *vdev, 
uint32_t queue_index)
 }
 }
 
-static void virtio_net_reset(VirtIODevice *vdev)
-{
-VirtIONet *n = VIRTIO_NET(vdev);
-int i;
-
-/* Reset back to compatibility mode */
-n->promisc = 1;
-n->allmulti = 0;
-n->alluni = 0;
-n->nomulti = 0;
-n->nouni = 0;
-n->nobcast = 0;
-/* multiqueue is disabled by default */
-n->curr_queue_pairs = 1;
-timer_del(n->announce_timer.tm);
-n->announce_timer.round = 0;
-n->status &= ~VIRTIO_NET_S_ANNOUNCE;
-
-/* Flush any MAC and VLAN filter table state */
-n->mac_table.in_use = 0;
-n->mac_table.first_multi = 0;
-n->mac_table.multi_overflow = 0;
-n->mac_table.uni_overflow = 0;
-memset(n->mac_table.macs, 0, MAC_TABLE_ENTRIES * ETH_ALEN);
-memcpy(>mac[0], >nic->conf->macaddr, sizeof(n->mac));
-qemu_format_nic_info_str(qemu_get_queue(n->nic), n->mac);
-memset(n->vlans, 0, MAX_VLAN >> 3);
-
-/* Flush any async TX */
-for (i = 0;  i < n->max_queue_pairs; i++) {
-flush_or_purge_queued_packets(qemu_get_subqueue(n->nic, i));
-}
-}
-
 static void peer_test_vnet_hdr(VirtIONet *n)
 {
 NetClientState *nc = qemu_get_queue(n->nic);
@@ -3805,6 +3771,42 @@ static void virtio_net_device_unrealize(DeviceState *dev)
 virtio_cleanup(vdev);
 }
 
+static void virtio_net_reset(VirtIODevice *vdev)
+{
+VirtIONet *n = VIRTIO_NET(vdev);
+int i;
+
+/* Reset back to compatibility mode */
+n->promisc = 1;
+n->allmulti = 0;
+n->alluni = 0;
+n->nomulti = 0;
+n->nouni = 0;
+n->nobcast = 0;
+/* multiqueue is disabled by default */
+n->curr_queue_pairs = 1;
+timer_del(n->announce_timer.tm);
+n->announce_timer.round = 0;
+n->status &= ~VIRTIO_NET_S_ANNOUNCE;
+
+/* Flush any MAC and VLAN filter table state */
+n->mac_table.in_use = 0;
+n->mac_table.first_multi = 0;
+n->mac_table.multi_overflow = 0;
+n->mac_table.uni_overflow = 0;
+memset(n->mac_table.macs, 0, MAC_TABLE_ENTRIES * ETH_ALEN);
+memcpy(>mac[0], >nic->conf->macaddr, sizeof(n->mac));
+qemu_format_nic_info_str(qemu_get_queue(n->nic), n->mac);
+memset(n->vlans, 0, MAX_VLAN >> 3);
+
+/* Flush any async TX */
+for (i = 0;  i < n->max_queue_pairs; i++) {
+flush_or_purge_queued_packets(qemu_get_subqueue(n->nic, i));
+}
+
+virtio_net_disable_rss(n);
+}
+
 static void virtio_net_instance_init(Object *obj)
 {
 VirtIONet *n = VIRTIO_NET(obj);
-- 
2.42.0

[PATCH v6 17/21] ebpf: Use standard section name

[Akihiko Odaki]

It makes easier to play with bpftool by allowing it to infer the program
type. It also makes it unnecessary to set the program type manually
when loading the program in ebpf_rss_load().

Signed-off-by: Akihiko Odaki 
---
 ebpf/rss.bpf.skeleton.h | 1514 ---
 ebpf/ebpf_rss.c |2 -
 tools/ebpf/rss.bpf.c|2 +-
 3 files changed, 760 insertions(+), 758 deletions(-)

diff --git a/ebpf/rss.bpf.skeleton.h b/ebpf/rss.bpf.skeleton.h
index 18eb2adb12..f011c3258e 100644
--- a/ebpf/rss.bpf.skeleton.h
+++ b/ebpf/rss.bpf.skeleton.h
@@ -176,796 +176,800 @@ err:
 
 static inline const void *rss_bpf__elf_bytes(size_t *sz)
 {
-   *sz = 20440;
+   *sz = 20520;
return (const void *)"\
 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\x98\x4c\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\
-\x01\0\xbf\x19\0\0\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\x54\xff\0\0\0\0\xbf\xa7\
-\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\0\xe8\x4c\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\
+\x01\0\xbf\x19\0\0\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\x4c\xff\0\0\0\0\xbf\xa7\
+\0\0\0\0\0\0\x07\x07\0\0\x4c\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
 \xbf\x72\0\0\0\0\0\0\x85\0\0\0\x01\0\0\0\xbf\x06\0\0\0\0\0\0\x18\x01\0\0\0\0\0\
 \0\0\0\0\0\0\0\0\0\xbf\x72\0\0\0\0\0\0\x85\0\0\0\x01\0\0\0\xbf\x08\0\0\0\0\0\0\
-\x18\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\x15\x06\x67\x02\0\0\0\0\xbf\x87\0\0\
-\0\0\0\0\x15\x07\x65\x02\0\0\0\0\x71\x61\0\0\0\0\0\0\x55\x01\x01\0\0\0\0\0\x05\
-\0\x5e\x02\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xc8\xff\0\0\0\0\x7b\x1a\xc0\xff\
-\0\0\0\0\x7b\x1a\xb8\xff\0\0\0\0\x7b\x1a\xb0\xff\0\0\0\0\x7b\x1a\xa8\xff\0\0\0\
-\0\x63\x1a\xa0\xff\0\0\0\0\x7b\x1a\x98\xff\0\0\0\0\x7b\x1a\x90\xff\0\0\0\0\x7b\
-\x1a\x88\xff\0\0\0\0\x7b\x1a\x80\xff\0\0\0\0\x7b\x1a\x78\xff\0\0\0\0\x7b\x1a\
-\x70\xff\0\0\0\0\x7b\x1a\x68\xff\0\0\0\0\x7b\x1a\x60\xff\0\0\0\0\x7b\x1a\x58\
-\xff\0\0\0\0\x15\x09\x4d\x02\0\0\0\0\x6b\x1a\xd0\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\
-\0\x07\x03\0\0\xd0\xff\xff\xff\xbf\x91\0\0\0\0\0\0\xb7\x02\0\0\x0c\0\0\0\xb7\
+\x18\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\x15\x06\x62\x02\0\0\0\0\xbf\x87\0\0\
+\0\0\0\0\x15\x07\x60\x02\0\0\0\0\x71\x61\0\0\0\0\0\0\x55\x01\x01\0\0\0\0\0\x05\
+\0\x59\x02\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xc0\xff\0\0\0\0\x7b\x1a\xb8\xff\
+\0\0\0\0\x7b\x1a\xb0\xff\0\0\0\0\x7b\x1a\xa8\xff\0\0\0\0\x7b\x1a\xa0\xff\0\0\0\
+\0\x63\x1a\x98\xff\0\0\0\0\x7b\x1a\x90\xff\0\0\0\0\x7b\x1a\x88\xff\0\0\0\0\x7b\
+\x1a\x80\xff\0\0\0\0\x7b\x1a\x78\xff\0\0\0\0\x7b\x1a\x70\xff\0\0\0\0\x7b\x1a\
+\x68\xff\0\0\0\0\x7b\x1a\x60\xff\0\0\0\0\x7b\x1a\x58\xff\0\0\0\0\x7b\x1a\x50\
+\xff\0\0\0\0\x15\x09\x48\x02\0\0\0\0\x6b\x1a\xc8\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\
+\0\x07\x03\0\0\xc8\xff\xff\xff\xbf\x91\0\0\0\0\0\0\xb7\x02\0\0\x0c\0\0\0\xb7\
 \x04\0\0\x02\0\0\0\xb7\x05\0\0\0\0\0\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\
-\x77\0\0\0\x20\0\0\0\x55\0\x42\x02\0\0\0\0\xb7\x02\0\0\x10\0\0\0\x69\xa1\xd0\
+\x77\0\0\0\x20\0\0\0\x55\0\x3d\x02\0\0\0\0\xb7\x02\0\0\x10\0\0\0\x69\xa1\xc8\
 \xff\0\0\0\0\xbf\x13\0\0\0\0\0\0\xdc\x03\0\0\x10\0\0\0\x15\x03\x02\0\0\x81\0\0\
 \x55\x03\x0b\0\xa8\x88\0\0\xb7\x02\0\0\x14\0\0\0\xbf\xa3\0\0\0\0\0\0\x07\x03\0\
-\0\xd0\xff\xff\xff\xbf\x91\0\0\0\0\0\0\xb7\x04\0\0\x02\0\0\0\xb7\x05\0\0\0\0\0\
-\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\x77\0\0\0\x20\0\0\0\x55\0\x32\x02\0\
-\0\0\0\x69\xa1\xd0\xff\0\0\0\0\x15\x01\x30\x02\0\0\0\0\x7b\x7a\x38\xff\0\0\0\0\
-\x7b\x9a\x40\xff\0\0\0\0\x15\x01\x55\0\x86\xdd\0\0\x55\x01\x39\0\x08\0\0\0\xb7\
-\x07\0\0\x01\0\0\0\x73\x7a\x58\xff\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xe0\xff\
-\0\0\0\0\x7b\x1a\xd8\xff\0\0\0\0\x7b\x1a\xd0\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\0\
-\x07\x03\0\0\xd0\xff\xff\xff\x79\xa1\x40\xff\0\0\0\0\xb7\x02\0\0\0\0\0\0\xb7\
+\0\xc8\xff\xff\xff\xbf\x91\0\0\0\0\0\0\xb7\x04\0\0\x02\0\0\0\xb7\x05\0\0\0\0\0\
+\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\0\x77\0\0\0\x20\0\0\0\x55\0\x2d\x02\0\
+\0\0\0\x69\xa1\xc8\xff\0\0\0\0\x15\x01\x2b\x02\0\0\0\0\x7b\x7a\x30\xff\0\0\0\0\
+\x7b\x9a\x38\xff\0\0\0\0\x15\x01\x55\0\x86\xdd\0\0\x55\x01\x39\0\x08\0\0\0\xb7\
+\x07\0\0\x01\0\0\0\x73\x7a\x50\xff\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xd8\xff\
+\0\0\0\0\x7b\x1a\xd0\xff\0\0\0\0\x7b\x1a\xc8\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\0\
+\x07\x03\0\0\xc8\xff\xff\xff\x79\xa1\x38\xff\0\0\0\0\xb7\x02\0\0\0\0\0\0\xb7\
 \x04\0\0\x14\0\0\0\xb7\x05\0\0\x01\0\0\0\x85\0\0\0\x44\0\0\0\x67\0\0\0\x20\0\0\
-\0\x77\0\0\0\x20\0\0\0\x55\0\x1c\x02\0\0\0\0\x69\xa1\xd6\xff\0\0\0\0\x55\x01\
-\x01\0\0\0\0\0\xb7\x07\0\0\0\0\0\0\x61\xa1\xdc\xff\0\0\0\0\x63\x1a\x64\xff\0\0\
-\0\0\x61\xa1\xe0\xff\0\0\0\0\x63\x1a\x68\xff\0\0\0\0\x71\xa9\xd9\xff\0\0\0\0\
-\x73\x7a\x5e\xff\0\0\0\0\x71\xa1\xd0\xff\0\0\0\0\x67\x01\0\0\x02\0\0\0\x57\x01\
-\0\0\x3c\0\0\0\x7b\x1a\x48\xff\0\0\0\0\xbf\x91\0\0\0\0\0\0\x57\x01\0\0\xff\0\0\
+\0\x77\0\0\0\x20\0\0\0\x55\0\x17\x02\0\0\0\0\x69\xa1\xce\xff\0\0\0\0\x55\x01\

[PATCH v6 18/21] ebpf: Simplify error handling

[Akihiko Odaki]

The error handling procedures required when rss_bpf__open() and
rss_bpf__load(rss_bpf_ctx) are different so it's better to implement
them separately.

Signed-off-by: Akihiko Odaki 
---
 ebpf/ebpf_rss.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/ebpf/ebpf_rss.c b/ebpf/ebpf_rss.c
index 3978333584..2de9e7851f 100644
--- a/ebpf/ebpf_rss.c
+++ b/ebpf/ebpf_rss.c
@@ -46,12 +46,13 @@ bool ebpf_rss_load(struct EBPFRSSContext *ctx)
 rss_bpf_ctx = rss_bpf__open();
 if (rss_bpf_ctx == NULL) {
 trace_ebpf_error("eBPF RSS", "can not open eBPF RSS object");
-goto error;
+return false;
 }
 
 if (rss_bpf__load(rss_bpf_ctx)) {
 trace_ebpf_error("eBPF RSS", "can not load RSS program");
-goto error;
+rss_bpf__destroy(rss_bpf_ctx);
+return false;
 }
 
 ctx->obj = rss_bpf_ctx;
@@ -65,11 +66,6 @@ bool ebpf_rss_load(struct EBPFRSSContext *ctx)
 rss_bpf_ctx->maps.tap_rss_map_toeplitz_key);
 
 return true;
-error:
-rss_bpf__destroy(rss_bpf_ctx);
-ctx->obj = NULL;
-
-return false;
 }
 
 static bool ebpf_rss_set_config(struct EBPFRSSContext *ctx,
-- 
2.42.0

[PATCH v6 13/21] virtio-net: Always set populate_hash

[Akihiko Odaki]

The member is not cleared during reset so may have a stale value.

Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 1fa020d905..0fe75b3c08 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -650,6 +650,7 @@ static void virtio_net_set_mrg_rx_bufs(VirtIONet *n, int 
mergeable_rx_bufs,
 n->guest_hdr_len = n->mergeable_rx_bufs ?
 sizeof(struct virtio_net_hdr_mrg_rxbuf) :
 sizeof(struct virtio_net_hdr);
+n->rss_data.populate_hash = false;
 }
 
 for (i = 0; i < n->max_queue_pairs; i++) {
-- 
2.42.0

[PATCH v6 07/21] tap: Shrink zeroed virtio-net header

[Akihiko Odaki]

tap prepends a zeroed virtio-net header when writing a packet to a
tap with virtio-net header enabled but not in use. This only happens
when s->host_vnet_hdr_len == sizeof(struct virtio_net_hdr).

Signed-off-by: Akihiko Odaki 
---
 net/tap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/tap.c b/net/tap.c
index ab4e5a0e91..bef680bdab 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -119,7 +119,7 @@ static ssize_t tap_receive_iov(NetClientState *nc, const 
struct iovec *iov,
 TAPState *s = DO_UPCAST(TAPState, nc, nc);
 const struct iovec *iovp = iov;
 g_autofree struct iovec *iov_copy = NULL;
-struct virtio_net_hdr_mrg_rxbuf hdr = { };
+struct virtio_net_hdr hdr = { };
 
 if (s->host_vnet_hdr_len && !s->using_vnet_hdr) {
 iov_copy = g_new(struct iovec, iovcnt + 1);
-- 
2.42.0

[PATCH v6 01/21] tap: Remove tap_probe_vnet_hdr_len()

[Akihiko Odaki]

It was necessary since an Linux older than 2.6.35 may implement the
virtio-net header but may not allow to change its length. Remove it
since such an old Linux is no longer supported.

Signed-off-by: Akihiko Odaki 
Acked-by: Michael S. Tsirkin 
---
 net/tap_int.h |  1 -
 net/tap-bsd.c |  5 -
 net/tap-linux.c   | 20 
 net/tap-solaris.c |  5 -
 net/tap-stub.c|  5 -
 net/tap.c | 10 ++
 6 files changed, 2 insertions(+), 44 deletions(-)

diff --git a/net/tap_int.h b/net/tap_int.h
index 9a2175655b..8857ff299d 100644
--- a/net/tap_int.h
+++ b/net/tap_int.h
@@ -35,7 +35,6 @@ ssize_t tap_read_packet(int tapfd, uint8_t *buf, int maxlen);
 
 void tap_set_sndbuf(int fd, const NetdevTapOptions *tap, Error **errp);
 int tap_probe_vnet_hdr(int fd, Error **errp);
-int tap_probe_vnet_hdr_len(int fd, int len);
 int tap_probe_has_ufo(int fd);
 int tap_probe_has_uso(int fd);
 void tap_fd_set_offload(int fd, int csum, int tso4, int tso6, int ecn, int ufo,
diff --git a/net/tap-bsd.c b/net/tap-bsd.c
index 274ea7bd2c..b4c84441ba 100644
--- a/net/tap-bsd.c
+++ b/net/tap-bsd.c
@@ -217,11 +217,6 @@ int tap_probe_has_uso(int fd)
 return 0;
 }
 
-int tap_probe_vnet_hdr_len(int fd, int len)
-{
-return 0;
-}
-
 void tap_fd_set_vnet_hdr_len(int fd, int len)
 {
 }
diff --git a/net/tap-linux.c b/net/tap-linux.c
index c7e514ecb0..1226d5fda2 100644
--- a/net/tap-linux.c
+++ b/net/tap-linux.c
@@ -185,26 +185,6 @@ int tap_probe_has_uso(int fd)
 return 1;
 }
 
-/* Verify that we can assign given length */
-int tap_probe_vnet_hdr_len(int fd, int len)
-{
-int orig;
-if (ioctl(fd, TUNGETVNETHDRSZ, ) == -1) {
-return 0;
-}
-if (ioctl(fd, TUNSETVNETHDRSZ, ) == -1) {
-return 0;
-}
-/* Restore original length: we can't handle failure. */
-if (ioctl(fd, TUNSETVNETHDRSZ, ) == -1) {
-fprintf(stderr, "TUNGETVNETHDRSZ ioctl() failed: %s. Exiting.\n",
-strerror(errno));
-abort();
-return -errno;
-}
-return 1;
-}
-
 void tap_fd_set_vnet_hdr_len(int fd, int len)
 {
 if (ioctl(fd, TUNSETVNETHDRSZ, ) == -1) {
diff --git a/net/tap-solaris.c b/net/tap-solaris.c
index 08b13af512..51b7830bef 100644
--- a/net/tap-solaris.c
+++ b/net/tap-solaris.c
@@ -221,11 +221,6 @@ int tap_probe_has_uso(int fd)
 return 0;
 }
 
-int tap_probe_vnet_hdr_len(int fd, int len)
-{
-return 0;
-}
-
 void tap_fd_set_vnet_hdr_len(int fd, int len)
 {
 }
diff --git a/net/tap-stub.c b/net/tap-stub.c
index 4b24f61e3a..38673434cb 100644
--- a/net/tap-stub.c
+++ b/net/tap-stub.c
@@ -52,11 +52,6 @@ int tap_probe_has_uso(int fd)
 return 0;
 }
 
-int tap_probe_vnet_hdr_len(int fd, int len)
-{
-return 0;
-}
-
 void tap_fd_set_vnet_hdr_len(int fd, int len)
 {
 }
diff --git a/net/tap.c b/net/tap.c
index c23d0323c2..5d6f292cfe 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -259,11 +259,7 @@ static bool tap_has_vnet_hdr(NetClientState *nc)
 
 static bool tap_has_vnet_hdr_len(NetClientState *nc, int len)
 {
-TAPState *s = DO_UPCAST(TAPState, nc, nc);
-
-assert(nc->info->type == NET_CLIENT_DRIVER_TAP);
-
-return !!tap_probe_vnet_hdr_len(s->fd, len);
+return tap_has_vnet_hdr(nc);
 }
 
 static int tap_get_vnet_hdr_len(NetClientState *nc)
@@ -432,9 +428,7 @@ static TAPState *net_tap_fd_init(NetClientState *peer,
  * Make sure host header length is set correctly in tap:
  * it might have been modified by another instance of qemu.
  */
-if (tap_probe_vnet_hdr_len(s->fd, s->host_vnet_hdr_len)) {
-tap_fd_set_vnet_hdr_len(s->fd, s->host_vnet_hdr_len);
-}
+tap_fd_set_vnet_hdr_len(s->fd, s->host_vnet_hdr_len);
 tap_read_poll(s, true);
 s->vhost_net = NULL;
 
-- 
2.42.0

[PATCH v6 20/21] ebpf: Refactor tun_rss_steering_prog()

[Akihiko Odaki]

This saves branches and makes later BPF program changes easier.

Signed-off-by: Akihiko Odaki 
---
 tools/ebpf/rss.bpf.c | 26 +++---
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/tools/ebpf/rss.bpf.c b/tools/ebpf/rss.bpf.c
index 22c75d5912..012af38df1 100644
--- a/tools/ebpf/rss.bpf.c
+++ b/tools/ebpf/rss.bpf.c
@@ -544,27 +544,23 @@ int tun_rss_steering_prog(struct __sk_buff *skb)
 config = bpf_map_lookup_elem(_rss_map_configurations, );
 toe = bpf_map_lookup_elem(_rss_map_toeplitz_key, );
 
-if (config && toe) {
-if (!config->redirect) {
-return config->default_queue;
-}
+if (!config || !toe) {
+return 0;
+}
 
-if (calculate_rss_hash(skb, config, toe, )) {
-__u32 table_idx = hash % config->indirections_len;
-__u16 *queue = 0;
+if (config->redirect && calculate_rss_hash(skb, config, toe, )) {
+__u32 table_idx = hash % config->indirections_len;
+__u16 *queue = 0;
 
-queue = bpf_map_lookup_elem(_rss_map_indirection_table,
-_idx);
+queue = bpf_map_lookup_elem(_rss_map_indirection_table,
+_idx);
 
-if (queue) {
-return *queue;
-}
+if (queue) {
+return *queue;
 }
-
-return config->default_queue;
 }
 
-return 0;
+return config->default_queue;
 }
 
 char _license[] SEC("license") = "GPL v2";
-- 
2.42.0

[PATCH v6 12/21] virtio-net: Enable software RSS

[Akihiko Odaki]

virtio-net implements software RSS but does not enable it. Enable it
when RSS is requested, but the eBPF implementation is not available.
We also check if vhost is in use in such a case since software RSS is
incompatible with vhost. A warning will be emitted when falling back to
software RSS since it provides no performance benefit.

Signed-off-by: Akihiko Odaki 
---
 hw/net/virtio-net.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 7bb91617d0..1fa020d905 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -1260,10 +1260,12 @@ static bool virtio_net_attach_epbf_rss(VirtIONet *n)
 
 if (!ebpf_rss_set_all(>ebpf_rss, ,
   n->rss_data.indirections_table, n->rss_data.key)) {
+warn_report("Failed to configure eBPF RSS");
 return false;
 }
 
 if (!virtio_net_attach_ebpf_to_backend(n->nic, n->ebpf_rss.program_fd)) {
+warn_report("Failed to attach eBPF to backend");
 return false;
 }
 
@@ -1278,16 +1280,10 @@ static void virtio_net_detach_epbf_rss(VirtIONet *n)
 static void virtio_net_commit_rss_config(VirtIONet *n)
 {
 if (n->rss_data.enabled) {
-n->rss_data.enabled_software_rss = n->rss_data.populate_hash;
+n->rss_data.enabled_software_rss = n->rss_data.populate_hash ||
+   !virtio_net_attach_epbf_rss(n);
 if (n->rss_data.populate_hash) {
 virtio_net_detach_epbf_rss(n);
-} else if (!virtio_net_attach_epbf_rss(n)) {
-if (get_vhost_net(qemu_get_queue(n->nic)->peer)) {
-warn_report("Can't load eBPF RSS for vhost");
-} else {
-warn_report("Can't load eBPF RSS - fallback to software RSS");
-n->rss_data.enabled_software_rss = true;
-}
 }
 
 trace_virtio_net_rss_enable(n->rss_data.hash_types,
@@ -3747,8 +3743,13 @@ static void virtio_net_device_realize(DeviceState *dev, 
Error **errp)
 
 if (virtio_has_feature(n->host_features, VIRTIO_NET_F_RSS) &&
 !virtio_net_load_ebpf(n)) {
-error_setg(errp, "Can't load eBPF RSS");
-virtio_net_device_unrealize(dev);
+if (get_vhost_net(nc->peer)) {
+error_setg(errp, "Can't load eBPF RSS for vhost");
+virtio_net_device_unrealize(dev);
+return;
+}
+
+warn_report_once("Can't load eBPF RSS - fallback to software RSS");
 }
 }
 
-- 
2.42.0

[PATCH v6 02/21] tap: Remove qemu_using_vnet_hdr()

[Akihiko Odaki]

Since qemu_set_vnet_hdr_len() is always called when
qemu_using_vnet_hdr() is called, we can merge them and save some code.

For consistency, express that the virtio-net header is not in use by
returning 0 with qemu_get_vnet_hdr_len() instead of having a dedicated
function, qemu_get_using_vnet_hdr().

Signed-off-by: Akihiko Odaki 
---
 include/net/net.h   |  6 --
 hw/net/e1000e.c |  1 -
 hw/net/igb.c|  1 -
 hw/net/net_tx_pkt.c |  4 ++--
 hw/net/virtio-net.c |  3 ---
 hw/net/vmxnet3.c|  2 --
 net/dump.c  |  4 +---
 net/net.c   | 18 --
 net/netmap.c|  5 -
 net/tap.c   | 22 ++
 10 files changed, 5 insertions(+), 61 deletions(-)

diff --git a/include/net/net.h b/include/net/net.h
index ffbd2c8d56..d98a2b136a 100644
--- a/include/net/net.h
+++ b/include/net/net.h
@@ -57,8 +57,6 @@ typedef bool (HasUfo)(NetClientState *);
 typedef bool (HasUso)(NetClientState *);
 typedef bool (HasVnetHdr)(NetClientState *);
 typedef bool (HasVnetHdrLen)(NetClientState *, int);
-typedef bool (GetUsingVnetHdr)(NetClientState *);
-typedef void (UsingVnetHdr)(NetClientState *, bool);
 typedef void (SetOffload)(NetClientState *, int, int, int, int, int, int, int);
 typedef int (GetVnetHdrLen)(NetClientState *);
 typedef void (SetVnetHdrLen)(NetClientState *, int);
@@ -88,8 +86,6 @@ typedef struct NetClientInfo {
 HasUso *has_uso;
 HasVnetHdr *has_vnet_hdr;
 HasVnetHdrLen *has_vnet_hdr_len;
-GetUsingVnetHdr *get_using_vnet_hdr;
-UsingVnetHdr *using_vnet_hdr;
 SetOffload *set_offload;
 GetVnetHdrLen *get_vnet_hdr_len;
 SetVnetHdrLen *set_vnet_hdr_len;
@@ -194,8 +190,6 @@ bool qemu_has_ufo(NetClientState *nc);
 bool qemu_has_uso(NetClientState *nc);
 bool qemu_has_vnet_hdr(NetClientState *nc);
 bool qemu_has_vnet_hdr_len(NetClientState *nc, int len);
-bool qemu_get_using_vnet_hdr(NetClientState *nc);
-void qemu_using_vnet_hdr(NetClientState *nc, bool enable);
 void qemu_set_offload(NetClientState *nc, int csum, int tso4, int tso6,
   int ecn, int ufo, int uso4, int uso6);
 int qemu_get_vnet_hdr_len(NetClientState *nc);
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
index e41a6c1038..4edb58858e 100644
--- a/hw/net/e1000e.c
+++ b/hw/net/e1000e.c
@@ -352,7 +352,6 @@ e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, 
uint8_t *macaddr)
 for (i = 0; i < s->conf.peers.queues; i++) {
 nc = qemu_get_subqueue(s->nic, i);
 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
-qemu_using_vnet_hdr(nc->peer, true);
 }
 }
 
diff --git a/hw/net/igb.c b/hw/net/igb.c
index 8b713843d9..cfdb148051 100644
--- a/hw/net/igb.c
+++ b/hw/net/igb.c
@@ -339,7 +339,6 @@ igb_init_net_peer(IGBState *s, PCIDevice *pci_dev, uint8_t 
*macaddr)
 for (i = 0; i < s->conf.peers.queues; i++) {
 nc = qemu_get_subqueue(s->nic, i);
 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
-qemu_using_vnet_hdr(nc->peer, true);
 }
 }
 
diff --git a/hw/net/net_tx_pkt.c b/hw/net/net_tx_pkt.c
index 2e5f58b3c9..668871f8d8 100644
--- a/hw/net/net_tx_pkt.c
+++ b/hw/net/net_tx_pkt.c
@@ -578,7 +578,7 @@ static void net_tx_pkt_sendv(
 {
 NetClientState *nc = opaque;
 
-if (qemu_get_using_vnet_hdr(nc->peer)) {
+if (qemu_get_vnet_hdr_len(nc->peer)) {
 qemu_sendv_packet(nc, virt_iov, virt_iov_cnt);
 } else {
 qemu_sendv_packet(nc, iov, iov_cnt);
@@ -808,7 +808,7 @@ static bool net_tx_pkt_do_sw_fragmentation(struct NetTxPkt 
*pkt,
 
 bool net_tx_pkt_send(struct NetTxPkt *pkt, NetClientState *nc)
 {
-bool offload = qemu_get_using_vnet_hdr(nc->peer);
+bool offload = !!qemu_get_vnet_hdr_len(nc->peer);
 return net_tx_pkt_send_custom(pkt, offload, net_tx_pkt_sendv, nc);
 }
 
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 80c56f0cfc..e12176acb1 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -3728,9 +3728,6 @@ static void virtio_net_device_realize(DeviceState *dev, 
Error **errp)
 
 peer_test_vnet_hdr(n);
 if (peer_has_vnet_hdr(n)) {
-for (i = 0; i < n->max_queue_pairs; i++) {
-qemu_using_vnet_hdr(qemu_get_subqueue(n->nic, i)->peer, true);
-}
 n->host_hdr_len = sizeof(struct virtio_net_hdr);
 } else {
 n->host_hdr_len = 0;
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 6fb4102d03..81ab8ada55 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -2091,8 +2091,6 @@ static void vmxnet3_net_init(VMXNET3State *s)
 if (s->peer_has_vhdr) {
 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
 sizeof(struct virtio_net_hdr));
-
-qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
 }
 
 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
diff --git a/net/dump.c b/net/dump.c
index 16073f2458..956e34a123 100644
--- a/net/dump.c
+++ b/net/dump.c
@@ -154,10 +154,8 @@ static ssize_t 

[PATCH v6 16/21] ebpf: Fix RSS error handling

[Akihiko Odaki]

calculate_rss_hash() was using hash value 0 to tell if it calculated
a hash, but the hash value may be 0 on a rare occasion. Have a
distinct bool value for correctness.

Fixes: f3fa412de2 ("ebpf: Added eBPF RSS program.")
Signed-off-by: Akihiko Odaki 
---
 tools/ebpf/rss.bpf.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/tools/ebpf/rss.bpf.c b/tools/ebpf/rss.bpf.c
index 20f227e2ac..667ea6899e 100644
--- a/tools/ebpf/rss.bpf.c
+++ b/tools/ebpf/rss.bpf.c
@@ -377,18 +377,19 @@ error:
 return err;
 }
 
-static inline __u32 calculate_rss_hash(struct __sk_buff *skb,
-struct rss_config_t *config, struct toeplitz_key_data_t *toe)
+static inline bool calculate_rss_hash(struct __sk_buff *skb,
+  struct rss_config_t *config,
+  struct toeplitz_key_data_t *toe,
+  __u32 *result)
 {
 __u8 rss_input[HASH_CALCULATION_BUFFER_SIZE] = {};
 size_t bytes_written = 0;
-__u32 result = 0;
 int err = 0;
 struct packet_hash_info_t packet_info = {};
 
 err = parse_packet(skb, _info);
 if (err) {
-return 0;
+return false;
 }
 
 if (packet_info.is_ipv4) {
@@ -521,11 +522,13 @@ static inline __u32 calculate_rss_hash(struct __sk_buff 
*skb,
 }
 }
 
-if (bytes_written) {
-net_toeplitz_add(, rss_input, bytes_written, toe);
+if (!bytes_written) {
+return false;
 }
 
-return result;
+net_toeplitz_add(result, rss_input, bytes_written, toe);
+
+return true;
 }
 
 SEC("tun_rss_steering")
@@ -546,8 +549,7 @@ int tun_rss_steering_prog(struct __sk_buff *skb)
 return config->default_queue;
 }
 
-hash = calculate_rss_hash(skb, config, toe);
-if (hash) {
+if (calculate_rss_hash(skb, config, toe, )) {
 __u32 table_idx = hash % config->indirections_len;
 __u16 *queue = 0;
 
-- 
2.42.0

[PATCH v6 05/21] tap: Remove tap_receive()

[Akihiko Odaki]

The receive member of NetClientInfo is only for legacy clients and the
receive_iov member is always used when it is set.

Signed-off-by: Akihiko Odaki 
---
 net/tap.c | 36 
 1 file changed, 36 deletions(-)

diff --git a/net/tap.c b/net/tap.c
index d54e90f184..ab4e5a0e91 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -133,41 +133,6 @@ static ssize_t tap_receive_iov(NetClientState *nc, const 
struct iovec *iov,
 return tap_write_packet(s, iovp, iovcnt);
 }
 
-static ssize_t tap_receive_raw(NetClientState *nc, const uint8_t *buf, size_t 
size)
-{
-TAPState *s = DO_UPCAST(TAPState, nc, nc);
-struct iovec iov[2];
-int iovcnt = 0;
-struct virtio_net_hdr_mrg_rxbuf hdr = { };
-
-if (s->host_vnet_hdr_len) {
-iov[iovcnt].iov_base = 
-iov[iovcnt].iov_len  = s->host_vnet_hdr_len;
-iovcnt++;
-}
-
-iov[iovcnt].iov_base = (char *)buf;
-iov[iovcnt].iov_len  = size;
-iovcnt++;
-
-return tap_write_packet(s, iov, iovcnt);
-}
-
-static ssize_t tap_receive(NetClientState *nc, const uint8_t *buf, size_t size)
-{
-TAPState *s = DO_UPCAST(TAPState, nc, nc);
-struct iovec iov[1];
-
-if (s->host_vnet_hdr_len && !s->using_vnet_hdr) {
-return tap_receive_raw(nc, buf, size);
-}
-
-iov[0].iov_base = (char *)buf;
-iov[0].iov_len  = size;
-
-return tap_write_packet(s, iov, 1);
-}
-
 #ifndef __sun__
 ssize_t tap_read_packet(int tapfd, uint8_t *buf, int maxlen)
 {
@@ -366,7 +331,6 @@ int tap_get_fd(NetClientState *nc)
 static NetClientInfo net_tap_info = {
 .type = NET_CLIENT_DRIVER_TAP,
 .size = sizeof(TAPState),
-.receive = tap_receive,
 .receive_iov = tap_receive_iov,
 .poll = tap_poll,
 .cleanup = tap_cleanup,
-- 
2.42.0

Re: [PATCH 0/1] Enable -Wshadow=local

[Stefan Hajnoczi]

On Fri, 27 Oct 2023 at 13:42, Markus Armbruster  wrote:
>
> Stefan Hajnoczi  writes:
>
> > On Thu, 26 Oct 2023 at 14:32, Markus Armbruster  wrote:
> >>
> >> Requires Brian's pull request and two patches from Thomas to compile:
> >>
> >> [PULL 0/2] hex queue - GETPC() fixes, shadowing fixes
> >> [PATCH v2] block/snapshot: Fix compiler warning with -Wshadow=local
> >> [PATCH v2] migration/ram: Fix compilation with -Wshadow=local
> >>
> >> Stefan, the PR was posted a week ago; anything blocking it?
> >
> > It's not in a pull request, so I won't see it. I don't have tooling
> > that can spot individual patch series that need to go into
> > qemu.git/master, so I rely on being emailed about them.
>
> I'm inquiring about this one:
>
> 
> https://lore.kernel.org/qemu-devel/20231019021733.2258592-1-bc...@quicinc.com/
>
> Looks like a PR to me.
>
> > Would you like me to merge this patch series into qemu.git/master?
>
> Yes, I'd like you merge Brian's PR I linked to.

Sorry, I missed that because of a bug in the 'patches' tool that I
use. The PR is running through CI now.

I've fixed the 'patches' tool to decode emails with
Content-Transfer-Encoding: base64 now:
https://github.com/stefanha/patches/commit/35531a8668f551356c019f68670fcb154535ccd3

Stefan

Re: [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension

[Alistair Francis]

On Thu, Oct 26, 2023 at 1:15 AM Max Chou  wrote:
>
> Vector crypto spec defines the Zvkt extension that included all of the
> instructions of Zvbb & Zvbc extensions and some vector instructions.
>
> Signed-off-by: Max Chou 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu_cfg.h | 1 +
>  target/riscv/tcg/tcg-cpu.c | 5 +
>  2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index e7ce977189c..d8d17dedeed 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -94,6 +94,7 @@ struct RISCVCPUConfig {
>  bool ext_zvknhb;
>  bool ext_zvksed;
>  bool ext_zvksh;
> +bool ext_zvkt;
>  bool ext_zmmul;
>  bool ext_zvfbfmin;
>  bool ext_zvfbfwma;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c5ff03efce9..b9eaecb699c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
> Error **errp)
>  return;
>  }
>
> +if (cpu->cfg.ext_zvkt) {
> +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
> +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
> +}
> +
>  /*
>   * In principle Zve*x would also suffice here, were they supported
>   * in qemu
> --
> 2.34.1
>
>

Re: Patch to fix malfunctioning of T2-T5 timers on the STM32 platform

[Alistair Francis]

On Sat, Oct 28, 2023 at 5:55 AM Lucjan Bryndza  wrote:
>
>
> Current implementation of T2 - T5 times on the STM32 platform does not work 
> properly.
> After configuring the timer-counter circuit to report interrupts every 10ms, 
> in reality the first interrupt is reported
> only once after a few seconds, while subsequent interrupts do not come.
> The current code also does not properly emulate the operation of even the 
> basic functions of the TIME-BASE unit.
> This patch contains fixes that reimplements the basic functionality
> of the time base unit such as up-counting down-counting , and alternate-mode 
> up-down counting.
> The ptimer() API is used to emulate timers.
> After applying the patch, STM32 timer works correctly in its basic 
> functionality.
> The ISIX-RTOS test unit was used to test the patch.
> Links and instructions can be found below:
>
> https://github.com/lucckb/isixrtos/blob/master/tests/libisix/01_basic_primitives.cpp
> https://github.com/lucckb/isixrtos/blob/master/extras/doc/unit_test_qemu.md
>
>
> qemu-system-arm -M olimex-stm32-h405  -kernel 
> build/tests/libisix/isixunittests.binary -nographic
> unittests_entry.cpp:146|ISIX VERSION pub/ep0319-157-gb239b35f-dirty
> unittests_entry.cpp:83|Exceptions pretest. OK
> 51 selected tests
> [   RUN] 01_base_00 TimeBase timer vs systick
> [  1001ms  ] ...
> [   RUN] 01_base_01 Basic heap allocator
> [   1ms] ...

Hello,

Thanks for the patch. The STM32 timers were tested when they were
written, but it is entirely possible there are bugs in there. It's
great to see you are using the STM32 emulation and contributing back.

When submitting patches, can you please follow the documentation on
the QEMU wiki: 
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#split-up-long-patches

The most important part is splitting up patches into small self
contained changes. That way it's easy to review and test each change.
You can then submit the changes as a patch series.

>
>
> Best Regards
> Lucjan Bryndza
>
>
> From 3ccfe70979d1b263d4fa22104ecf42ac5a628554 Mon Sep 17 00:00:00 2001
> From: Lucjan Bryndza 
> Date: Thu, 26 Oct 2023 22:45:26 +0200
> Subject: [PATCH] Fixing the basic functionality of STM32 timers

When submitting a patch please use git send-email, there are
instructions here:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#submitting-your-patches

>
> The current implementation of timers does not work properly
> even in the basic functionality. A counter configured to report
> an interrupt 10ms every reports the first interrupts after a
> few seconds.   Count up and
> count down modes are also not properly implemented. This commit fixes bugs 
> with interrupt
> reporting and implements the basic modes of the counter's
> time-base block.
>
> Signed-off-by: Lucjan Bryndza 
> ---
>  hw/arm/stm32f405_soc.c |   2 +-
>  hw/timer/stm32f2xx_timer.c | 291 ++---
>  include/hw/timer/stm32f2xx_timer.h |  23 ++-
>  3 files changed, 202 insertions(+), 114 deletions(-)
>
> diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
> index cef23d7ee4..69316181b3 100644
> --- a/hw/arm/stm32f405_soc.c
> +++ b/hw/arm/stm32f405_soc.c
> @@ -183,7 +183,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, 
> Error **errp)
>  /* Timer 2 to 5 */
>  for (i = 0; i < STM_NUM_TIMERS; i++) {
>  dev = DEVICE(&(s->timer[i]));
> -qdev_prop_set_uint64(dev, "clock-frequency", 10);
> +   qdev_prop_set_uint64(dev, "clock-frequency", 4800);
>  if (!sysbus_realize(SYS_BUS_DEVICE(>timer[i]), errp)) {
>  return;
>  }
> diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
> index ba8694dcd3..65f3287125 100644
> --- a/hw/timer/stm32f2xx_timer.c
> +++ b/hw/timer/stm32f2xx_timer.c
> @@ -29,11 +29,18 @@
>  #include "migration/vmstate.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> +#include "qemu/typedefs.h"
> +#include "qemu/timer.h"
> +#include "qemu/main-loop.h"
> +#include "sysemu/dma.h"
>
>  #ifndef STM_TIMER_ERR_DEBUG
>  #define STM_TIMER_ERR_DEBUG 0
>  #endif
>
> +/* PCLK /4 */
> +#define CLOCK_FREQUENCY 4800ULL
> +
>  #define DB_PRINT_L(lvl, fmt, args...) do { \
>  if (STM_TIMER_ERR_DEBUG >= lvl) { \
>  qemu_log("%s: " fmt, __func__, ## args); \
> @@ -42,63 +49,87 @@
>
>  #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>
> -static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now);
>
> -static void stm32f2xx_timer_interrupt(void *opaque)
> +static uint32_t stm32f2xx_timer_get_count(STM32F2XXTimerState *s)
>  {
> -STM32F2XXTimerState *s = opaque;
> -
> -DB_PRINT("Interrupt\n");
> -
> -if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
> -s->tim_sr |= 1;
> -qemu_irq_pulse(s->irq);
> -stm32f2xx_timer_set_alarm(s, s->hit_time);
> -}
> -
> -if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) 

Re: Patch to fix malfunctioning of T2-T5 timers on the STM32 platform

[Philippe Mathieu-Daudé]

Hi Lucjan,

On 27/10/23 21:37, Lucjan Bryndza wrote:


Current implementation of T2 - T5 times on the STM32 platform does not 
work properly.
After configuring the timer-counter circuit to report interrupts every 
10ms, in reality the first interrupt is reported

only once after a few seconds, while subsequent interrupts do not come.
The current code also does not properly emulate the operation of even 
the basic functions of the TIME-BASE unit.

This patch contains fixes that reimplements the basic functionality
of the time base unit such as up-counting down-counting , and 
alternate-mode up-down counting.

The ptimer() API is used to emulate timers.
After applying the patch, STM32 timer works correctly in its basic 
functionality.

The ISIX-RTOS test unit was used to test the patch.
Links and instructions can be found below:

https://github.com/lucckb/isixrtos/blob/master/tests/libisix/01_basic_primitives.cpp 

https://github.com/lucckb/isixrtos/blob/master/extras/doc/unit_test_qemu.md 



qemu-system-arm -M olimex-stm32-h405  -kernel 
build/tests/libisix/isixunittests.binary -nographic

unittests_entry.cpp:146|ISIX VERSION pub/ep0319-157-gb239b35f-dirty
unittests_entry.cpp:83|Exceptions pretest. OK
51 selected tests
[   RUN    ] 01_base_00 TimeBase timer vs systick
[  1001ms  ] ...
[   RUN    ] 01_base_01 Basic heap allocator
[   1ms    ] ...


Best Regards
Lucjan Bryndza


 From 3ccfe70979d1b263d4fa22104ecf42ac5a628554 Mon Sep 17 00:00:00 2001
From: Lucjan Bryndza 
Date: Thu, 26 Oct 2023 22:45:26 +0200
Subject: [PATCH] Fixing the basic functionality of STM32 timers

The current implementation of timers does not work properly
even in the basic functionality. A counter configured to report
an interrupt 10ms every reports the first interrupts after a
few seconds.   Count up and
count down modes are also not properly implemented. This commit fixes 
bugs with interrupt

reporting and implements the basic modes of the counter's
time-base block.

Signed-off-by: Lucjan Bryndza 
---
  hw/arm/stm32f405_soc.c             |   2 +-
  hw/timer/stm32f2xx_timer.c         | 291 ++---
  include/hw/timer/stm32f2xx_timer.h |  23 ++-
  3 files changed, 202 insertions(+), 114 deletions(-)

diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index cef23d7ee4..69316181b3 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -183,7 +183,7 @@ static void stm32f405_soc_realize(DeviceState 
*dev_soc, Error **errp)

      /* Timer 2 to 5 */
      for (i = 0; i < STM_NUM_TIMERS; i++) {
          dev = DEVICE(&(s->timer[i]));
-        qdev_prop_set_uint64(dev, "clock-frequency", 10);
+       qdev_prop_set_uint64(dev, "clock-frequency", 4800);


Correct, this is for the 405 SoC.


          if (!sysbus_realize(SYS_BUS_DEVICE(>timer[i]), errp)) {
              return;
          }
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index ba8694dcd3..65f3287125 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -29,11 +29,18 @@
  #include "migration/vmstate.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
+#include "qemu/typedefs.h"
+#include "qemu/timer.h"
+#include "qemu/main-loop.h"
+#include "sysemu/dma.h"
  #ifndef STM_TIMER_ERR_DEBUG
  #define STM_TIMER_ERR_DEBUG 0
  #endif
+/* PCLK /4 */
+#define CLOCK_FREQUENCY 4800ULL


This timer is generic, we shouldn't enforce a frequency from a
particular SoC.



  static const MemoryRegionOps stm32f2xx_timer_ops = {
@@ -275,7 +353,7 @@ static const VMStateDescription 
vmstate_stm32f2xx_timer = {

      .version_id = 1,
      .minimum_version_id = 1,
      .fields = (VMStateField[]) {
-        VMSTATE_INT64(tick_offset, STM32F2XXTimerState),
+        VMSTATE_INT32(count_mode, STM32F2XXTimerState),
          VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState),
          VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState),
          VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState),
@@ -300,25 +378,24 @@ static const VMStateDescription 
vmstate_stm32f2xx_timer = {

  static Property stm32f2xx_timer_properties[] = {
      DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState,
-                       freq_hz, 10),
+                       freq_hz, CLOCK_FREQUENCY),


So here I suggest using '0', and in stm32f2xx_timer_realize() propagate
an error if the frequency is still 0.


      DEFINE_PROP_END_OF_LIST(),
  };


Regards,

Phil.

Re: [PATCH v5 04/21] net: Remove receive_raw()

[Akihiko Odaki]

On 2023/10/30 13:08, Jason Wang wrote:

On Mon, Oct 30, 2023 at 12:03 PM Akihiko Odaki  wrote:


On 2023/10/30 12:06, Jason Wang wrote:


在 2023/10/27 15:52, Akihiko Odaki 写道:

On 2023/10/27 15:49, Jason Wang wrote:

On Tue, Oct 17, 2023 at 12:09 PM Akihiko Odaki
 wrote:


While netmap implements virtio-net header, it does not implement
receive_raw().


The only user for raw is the announcing. Netmap probably doesn't it
at all.


In my understanding, the announcing *sends* a raw packet.



It's send via NIC and receive by its peer which is the TAP

qemu_send_packet_raw() -> nc -> nc->peer -> peer->receive_raw()?

Anything I miss?


The problem is that the peer can be netmap and netmap also requires a
virtio-net header.


Right, but I don't know whether netmap can migrate.


Thinking of the condition that announcement can happen, I'm not aware 
anything that prevents migration with netamp. It also is apparently 
possible to make an announcement with HMP/QMP.
In any case, I think it's better to fix qemu_send_packet_raw() for 
netmap to prevent potential breakage especially if it costs nothing 
(actually it saves some code).


Regards,
Akihiko Odaki

Re: [PATCH] hw/ufs: Modify lu.c to share codes with SCSI subsystem

[Philippe Mathieu-Daudé]

Hi Jeuk,

On 20/10/23 03:51, Jeuk Kim wrote:

This patch removes the code that ufs-lu was duplicating from
scsi-hd and allows them to share code.

It makes ufs-lu have a virtual scsi-bus and scsi-hd internally.
This allows scsi related commands to be passed thorugh to the scsi-hd.
The query request and nop command work the same as the existing logic.

Well-known lus do not have a virtual scsi-bus and scsi-hd, and
handle the necessary scsi commands by emulating them directly.

Signed-off-by: Jeuk Kim 
---
  hw/ufs/lu.c| 1473 +++-


I liked this patch intent, but almost 1500 lines changed in a single
patch make it impossible to review. Ideally each patch shouldn't modify
more than 100 lines, otherwise reviewers are either exhausted or can't
be careful enough and miss possible bugs or design issues.

Regards,

Phil.


  hw/ufs/trace-events|   25 -
  hw/ufs/ufs.c   |  202 +-
  hw/ufs/ufs.h   |   36 +-
  include/block/ufs.h|2 +-
  tests/qtest/ufs-test.c |   37 +-
  6 files changed, 315 insertions(+), 1460 deletions(-)

Re: [PATCH v5 04/21] net: Remove receive_raw()

[Jason Wang]

On Mon, Oct 30, 2023 at 12:03 PM Akihiko Odaki  wrote:
>
> On 2023/10/30 12:06, Jason Wang wrote:
> >
> > 在 2023/10/27 15:52, Akihiko Odaki 写道:
> >> On 2023/10/27 15:49, Jason Wang wrote:
> >>> On Tue, Oct 17, 2023 at 12:09 PM Akihiko Odaki
> >>>  wrote:
> 
>  While netmap implements virtio-net header, it does not implement
>  receive_raw().
> >>>
> >>> The only user for raw is the announcing. Netmap probably doesn't it
> >>> at all.
> >>
> >> In my understanding, the announcing *sends* a raw packet.
> >
> >
> > It's send via NIC and receive by its peer which is the TAP
> >
> > qemu_send_packet_raw() -> nc -> nc->peer -> peer->receive_raw()?
> >
> > Anything I miss?
>
> The problem is that the peer can be netmap and netmap also requires a
> virtio-net header.

Right, but I don't know whether netmap can migrate.

Thanks

>
> Regards,
> Akihiko Odaki
>

Re: [PATCH v9 4/7] hw/isa/vt82c686: Implement PCI IRQ routing

[Philippe Mathieu-Daudé]

Hi Zoltan,

On 7/3/23 12:42, BALATON Zoltan wrote:

The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well. The real chip may allow routing IRQs from
internal functions independently of PCI interrupts but since guests
usually configute it to a single shared interrupt we don't model that
here for simplicity.

Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4.

Suggested-by: Bernhard Beschow 
Signed-off-by: BALATON Zoltan 
Reviewed-by: Bernhard Beschow 
Tested-by: Rene Engel 
---
  hw/isa/vt82c686.c | 42 ++
  1 file changed, 42 insertions(+)




+static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num)
+{
+switch (irq_num) {
+case 0:
+return s->dev.config[0x55] >> 4;
+case 1:
+return s->dev.config[0x56] & 0xf;
+case 2:
+return s->dev.config[0x56] >> 4;
+case 3:
+return s->dev.config[0x57] >> 4;


Shouldn't this be & 0xf?

(This is why I prefer extract8() over manual bits extraction)


+}
+return 0;
+}

[PULL 1/1] hw/ufs: Modify lu.c to share codes with SCSI subsystem

[Jeuk Kim]

From: Jeuk Kim 

This patch removes the code that ufs-lu was duplicating from
scsi-hd and allows them to share code.

It makes ufs-lu have a virtual scsi-bus and scsi-hd internally.
This allows scsi related commands to be passed thorugh to the scsi-hd.
The query request and nop command work the same as the existing logic.

Well-known lus do not have a virtual scsi-bus and scsi-hd, and
handle the necessary scsi commands by emulating them directly.

Signed-off-by: Jeuk Kim 
---
 hw/ufs/lu.c| 1473 +++-
 hw/ufs/trace-events|   25 -
 hw/ufs/ufs.c   |  202 +-
 hw/ufs/ufs.h   |   36 +-
 include/block/ufs.h|2 +-
 tests/qtest/ufs-test.c |   37 +-
 6 files changed, 315 insertions(+), 1460 deletions(-)

diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c
index 13b5e37b53..81bfff9b4e 100644
--- a/hw/ufs/lu.c
+++ b/hw/ufs/lu.c
@@ -19,57 +19,117 @@
 #include "trace.h"
 #include "ufs.h"
 
-/*
- * The code below handling SCSI commands is copied from hw/scsi/scsi-disk.c,
- * with minor adjustments to make it work for UFS.
- */
+#define SCSI_COMMAND_FAIL (-1)
 
-#define SCSI_DMA_BUF_SIZE (128 * KiB)
-#define SCSI_MAX_INQUIRY_LEN 256
-#define SCSI_INQUIRY_DATA_SIZE 36
-#define SCSI_MAX_MODE_LEN 256
-
-typedef struct UfsSCSIReq {
-SCSIRequest req;
-/* Both sector and sector_count are in terms of BDRV_SECTOR_SIZE bytes.  */
-uint64_t sector;
-uint32_t sector_count;
-uint32_t buflen;
-bool started;
-bool need_fua_emulation;
-struct iovec iov;
-QEMUIOVector qiov;
-BlockAcctCookie acct;
-} UfsSCSIReq;
-
-static void ufs_scsi_free_request(SCSIRequest *req)
+static void ufs_build_upiu_sense_data(UfsRequest *req, uint8_t *sense,
+  uint32_t sense_len)
 {
-UfsSCSIReq *r = DO_UPCAST(UfsSCSIReq, req, req);
+req->rsp_upiu.sr.sense_data_len = cpu_to_be16(sense_len);
+assert(sense_len <= SCSI_SENSE_LEN);
+memcpy(req->rsp_upiu.sr.sense_data, sense, sense_len);
+}
+
+static void ufs_build_scsi_response_upiu(UfsRequest *req, uint8_t *sense,
+ uint32_t sense_len,
+ uint32_t transfered_len,
+ int16_t status)
+{
+uint32_t expected_len = 
be32_to_cpu(req->req_upiu.sc.exp_data_transfer_len);
+uint8_t flags = 0, response = UFS_COMMAND_RESULT_SUCCESS;
+uint16_t data_segment_length;
+
+if (expected_len > transfered_len) {
+req->rsp_upiu.sr.residual_transfer_count =
+cpu_to_be32(expected_len - transfered_len);
+flags |= UFS_UPIU_FLAG_UNDERFLOW;
+} else if (expected_len < transfered_len) {
+req->rsp_upiu.sr.residual_transfer_count =
+cpu_to_be32(transfered_len - expected_len);
+flags |= UFS_UPIU_FLAG_OVERFLOW;
+}
 
-qemu_vfree(r->iov.iov_base);
+if (status != 0) {
+ufs_build_upiu_sense_data(req, sense, sense_len);
+response = UFS_COMMAND_RESULT_FAIL;
+}
+
+data_segment_length =
+cpu_to_be16(sense_len + sizeof(req->rsp_upiu.sr.sense_data_len));
+ufs_build_upiu_header(req, UFS_UPIU_TRANSACTION_RESPONSE, flags, response,
+  status, data_segment_length);
 }
 
-static void scsi_check_condition(UfsSCSIReq *r, SCSISense sense)
+static void ufs_scsi_command_complete(SCSIRequest *scsi_req, size_t resid)
 {
-trace_ufs_scsi_check_condition(r->req.tag, sense.key, sense.asc,
-   sense.ascq);
-scsi_req_build_sense(>req, sense);
-scsi_req_complete(>req, CHECK_CONDITION);
+UfsRequest *req = scsi_req->hba_private;
+int16_t status = scsi_req->status;
+
+uint32_t transfered_len = scsi_req->cmd.xfer - resid;
+
+ufs_build_scsi_response_upiu(req, scsi_req->sense, scsi_req->sense_len,
+ transfered_len, status);
+
+ufs_complete_req(req, UFS_REQUEST_SUCCESS);
+
+scsi_req->hba_private = NULL;
+scsi_req_unref(scsi_req);
 }
 
-static int ufs_scsi_emulate_vpd_page(SCSIRequest *req, uint8_t *outbuf,
- uint32_t outbuf_len)
+static QEMUSGList *ufs_get_sg_list(SCSIRequest *scsi_req)
 {
-UfsHc *u = UFS(req->bus->qbus.parent);
-UfsLu *lu = DO_UPCAST(UfsLu, qdev, req->dev);
-uint8_t page_code = req->cmd.buf[2];
-int start, buflen = 0;
+UfsRequest *req = scsi_req->hba_private;
+return req->sg;
+}
+
+static const struct SCSIBusInfo ufs_scsi_info = {
+.tcq = true,
+.max_target = 0,
+.max_lun = UFS_MAX_LUS,
+.max_channel = 0,
+
+.get_sg_list = ufs_get_sg_list,
+.complete = ufs_scsi_command_complete,
+};
+
+static int ufs_emulate_report_luns(UfsRequest *req, uint8_t *outbuf,
+   uint32_t outbuf_len)
+{
+UfsHc *u = req->hc;
+int len = 0;
 
-if (outbuf_len < SCSI_INQUIRY_DATA_SIZE) {
-return -1;
+/* TODO: Support for cases where 

[PULL 0/1] ufs queue

[Jeuk Kim]

From: Jeuk Kim 

The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:

  Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging 
(2023-10-27 09:43:53 +0900)

are available in the Git repository at:

  https://gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-20231030

for you to fetch changes up to 096434fea13acd19f4ead00cdf9babea8dc7e61e:

  hw/ufs: Modify lu.c to share codes with SCSI subsystem (2023-10-30 10:28:04 
+0900)


ufs queue:

* Modify lu.c to share codes with SCSI


Jeuk Kim (1):
  hw/ufs: Modify lu.c to share codes with SCSI subsystem

 hw/ufs/lu.c| 1473 
 hw/ufs/trace-events|   25 -
 hw/ufs/ufs.c   |  202 +--
 hw/ufs/ufs.h   |   36 +-
 include/block/ufs.h|2 +-
 tests/qtest/ufs-test.c |   37 +-
 6 files changed, 315 insertions(+), 1460 deletions(-)

Re: [PATCH v5 04/21] net: Remove receive_raw()

[Akihiko Odaki]

On 2023/10/30 12:06, Jason Wang wrote:


在 2023/10/27 15:52, Akihiko Odaki 写道:

On 2023/10/27 15:49, Jason Wang wrote:
On Tue, Oct 17, 2023 at 12:09 PM Akihiko Odaki 
 wrote:


While netmap implements virtio-net header, it does not implement
receive_raw().


The only user for raw is the announcing. Netmap probably doesn't it 
at all.


In my understanding, the announcing *sends* a raw packet.



It's send via NIC and receive by its peer which is the TAP

qemu_send_packet_raw() -> nc -> nc->peer -> peer->receive_raw()?

Anything I miss?


The problem is that the peer can be netmap and netmap also requires a 
virtio-net header.


Regards,
Akihiko Odaki

Re: [PATCH v6 12/12] target/riscv/tcg: warn if profile exts are disabled

[Alistair Francis]

On Sat, Oct 28, 2023 at 8:07 PM Daniel Henrique Barboza
 wrote:
>
> Enabling a profile and then disabling some of its mandatory extensions
> is a valid use. It can be useful for debugging and testing. But the
> common expected use of enabling a profile is to enable all its mandatory
> extensions.
>
> Add an user warning when mandatory extensions from an enabled profile
> are disabled in the command line, like we're already doing with RVG.
>
> After this patch, this will throw warnings:
>
> -cpu rv64,rva22u64=true,zihintpause=false,zicbom=false,zicboz=false
>
> qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension 
> zihintpause
> qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension 
> zicbom
> qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension 
> zicboz
>
> Note that the following  will NOT throw warnings because the profile is
> being enabled last, hence all its mandatory extensions will be enabled:
>
> -cpu rv64,zihintpause=false,zicbom=false,zicboz=false,rva22u64=true
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Andrew Jones 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 61 ++
>  1 file changed, 61 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 953e8432d6..5e7855b41b 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -147,6 +147,27 @@ static int cpu_cfg_ext_get_min_version(uint32_t 
> ext_offset)
>  g_assert_not_reached();
>  }
>
> +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset)
> +{
> +const RISCVCPUMultiExtConfig *feat;
> +const RISCVIsaExtData *edata;
> +
> +for (edata = isa_edata_arr; edata && edata->name; edata++) {
> +if (edata->ext_enable_offset == ext_offset) {
> +return edata->name;
> +}
> +}
> +
> +for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) {
> +if (feat->offset == ext_offset) {
> +return feat->name;
> +}
> +}
> +
> +g_assert_not_reached();
> +}
> +
> +
>  static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
>  bool value)
>  {
> @@ -631,6 +652,45 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
> Error **errp)
>  riscv_cpu_disable_priv_spec_isa_exts(cpu);
>  }
>
> +static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> +   RISCVCPUProfile *profile)
> +{
> +const char *warn_msg = "Profile %s mandates disabled extension %s";
> +int i;
> +
> +for (i = 0; misa_bits[i] != 0; i++) {
> +uint32_t bit = misa_bits[i];
> +
> +if (!(profile->misa_ext & bit)) {
> +continue;
> +}
> +
> +if (!riscv_has_ext(>env, bit)) {
> +warn_report(warn_msg, profile->name, 
> riscv_get_misa_ext_name(bit));
> +}
> +}
> +
> +for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
> +int ext_offset = profile->ext_offsets[i];
> +
> +if (!isa_ext_is_enabled(cpu, ext_offset)) {
> +warn_report(warn_msg, profile->name,
> +cpu_cfg_ext_get_name(ext_offset));
> +}
> +}
> +}
> +
> +static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
> +{
> +for (int i = 0; riscv_profiles[i] != NULL; i++) {
> +RISCVCPUProfile *profile = riscv_profiles[i];
> +
> +if (profile->user_set && profile->enabled) {
> +riscv_cpu_validate_profile(cpu, profile);
> +}
> +}
> +}
> +
>  void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
>  {
>  CPURISCVState *env = >env;
> @@ -649,6 +709,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error 
> **errp)
>  }
>
>  riscv_cpu_validate_named_features(cpu);
> +riscv_cpu_validate_profiles(cpu);
>
>  if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
>  /*
> --
> 2.41.0
>
>

Re: [PATCH v5 15/21] virtio-net: Do not clear VIRTIO_NET_F_HASH_REPORT

[Akihiko Odaki]

On 2023/10/30 6:56, Yuri Benditovich wrote:
This patch allows  VIRTIO_NET_F_HASH_REPORT feature to the adapter whose 
backend does not have a virtio header and does not have offload features 
that depend on it.
The migration between such different systems is very problematic even if 
it seems successful, such setups are not performance-oriented and 
especially supporting the hash delivery for them is (IMHO) redundant, it 
just requires more testing and does not bring any advantage.


Whether the peer has virtio headers or not is irrelevant if 
VIRTIO_NET_F_HASH_REPORT is offloaded or not. Currently QEMU always 
implements hash reporting by itself and does not offload at all.

Re: [PATCH v6 11/12] target/riscv/tcg: honor user choice for G MISA bits

[Alistair Francis]

On Sat, Oct 28, 2023 at 6:56 PM Daniel Henrique Barboza
 wrote:
>
> RVG behaves like a profile: a single flag enables a set of bits. Right
> now we're considering user choice when handling RVG and zicsr/zifencei
> and ignoring user choice on MISA bits.
>
> We'll add user warnings for profiles when the user disables its
> mandatory extensions in the next patch. We'll do the same thing with RVG
> now to keep consistency between RVG and profile handling.
>
> First and foremost, create a new RVG only helper to avoid clogging
> riscv_cpu_validate_set_extensions(). We do not want to annoy users with
> RVG warnings like we did in the past (see 9b9741c38f), thus we'll only
> warn if RVG was user set and the user disabled a RVG extension in the
> command line.
>
> For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then
> becomes:
>
> - if enabled, do nothing;
> - if disabled and not user set, enable it;
> - if disabled and user set, throw a warning that it's a RVG mandatory
>   extension.
>
> This same logic will be used for profiles in the next patch.
>
> Note that this is a behavior change, where we would error out if the
> user disabled either zicsr or zifencei. As long as users are explicitly
> disabling things in the command line we'll let them have a go at it, at
> least in this step. We'll error out later in the validation if needed.
>
> Other notable changes from the previous RVG code:
>
> - use riscv_cpu_write_misa_bit() instead of manually updating both
>   env->misa_ext and env->misa_ext_mask;
>
> - set zicsr and zifencei directly. We're already checking if they
>   were user set and priv version will never fail for these
>   extensions, making cpu_cfg_ext_auto_update() redundant.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Andrew Jones 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 73 +-
>  1 file changed, 48 insertions(+), 25 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 3a96b1f476..953e8432d6 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
>   GUINT_TO_POINTER(ext_offset));
>  }
>
> +static bool cpu_misa_ext_is_user_set(uint32_t misa_bit)
> +{
> +return g_hash_table_contains(misa_ext_user_opts,
> + GUINT_TO_POINTER(misa_bit));
> +}
> +
>  static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value)
>  {
>  g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset),
> @@ -303,6 +309,46 @@ static void riscv_cpu_validate_named_features(RISCVCPU 
> *cpu)
>  riscv_cpu_validate_zic64b(cpu);
>  }
>
> +static void riscv_cpu_validate_g(RISCVCPU *cpu)
> +{
> +const char *warn_msg = "RVG mandates disabled extension %s";
> +uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD};
> +bool send_warn = cpu_misa_ext_is_user_set(RVG);
> +
> +for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) {
> +uint32_t bit = g_misa_bits[i];
> +
> +if (riscv_has_ext(>env, bit)) {
> +continue;
> +}
> +
> +if (!cpu_misa_ext_is_user_set(bit)) {
> +riscv_cpu_write_misa_bit(cpu, bit, true);
> +continue;
> +}
> +
> +if (send_warn) {
> +warn_report(warn_msg, riscv_get_misa_ext_name(bit));
> +}
> +}
> +
> +if (!cpu->cfg.ext_zicsr) {
> +if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) {
> +cpu->cfg.ext_zicsr = true;
> +} else if (send_warn) {
> +warn_report(warn_msg, "zicsr");
> +}
> +}
> +
> +if (!cpu->cfg.ext_zifencei) {
> +if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) {
> +cpu->cfg.ext_zifencei = true;
> +} else if (send_warn) {
> +warn_report(warn_msg, "zifencei");
> +}
> +}
> +}
> +
>  /*
>   * Check consistency between chosen extensions while setting
>   * cpu->cfg accordingly.
> @@ -312,31 +358,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
> Error **errp)
>  CPURISCVState *env = >env;
>  Error *local_err = NULL;
>
> -/* Do some ISA extension error checking */
> -if (riscv_has_ext(env, RVG) &&
> -!(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
> -  riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
> -  riscv_has_ext(env, RVD) &&
> -  cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) {
> -
> -if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) &&
> -!cpu->cfg.ext_zicsr) {
> -error_setg(errp, "RVG requires Zicsr but user set Zicsr to 
> false");
> -return;
> -}
> -
> -if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) &&
> -!cpu->cfg.ext_zifencei) {
> -error_setg(errp, "RVG requires 

Re: [PATCH v6 09/12] target/riscv/tcg: handle profile MISA bits

[Alistair Francis]

On Sat, Oct 28, 2023 at 7:35 PM Daniel Henrique Barboza
 wrote:
>
> The profile support is handling multi-letter extensions only. Let's add
> support for MISA bits as well.
>
> We'll go through every known MISA bit. If the profile doesn't declare
> the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
> and env->misa_ext_mask.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Andrew Jones 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 910360ce37..6ba27b824b 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -828,6 +828,19 @@ static void cpu_set_profile(Object *obj, Visitor *v, 
> const char *name,
>  return;
>  }
>
> +for (i = 0; misa_bits[i] != 0; i++) {
> +uint32_t bit = misa_bits[i];
> +
> +if  (!(profile->misa_ext & bit)) {
> +continue;
> +}
> +
> +g_hash_table_insert(misa_ext_user_opts,
> +GUINT_TO_POINTER(bit),
> +(gpointer)value);
> +riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
> +}
> +
>  for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
>  ext_offset = profile->ext_offsets[i];
>
> --
> 2.41.0
>
>

Re: [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support

[Alistair Francis]

On Sat, Oct 28, 2023 at 8:44 PM Andrew Jones  wrote:
>
> On Sat, Oct 28, 2023 at 05:54:21AM -0300, Daniel Henrique Barboza wrote:
> > The TCG emulation implements all the extensions described in the
> > RVA22U64 profile, both mandatory and optional. The mandatory extensions
> > will be enabled via the profile flag. We'll leave the optional
> > extensions to be enabled by hand.
> >
> > Given that this is the first profile we're implementing in TCG we'll
> > need some ground work first:
> >
> > - all profiles declared in riscv_profiles[] will be exposed to users.
> > TCG is the main accelerator we're considering when adding profile
> > support in QEMU, so for now it's safe to assume that all profiles in
> > riscv_profiles[] will be relevant to TCG;
> >
> > - we'll not support user profile settings for vendor CPUs. The flags
> > will still be exposed but users won't be able to change them. The idea
> > is that vendor CPUs in the future can enable profiles internally in
> > their cpu_init() functions, showing to the external world that the CPU
> > supports a certain profile. But users won't be able to enable/disable
> > it;
> >
> > - Setting a profile to 'true' means 'enable all mandatory extensions of
> > this profile, setting it to 'false' means 'do not enable all mandatory
> > extensions for this profile'.
>
> While this definition of profile=off looks appealing at first, it's really
> just saying 'do not do anything', which means it's limiting the potential
> of the property. But, I'll stop talking about this now, as I have another

This seems like the way to go to me

> design suggestion instead:
>
> Since profiles are like G, and other shorthand extensions (just without an
> official shorthand extension name), then I believe they should behave like
> shorthand extensions. Also, since shorthand extensions can be derived from
> their parts, then I think shorthand extensions should behave like
> synthetic extensions. For example, zic64b starts 'false', but, at realize
> time, if all its conditions are present, then it turns 'true'. Shorthand
> extensions should be able to do that too by detecting that each of the
> extensions they represent is present.
>
> So, I think we should automatically turn G and profiles (and future
> shorthand extensions) on when all their respective extensions are present.

I think that's a good idea and something we should support

Alistair

>
> Thanks,
> drew
>

Re: [PATCH v5 11/21] virtio-net: Return an error when vhost cannot enable RSS

[Jason Wang]

在 2023/10/27 15:54, Akihiko Odaki 写道:

On 2023/10/27 16:07, Jason Wang wrote:
On Tue, Oct 17, 2023 at 12:10 PM Akihiko Odaki 
 wrote:


vhost requires eBPF for RSS. Even when eBPF is not available, 
virtio-net

reported RSS availability, and raised a warning only after the
guest requested RSS, and the guest could not know that RSS is not
available.

Check RSS availability during device realization and return an error
if RSS is requested but not available. Assert RSS availability when
the guest actually requests the feature.

Signed-off-by: Akihiko Odaki 
---
  ebpf/ebpf_rss.h  |   2 +-
  ebpf/ebpf_rss-stub.c |   4 +-
  ebpf/ebpf_rss.c  |  68 +-
  hw/net/virtio-net.c  | 114 
+--

  4 files changed, 82 insertions(+), 106 deletions(-)

diff --git a/ebpf/ebpf_rss.h b/ebpf/ebpf_rss.h
index bf3f2572c7..1128173572 100644
--- a/ebpf/ebpf_rss.h
+++ b/ebpf/ebpf_rss.h
@@ -36,7 +36,7 @@ bool ebpf_rss_is_loaded(struct EBPFRSSContext *ctx);

  bool ebpf_rss_load(struct EBPFRSSContext *ctx);

-bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct 
EBPFRSSConfig *config,
+void ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct 
EBPFRSSConfig *config,
    uint16_t *indirections_table, uint8_t 
*toeplitz_key);


  void ebpf_rss_unload(struct EBPFRSSContext *ctx);
diff --git a/ebpf/ebpf_rss-stub.c b/ebpf/ebpf_rss-stub.c
index e71e229190..525b358597 100644
--- a/ebpf/ebpf_rss-stub.c
+++ b/ebpf/ebpf_rss-stub.c
@@ -28,10 +28,10 @@ bool ebpf_rss_load(struct EBPFRSSContext *ctx)
  return false;
  }

-bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct 
EBPFRSSConfig *config,
+void ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct 
EBPFRSSConfig *config,
    uint16_t *indirections_table, uint8_t 
*toeplitz_key)

  {
-    return false;
+    g_assert_not_reached();
  }

  void ebpf_rss_unload(struct EBPFRSSContext *ctx)
diff --git a/ebpf/ebpf_rss.c b/ebpf/ebpf_rss.c
index cee658c158..6cdf82d059 100644
--- a/ebpf/ebpf_rss.c
+++ b/ebpf/ebpf_rss.c
@@ -74,42 +74,32 @@ error:
  return false;
  }

-static bool ebpf_rss_set_config(struct EBPFRSSContext *ctx,
+static void ebpf_rss_set_config(struct EBPFRSSContext *ctx,
  struct EBPFRSSConfig *config)
  {
  uint32_t map_key = 0;

-    if (!ebpf_rss_is_loaded(ctx)) {
-    return false;
-    }
-    if (bpf_map_update_elem(ctx->map_configuration,
-    _key, config, 0) < 0) {
-    return false;
-    }
-    return true;
+    assert(ebpf_rss_is_loaded(ctx));
+    assert(!bpf_map_update_elem(ctx->map_configuration, _key, 
config, 0));


Guest trigger-rable assertion should be avoided as much as possible.


These assertions should never be triggered by the guest as the feature 
availability is checked at the device realization. Are these 
assertions still problematic?



I still think it's better to avoid assertions as code could be changed 
by various people so it may end up with such possibility in the future.


Thanks




Regards,
Akihiko Odaki

Re: [PATCH] linux-user/elfload: Add missing arm64 hwcap values

[Philippe Mathieu-Daudé]

On 29/10/23 22:00, Marielle Novastrider wrote:

Specifically DIT, LSE2, and MTE3.

We already expose detection of these via the CPUID interface, but
missed these from ELF hwcaps.

Signed-off-by: Marielle Novastrider 
---
  linux-user/elfload.c | 3 +++
  target/arm/cpu.h | 5 +
  2 files changed, 8 insertions(+)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 6/6] system/memory: Trace names of MemoryRegions rather than host pointers

[Philippe Mathieu-Daudé]

Hi Bernhard,

On 28/10/23 14:24, Bernhard Beschow wrote:

Tracing the host pointer of the accessed MemoryRegion seems to be a debug
feature for developing QEMU itself. When analyzing guest behavior by comparing
traces, these pointers generate a lot of noise since the pointers differ between
QEMU invocations, making this task harder than it needs to be. Moreover, the
pointers seem to be redundant to the names already assigned to MemoryRegions.


I tried that few years ago but this got lost:
https://lore.kernel.org/qemu-devel/20210307074833.143106-1-f4...@amsat.org/


Remove the pointers from the traces and trace the names where missing. When
developing QEMU, developers could just add the host pointer tracing for
themselves.


But sometimes an object exposing a MR is instantiated multiple times,
each time, and now you can not distinct which object is accessed.

IIRC a suggestion was to cache the QOM parent path and display that,
which should be constant to diff tracing logs. But then IIRC again the
issue was the QOM path is resolved once the object is realized, which
happens *after* we initialize the MR within the object. Maybe the
solution is to add a memory_region_qom_pathname() getter and do lazy
initialization?


Signed-off-by: Bernhard Beschow 
---
  docs/devel/tracing.rst |  4 ++--
  system/memory.c| 26 --
  system/trace-events| 12 ++--
  3 files changed, 24 insertions(+), 18 deletions(-)

diff --git a/docs/devel/tracing.rst b/docs/devel/tracing.rst
index d288480db1..8c31d5f76e 100644
--- a/docs/devel/tracing.rst
+++ b/docs/devel/tracing.rst
@@ -18,8 +18,8 @@ events::
  
  $ qemu --trace "memory_region_ops_*" ...

  ...
-719585@1608130130.441188:memory_region_ops_read cpu 0 mr 0x562fdfbb3820 
addr 0x3cc value 0x67 size 1
-719585@1608130130.441190:memory_region_ops_write cpu 0 mr 0x562fdfbd2f00 
addr 0x3d4 value 0x70e size 2
+719585@1608130130.441188:memory_region_ops_read cpu 0 addr 0x3cc value 
0x67 size 1
+719585@1608130130.441190:memory_region_ops_write cpu 0 addr 0x3d4 value 
0x70e size 2


Is this example missing the MR name?

  
  This output comes from the "log" trace backend that is enabled by default when

  ``./configure --enable-trace-backends=BACKENDS`` was not explicitly specified.
diff --git a/system/memory.c b/system/memory.c
index 4928f2525d..076a992b74 100644
--- a/system/memory.c
+++ b/system/memory.c
@@ -444,10 +444,11 @@ static MemTxResult  
memory_region_read_accessor(MemoryRegion *mr,
  
  tmp = mr->ops->read(mr->opaque, addr, size);

  if (mr->subpage) {
-trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
+trace_memory_region_subpage_read(get_cpu_index(), addr, tmp, size,
+ memory_region_name(mr));
  } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
  hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
-trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size,
+trace_memory_region_ops_read(get_cpu_index(), abs_addr, tmp, size,
   memory_region_name(mr));
  }
  memory_region_shift_read_access(value, shift, mask, tmp);
@@ -467,10 +468,11 @@ static MemTxResult 
memory_region_read_with_attrs_accessor(MemoryRegion *mr,
  
  r = mr->ops->read_with_attrs(mr->opaque, addr, , size, attrs);

  if (mr->subpage) {
-trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
+trace_memory_region_subpage_read(get_cpu_index(), addr, tmp, size,
+ memory_region_name(mr));
  } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
  hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
-trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size,
+trace_memory_region_ops_read(get_cpu_index(), abs_addr, tmp, size,
   memory_region_name(mr));
  }
  memory_region_shift_read_access(value, shift, mask, tmp);
@@ -488,10 +490,11 @@ static MemTxResult 
memory_region_write_accessor(MemoryRegion *mr,
  uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
  
  if (mr->subpage) {

-trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, 
size);
+trace_memory_region_subpage_write(get_cpu_index(), addr, tmp, size,
+  memory_region_name(mr));
  } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) 
{
  hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
-trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size,
+trace_memory_region_ops_write(get_cpu_index(), abs_addr, tmp, size,
memory_region_name(mr));
  }
  mr->ops->write(mr->opaque, addr, tmp, size);
@@ 

Re: [PATCH v1 5/6] linux-user/loongarch64: Add LSX sigcontext save/restore

[gaosong]

在 2023/10/29 上午5:35, Richard Henderson 写道:

On 10/9/23 20:37, Song Gao wrote:

Signed-off-by: Song Gao 
---
  linux-user/loongarch64/signal.c | 107 ++--
  1 file changed, 87 insertions(+), 20 deletions(-)

diff --git a/linux-user/loongarch64/signal.c 
b/linux-user/loongarch64/signal.c

index 277e9f5757..4b09e50a5f 100644
--- a/linux-user/loongarch64/signal.c
+++ b/linux-user/loongarch64/signal.c
@@ -33,6 +33,14 @@ struct target_fpu_context {
  uint32_t fcsr;
  } QEMU_ALIGNED(FPU_CTX_ALIGN);
  +#define LSX_CTX_MAGIC   0x53580001
+#define LSX_CTX_ALIGN   16
+struct target_lsx_context {
+    uint64_t regs[2 * 32];
+    uint64_t fcc;
+    uint32_t fcsr;
+} QEMU_ALIGNED(LSX_CTX_ALIGN);


It probably doesn't matter here because fo the alignment, but all 
types within target structures should be using abi_{ullong,uint} etc.




Ok,
@@ -99,8 +109,15 @@ static abi_ptr setup_extcontext(struct 
extctx_layout *extctx, abi_ptr sp)
    /* For qemu, there is no lazy fp context switch, so fp always 
present. */

  extctx->flags = SC_USED_FP;
-    sp = extframe_alloc(extctx, >fpu,
+
+    if (env->extctx_flags & EXTCTX_FLAGS_LSX) {
+    sp = extframe_alloc(extctx, >lsx,
+    sizeof(struct target_lsx_context), 
LSX_CTX_ALIGN, sp);

+
+    } else if (env->extctx_flags & EXTCTX_FLAGS_FPU) {
+    sp = extframe_alloc(extctx, >fpu,
  sizeof(struct target_fpu_context), 
FPU_CTX_ALIGN, sp);

+    }


I think this is overly complicated.  (1) The fpu is always present, 
and (2) you don't need a special flag on env, you can check the same 
CSR bits as for system mode.


I think extctx_flags is incorrectly named, fp_alive_flags or 
vec_alive_flags would be more appropriate.
The flags function like the kernel's 'thread_lsx_context_live', 
'thread_lasx_context_live' functions, checking if the LSX/LASX 
instructions are used.
If we don't use the LSX/LASX instructions, we don't need to use 
lsx_context/lasx_context even though the LSX/LASX enable bit is set.


and  EXTCTX_FLAGS_FPU is not required.

Thanks.
Song Gao
I'll note that while this layout matches the kernel, it is an 
unfortunate set of data structures.  Any program has to look for all 
of {FPU,LSX,LASX}_CTX_MAGIC in order to find the basic fp registers.



r~

Re: [PATCH v1 2/6] target/loongarch: Add set_vec_extctx to set LSX/LASX instructions extctx_flags

[gaosong]

在 2023/10/29 上午5:40, Richard Henderson 写道:

On 10/9/23 20:36, Song Gao wrote:

Signed-off-by: Song Gao 
---
  target/loongarch/insn_trans/trans_vec.c.inc | 12 
  target/loongarch/internals.h    |  2 ++
  2 files changed, 14 insertions(+)

diff --git a/target/loongarch/insn_trans/trans_vec.c.inc 
b/target/loongarch/insn_trans/trans_vec.c.inc

index 98f856bb29..aef16ef44a 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -23,8 +23,20 @@ static bool check_vec(DisasContext *ctx, uint32_t 
oprsz)

    #else
  +static void set_vec_extctx(DisasContext *ctx, uint32_t oprsz)
+{
+    if (oprsz == 16) {
+    ctx->extctx_flags |= EXTCTX_FLAGS_LSX;
+    }
+
+    if (oprsz == 32) {
+    ctx->extctx_flags |= EXTCTX_FLAGS_LASX;
+    }
+}
+
  static bool check_vec(DisasContext *ctx, uint32_t oprsz)
  {
+    set_vec_extctx(ctx, oprsz);
  return true;
  }


This doesn't do anything.  Nothing copies the changed value back to env.
Anyway, I think this is the wrong way to go about it.


Oh, It is on patch1.

@@ -294,6 +296,7 @@ static void 
loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)

 generate_exception(ctx, EXCCODE_INE);
 }

+    env->extctx_flags |= ctx->extctx_flags;
 ctx->base.pc_next += 4;


Thanks.
Song Gao
If you want to track what the program is using, you should do it 
exactly like the real kernel: disable the execution unit, have the 
program trap, and the enable the execution unit when the trap occurs.  
At this point, CSR_EUEN enable bits contain exactly which units have 
been used by the program.



r~

Re: [PATCH 5/6] hw/i2c/pm_smbus: Convert DPRINTF to trace events

[Philippe Mathieu-Daudé]

On 28/10/23 14:24, Bernhard Beschow wrote:

Let the trace messages slightly deviate from the function names
("smb" -> "smbus") being traced in order to avoid conflights with the SMB
protocol.

Signed-off-by: Bernhard Beschow 
---
  hw/i2c/pm_smbus.c   | 18 --
  hw/i2c/trace-events |  6 ++
  2 files changed, 10 insertions(+), 14 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 4/6] hw/misc/imx6_ccm: Convert DPRINTF to trace events

[Philippe Mathieu-Daudé]

Hi Bernhard,

On 28/10/23 14:24, Bernhard Beschow wrote:

Signed-off-by: Bernhard Beschow 
---
  hw/misc/imx6_ccm.c   | 41 ++---
  hw/misc/trace-events | 15 +++
  2 files changed, 29 insertions(+), 27 deletions(-)




+# imx6_ccm.c
+imx6_analog_get_periph_clk(uint32_t freq) "freq = %u"


Preferably explicit the unit, as "freq = %u Hz".


+imx6_analog_get_pll2_clk(uint32_t freq) "freq = %u"
+imx6_analog_get_pll2_pfd0_clk(uint32_t freq) "freq = %u"
+imx6_analog_get_pll2_pfd2_clk(uint32_t freq) "freq = %u"



+imx6_ccm_get_ahb_clk(uint32_t freq) "freq = %u"
+imx6_ccm_get_ipg_clk(uint32_t freq) "freq = %u"
+imx6_ccm_get_per_clk(uint32_t freq) "freq = %u"
+imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(Clock = %d) = %u"


'freq' is uint64_t, but I suppose 32-bit is enough, so I'm
not against the implicit cast.

Reviewed-by: Philippe Mathieu-Daudé 

RE: [PATCH v3 18/37] vfio/container: Implement attach/detach_device

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Saturday, October 28, 2023 12:07 AM
>Subject: Re: [PATCH v3 18/37] vfio/container: Implement attach/detach_device
>
>Sorry, previous email was empty. Friday effect !
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> From: Eric Auger 
>>
>> No fucntional change intended.
>>
>> Signed-off-by: Eric Auger 
>> Signed-off-by: Yi Liu 
>> Signed-off-by: Yi Sun 
>> Signed-off-by: Zhenzhong Duan 
>> Signed-off-by: Cédric Le Goater 
>> ---
>>   hw/vfio/common.c| 16 
>>   hw/vfio/container.c | 12 +---
>>   2 files changed, 21 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
>> index d62c815d7f..64565b4ae9 100644
>> --- a/hw/vfio/common.c
>> +++ b/hw/vfio/common.c
>> @@ -1500,3 +1500,19 @@ retry:
>>
>>   return info;
>>   }
>> +
>> +int vfio_attach_device(char *name, VFIODevice *vbasedev,
>> +   AddressSpace *as, Error **errp)
>> +{
>> +const VFIOIOMMUOps *ops = _legacy_ops;
>
>hmm, this looks wrong. please explain.

The final shape will be:

int vfio_attach_device(char *name, VFIODevice *vbasedev,
   AddressSpace *as, Error **errp)
{
const VFIOIOMMUOps *ops;

#ifdef CONFIG_IOMMUFD
if (vbasedev->iommufd) {
ops = _iommufd_ops;
} else
#endif
{
ops = _legacy_ops;
}
return ops->attach_device(name, vbasedev, as, errp);
}

Depending on if iommufd is selected, different ops will be chosen.
Then corresponding attach_device callback is called to attach to
iommufd or legacy container.

Thanks
Zhenzhong

Re: [PATCH 3/6] hw/misc/imx7_snvs: Trace MMIO access

[Philippe Mathieu-Daudé]

On 28/10/23 14:24, Bernhard Beschow wrote:

Signed-off-by: Bernhard Beschow 
---
  hw/misc/imx7_snvs.c  | 5 +
  hw/misc/trace-events | 4 
  2 files changed, 9 insertions(+)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 1/6] hw/watchdog/wdt_imx2: Trace MMIO access

[Philippe Mathieu-Daudé]

On 28/10/23 14:24, Bernhard Beschow wrote:

Signed-off-by: Bernhard Beschow 
---
  hw/watchdog/wdt_imx2.c   | 24 ++--
  hw/watchdog/trace-events |  4 
  2 files changed, 22 insertions(+), 6 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support

[Alistair Francis]

On Tue, Oct 24, 2023 at 1:40 AM Daniel Henrique Barboza
 wrote:
>
> Hi,
>
> In this v3 the patches that added the extensions flags were squashed
> with the patches that handled the disablement of the extensions in TCG,
> as suggested by Alistair in v2.
>
> No other change made. Patches based on Alistair's riscv-to-apply.next.
>
> Patches missing acks: patch 3
>
> Changes from v2:
> - patch 2: squashed with patch 1
> - patch 5: squashed with patch 4
> - v2 link: 
> https://lore.kernel.org/qemu-riscv/20231017221226.136764-1-dbarb...@ventanamicro.com/
>
> Daniel Henrique Barboza (4):
>   target/riscv: add zicntr extension flag for TCG
>   target/riscv/kvm: add zicntr reg
>   target/riscv: add zihpm extension flag for TCG
>   target/riscv/kvm: add zihpm reg

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c | 15 +++
>  target/riscv/cpu_cfg.h |  2 ++
>  target/riscv/csr.c |  4 
>  target/riscv/kvm/kvm-cpu.c |  2 ++
>  target/riscv/tcg/tcg-cpu.c | 21 +
>  5 files changed, 44 insertions(+)
>
> --
> 2.41.0
>
>

RE: [PATCH v3 19/37] vfio/spapr: Introduce spapr backend and target interface

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Saturday, October 28, 2023 12:05 AM
>Subject: Re: [PATCH v3 19/37] vfio/spapr: Introduce spapr backend and target
>interface
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> Introduce an empry spapr backend which will hold spapr specific
>> content, currently only prereg_listener and hostwin_list.
>>
>> Also introduce and instantiate a spapr specific target interface,
>> currently only has add/del_window callbacks.
>>
>> Signed-off-by: Zhenzhong Duan 
>> ---
>>   include/hw/vfio/vfio-common.h | 8 
>>   include/hw/vfio/vfio-container-base.h | 2 ++
>>   hw/vfio/spapr.c   | 8 
>>   3 files changed, 18 insertions(+)
>>
>> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
>> index 938f75e70c..a74e60e677 100644
>> --- a/include/hw/vfio/vfio-common.h
>> +++ b/include/hw/vfio/vfio-common.h
>> @@ -169,6 +169,14 @@ VFIOAddressSpace
>*vfio_get_address_space(AddressSpace *as);
>>   void vfio_put_address_space(VFIOAddressSpace *space);
>>
>>   /* SPAPR specific */
>> +typedef struct VFIOIOMMUSpaprOps {
>> +int (*add_window)(VFIOContainerBase *bcontainer,
>> +  MemoryRegionSection *section,
>> +  Error **errp);
>> +void (*del_window)(VFIOContainerBase *bcontainer,
>> +   MemoryRegionSection *section);
>> +} VFIOIOMMUSpaprOps;
>
>I don't think we need a new structure type.
>
>If possible, these callbacks should be under VFIOIOMMUOps and only
>defined in the VFIOIOMMUOps struct for spapr. This struct would a
>copy of vfio_legacy_ops plus the two add/del_window  handlers.

Understood, will update.

Thanks
Zhenzhong

RE: [PATCH v3 14/37] vfio/container: Move vrdl_list, pgsizes and dma_max_mappings to base container

[Duan, Zhenzhong]

Hi Cédric,

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 11:52 PM
>Subject: Re: [PATCH v3 14/37] vfio/container: Move vrdl_list, pgsizes and
>dma_max_mappings to base container
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> From: Eric Auger 
>>
...

>>   void vfio_container_destroy(VFIOContainerBase *bcontainer)
>>   {
>> +VFIORamDiscardListener *vrdl, *vrdl_tmp;
>>   VFIOGuestIOMMU *giommu, *tmp;
>>
>>   QLIST_REMOVE(bcontainer, next);
>>
>> +QLIST_FOREACH_SAFE(vrdl, >vrdl_list, next, vrdl_tmp) {
>> +RamDiscardManager *rdm;
>> +
>> +rdm = memory_region_get_ram_discard_manager(vrdl->mr);
>> +ram_discard_manager_unregister_listener(rdm, >listener);
>> +QLIST_REMOVE(vrdl, next);
>> +g_free(vrdl);
>> +}
>
>Where was this done previously ?

Good catch! This should be removed.

>May be the vrdl list should be handled
>separatly from pgsizes and dma_max_mappings.

Good suggestion! Will do.

>
>>   QLIST_FOREACH_SAFE(giommu, >giommu_list, giommu_next,
>tmp) {
>>   memory_region_unregister_iommu_notifier(
>>   MEMORY_REGION(giommu->iommu_mr), >n);
>> diff --git a/hw/vfio/container.c b/hw/vfio/container.c
>> index 8d5b408e86..0e265ffa67 100644
>> --- a/hw/vfio/container.c
>> +++ b/hw/vfio/container.c
>> @@ -154,7 +154,7 @@ static int vfio_legacy_dma_unmap(VFIOContainerBase
>*bcontainer, hwaddr iova,
>>   if (errno == EINVAL && unmap.size && !(unmap.iova + unmap.size) &&
>>   container->iommu_type == VFIO_TYPE1v2_IOMMU) {
>>   trace_vfio_legacy_dma_unmap_overflow_workaround();
>> -unmap.size -= 1ULL << ctz64(container->pgsizes);
>> +unmap.size -= 1ULL << ctz64(container->bcontainer.pgsizes);
>>   continue;
>>   }
>>   error_report("VFIO_UNMAP_DMA failed: %s", strerror(errno));
>> @@ -559,9 +559,7 @@ static int vfio_connect_container(VFIOGroup *group,
>AddressSpace *as,
>>   container = g_malloc0(sizeof(*container));
>>   container->fd = fd;
>>   container->error = NULL;
>> -container->dma_max_mappings = 0;
>>   container->iova_ranges = NULL;
>> -QLIST_INIT(>vrdl_list);
>>   bcontainer = >bcontainer;
>>   vfio_container_init(bcontainer, space, _legacy_ops);
>>
>> @@ -589,13 +587,13 @@ static int vfio_connect_container(VFIOGroup *group,
>AddressSpace *as,
>>   }
>>
>>   if (info->flags & VFIO_IOMMU_INFO_PGSIZES) {
>> -container->pgsizes = info->iova_pgsizes;
>> +container->bcontainer.pgsizes = info->iova_pgsizes;
>>   } else {
>> -container->pgsizes = qemu_real_host_page_size();
>> +container->bcontainer.pgsizes = qemu_real_host_page_size();
>>   }
>>
>> -if (!vfio_get_info_dma_avail(info, >dma_max_mappings)) {
>> -container->dma_max_mappings = 65535;
>> +if (!vfio_get_info_dma_avail(info, >dma_max_mappings)) {
>> +container->bcontainer.dma_max_mappings = 65535;
>>   }
>>
>>   vfio_get_info_iova_range(info, container);
>> diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c
>> index 3495737ab2..dbc4c24052 100644
>> --- a/hw/vfio/spapr.c
>> +++ b/hw/vfio/spapr.c
>> @@ -223,13 +223,13 @@ static int vfio_spapr_create_window(VFIOContainer
>*container,
>>   if (pagesize > rampagesize) {
>>   pagesize = rampagesize;
>>   }
>> -pgmask = container->pgsizes & (pagesize | (pagesize - 1));
>> +pgmask = container->bcontainer.pgsizes & (pagesize | (pagesize - 1));
>>   pagesize = pgmask ? (1ULL << (63 - clz64(pgmask))) : 0;
>>   if (!pagesize) {
>>   error_report("Host doesn't support page size 0x%"PRIx64
>>", the supported mask is 0x%lx",
>>memory_region_iommu_get_min_page_size(iommu_mr),
>> - container->pgsizes);
>> + container->bcontainer.pgsizes);
>>   return -EINVAL;
>>   }
>>
>> @@ -385,7 +385,7 @@ void
>vfio_container_del_section_window(VFIOContainer *container,
>>
>>   bool vfio_spapr_container_init(VFIOContainer *container, Error **errp)
>>   {
>> -
>> +VFIOContainerBase *bcontainer = >bcontainer;
>>   struct vfio_iommu_spapr_tce_info info;
>>   bool v2 = container->iommu_type == VFIO_SPAPR_TCE_v2_IOMMU;
>>   int ret, fd = container->fd;
>> @@ -424,7 +424,7 @@ bool vfio_spapr_container_init(VFIOContainer
>*container, Error **errp)
>>   }
>>
>>   if (v2) {
>> -container->pgsizes = info.ddw.pgsizes;
>> +bcontainer->pgsizes = info.ddw.pgsizes;
>>   /*
>>* There is a default window in just created container.
>>* To make region_add/del simpler, we better remove this
>> @@ -439,7 +439,7 @@ bool vfio_spapr_container_init(VFIOContainer
>*container, Error **errp)
>>   }
>>   } else {
>>   /* The default table uses 4K pages */
>> -  

Re: [PATCH v3 3/4] target/riscv: add zihpm extension flag for TCG

[Alistair Francis]

On Tue, Oct 24, 2023 at 1:40 AM Daniel Henrique Barboza
 wrote:
>
> zihpm is the Hardware Performance Counters extension described in
> chapter 12 of the unprivileged spec. It describes support for 29
> unprivileged performance counters, hpmcounter3-hpmcounter31.
>
> As with zicntr, QEMU already implements zihpm before it was even an
> extension. zihpm is also part of the RVA22 profile, so add it to QEMU
> to complement the future profile implementation. Default it to 'true'
> for all existing CPUs since it was always present in the code.
>
> As for disabling it, there is already code in place in
> target/riscv/csr.c in all predicates for these counters (ctr() and
> mctr()) that disables them if cpu->cfg.pmu_num is zero. Thus, setting
> cpu->cfg.pmu_num to zero if 'zihpm=false' is enough to disable the
> extension.
>
> Set cpu->pmu_avail_ctrs mask to zero as well since this is also checked
> to verify if the counters exist.
>
> Signed-off-by: Daniel Henrique Barboza 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c |  3 +++
>  target/riscv/cpu_cfg.h |  1 +
>  target/riscv/tcg/tcg-cpu.c | 13 +
>  3 files changed, 17 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 69d64ec4ca..f40da4c661 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -85,6 +85,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>  ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
>  ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
>  ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
> +ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
>  ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
>  ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
>  ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
> @@ -1218,6 +1219,7 @@ static void riscv_cpu_init(Object *obj)
>   * users disable them.
>   */
>  RISCV_CPU(obj)->cfg.ext_zicntr = true;
> +RISCV_CPU(obj)->cfg.ext_zihpm = true;
>  }
>
>  typedef struct misa_ext_info {
> @@ -1308,6 +1310,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>  MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
>
>  MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
> +MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true),
>
>  MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
>  MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 73fd4b3231..6eef4a51ea 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -69,6 +69,7 @@ struct RISCVCPUConfig {
>  bool ext_zicond;
>  bool ext_zihintntl;
>  bool ext_zihintpause;
> +bool ext_zihpm;
>  bool ext_smstateen;
>  bool ext_sstc;
>  bool ext_svadu;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a1e4ed2e24..093bda2e75 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -549,6 +549,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
> Error **errp)
>  cpu->cfg.ext_zicntr = false;
>  }
>
> +if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) {
> +if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) {
> +error_setg(errp, "zihpm requires zicsr");
> +return;
> +}
> +cpu->cfg.ext_zihpm = false;
> +}
> +
> +if (!cpu->cfg.ext_zihpm) {
> +cpu->cfg.pmu_num = 0;
> +cpu->pmu_avail_ctrs = 0;
> +}
> +
>  /*
>   * Disable isa extensions based on priv spec after we
>   * validated and set everything we need.
> --
> 2.41.0
>
>

Re: [PATCH v5 04/21] net: Remove receive_raw()

[Jason Wang]

在 2023/10/27 15:52, Akihiko Odaki 写道:

On 2023/10/27 15:49, Jason Wang wrote:
On Tue, Oct 17, 2023 at 12:09 PM Akihiko Odaki 
 wrote:


While netmap implements virtio-net header, it does not implement
receive_raw().


The only user for raw is the announcing. Netmap probably doesn't it 
at all.


In my understanding, the announcing *sends* a raw packet.



It's send via NIC and receive by its peer which is the TAP

qemu_send_packet_raw() -> nc -> nc->peer -> peer->receive_raw()?

Anything I miss?

Thanks



Both of tap and netmap *receive* packets with virtio-net headers.

Regards,
Akihiko Odaki

Re: [PATCH v4 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT

[Alistair Francis]

On Thu, Oct 26, 2023 at 6:15 AM Sunil V L  wrote:
>
> Add PLIC structures for each socket in the MADT when system is
> configured with PLIC as the external interrupt controller.
>
> Signed-off-by: Haibo Xu 
> Signed-off-by: Sunil V L 
> Reviewed-by: Daniel Henrique Barboza 
> Reviewed-by: Andrew Jones 

Acked-by: Alistair Francis 

Alistair

> ---
>  hw/riscv/virt-acpi-build.c | 29 +
>  1 file changed, 29 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index c410fe7d5c..cc934a5c4b 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -85,6 +85,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
>arch_ids->cpus[uid].props.node_id,
>local_cpu_id),
>4);
> +} else if (aia_type == VIRT_AIA_TYPE_NONE) {
> +build_append_int_noprefix(entry,
> +  ACPI_BUILD_INTC_ID(
> +  arch_ids->cpus[uid].props.node_id,
> +  2 * local_cpu_id + 1),
> +  4);
>  } else {
>  build_append_int_noprefix(entry, 0, 4);
>  }
> @@ -515,6 +521,29 @@ static void build_madt(GArray *table_data,
>  build_append_int_noprefix(table_data,
>s->memmap[VIRT_APLIC_S].size, 4);
>  }
> +} else {
> +/* PLICs */
> +for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> +aplic_addr = s->memmap[VIRT_PLIC].base +
> + s->memmap[VIRT_PLIC].size * socket;
> +gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> +build_append_int_noprefix(table_data, 0x1B, 1);   /* Type */
> +build_append_int_noprefix(table_data, 36, 1); /* Length */
> +build_append_int_noprefix(table_data, 1, 1);  /* Version */
> +build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
> +build_append_int_noprefix(table_data, 0, 8);  /* Hardware ID 
> */
> +/* Total External Interrupt Sources Supported */
> +build_append_int_noprefix(table_data,
> +  VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
> +build_append_int_noprefix(table_data, 0, 2); /* Max Priority 
> */
> +build_append_int_noprefix(table_data, 0, 4); /* Flags */
> +/* PLIC Size */
> +build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 
> 4);
> +/* PLIC Address */
> +build_append_int_noprefix(table_data, aplic_addr, 8);
> +/* Global System Interrupt Vector Base */
> +build_append_int_noprefix(table_data, gsi_base, 4);
> +}
>  }
>
>  acpi_table_end(linker, );
> --
> 2.39.2
>
>

Re: [PATCH v4 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices

[Alistair Francis]

On Thu, Oct 26, 2023 at 6:15 AM Sunil V L  wrote:
>
> Add basic IO controllers and devices like PCI, VirtIO and UART in the
> ACPI namespace.
>
> Signed-off-by: Sunil V L 
> Reviewed-by: Daniel Henrique Barboza 

Acked-by: Alistair Francis 

Alistair

> ---
>  hw/riscv/Kconfig   |  1 +
>  hw/riscv/virt-acpi-build.c | 79 --
>  2 files changed, 76 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index b6a5eb4452..a50717be87 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -45,6 +45,7 @@ config RISCV_VIRT
>  select FW_CFG_DMA
>  select PLATFORM_BUS
>  select ACPI
> +select ACPI_PCI
>
>  config SHAKTI_C
>  bool
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index dc7c0213f5..c410fe7d5c 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -27,15 +27,18 @@
>  #include "hw/acpi/acpi-defs.h"
>  #include "hw/acpi/acpi.h"
>  #include "hw/acpi/aml-build.h"
> +#include "hw/acpi/pci.h"
>  #include "hw/acpi/utils.h"
> +#include "hw/intc/riscv_aclint.h"
>  #include "hw/nvram/fw_cfg_acpi.h"
> +#include "hw/pci-host/gpex.h"
> +#include "hw/riscv/virt.h"
> +#include "hw/riscv/numa.h"
> +#include "hw/virtio/virtio-acpi.h"
> +#include "migration/vmstate.h"
>  #include "qapi/error.h"
>  #include "qemu/error-report.h"
>  #include "sysemu/reset.h"
> -#include "migration/vmstate.h"
> -#include "hw/riscv/virt.h"
> -#include "hw/riscv/numa.h"
> -#include "hw/intc/riscv_aclint.h"
>
>  #define ACPI_BUILD_TABLE_SIZE 0x2
>  #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
> @@ -139,6 +142,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, 
> RISCVVirtState *s)
>  }
>  }
>
> +static void
> +acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> +uint32_t uart_irq)
> +{
> +Aml *dev = aml_device("COM0");
> +aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
> +aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> +Aml *crs = aml_resource_template();
> +aml_append(crs, aml_memory32_fixed(uart_memmap->base,
> + uart_memmap->size, AML_READ_WRITE));
> +aml_append(crs,
> +aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> +   AML_EXCLUSIVE, _irq, 1));
> +aml_append(dev, aml_name_decl("_CRS", crs));
> +
> +Aml *pkg = aml_package(2);
> +aml_append(pkg, aml_string("clock-frequency"));
> +aml_append(pkg, aml_int(3686400));
> +
> +Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
> +
> +Aml *pkg1 = aml_package(1);
> +aml_append(pkg1, pkg);
> +
> +Aml *package = aml_package(2);
> +aml_append(package, UUID);
> +aml_append(package, pkg1);
> +
> +aml_append(dev, aml_name_decl("_DSD", package));
> +aml_append(scope, dev);
> +}
> +
>  /* RHCT Node[N] starts at offset 56 */
>  #define RHCT_NODE_ARRAY_OFFSET 56
>
> @@ -318,6 +354,8 @@ static void build_dsdt(GArray *table_data,
> RISCVVirtState *s)
>  {
>  Aml *scope, *dsdt;
> +MachineState *ms = MACHINE(s);
> +uint8_t socket_count;
>  const MemMapEntry *memmap = s->memmap;
>  AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
>  .oem_table_id = s->oem_table_id };
> @@ -337,6 +375,29 @@ static void build_dsdt(GArray *table_data,
>
>  fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
>
> +socket_count = riscv_socket_count(ms);
> +
> +acpi_dsdt_add_uart(scope, [VIRT_UART0], UART0_IRQ);
> +
> +if (socket_count == 1) {
> +virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
> + memmap[VIRT_VIRTIO].size,
> + VIRTIO_IRQ, 0, VIRTIO_COUNT);
> +acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
> +} else if (socket_count == 2) {
> +virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
> + memmap[VIRT_VIRTIO].size,
> + VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
> + VIRTIO_COUNT);
> +acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
> +} else {
> +virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
> + memmap[VIRT_VIRTIO].size,
> + VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
> + VIRTIO_COUNT);
> +acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 
> 2);
> +}
> +
>  aml_append(dsdt, scope);
>
>  /* copy AML table into ACPI tables blob and patch header there */
> @@ -486,6 +547,16 @@ static void virt_acpi_build(RISCVVirtState *s, 
> AcpiBuildTables *tables)
>  acpi_add_table(table_offsets, tables_blob);
>  build_rhct(tables_blob, tables->linker, s);
>
> +

RE: [PATCH v3 11/37] vfio/container: Switch to IOMMU BE set_dirty_page_tracking/query_dirty_bitmap API

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 10:53 PM
>Subject: Re: [PATCH v3 11/37] vfio/container: Switch to IOMMU BE
>set_dirty_page_tracking/query_dirty_bitmap API
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> From: Eric Auger 
>>
>> dirty_pages_supported field is also moved to the base container
>>
>> No fucntional change intended.
>>
>> Signed-off-by: Eric Auger 
>> Signed-off-by: Yi Liu 
>> Signed-off-by: Yi Sun 
>> Signed-off-by: Zhenzhong Duan 
>> Signed-off-by: Cédric Le Goater 
>> ---
>>   include/hw/vfio/vfio-common.h |  6 --
>>   include/hw/vfio/vfio-container-base.h |  6 ++
>>   hw/vfio/common.c  | 12 
>>   hw/vfio/container-base.c  | 23 +++
>>   hw/vfio/container.c   | 21 ++---
>>   5 files changed, 51 insertions(+), 17 deletions(-)
>>
>> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
>> index 857d2b8076..d053c61872 100644
>> --- a/include/hw/vfio/vfio-common.h
>> +++ b/include/hw/vfio/vfio-common.h
>> @@ -83,7 +83,6 @@ typedef struct VFIOContainer {
>>   unsigned iommu_type;
>>   Error *error;
>>   bool initialized;
>> -bool dirty_pages_supported;
>>   uint64_t dirty_pgsizes;
>>   uint64_t max_dirty_bitmap_size;
>>   unsigned long pgsizes;
>> @@ -190,11 +189,6 @@ VFIOAddressSpace
>*vfio_get_address_space(AddressSpace *as);
>>   void vfio_put_address_space(VFIOAddressSpace *space);
>>   bool vfio_devices_all_running_and_saving(VFIOContainer *container);
>>
>> -/* container->fd */
>> -int vfio_set_dirty_page_tracking(VFIOContainer *container, bool start);
>> -int vfio_query_dirty_bitmap(VFIOContainer *container, VFIOBitmap *vbmap,
>> -hwaddr iova, hwaddr size);
>> -
>>   /* SPAPR specific */
>>   int vfio_container_add_section_window(VFIOContainer *container,
>> MemoryRegionSection *section,
>> diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-
>container-base.h
>> index a5fef3e6a8..ea8436a064 100644
>> --- a/include/hw/vfio/vfio-container-base.h
>> +++ b/include/hw/vfio/vfio-container-base.h
>> @@ -50,6 +50,7 @@ typedef struct VFIOAddressSpace {
>>   typedef struct VFIOContainerBase {
>>   const VFIOIOMMUOps *ops;
>>   VFIOAddressSpace *space;
>> +bool dirty_pages_supported;
>>   QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
>>   QLIST_ENTRY(VFIOContainerBase) next;
>>   } VFIOContainerBase;
>> @@ -68,6 +69,11 @@ int vfio_container_dma_map(VFIOContainerBase
>*bcontainer,
>>   int vfio_container_dma_unmap(VFIOContainerBase *bcontainer,
>>hwaddr iova, ram_addr_t size,
>>IOMMUTLBEntry *iotlb);
>> +int vfio_container_set_dirty_page_tracking(VFIOContainerBase *bcontainer,
>> +   bool start);
>> +int vfio_container_query_dirty_bitmap(VFIOContainerBase *bcontainer,
>> +  VFIOBitmap *vbmap,
>> +  hwaddr iova, hwaddr size);
>>
>>   void vfio_container_init(VFIOContainerBase *bcontainer,
>>VFIOAddressSpace *space,
>> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
>> index f87a0dcec3..7d9b87fc67 100644
>> --- a/hw/vfio/common.c
>> +++ b/hw/vfio/common.c
>> @@ -1081,7 +1081,8 @@ static void
>vfio_listener_log_global_start(MemoryListener *listener)
>>   if (vfio_devices_all_device_dirty_tracking(container)) {
>>   ret = vfio_devices_dma_logging_start(container);
>>   } else {
>> -ret = vfio_set_dirty_page_tracking(container, true);
>> +ret = vfio_container_set_dirty_page_tracking(>bcontainer,
>> + true);
>>   }
>>
>>   if (ret) {
>> @@ -1099,7 +1100,8 @@ static void
>vfio_listener_log_global_stop(MemoryListener *listener)
>>   if (vfio_devices_all_device_dirty_tracking(container)) {
>>   vfio_devices_dma_logging_stop(container);
>>   } else {
>> -ret = vfio_set_dirty_page_tracking(container, false);
>> +ret = vfio_container_set_dirty_page_tracking(>bcontainer,
>> + false);
>>   }
>>
>>   if (ret) {
>> @@ -1167,7 +1169,8 @@ int vfio_get_dirty_bitmap(VFIOContainer *container,
>uint64_t iova,
>>   VFIOBitmap vbmap;
>>   int ret;
>>
>> -if (!container->dirty_pages_supported && !all_device_dirty_tracking) {
>> +if (!container->bcontainer.dirty_pages_supported &&
>> +!all_device_dirty_tracking) {
>>   cpu_physical_memory_set_dirty_range(ram_addr, size,
>>   tcg_enabled() ? 
>> DIRTY_CLIENTS_ALL :
>>   DIRTY_CLIENTS_NOCODE);
>> @@ -1182,7 +1185,8 @@ int vfio_get_dirty_bitmap(VFIOContainer 

RE: [PATCH v3 10/37] vfio/container: Move space field to base container

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 10:46 PM
>Subject: Re: [PATCH v3 10/37] vfio/container: Move space field to base 
>container
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> From: Eric Auger 
>>
>> Move the space field to the base object. Also the VFIOAddressSpace
>> now contains a list of base containers.
>>
>> No fucntional change intended.
>>
>> Signed-off-by: Eric Auger 
>> Signed-off-by: Yi Liu 
>> Signed-off-by: Yi Sun 
>> Signed-off-by: Zhenzhong Duan 
>> [ clg: context changes ]
>> Signed-off-by: Cédric Le Goater 
>> ---
>>   include/hw/vfio/vfio-common.h |  8 
>>   include/hw/vfio/vfio-container-base.h |  9 +
>>   hw/ppc/spapr_pci_vfio.c   | 10 +-
>>   hw/vfio/common.c  |  4 ++--
>>   hw/vfio/container-base.c  |  6 +-
>>   hw/vfio/container.c   | 18 +-
>>   6 files changed, 30 insertions(+), 25 deletions(-)
>>
>> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
>> index fcb4003a21..857d2b8076 100644
>> --- a/include/hw/vfio/vfio-common.h
>> +++ b/include/hw/vfio/vfio-common.h
>> @@ -73,17 +73,10 @@ typedef struct VFIOMigration {
>>   bool initial_data_sent;
>>   } VFIOMigration;
>>
>> -typedef struct VFIOAddressSpace {
>> -AddressSpace *as;
>> -QLIST_HEAD(, VFIOContainer) containers;
>> -QLIST_ENTRY(VFIOAddressSpace) list;
>> -} VFIOAddressSpace;
>> -
>>   struct VFIOGroup;
>>
>>   typedef struct VFIOContainer {
>>   VFIOContainerBase bcontainer;
>> -VFIOAddressSpace *space;
>>   int fd; /* /dev/vfio/vfio, empowered by the attached groups */
>>   MemoryListener listener;
>>   MemoryListener prereg_listener;
>> @@ -98,7 +91,6 @@ typedef struct VFIOContainer {
>>   QLIST_HEAD(, VFIOHostDMAWindow) hostwin_list;
>>   QLIST_HEAD(, VFIOGroup) group_list;
>>   QLIST_HEAD(, VFIORamDiscardListener) vrdl_list;
>> -QLIST_ENTRY(VFIOContainer) next;
>>   QLIST_HEAD(, VFIODevice) device_list;
>>   GList *iova_ranges;
>>   } VFIOContainer;
>> diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-
>container-base.h
>> index 71e1e4324e..a5fef3e6a8 100644
>> --- a/include/hw/vfio/vfio-container-base.h
>> +++ b/include/hw/vfio/vfio-container-base.h
>> @@ -38,12 +38,20 @@ typedef struct {
>>   hwaddr pages;
>>   } VFIOBitmap;
>>
>> +typedef struct VFIOAddressSpace {
>> +AddressSpace *as;
>> +QLIST_HEAD(, VFIOContainerBase) containers;
>> +QLIST_ENTRY(VFIOAddressSpace) list;
>> +} VFIOAddressSpace;
>> +
>>   /*
>>* This is the base object for vfio container backends
>>*/
>>   typedef struct VFIOContainerBase {
>>   const VFIOIOMMUOps *ops;
>> +VFIOAddressSpace *space;
>>   QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
>> +QLIST_ENTRY(VFIOContainerBase) next;
>>   } VFIOContainerBase;
>>
>>   typedef struct VFIOGuestIOMMU {
>> @@ -62,6 +70,7 @@ int vfio_container_dma_unmap(VFIOContainerBase
>*bcontainer,
>>IOMMUTLBEntry *iotlb);
>>
>>   void vfio_container_init(VFIOContainerBase *bcontainer,
>> + VFIOAddressSpace *space,
>>const VFIOIOMMUOps *ops);
>>   void vfio_container_destroy(VFIOContainerBase *bcontainer);
>>
>> diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
>> index f283f7e38d..d1d07bec46 100644
>> --- a/hw/ppc/spapr_pci_vfio.c
>> +++ b/hw/ppc/spapr_pci_vfio.c
>> @@ -84,27 +84,27 @@ static int vfio_eeh_container_op(VFIOContainer
>*container, uint32_t op)
>>   static VFIOContainer *vfio_eeh_as_container(AddressSpace *as)
>>   {
>>   VFIOAddressSpace *space = vfio_get_address_space(as);
>> -VFIOContainer *container = NULL;
>> +VFIOContainerBase *bcontainer = NULL;
>>
>>   if (QLIST_EMPTY(>containers)) {
>>   /* No containers to act on */
>>   goto out;
>>   }
>>
>> -container = QLIST_FIRST(>containers);
>> +bcontainer = QLIST_FIRST(>containers);
>>
>> -if (QLIST_NEXT(container, next)) {
>> +if (QLIST_NEXT(bcontainer, next)) {
>>   /*
>>* We don't yet have logic to synchronize EEH state across
>>* multiple containers
>>*/
>> -container = NULL;
>> +bcontainer = NULL;
>>   goto out;
>>   }
>>
>>   out:
>>   vfio_put_address_space(space);
>> -return container;
>> +return container_of(bcontainer, VFIOContainer, bcontainer);
>>   }
>>
>>   static bool vfio_eeh_as_ok(AddressSpace *as)
>> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
>> index 4f130ad87c..f87a0dcec3 100644
>> --- a/hw/vfio/common.c
>> +++ b/hw/vfio/common.c
>> @@ -145,7 +145,7 @@ void vfio_unblock_multiple_devices_migration(void)
>>
>>   bool vfio_viommu_preset(VFIODevice *vbasedev)
>>   {
>> -return vbasedev->container->space->as != _space_memory;
>> +return vbasedev->container->bcontainer.space->as !=

Re: [PATCH v4 11/13] hw/riscv/virt: Update GPEX MMIO related properties

[Alistair Francis]

On Thu, Oct 26, 2023 at 6:09 AM Sunil V L  wrote:
>
> Update the GPEX host bridge properties related to MMIO ranges with
> values set for the virt machine.
>
> Suggested-by: Igor Mammedov 
> Signed-off-by: Sunil V L 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  hw/riscv/virt.c | 47 -
>  include/hw/riscv/virt.h |  1 +
>  2 files changed, 33 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 085654ab2f..e64886a4d8 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const 
> MemMapEntry *memmap)
>  }
>
>  static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> -  hwaddr ecam_base, hwaddr ecam_size,
> -  hwaddr mmio_base, hwaddr mmio_size,
> -  hwaddr high_mmio_base,
> -  hwaddr high_mmio_size,
> -  hwaddr pio_base,
> -  DeviceState *irqchip)
> +  DeviceState *irqchip,
> +  RISCVVirtState *s)
>  {
>  DeviceState *dev;
>  MemoryRegion *ecam_alias, *ecam_reg;
>  MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
> +hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
> +hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
> +hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
> +hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
> +hwaddr high_mmio_base = virt_high_pcie_memmap.base;
> +hwaddr high_mmio_size = virt_high_pcie_memmap.size;
> +hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
> +hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
>  qemu_irq irq;
>  int i;
>
>  dev = qdev_new(TYPE_GPEX_HOST);
>
> +/* Set GPEX object properties for the virt machine */
> +object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
> +ecam_base, NULL);
> +object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
> +ecam_size, NULL);
> +object_property_set_uint(OBJECT(GPEX_HOST(dev)),
> + PCI_HOST_BELOW_4G_MMIO_BASE,
> + mmio_base, NULL);
> +object_property_set_int(OBJECT(GPEX_HOST(dev)), 
> PCI_HOST_BELOW_4G_MMIO_SIZE,
> +mmio_size, NULL);
> +object_property_set_uint(OBJECT(GPEX_HOST(dev)),
> + PCI_HOST_ABOVE_4G_MMIO_BASE,
> + high_mmio_base, NULL);
> +object_property_set_int(OBJECT(GPEX_HOST(dev)), 
> PCI_HOST_ABOVE_4G_MMIO_SIZE,
> +high_mmio_size, NULL);
> +object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
> +pio_base, NULL);
> +object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
> +pio_size, NULL);
> +
>  sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
>
>  ecam_alias = g_new0(MemoryRegion, 1);
> @@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion 
> *sys_mem,
>  gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
>  }
>
> +GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
>  return dev;
>  }
>
> @@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
>  qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
>  }
>
> -gpex_pcie_init(system_memory,
> -   memmap[VIRT_PCIE_ECAM].base,
> -   memmap[VIRT_PCIE_ECAM].size,
> -   memmap[VIRT_PCIE_MMIO].base,
> -   memmap[VIRT_PCIE_MMIO].size,
> -   virt_high_pcie_memmap.base,
> -   virt_high_pcie_memmap.size,
> -   memmap[VIRT_PCIE_PIO].base,
> -   pcie_irqchip);
> +gpex_pcie_init(system_memory, pcie_irqchip, s);
>
>  create_platform_bus(s, mmio_irqchip);
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 5b03575ed3..f89790fd58 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -61,6 +61,7 @@ struct RISCVVirtState {
>  char *oem_table_id;
>  OnOffAuto acpi;
>  const MemMapEntry *memmap;
> +struct GPEXHost *gpex_host;
>  };
>
>  enum {
> --
> 2.39.2
>
>

RE: [PATCH v3 09/37] vfio/common: Move giommu_list in base container

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 10:39 PM
>Subject: Re: [PATCH v3 09/37] vfio/common: Move giommu_list in base
>container
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> From: Eric Auger 
>>
>> Move the giommu_list field in the base object and store the
>> base container in the VFIOGuestIOMMU.
>>
>> We introduce vfio_container_init/destroy helper on the base
>> container.
>
>This could have been a prereq patch.

Yes.

>
>>
>> No fucntional change intended.
>
>functional
Will fix.

>
>>
>> Signed-off-by: Eric Auger 
>> Signed-off-by: Yi Liu 
>> Signed-off-by: Yi Sun 
>> Signed-off-by: Zhenzhong Duan 
>> [ clg: context changes ]
>> Signed-off-by: Cédric Le Goater 
>
>You can drop my Sob here and in all patches. The changes I did were
>due to the recent 'iova_ranges' addition and the context was fuzzy.
>Nothing major.

Got it, will do.

Thanks
Zhenzhong

>
>The rest looks good.
>
>Thanks,
>
>C.
>
>> ---
>>   include/hw/vfio/vfio-common.h |  9 -
>>   include/hw/vfio/vfio-container-base.h | 13 +
>>   hw/vfio/common.c  | 17 +++--
>>   hw/vfio/container-base.c  | 18 ++
>>   hw/vfio/container.c   | 13 +++--
>>   5 files changed, 45 insertions(+), 25 deletions(-)
>>
>> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
>> index 97056224f4..fcb4003a21 100644
>> --- a/include/hw/vfio/vfio-common.h
>> +++ b/include/hw/vfio/vfio-common.h
>> @@ -95,7 +95,6 @@ typedef struct VFIOContainer {
>>   uint64_t max_dirty_bitmap_size;
>>   unsigned long pgsizes;
>>   unsigned int dma_max_mappings;
>> -QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
>>   QLIST_HEAD(, VFIOHostDMAWindow) hostwin_list;
>>   QLIST_HEAD(, VFIOGroup) group_list;
>>   QLIST_HEAD(, VFIORamDiscardListener) vrdl_list;
>> @@ -104,14 +103,6 @@ typedef struct VFIOContainer {
>>   GList *iova_ranges;
>>   } VFIOContainer;
>>
>> -typedef struct VFIOGuestIOMMU {
>> -VFIOContainer *container;
>> -IOMMUMemoryRegion *iommu_mr;
>> -hwaddr iommu_offset;
>> -IOMMUNotifier n;
>> -QLIST_ENTRY(VFIOGuestIOMMU) giommu_next;
>> -} VFIOGuestIOMMU;
>> -
>>   typedef struct VFIORamDiscardListener {
>>   VFIOContainer *container;
>>   MemoryRegion *mr;
>> diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-
>container-base.h
>> index 077e638ee8..71e1e4324e 100644
>> --- a/include/hw/vfio/vfio-container-base.h
>> +++ b/include/hw/vfio/vfio-container-base.h
>> @@ -43,8 +43,17 @@ typedef struct {
>>*/
>>   typedef struct VFIOContainerBase {
>>   const VFIOIOMMUOps *ops;
>> +QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
>>   } VFIOContainerBase;
>>
>> +typedef struct VFIOGuestIOMMU {
>> +VFIOContainerBase *bcontainer;
>> +IOMMUMemoryRegion *iommu_mr;
>> +hwaddr iommu_offset;
>> +IOMMUNotifier n;
>> +QLIST_ENTRY(VFIOGuestIOMMU) giommu_next;
>> +} VFIOGuestIOMMU;
>> +
>>   int vfio_container_dma_map(VFIOContainerBase *bcontainer,
>>  hwaddr iova, ram_addr_t size,
>>  void *vaddr, bool readonly);
>> @@ -52,6 +61,10 @@ int vfio_container_dma_unmap(VFIOContainerBase
>*bcontainer,
>>hwaddr iova, ram_addr_t size,
>>IOMMUTLBEntry *iotlb);
>>
>> +void vfio_container_init(VFIOContainerBase *bcontainer,
>> + const VFIOIOMMUOps *ops);
>> +void vfio_container_destroy(VFIOContainerBase *bcontainer);
>> +
>>   struct VFIOIOMMUOps {
>>   /* basic feature */
>>   int (*dma_map)(VFIOContainerBase *bcontainer,
>> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
>> index 141f2b54a4..4f130ad87c 100644
>> --- a/hw/vfio/common.c
>> +++ b/hw/vfio/common.c
>> @@ -292,7 +292,7 @@ static bool vfio_get_xlat_addr(IOMMUTLBEntry *iotlb,
>void **vaddr,
>>   static void vfio_iommu_map_notify(IOMMUNotifier *n, IOMMUTLBEntry
>*iotlb)
>>   {
>>   VFIOGuestIOMMU *giommu = container_of(n, VFIOGuestIOMMU, n);
>> -VFIOContainerBase *bcontainer = >container->bcontainer;
>> +VFIOContainerBase *bcontainer = giommu->bcontainer;
>>   hwaddr iova = iotlb->iova + giommu->iommu_offset;
>>   void *vaddr;
>>   int ret;
>> @@ -569,6 +569,7 @@ static void vfio_listener_region_add(MemoryListener
>*listener,
>>MemoryRegionSection *section)
>>   {
>>   VFIOContainer *container = container_of(listener, VFIOContainer, 
>> listener);
>> +VFIOContainerBase *bcontainer = >bcontainer;
>>   hwaddr iova, end;
>>   Int128 llend, llsize;
>>   void *vaddr;
>> @@ -613,7 +614,7 @@ static void vfio_listener_region_add(MemoryListener
>*listener,
>>   giommu->iommu_mr = iommu_mr;
>>   giommu->iommu_offset = section->offset_within_address_space -
>>  section->offset_within_region;
>> - 

RE: [PATCH v3 08/37] vfio/container: Switch to dma_map|unmap API

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 10:26 PM
>Subject: Re: [PATCH v3 08/37] vfio/container: Switch to dma_map|unmap API
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> From: Eric Auger 
>>
>> No fucntional change intended.
>>
>> Signed-off-by: Eric Auger 
>> Signed-off-by: Yi Liu 
>> Signed-off-by: Yi Sun 
>> Signed-off-by: Zhenzhong Duan 
...

>> diff --git a/hw/vfio/container-base.c b/hw/vfio/container-base.c
>> new file mode 100644
>> index 00..9db8b89b2f
>> --- /dev/null
>> +++ b/hw/vfio/container-base.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * VFIO BASE CONTAINER
>> + *
>> + * Copyright (C) 2023 Intel Corporation.
>> + * Copyright Red Hat, Inc. 2023
>> + *
>> + * Authors: Yi Liu 
>> + *  Eric Auger 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> +
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> +
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see .
>> + */
>
>Please reduce the header with an SPDX identifier.

Will fix.

>
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "qemu/error-report.h"
>> +#include "hw/vfio/vfio-container-base.h"
>> +
>> +int vfio_container_dma_map(VFIOContainerBase *bcontainer,
>> +   hwaddr iova, ram_addr_t size,
>> +   void *vaddr, bool readonly)
>> +{
>> +if (!bcontainer->ops->dma_map) {
>
>I think this could be an assert instead ?

Good suggestion, will fix.

>
>> +return -EINVAL;
>> +}
>> +
>> +return bcontainer->ops->dma_map(bcontainer, iova, size, vaddr, 
>> readonly);
>> +}
>> +
>> +int vfio_container_dma_unmap(VFIOContainerBase *bcontainer,
>> + hwaddr iova, ram_addr_t size,
>> + IOMMUTLBEntry *iotlb)
>> +{
>> +if (!bcontainer->ops->dma_unmap) {
>> +return -EINVAL;
>> +}

and here.

Thanks
Zhenzhong

RE: [PATCH v3 07/37] vfio/container: Introduce a empty VFIOIOMMUOps

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 10:21 PM
>Subject: Re: [PATCH v3 07/37] vfio/container: Introduce a empty
>VFIOIOMMUOps
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> This empty VFIOIOMMUOps named vfio_legacy_ops will hold all general
>> IOMMU ops of legacy container.
>>
>> Signed-off-by: Zhenzhong Duan 
>> ---
>>   include/hw/vfio/vfio-common.h | 2 +-
>>   hw/vfio/container.c   | 5 +
>>   2 files changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
>> index d8f293cb57..8ded5cd8e4 100644
>> --- a/include/hw/vfio/vfio-common.h
>> +++ b/include/hw/vfio/vfio-common.h
>> @@ -255,7 +255,7 @@ typedef QLIST_HEAD(VFIOGroupList, VFIOGroup)
>VFIOGroupList;
>>   typedef QLIST_HEAD(VFIODeviceList, VFIODevice) VFIODeviceList;
>>   extern VFIOGroupList vfio_group_list;
>>   extern VFIODeviceList vfio_device_list;
>> -
>> +extern const VFIOIOMMUOps vfio_legacy_ops;
>
>
>why does it need to be external ?

It is referenced by vfio_connect_container() and vfio_attach_device().

Thanks
Zhenzhong

RE: [PATCH v3 06/37] vfio: Introduce base object for VFIOContainer and targetted interface

[Duan, Zhenzhong]

>-Original Message-
>From: Cédric Le Goater 
>Sent: Friday, October 27, 2023 10:03 PM
>Subject: Re: [PATCH v3 06/37] vfio: Introduce base object for VFIOContainer and
>targetted interface
>
>On 10/26/23 12:30, Zhenzhong Duan wrote:
>> Introduce a dumb VFIOContainer base object and its targetted interface.
>
>targeted

Will fix.

>
>
>> This is willingly not a QOM object because we don't want it to be
>> visible from the user interface.  The VFIOContainer will be smoothly
>> populated in subsequent patches as well as interfaces.
>>
>> No fucntional change intended.
>>
>> Signed-off-by: Eric Auger 
>> Signed-off-by: Yi Liu 
>> Signed-off-by: Yi Sun 
>> Signed-off-by: Zhenzhong Duan 
>> ---
>>   include/hw/vfio/vfio-common.h |  8 +---
>>   include/hw/vfio/vfio-container-base.h | 64 +++
>>   2 files changed, 66 insertions(+), 6 deletions(-)
>>   create mode 100644 include/hw/vfio/vfio-container-base.h
>>
>> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
>> index b9c7a7e588..d8f293cb57 100644
>> --- a/include/hw/vfio/vfio-common.h
>> +++ b/include/hw/vfio/vfio-common.h
>> @@ -30,6 +30,7 @@
>>   #include 
>>   #endif
>>   #include "sysemu/sysemu.h"
>> +#include "hw/vfio/vfio-container-base.h"
>>
>>   #define VFIO_MSG_PREFIX "vfio %s: "
>>
>> @@ -81,6 +82,7 @@ typedef struct VFIOAddressSpace {
>>   struct VFIOGroup;
>>
>>   typedef struct VFIOContainer {
>> +VFIOContainerBase bcontainer;
>>   VFIOAddressSpace *space;
>>   int fd; /* /dev/vfio/vfio, empowered by the attached groups */
>>   MemoryListener listener;
>> @@ -201,12 +203,6 @@ typedef struct VFIODisplay {
>>   } dmabuf;
>>   } VFIODisplay;
>>
>> -typedef struct {
>> -unsigned long *bitmap;
>> -hwaddr size;
>> -hwaddr pages;
>> -} VFIOBitmap;
>> -
>>   VFIOAddressSpace *vfio_get_address_space(AddressSpace *as);
>>   void vfio_put_address_space(VFIOAddressSpace *space);
>>   bool vfio_devices_all_running_and_saving(VFIOContainer *container);
>> diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-
>container-base.h
>> new file mode 100644
>> index 00..5becbd51a7
>> --- /dev/null
>> +++ b/include/hw/vfio/vfio-container-base.h
>> @@ -0,0 +1,64 @@
>> +/*
>> + * VFIO BASE CONTAINER
>> + *
>> + * Copyright (C) 2023 Intel Corporation.
>> + * Copyright Red Hat, Inc. 2023
>> + *
>> + * Authors: Yi Liu 
>> + *  Eric Auger 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> +
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> +
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see .
>
>This should be enough :
>
>   SPDX-License-Identifier: GPL-2.0-or-later

Will do.

>
>> + */
>> +
>> +#ifndef HW_VFIO_VFIO_BASE_CONTAINER_H
>> +#define HW_VFIO_VFIO_BASE_CONTAINER_H
>
>HW_VFIO_VFIO_CONTAINER_BASE_H
>
>> +
>> +#include "exec/memory.h"
>> +#ifndef CONFIG_USER_ONLY
>> +#include "exec/hwaddr.h"
>> +#endif
>
>including "exec/memory.h" should be enough.

Will do.

>
>
>> +
>> +typedef struct VFIODevice VFIODevice;
>> +typedef struct VFIOIOMMUOps VFIOIOMMUOps;
>> +
>> +typedef struct {
>> +unsigned long *bitmap;
>> +hwaddr size;
>> +hwaddr pages;
>> +} VFIOBitmap;
>> +
>> +/*
>> + * This is the base object for vfio container backends
>> + */
>> +typedef struct VFIOContainerBase {
>> +const VFIOIOMMUOps *ops;
>> +} VFIOContainerBase;
>> +
>> +struct VFIOIOMMUOps {
>> +/* basic feature */
>> +int (*dma_map)(VFIOContainerBase *bcontainer,
>> +   hwaddr iova, ram_addr_t size,
>> +   void *vaddr, bool readonly);
>> +int (*dma_unmap)(VFIOContainerBase *bcontainer,
>> + hwaddr iova, ram_addr_t size,
>> + IOMMUTLBEntry *iotlb);
>
>Could the VFIOContainerBase *parameter be const ?

Yes, VFIOContainerBase is not changed by dma_unmap and other
functions dma_unmap calls. I tried and found making it const here
would impact all functions it called with same parameter be const
in following patches which looks unrelated to the patch itself
to avoid compile error.

E.g. below functions are impacted,
vfio_devices_all_running_and_mig_active
vfio_devices_all_device_dirty_tracking
vfio_devices_query_dirty_bitmap
vfio_container_query_dirty_bitmap
vfio_legacy_query_dirty_bitmap

To make following patches cleaner to review, I would like to keep
current code except you or others have a strong opinion.
Another choice I can think of is to 

Re: [PATCH v4 10/13] hw/pci-host/gpex: Define properties for MMIO ranges

[Alistair Francis]

On Thu, Oct 26, 2023 at 6:12 AM Sunil V L  wrote:
>
> ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
> and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
> making these values machine specific, create properties for the GPEX
> host bridge with default value 0. During initialization, the firmware
> can initialize these properties with correct values for the platform.
> This basically allows DSDT generator code independent of the machine
> specific memory map accesses.
>
> Suggested-by: Igor Mammedov 
> Signed-off-by: Sunil V L 

Acked-by: Alistair Francis 

Alistair

> ---
>  hw/pci-host/gpex-acpi.c| 13 +
>  hw/pci-host/gpex.c | 12 
>  include/hw/pci-host/gpex.h | 28 
>  3 files changed, 45 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
> index 1092dc3b70..f69413ea2c 100644
> --- a/hw/pci-host/gpex-acpi.c
> +++ b/hw/pci-host/gpex-acpi.c
> @@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig 
> *cfg)
>
>  crs_range_set_free(_range_set);
>  }
> +
> +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
> +{
> +bool ambig;
> +Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, );
> +
> +if (!obj || ambig) {
> +return;
> +}
> +
> +GPEX_HOST(obj)->gpex_cfg.irq = irq;
> +acpi_dsdt_add_gpex(scope, _HOST(obj)->gpex_cfg);
> +}
> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
> index a6752fac5e..41f4e73f6e 100644
> --- a/hw/pci-host/gpex.c
> +++ b/hw/pci-host/gpex.c
> @@ -154,6 +154,18 @@ static Property gpex_host_properties[] = {
>   */
>  DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
>   allow_unmapped_accesses, true),
> +DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0),
> +DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0),
> +DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0),
> +DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0),
> +DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost,
> +   gpex_cfg.mmio32.base, 0),
> +DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost,
> + gpex_cfg.mmio32.size, 0),
> +DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost,
> +   gpex_cfg.mmio64.base, 0),
> +DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
> + gpex_cfg.mmio64.size, 0),
>  DEFINE_PROP_END_OF_LIST(),
>  };
>
> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
> index b0240bd768..441c6b8b20 100644
> --- a/include/hw/pci-host/gpex.h
> +++ b/include/hw/pci-host/gpex.h
> @@ -40,6 +40,15 @@ struct GPEXRootState {
>  /*< public >*/
>  };
>
> +struct GPEXConfig {
> +MemMapEntry ecam;
> +MemMapEntry mmio32;
> +MemMapEntry mmio64;
> +MemMapEntry pio;
> +int irq;
> +PCIBus  *bus;
> +};
> +
>  struct GPEXHost {
>  /*< private >*/
>  PCIExpressHost parent_obj;
> @@ -55,19 +64,22 @@ struct GPEXHost {
>  int irq_num[GPEX_NUM_IRQS];
>
>  bool allow_unmapped_accesses;
> -};
>
> -struct GPEXConfig {
> -MemMapEntry ecam;
> -MemMapEntry mmio32;
> -MemMapEntry mmio64;
> -MemMapEntry pio;
> -int irq;
> -PCIBus  *bus;
> +struct GPEXConfig gpex_cfg;
>  };
>
>  int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
>
>  void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
> +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);
> +
> +#define PCI_HOST_PIO_BASE   "pio-base"
> +#define PCI_HOST_PIO_SIZE   "pio-size"
> +#define PCI_HOST_ECAM_BASE  "ecam-base"
> +#define PCI_HOST_ECAM_SIZE  "ecam-size"
> +#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base"
> +#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size"
> +#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base"
> +#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size"
>
>  #endif /* HW_GPEX_H */
> --
> 2.39.2
>
>

Re: [PATCH v4 03/13] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT

[Alistair Francis]

On Thu, Oct 26, 2023 at 7:23 AM Sunil V L  wrote:
>
> With common function to add virtio in DSDT created now, update microvm
> code also to use it instead of duplicate code.
>
> Suggested-by: Andrew Jones 
> Signed-off-by: Sunil V L 

Acked-by: Alistair Francis 

Alistair

> ---
>  hw/i386/acpi-microvm.c | 15 ++-
>  1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
> index 2909a73933..279da6b4aa 100644
> --- a/hw/i386/acpi-microvm.c
> +++ b/hw/i386/acpi-microvm.c
> @@ -37,6 +37,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pcie_host.h"
>  #include "hw/usb/xhci.h"
> +#include "hw/virtio/virtio-acpi.h"
>  #include "hw/virtio/virtio-mmio.h"
>  #include "hw/input/i8042.h"
>
> @@ -77,19 +78,7 @@ static void acpi_dsdt_add_virtio(Aml *scope,
>  uint32_t irq = mms->virtio_irq_base + index;
>  hwaddr base = VIRTIO_MMIO_BASE + index * 512;
>  hwaddr size = 512;
> -
> -Aml *dev = aml_device("VR%02u", (unsigned)index);
> -aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> -aml_append(dev, aml_name_decl("_UID", aml_int(index)));
> -aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> -
> -Aml *crs = aml_resource_template();
> -aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> -aml_append(crs,
> -   aml_interrupt(AML_CONSUMER, AML_LEVEL, 
> AML_ACTIVE_HIGH,
> - AML_EXCLUSIVE, , 1));
> -aml_append(dev, aml_name_decl("_CRS", crs));
> -aml_append(scope, dev);
> +virtio_acpi_dsdt_add(scope, base, size, irq, index, 1);
>  }
>  }
>  }
> --
> 2.39.2
>
>

Re: [PATCH 1/1] target/riscv: correct csr_ops[CSR_MSECCFG]

[Alistair Francis]

On Sun, Oct 29, 2023 at 10:47 AM Heinrich Schuchardt
 wrote:
>
> The CSR register mseccfg is used by multiple extensions: Smepm and Zkr.
>
> Consider this when checking the existence of the register.
>
> Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr")
> Signed-off-by: Heinrich Schuchardt 

Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
sending a v2?

Alistair

> ---
>  target/riscv/csr.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4b4ab56c40..07c0cfb7d8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -523,11 +523,14 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
>  {
>  if (riscv_cpu_cfg(env)->epmp) {
>  return RISCV_EXCP_NONE;
>  }
> +if (riscv_cpu_cfg(env)->ext_zkr) {
> +return RISCV_EXCP_NONE;
> +}
>
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
> @@ -4379,7 +4382,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>  [CSR_VSIPH]   = { "vsiph",   aia_hmode32, NULL, NULL, rmw_vsiph 
> },
>
>  /* Physical Memory Protection */
> -[CSR_MSECCFG]= { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
> +[CSR_MSECCFG]= { "mseccfg",   have_mseccfg, read_mseccfg, 
> write_mseccfg,
>   .min_priv_ver = PRIV_VERSION_1_11_0   },
>  [CSR_PMPCFG0]= { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
>  [CSR_PMPCFG1]= { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
> --
> 2.40.1
>
>

Re: [PATCH 1/1] target/riscv: correct csr_ops[CSR_MSECCFG]

[Alistair Francis]

On Sun, Oct 29, 2023 at 10:47 AM Heinrich Schuchardt
 wrote:
>
> The CSR register mseccfg is used by multiple extensions: Smepm and Zkr.
>
> Consider this when checking the existence of the register.
>
> Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr")
> Signed-off-by: Heinrich Schuchardt 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/csr.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4b4ab56c40..07c0cfb7d8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -523,11 +523,14 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
>  {
>  if (riscv_cpu_cfg(env)->epmp) {
>  return RISCV_EXCP_NONE;
>  }
> +if (riscv_cpu_cfg(env)->ext_zkr) {
> +return RISCV_EXCP_NONE;
> +}
>
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
> @@ -4379,7 +4382,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>  [CSR_VSIPH]   = { "vsiph",   aia_hmode32, NULL, NULL, rmw_vsiph 
> },
>
>  /* Physical Memory Protection */
> -[CSR_MSECCFG]= { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
> +[CSR_MSECCFG]= { "mseccfg",   have_mseccfg, read_mseccfg, 
> write_mseccfg,
>   .min_priv_ver = PRIV_VERSION_1_11_0   },
>  [CSR_PMPCFG0]= { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
>  [CSR_PMPCFG1]= { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
> --
> 2.40.1
>
>

Re: [PATCH] MAINTAINERS: Add the can documenation file to the CAN section

[Pavel Pisa]

Hello Thomas and others,

On Friday 27 of October 2023 08:09:31 Thomas Huth wrote:
> Add can.rst to the corresponding section in MAINTAINERS, so that
> the maintainers get CC:-ed on corresponding patches.
>
> Signed-off-by: Thomas Huth 
> ---
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cce6feff35..48d45b958f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2606,6 +2606,7 @@ W: https://canbus.pages.fel.cvut.cz/
>  F: net/can/*
>  F: hw/net/can/*
>  F: include/net/can_*.h
> +F: docs/system/devices/can.rst

Acked-by: Pavel Pisa 

I do not have commit right to the Qemu Git.
Please, Paolo or somebody else commit the patch
into mainline.

Best wishes,

Pavel

-- 
Pavel Pisa
phone:  +420 603531357
e-mail: p...@cmp.felk.cvut.cz
Department of Control Engineering FEE CVUT
Karlovo namesti 13, 121 35, Prague 2
university: http://control.fel.cvut.cz/
personal:   http://cmp.felk.cvut.cz/~pisa
social: https://social.kernel.org/ppisa
projects:   https://www.openhub.net/accounts/ppisa
CAN related:http://canbus.pages.fel.cvut.cz/
RISC-V education: https://comparch.edu.cvut.cz/
Open Technologies Research Education and Exchange Services
https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home

Re: [PULL 00/41] target-arm queue

[Stefan Hajnoczi]

On Fri, 27 Oct 2023 at 23:41, Peter Maydell  wrote:
>
> Hi; here's the latest target-arm queue. Mostly this is refactoring
> and cleanup type patches.
>
> thanks
> -- PMM

Hi Peter,
I can't find this email thread on lore.kernel.org and your git repo
doesn't let me fetch the tag:

  $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20231027
  fatal: couldn't find remote ref tags/pull-target-arm-20231027

cgit shows the tag though, for some reason:
https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027

Any idea what's up with this pull request? Thanks!

Stefan

>
> The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:
>
>   Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into 
> staging (2023-10-27 09:43:53 +0900)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20231027
>
> for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229:
>
>   hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 
> 15:27:06 +0100)
>
> 
> target-arm queue:
>  * Correct minor errors in Cortex-A710 definition
>  * Implement Neoverse N2 CPU model
>  * Refactor feature test functions out into separate header
>  * Fix syndrome for FGT traps on ERET
>  * Remove 'hw/arm/boot.h' includes from various header files
>  * pxa2xx: Refactoring/cleanup
>  * Avoid using 'first_cpu' when first ARM CPU is reachable
>  * misc/led: LED state is set opposite of what is expected
>  * hw/net/cadence_gen: clean up to use FIELD macros
>  * hw/net/cadence_gem: perform PHY access on write only
>  * hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> 
> Glenn Miles (1):
>   misc/led: LED state is set opposite of what is expected
>
> Luc Michel (11):
>   hw/net/cadence_gem: use REG32 macro for register definitions
>   hw/net/cadence_gem: use FIELD for screening registers
>   hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
>   hw/net/cadence_gem: use FIELD to describe NWCFG register fields
>   hw/net/cadence_gem: use FIELD to describe DMACFG register fields
>   hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
>   hw/net/cadence_gem: use FIELD to describe IRQ register fields
>   hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
>   hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
>   hw/net/cadence_gem: perform PHY access on write only
>   hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> Peter Maydell (9):
>   target/arm: Correct minor errors in Cortex-A710 definition
>   target/arm: Implement Neoverse N2 CPU model
>   target/arm: Move feature test functions to their own header
>   target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
>   target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
>   target/arm: Move ID_AA64ISAR* test functions together
>   target/arm: Move ID_AA64PFR* tests together
>   target/arm: Move ID_AA64DFR* feature tests together
>   target/arm: Fix syndrome for FGT traps on ERET
>
> Philippe Mathieu-Daudé (20):
>   hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
>   hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
>   hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
>   hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
>   hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
>   hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
>   hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
>   hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
>   hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
>   hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
>   hw/sd/pxa2xx: Realize sysbus device before accessing it
>   hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
>   hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
>   hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
>   hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
>   hw/intc/pxa2xx: Convert to Resettable interface
>   hw/intc/pxa2xx: Pass CPU reference using QOM link property
>   hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
>   hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
>   hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
>
>  docs/system/arm/virt.rst  |   1 +
>  bsd-user/arm/target_arch.h|   1 +
>  include/hw/arm/allwinner-a10.h|   1 -
>  include/hw/arm/allwinner-h3.h |   1 -
>  include/hw/arm/allwinner-r40.h|   1 -
>  include/hw/arm/fsl-imx25.h|   1 -
>  include/hw/arm/fsl-imx31.h|   1 -
>  include/hw/arm/fsl-imx6.h 

Re: [PATCH v5 11/21] virtio-net: Return an error when vhost cannot enable RSS

[Yuri Benditovich]

On Tue, Oct 17, 2023 at 7:10 AM Akihiko Odaki 
wrote:

> vhost requires eBPF for RSS. Even when eBPF is not available, virtio-net
> reported RSS availability, and raised a warning only after the
> guest requested RSS, and the guest could not know that RSS is not
> available.
>
>
The existing code suggests the RSS feature for vhost case only when the
ebpf is loaded.
https://github.com/qemu/qemu/blob/master/hw/net/virtio-net.c#L828
Am I wrong?



> Check RSS availability during device realization and return an error
> if RSS is requested but not available. Assert RSS availability when
> the guest actually requests the feature.
>
> Signed-off-by: Akihiko Odaki 
> ---
>  ebpf/ebpf_rss.h  |   2 +-
>  ebpf/ebpf_rss-stub.c |   4 +-
>  ebpf/ebpf_rss.c  |  68 +-
>  hw/net/virtio-net.c  | 114 +--
>  4 files changed, 82 insertions(+), 106 deletions(-)
>
> diff --git a/ebpf/ebpf_rss.h b/ebpf/ebpf_rss.h
> index bf3f2572c7..1128173572 100644
> --- a/ebpf/ebpf_rss.h
> +++ b/ebpf/ebpf_rss.h
> @@ -36,7 +36,7 @@ bool ebpf_rss_is_loaded(struct EBPFRSSContext *ctx);
>
>  bool ebpf_rss_load(struct EBPFRSSContext *ctx);
>
> -bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig
> *config,
> +void ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig
> *config,
>uint16_t *indirections_table, uint8_t
> *toeplitz_key);
>
>  void ebpf_rss_unload(struct EBPFRSSContext *ctx);
> diff --git a/ebpf/ebpf_rss-stub.c b/ebpf/ebpf_rss-stub.c
> index e71e229190..525b358597 100644
> --- a/ebpf/ebpf_rss-stub.c
> +++ b/ebpf/ebpf_rss-stub.c
> @@ -28,10 +28,10 @@ bool ebpf_rss_load(struct EBPFRSSContext *ctx)
>  return false;
>  }
>
> -bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig
> *config,
> +void ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig
> *config,
>uint16_t *indirections_table, uint8_t *toeplitz_key)
>  {
> -return false;
> +g_assert_not_reached();
>  }
>
>  void ebpf_rss_unload(struct EBPFRSSContext *ctx)
> diff --git a/ebpf/ebpf_rss.c b/ebpf/ebpf_rss.c
> index cee658c158..6cdf82d059 100644
> --- a/ebpf/ebpf_rss.c
> +++ b/ebpf/ebpf_rss.c
> @@ -74,42 +74,32 @@ error:
>  return false;
>  }
>
> -static bool ebpf_rss_set_config(struct EBPFRSSContext *ctx,
> +static void ebpf_rss_set_config(struct EBPFRSSContext *ctx,
>  struct EBPFRSSConfig *config)
>  {
>  uint32_t map_key = 0;
>
> -if (!ebpf_rss_is_loaded(ctx)) {
> -return false;
> -}
> -if (bpf_map_update_elem(ctx->map_configuration,
> -_key, config, 0) < 0) {
> -return false;
> -}
> -return true;
> +assert(ebpf_rss_is_loaded(ctx));
> +assert(!bpf_map_update_elem(ctx->map_configuration, _key, config,
> 0));
>  }
>
> -static bool ebpf_rss_set_indirections_table(struct EBPFRSSContext *ctx,
> +static void ebpf_rss_set_indirections_table(struct EBPFRSSContext *ctx,
>  uint16_t *indirections_table,
>  size_t len)
>  {
>  uint32_t i = 0;
>
> -if (!ebpf_rss_is_loaded(ctx) || indirections_table == NULL ||
> -   len > VIRTIO_NET_RSS_MAX_TABLE_LEN) {
> -return false;
> -}
> +assert(ebpf_rss_is_loaded(ctx));
> +assert(indirections_table);
> +assert(len <= VIRTIO_NET_RSS_MAX_TABLE_LEN);
>
>  for (; i < len; ++i) {
> -if (bpf_map_update_elem(ctx->map_indirections_table, ,
> -indirections_table + i, 0) < 0) {
> -return false;
> -}
> +assert(!bpf_map_update_elem(ctx->map_indirections_table, ,
> +indirections_table + i, 0));
>  }
> -return true;
>  }
>
> -static bool ebpf_rss_set_toepliz_key(struct EBPFRSSContext *ctx,
> +static void ebpf_rss_set_toepliz_key(struct EBPFRSSContext *ctx,
>   uint8_t *toeplitz_key)
>  {
>  uint32_t map_key = 0;
> @@ -117,41 +107,29 @@ static bool ebpf_rss_set_toepliz_key(struct
> EBPFRSSContext *ctx,
>  /* prepare toeplitz key */
>  uint8_t toe[VIRTIO_NET_RSS_MAX_KEY_SIZE] = {};
>
> -if (!ebpf_rss_is_loaded(ctx) || toeplitz_key == NULL) {
> -return false;
> -}
> +assert(ebpf_rss_is_loaded(ctx));
> +assert(toeplitz_key);
> +
>  memcpy(toe, toeplitz_key, VIRTIO_NET_RSS_MAX_KEY_SIZE);
>  *(uint32_t *)toe = ntohl(*(uint32_t *)toe);
>
> -if (bpf_map_update_elem(ctx->map_toeplitz_key, _key, toe,
> -0) < 0) {
> -return false;
> -}
> -return true;
> +assert(!bpf_map_update_elem(ctx->map_toeplitz_key, _key, toe, 0));
>  }
>
> -bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig
> *config,
> +void ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig
> *config,
>   

Re: [PATCH v5 15/21] virtio-net: Do not clear VIRTIO_NET_F_HASH_REPORT

[Yuri Benditovich]

This patch allows  VIRTIO_NET_F_HASH_REPORT feature to the adapter whose
backend does not have a virtio header and does not have offload features
that depend on it.
The migration between such different systems is very problematic even if it
seems successful, such setups are not performance-oriented and especially
supporting the hash delivery for them is (IMHO) redundant, it just requires
more testing and does not bring any advantage.


On Fri, Oct 27, 2023 at 11:07 AM Akihiko Odaki 
wrote:

> On 2023/10/27 16:14, Jason Wang wrote:
> > On Tue, Oct 17, 2023 at 12:14 PM Akihiko Odaki 
> wrote:
> >>
> >> virtio-net can report hash values even if the peer does not have a
> >> virtio-net header.
> >
> > Do we need a compat flag for this?
>
> I don't think so. This change actually fixes the migration from a system
> with tap devices that support virtio-net headers to a system with tap
> devices that do not support virtio-net headers. Such a compatibility
> flag will revert the fix.
>
> Regards,
> Akihiko Odaki
>

[PATCH] linux-user/elfload: Add missing arm64 hwcap values

[Marielle Novastrider]

Specifically DIT, LSE2, and MTE3.

We already expose detection of these via the CPUID interface, but
missed these from ELF hwcaps.

Signed-off-by: Marielle Novastrider 
---
 linux-user/elfload.c | 3 +++
 target/arm/cpu.h | 5 +
 2 files changed, 8 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 2e3809f03c..d9683809a1 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -768,12 +768,14 @@ uint32_t get_elf_hwcap(void)
 GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
 GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
 GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
+GET_FEATURE_ID(aa64_lse2, ARM_HWCAP_A64_USCAT);
 GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
 GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
 GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
 GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
 GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
 GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
+GET_FEATURE_ID(aa64_dit, ARM_HWCAP_A64_DIT);
 GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
 GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
 GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
@@ -807,6 +809,7 @@ uint32_t get_elf_hwcap2(void)
 GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
 GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
 GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
+GET_FEATURE_ID(aa64_mte3, ARM_HWCAP2_A64_MTE3);
 GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME |
   ARM_HWCAP2_A64_SME_F32F32 |
   ARM_HWCAP2_A64_SME_B16F32 |
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 76d4cef9e3..7605d6ee3a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4073,6 +4073,11 @@ static inline bool isar_feature_aa64_mte(const 
ARMISARegisters *id)
 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
 }
 
+static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 3;
+}
+
 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
 {
 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
-- 
2.39.3 (Apple Git-145)

[PATCH 10/11] tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 11 ++
 include/tcg/tcg-temp-internal.h | 27 +++---
 include/tcg/tcg.h   | 51 --
 tcg/tcg.c   | 64 +++--
 4 files changed, 76 insertions(+), 77 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index dddf93067e..2d932a515e 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -17,6 +17,17 @@ TCGv_i64 tcg_constant_i64(int64_t val);
 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
 
+TCGv_i32 tcg_temp_new_i32(void);
+TCGv_i64 tcg_temp_new_i64(void);
+TCGv_ptr tcg_temp_new_ptr(void);
+TCGv_i128 tcg_temp_new_i128(void);
+TCGv_vec tcg_temp_new_vec(TCGType type);
+TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
+
+TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t off, const char *name);
+TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name);
+TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *name);
+
 /* Generic ops.  */
 
 void gen_set_label(TCGLabel *l);
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index dded2917e5..2d45cc45d2 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -56,28 +56,9 @@ static inline void tcg_temp_free_vec(TCGv_vec arg)
 tcg_temp_free_internal(tcgv_vec_temp(arg));
 }
 
-static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
-return temp_tcgv_i32(t);
-}
-
-static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
-return temp_tcgv_i64(t);
-}
-
-static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
-return temp_tcgv_i128(t);
-}
-
-static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
-return temp_tcgv_ptr(t);
-}
+TCGv_i32 tcg_temp_ebb_new_i32(void);
+TCGv_i64 tcg_temp_ebb_new_i64(void);
+TCGv_ptr tcg_temp_ebb_new_ptr(void);
+TCGv_i128 tcg_temp_ebb_new_i128(void);
 
 #endif /* TCG_TEMP_FREE_H */
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index a5ecab3cb3..45df817e20 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -795,57 +795,6 @@ void tb_target_set_jmp_target(const TranslationBlock *, 
int,
 
 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 
-TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
- intptr_t, const char *);
-TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind);
-TCGv_vec tcg_temp_new_vec(TCGType type);
-TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
-
-static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
-  const char *name)
-{
-TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
-return temp_tcgv_i32(t);
-}
-
-static inline TCGv_i32 tcg_temp_new_i32(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB);
-return temp_tcgv_i32(t);
-}
-
-static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
-  const char *name)
-{
-TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
-return temp_tcgv_i64(t);
-}
-
-static inline TCGv_i64 tcg_temp_new_i64(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB);
-return temp_tcgv_i64(t);
-}
-
-static inline TCGv_i128 tcg_temp_new_i128(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB);
-return temp_tcgv_i128(t);
-}
-
-static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
-  const char *name)
-{
-TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
-return temp_tcgv_ptr(t);
-}
-
-static inline TCGv_ptr tcg_temp_new_ptr(void)
-{
-TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB);
-return temp_tcgv_ptr(t);
-}
-
 void tcg_dump_info(GString *buf);
 void tcg_dump_op_count(GString *buf);
 
diff --git a/tcg/tcg.c b/tcg/tcg.c
index c77b1fd943..29dbb29a0a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1568,8 +1568,8 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t 
start, intptr_t size)
 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
 }
 
-TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
- intptr_t offset, const char *name)
+static TCGTemp *tcg_global_mem_new_internal(TCGv_ptr base, intptr_t offset,
+const char *name, TCGType type)
 {
 TCGContext *s = 

[PATCH 03/11] tcg: Move generic expanders out of line

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 19 +++
 tcg/tcg-op.c| 16 
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index e093f541a7..2134961a98 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -72,12 +72,7 @@ void tcg_gen_op6ii_i64(TCGOpcode, TCGv_i64, TCGv_i64, 
TCGv_i64,
 
 /* Generic ops.  */
 
-static inline void gen_set_label(TCGLabel *l)
-{
-l->present = 1;
-tcg_gen_op1(INDEX_op_set_label, label_arg(l));
-}
-
+void gen_set_label(TCGLabel *l);
 void tcg_gen_br(TCGLabel *l);
 void tcg_gen_mb(TCGBar);
 
@@ -121,16 +116,8 @@ void tcg_gen_goto_tb(unsigned idx);
  */
 void tcg_gen_lookup_and_goto_ptr(void);
 
-static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type,
-   unsigned wr)
-{
-tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr);
-}
-
-static inline void tcg_gen_plugin_cb_end(void)
-{
-tcg_emit_op(INDEX_op_plugin_cb_end, 0);
-}
+void tcg_gen_plugin_cb_start(unsigned from, unsigned type, unsigned wr);
+void tcg_gen_plugin_cb_end(void);
 
 /* 32 bit ops */
 
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 6c826b46b0..a8cbad212d 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -300,6 +300,12 @@ void DNI tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, 
TCGv_i64 a2,
 
 /* Generic ops.  */
 
+void gen_set_label(TCGLabel *l)
+{
+l->present = 1;
+tcg_gen_op1(INDEX_op_set_label, label_arg(l));
+}
+
 static void add_last_as_label_use(TCGLabel *l)
 {
 TCGLabelUse *u = tcg_malloc(sizeof(TCGLabelUse));
@@ -333,6 +339,16 @@ void tcg_gen_mb(TCGBar mb_type)
 }
 }
 
+void tcg_gen_plugin_cb_start(unsigned from, unsigned type, unsigned wr)
+{
+tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr);
+}
+
+void tcg_gen_plugin_cb_end(void)
+{
+tcg_emit_op(INDEX_op_plugin_cb_end, 0);
+}
+
 /* 32 bit ops */
 
 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
-- 
2.34.1

[PATCH 00/11] tcg: Move tcg expanders out of line

[Richard Henderson]

This reduces the amount of code within tcg-op-common.h, and the amount
of code in the code segment full stop.

With many translators these days, we're putting the expander function
addresses into tables, or pass them to other general target-specific
expansion helpers.  At present that means we get out-of-line copies of 
these functions anyway.  If the target is implemented with multiple
translation units, we can get multiple out-of-line copies.

This is also a necessary step in making tcg/arch/tcg-target.h private.

Top few code size reductions:

-89kqemu-system-ppc64
-88kqemu-system-aarch64
-60kqemu-system-mipsel
-50kqemu-system-arm
-42kqemu-system-riscv64
-33kqemu-system-i386
-33kqemu-system-m68k
-32kqemu-system-tricore


r~


Richard Henderson (11):
  tcg: Mark tcg_gen_op* as noinline
  tcg: Move tcg_gen_op* out of line
  tcg: Move generic expanders out of line
  tcg: Move 32-bit expanders out of line
  tcg: Move 64-bit expanders out of line
  tcg: Move vec_gen_* declarations to tcg-internal.h
  tcg: Move tcg_gen_opN declarations to tcg-internal.h
  tcg: Unexport tcg_gen_op*_{i32,i64}
  tcg: Move tcg_constant_* out of line
  tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line
  tcg: Move tcg_temp_free_* out of line

 include/tcg/tcg-op-common.h | 538 +++---
 include/tcg/tcg-temp-internal.h |  56 +---
 include/tcg/tcg.h   |  77 -
 tcg/tcg-internal.h  |  18 +
 tcg/tcg-op.c| 566 +++-
 tcg/tcg.c   | 104 +-
 6 files changed, 664 insertions(+), 695 deletions(-)

-- 
2.34.1

[PATCH 02/11] tcg: Move tcg_gen_op* out of line

[Richard Henderson]

In addition to moving out of line, with CONFIG_DEBUG_TCG
mark them all noinline.

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 252 +++-
 tcg/tcg-op.c| 208 +
 2 files changed, 252 insertions(+), 208 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 677aea6dd1..e093f541a7 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -25,214 +25,50 @@ void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, 
TCGArg);
 void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
 void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
 
-static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
-{
-tcg_gen_op1(opc, tcgv_i32_arg(a1));
-}
-
-static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
-{
-tcg_gen_op1(opc, tcgv_i64_arg(a1));
-}
-
-static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
-{
-tcg_gen_op1(opc, a1);
-}
-
-static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
-{
-tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
-}
-
-static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
-{
-tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
-}
-
-static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
-{
-tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
-}
-
-static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
-{
-tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
-}
-
-static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
-{
-tcg_gen_op2(opc, a1, a2);
-}
-
-static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
-   TCGv_i32 a2, TCGv_i32 a3)
-{
-tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
-}
-
-static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
-   TCGv_i64 a2, TCGv_i64 a3)
-{
-tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
-}
-
-static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
-TCGv_i32 a2, TCGArg a3)
-{
-tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
-}
-
-static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
-TCGv_i64 a2, TCGArg a3)
-{
-tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
-}
-
-static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
-   TCGv_ptr base, TCGArg offset)
-{
-tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
-}
-
-static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
-   TCGv_ptr base, TCGArg offset)
-{
-tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
-}
-
-static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
-   TCGv_i32 a3, TCGv_i32 a4)
-{
-tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
-tcgv_i32_arg(a3), tcgv_i32_arg(a4));
-}
-
-static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
-   TCGv_i64 a3, TCGv_i64 a4)
-{
-tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
-tcgv_i64_arg(a3), tcgv_i64_arg(a4));
-}
-
-static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
-TCGv_i32 a3, TCGArg a4)
-{
-tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
-tcgv_i32_arg(a3), a4);
-}
-
-static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
-TCGv_i64 a3, TCGArg a4)
-{
-tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
-tcgv_i64_arg(a3), a4);
-}
-
-static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGArg a3, TCGArg a4)
-{
-tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
-}
-
-static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGArg a3, TCGArg a4)
-{
-tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
-}
-
-static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
-   TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
-{
-tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
-tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
-}
-
-static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
-   TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
-{
-tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
-tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
-}
-
-static inline void 

[PATCH 07/11] tcg: Move tcg_gen_opN declarations to tcg-internal.h

[Richard Henderson]

These are used within tcg-op.c and tcg-op-ldst.c.
There are no uses outside tcg/.

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 7 ---
 tcg/tcg-internal.h  | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 3f8b214376..b922545118 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -14,13 +14,6 @@
 
 /* Basic output routines.  Not for general consumption.  */
 
-void tcg_gen_op1(TCGOpcode, TCGArg);
-void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
-void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
-
 void tcg_gen_op1_i32(TCGOpcode, TCGv_i32);
 void tcg_gen_op1_i64(TCGOpcode, TCGv_i64);
 void tcg_gen_op1i(TCGOpcode, TCGArg);
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
index f18d282abb..c9ac34fc3d 100644
--- a/tcg/tcg-internal.h
+++ b/tcg/tcg-internal.h
@@ -83,6 +83,13 @@ static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t)
 
 bool tcg_target_has_memory_bswap(MemOp memop);
 
+void tcg_gen_op1(TCGOpcode, TCGArg);
+void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
+void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+
 void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
 void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
 void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
-- 
2.34.1

[PATCH 06/11] tcg: Move vec_gen_* declarations to tcg-internal.h

[Richard Henderson]

These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc.
There are no uses outside tcg/.

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 4 
 tcg/tcg-internal.h  | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index f5ec54f874..3f8b214376 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -21,10 +21,6 @@ void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
 void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
 void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
 
-void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
-void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
-void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
-
 void tcg_gen_op1_i32(TCGOpcode, TCGv_i32);
 void tcg_gen_op1_i64(TCGOpcode, TCGv_i64);
 void tcg_gen_op1i(TCGOpcode, TCGArg);
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
index 40a69e6e6e..f18d282abb 100644
--- a/tcg/tcg-internal.h
+++ b/tcg/tcg-internal.h
@@ -83,4 +83,8 @@ static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t)
 
 bool tcg_target_has_memory_bswap(MemOp memop);
 
+void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
+void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
+void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
+
 #endif /* TCG_INTERNAL_H */
-- 
2.34.1

[PATCH 11/11] tcg: Move tcg_temp_free_* out of line

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-temp-internal.h | 29 +
 tcg/tcg.c   | 25 +
 2 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index 2d45cc45d2..44192c55a9 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -31,30 +31,11 @@
 
 void tcg_temp_free_internal(TCGTemp *);
 
-static inline void tcg_temp_free_i32(TCGv_i32 arg)
-{
-tcg_temp_free_internal(tcgv_i32_temp(arg));
-}
-
-static inline void tcg_temp_free_i64(TCGv_i64 arg)
-{
-tcg_temp_free_internal(tcgv_i64_temp(arg));
-}
-
-static inline void tcg_temp_free_i128(TCGv_i128 arg)
-{
-tcg_temp_free_internal(tcgv_i128_temp(arg));
-}
-
-static inline void tcg_temp_free_ptr(TCGv_ptr arg)
-{
-tcg_temp_free_internal(tcgv_ptr_temp(arg));
-}
-
-static inline void tcg_temp_free_vec(TCGv_vec arg)
-{
-tcg_temp_free_internal(tcgv_vec_temp(arg));
-}
+void tcg_temp_free_i32(TCGv_i32 arg);
+void tcg_temp_free_i64(TCGv_i64 arg);
+void tcg_temp_free_i128(TCGv_i128 arg);
+void tcg_temp_free_ptr(TCGv_ptr arg);
+void tcg_temp_free_vec(TCGv_vec arg);
 
 TCGv_i32 tcg_temp_ebb_new_i32(void);
 TCGv_i64 tcg_temp_ebb_new_i64(void);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 29dbb29a0a..4ab6a35398 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1805,6 +1805,31 @@ void tcg_temp_free_internal(TCGTemp *ts)
 }
 }
 
+void tcg_temp_free_i32(TCGv_i32 arg)
+{
+tcg_temp_free_internal(tcgv_i32_temp(arg));
+}
+
+void tcg_temp_free_i64(TCGv_i64 arg)
+{
+tcg_temp_free_internal(tcgv_i64_temp(arg));
+}
+
+void tcg_temp_free_i128(TCGv_i128 arg)
+{
+tcg_temp_free_internal(tcgv_i128_temp(arg));
+}
+
+void tcg_temp_free_ptr(TCGv_ptr arg)
+{
+tcg_temp_free_internal(tcgv_ptr_temp(arg));
+}
+
+void tcg_temp_free_vec(TCGv_vec arg)
+{
+tcg_temp_free_internal(tcgv_vec_temp(arg));
+}
+
 TCGTemp *tcg_constant_internal(TCGType type, int64_t val)
 {
 TCGContext *s = tcg_ctx;
-- 
2.34.1

[PATCH 04/11] tcg: Move 32-bit expanders out of line

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 140 ++--
 tcg/tcg-op.c| 116 ++
 2 files changed, 137 insertions(+), 119 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 2134961a98..cdaa1415d1 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -197,128 +197,30 @@ void tcg_gen_abs_i32(TCGv_i32, TCGv_i32);
 /* Replicate a value of size @vece from @in to all the lanes in @out */
 void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in);
 
-static inline void tcg_gen_discard_i32(TCGv_i32 arg)
-{
-tcg_gen_op1_i32(INDEX_op_discard, arg);
-}
+void tcg_gen_discard_i32(TCGv_i32 arg);
+void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg);
 
-static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
-{
-if (ret != arg) {
-tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
-}
-}
+void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset);
+void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset);
+void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset);
+void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset);
+void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset);
 
-static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
-}
+void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
+void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
+void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
 
-static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
-  tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
-   tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
-  tcg_target_long offset)
-{
-tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
-tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
-{
-if (TCG_TARGET_HAS_neg_i32) {
-tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
-} else {
-tcg_gen_subfi_i32(ret, 0, arg);
-}
-}
-
-static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
-{
-if (TCG_TARGET_HAS_not_i32) {
-tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
-} else {
-tcg_gen_xori_i32(ret, arg, -1);
-}
-}
+void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
+void 

[PATCH 05/11] tcg: Move 64-bit expanders out of line

[Richard Henderson]

This one is more complicated, combining 32-bit and 64-bit
expansion with C if instead of preprocessor #if.

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h | 144 +-
 tcg/tcg-op.c| 231 +---
 2 files changed, 169 insertions(+), 206 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index cdaa1415d1..f5ec54f874 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -305,130 +305,6 @@ void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
 /* Replicate a value of size @vece from @in to all the lanes in @out */
 void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in);
 
-#if TCG_TARGET_REG_BITS == 64
-static inline void tcg_gen_discard_i64(TCGv_i64 arg)
-{
-tcg_gen_op1_i64(INDEX_op_discard, arg);
-}
-
-static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
-{
-if (ret != arg) {
-tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
-}
-}
-
-static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
-  tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
-   tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
-tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
-  tcg_target_long offset)
-{
-tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
-tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
-}
-#else /* TCG_TARGET_REG_BITS == 32 */
 void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
 void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
 void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
@@ -453,16 +329,8 @@ void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 
arg2);
 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
 void 

[PATCH 09/11] tcg: Move tcg_constant_* out of line

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h |  8 
 include/tcg/tcg.h   | 26 --
 tcg/tcg-internal.h  |  7 +++
 tcg/tcg.c   | 15 +++
 4 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 760c67683b..dddf93067e 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -12,6 +12,11 @@
 #include "exec/helper-proto-common.h"
 #include "exec/helper-gen-common.h"
 
+TCGv_i32 tcg_constant_i32(int32_t val);
+TCGv_i64 tcg_constant_i64(int64_t val);
+TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
+TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
+
 /* Generic ops.  */
 
 void gen_set_label(TCGLabel *l);
@@ -459,6 +464,9 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg 
offset, TCGType t);
 # define NAT  TCGv_i64
 #endif
 
+TCGv_ptr tcg_constant_ptr_int(intptr_t x);
+#define tcg_constant_ptr(X)  tcg_constant_ptr_int((intptr_t)(X))
+
 static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
 {
 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index a9282cdcc6..a5ecab3cb3 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -937,32 +937,6 @@ void tcg_remove_ops_after(TCGOp *op);
 
 void tcg_optimize(TCGContext *s);
 
-/*
- * Locate or create a read-only temporary that is a constant.
- * This kind of temporary need not be freed, but for convenience
- * will be silently ignored by tcg_temp_free_*.
- */
-TCGTemp *tcg_constant_internal(TCGType type, int64_t val);
-
-static inline TCGv_i32 tcg_constant_i32(int32_t val)
-{
-return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val));
-}
-
-static inline TCGv_i64 tcg_constant_i64(int64_t val)
-{
-return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val));
-}
-
-TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
-TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
-
-#if UINTPTR_MAX == UINT32_MAX
-# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
-#else
-# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
-#endif
-
 TCGLabel *gen_new_label(void);
 
 /**
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
index c9ac34fc3d..6c9d9e48db 100644
--- a/tcg/tcg-internal.h
+++ b/tcg/tcg-internal.h
@@ -83,6 +83,13 @@ static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t)
 
 bool tcg_target_has_memory_bswap(MemOp memop);
 
+/*
+ * Locate or create a read-only temporary that is a constant.
+ * This kind of temporary need not be freed, but for convenience
+ * will be silently ignored by tcg_temp_free_*.
+ */
+TCGTemp *tcg_constant_internal(TCGType type, int64_t val);
+
 void tcg_gen_op1(TCGOpcode, TCGArg);
 void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
 void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 58b431b579..c77b1fd943 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1802,6 +1802,21 @@ TCGTemp *tcg_constant_internal(TCGType type, int64_t val)
 return ts;
 }
 
+TCGv_i32 tcg_constant_i32(int32_t val)
+{
+return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val));
+}
+
+TCGv_i64 tcg_constant_i64(int64_t val)
+{
+return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val));
+}
+
+TCGv_ptr tcg_constant_ptr_int(intptr_t val)
+{
+return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR, val));
+}
+
 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val)
 {
 val = dup_const(vece, val);
-- 
2.34.1

[PATCH 08/11] tcg: Unexport tcg_gen_op*_{i32,i64}

[Richard Henderson]

These functions are no longer used outside tcg-op.c.
There are several that are completely unused, so remove them.

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-op-common.h |  47 -
 tcg/tcg-op.c| 131 ++--
 2 files changed, 52 insertions(+), 126 deletions(-)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index b922545118..760c67683b 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -12,53 +12,6 @@
 #include "exec/helper-proto-common.h"
 #include "exec/helper-gen-common.h"
 
-/* Basic output routines.  Not for general consumption.  */
-
-void tcg_gen_op1_i32(TCGOpcode, TCGv_i32);
-void tcg_gen_op1_i64(TCGOpcode, TCGv_i64);
-void tcg_gen_op1i(TCGOpcode, TCGArg);
-void tcg_gen_op2_i32(TCGOpcode, TCGv_i32, TCGv_i32);
-void tcg_gen_op2_i64(TCGOpcode, TCGv_i64, TCGv_i64);
-void tcg_gen_op2i_i32(TCGOpcode, TCGv_i32, TCGArg);
-void tcg_gen_op2i_i64(TCGOpcode, TCGv_i64, TCGArg);
-void tcg_gen_op2ii(TCGOpcode, TCGArg, TCGArg);
-void tcg_gen_op3_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32);
-void tcg_gen_op3_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64);
-void tcg_gen_op3i_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGArg);
-void tcg_gen_op3i_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGArg);
-void tcg_gen_ldst_op_i32(TCGOpcode, TCGv_i32, TCGv_ptr, TCGArg);
-void tcg_gen_ldst_op_i64(TCGOpcode, TCGv_i64, TCGv_ptr, TCGArg);
-void tcg_gen_op4_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
-void tcg_gen_op4_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
-void tcg_gen_op4i_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32, TCGArg);
-void tcg_gen_op4i_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64, TCGArg);
-void tcg_gen_op4ii_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGArg, TCGArg);
-void tcg_gen_op4ii_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGArg, TCGArg);
-void tcg_gen_op5_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32,
- TCGv_i32, TCGv_i32);
-void tcg_gen_op5_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64,
- TCGv_i64, TCGv_i64);
-void tcg_gen_op5i_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32,
-  TCGv_i32, TCGArg);
-void tcg_gen_op5i_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64,
-  TCGv_i64, TCGArg);
-void tcg_gen_op5ii_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32,
-   TCGArg, TCGArg);
-void tcg_gen_op5ii_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64,
-   TCGArg, TCGArg);
-void tcg_gen_op6_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32,
- TCGv_i32, TCGv_i32, TCGv_i32);
-void tcg_gen_op6_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64,
- TCGv_i64, TCGv_i64, TCGv_i64);
-void tcg_gen_op6i_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32,
-  TCGv_i32, TCGv_i32, TCGArg);
-void tcg_gen_op6i_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64,
-  TCGv_i64, TCGv_i64, TCGArg);
-void tcg_gen_op6ii_i32(TCGOpcode, TCGv_i32, TCGv_i32, TCGv_i32,
-   TCGv_i32, TCGArg, TCGArg);
-void tcg_gen_op6ii_i64(TCGOpcode, TCGv_i64, TCGv_i64, TCGv_i64,
-   TCGv_i64, TCGArg, TCGArg);
-
 /* Generic ops.  */
 
 void gen_set_label(TCGLabel *l);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 579a2aab15..9aba103590 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -100,204 +100,177 @@ void NI tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg 
a2, TCGArg a3,
 # define DNI
 #endif
 
-void DNI tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
+static void DNI tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
 {
 tcg_gen_op1(opc, tcgv_i32_arg(a1));
 }
 
-void DNI tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
+static void DNI tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
 {
 tcg_gen_op1(opc, tcgv_i64_arg(a1));
 }
 
-void DNI tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
+static void DNI tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
 {
 tcg_gen_op1(opc, a1);
 }
 
-void DNI tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
+static void DNI tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
 {
 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
 }
 
-void DNI tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
+static void DNI tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
 {
 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
 }
 
-void DNI tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
-{
-tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
-}
-
-void DNI tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
-{
-tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
-}
-
-void DNI tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
-{
-tcg_gen_op2(opc, a1, a2);
-}
-
-void DNI tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3)
+static void DNI tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
+TCGv_i32 a2, TCGv_i32 a3)
 {
 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 

[PATCH 01/11] tcg: Mark tcg_gen_op* as noinline

[Richard Henderson]

Encourage the compiler to tail-call rather than inline
across the dozens of opcode expanders.

Signed-off-by: Richard Henderson 
---
 tcg/tcg-op.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 828eb9ee46..9aed19e957 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -31,20 +31,26 @@
 #include "tcg-internal.h"
 
 
-void tcg_gen_op1(TCGOpcode opc, TCGArg a1)
+/*
+ * Encourage the compiler to tail-call to a function, rather than inlining.
+ * Minimizes code size across 99 bottles of beer on the wall.
+ */
+#define NI  __attribute__((noinline))
+
+void NI tcg_gen_op1(TCGOpcode opc, TCGArg a1)
 {
 TCGOp *op = tcg_emit_op(opc, 1);
 op->args[0] = a1;
 }
 
-void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
+void NI tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
 {
 TCGOp *op = tcg_emit_op(opc, 2);
 op->args[0] = a1;
 op->args[1] = a2;
 }
 
-void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
+void NI tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
 {
 TCGOp *op = tcg_emit_op(opc, 3);
 op->args[0] = a1;
@@ -52,7 +58,7 @@ void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg 
a3)
 op->args[2] = a3;
 }
 
-void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
+void NI tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
 {
 TCGOp *op = tcg_emit_op(opc, 4);
 op->args[0] = a1;
@@ -61,8 +67,8 @@ void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg 
a3, TCGArg a4)
 op->args[3] = a4;
 }
 
-void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
- TCGArg a4, TCGArg a5)
+void NI tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
+ TCGArg a4, TCGArg a5)
 {
 TCGOp *op = tcg_emit_op(opc, 5);
 op->args[0] = a1;
@@ -72,8 +78,8 @@ void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg 
a3,
 op->args[4] = a5;
 }
 
-void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
- TCGArg a4, TCGArg a5, TCGArg a6)
+void NI tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
+ TCGArg a4, TCGArg a5, TCGArg a6)
 {
 TCGOp *op = tcg_emit_op(opc, 6);
 op->args[0] = a1;
-- 
2.34.1

qemu-system-i386

[Joachim Roden]

<<< text/html; charset=UTF-8: Unrecognized >>>

Re: [PATCH v2 14/19] tests/docker: use debian-all-test-cross for sparc64

[Richard Henderson]

On 10/29/23 07:50, Alex Bennée wrote:

Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on gitlab.

Signed-off-by: Alex Bennée 
Message-Id: <20231028103311.347104-13-alex.ben...@linaro.org>

---
v2
   - s/debian-test-cross/debian-all-test-cross/
---
  configure |  4 
  .gitlab-ci.d/container-cross.yml  |  6 --
  tests/docker/Makefile.include |  1 -
  .../dockerfiles/debian-sparc64-cross.docker   | 19 ---
  4 files changed, 4 insertions(+), 26 deletions(-)
  delete mode 100644 tests/docker/dockerfiles/debian-sparc64-cross.docker


Reviewed-by: Richard Henderson 


r~

Re: [PATCH v2 07/19] tests/docker: move sh4 to use debian-legacy-test-cross

[Richard Henderson]

On 10/29/23 07:50, Alex Bennée wrote:

diff --git a/tests/docker/dockerfiles/debian-all-test-cross.docker 
b/tests/docker/dockerfiles/debian-all-test-cross.docker
index 205173b0a5..43cc083318 100644
--- a/tests/docker/dockerfiles/debian-all-test-cross.docker
+++ b/tests/docker/dockerfiles/debian-all-test-cross.docker
@@ -52,8 +52,6 @@ RUN DEBIAN_FRONTEND=noninteractive eatmydata \
  libc6-dev-riscv64-cross \
  gcc-s390x-linux-gnu \
  libc6-dev-s390x-cross \
-gcc-sh4-linux-gnu \
-libc6-dev-sh4-cross \


compiler removed here...


diff --git a/tests/docker/dockerfiles/debian-legacy-test-cross.docker 
b/tests/docker/dockerfiles/debian-legacy-test-cross.docker
index 763d36dfe3..d9b37995a2 100644
--- a/tests/docker/dockerfiles/debian-legacy-test-cross.docker
+++ b/tests/docker/dockerfiles/debian-legacy-test-cross.docker
@@ -4,6 +4,7 @@
  # upgrade. Currently:
  #
  #   libc6.1-dev-alpha-cross: 
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1054412
+#   sh4-linux-user: binaries don't run with bookworm compiler
  #
  # As we are targeting check-tcg here we only need minimal qemu
  # dependencies and the relevant cross compilers.
@@ -38,7 +39,7 @@ RUN DEBIAN_FRONTEND=noninteractive eatmydata \
  RUN /usr/bin/pip3 install tomli
  
  ENV QEMU_CONFIGURE_OPTS --disable-system --disable-docs --disable-tools

-ENV DEF_TARGET_LIST alpha-linux-user
+ENV DEF_TARGET_LIST alpha-linux-user,sh4-linux-user


... but not added here.


r~

Re: [PATCH v3 3/3] hw/ppc: Nest1 chiplet wiring

[Cédric Le Goater]

On 10/28/23 13:30, Chalapathi V wrote:

This part of the patchset connects the nest1 chiplet model to p10 chip.

Signed-off-by: Chalapathi V 



Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
  hw/ppc/pnv.c  | 11 +++
  include/hw/ppc/pnv_chip.h |  2 ++
  2 files changed, 13 insertions(+)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index eb54f93986..a5abaf5608 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1660,6 +1660,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
  object_initialize_child(obj, "occ",  >occ, TYPE_PNV10_OCC);
  object_initialize_child(obj, "sbe",  >sbe, TYPE_PNV10_SBE);
  object_initialize_child(obj, "homer", >homer, TYPE_PNV10_HOMER);
+object_initialize_child(obj, "nest1_chiplet", >nest1_chiplet,
+TYPE_PNV_NEST1_CHIPLET);
  
  chip->num_pecs = pcc->num_pecs;
  
@@ -1829,6 +1831,15 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)

  memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
  >homer.regs);
  
+/* nest1 chiplet control regs */

+object_property_set_link(OBJECT(>nest1_chiplet), "chip",
+ OBJECT(chip), _abort);
+if (!qdev_realize(DEVICE(>nest1_chiplet), NULL, errp)) {
+return;
+}
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE,
+   
>nest1_chiplet.perv_chiplet.xscom_perv_ctrl_regs);
+
  /* PHBs */
  pnv_chip_power10_phb_realize(chip, _err);
  if (local_err) {
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 53e1d921d7..4bcb92595a 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -4,6 +4,7 @@
  #include "hw/pci-host/pnv_phb4.h"
  #include "hw/ppc/pnv_core.h"
  #include "hw/ppc/pnv_homer.h"
+#include "hw/ppc/pnv_nest_chiplet.h"
  #include "hw/ppc/pnv_lpc.h"
  #include "hw/ppc/pnv_occ.h"
  #include "hw/ppc/pnv_psi.h"
@@ -109,6 +110,7 @@ struct Pnv10Chip {
  PnvOCC   occ;
  PnvSBE   sbe;
  PnvHomer homer;
+PnvNest1Chiplet nest1_chiplet;
  
  uint32_t nr_quads;

  PnvQuad  *quads;

Re: [PATCH v3 2/3] hw/ppc: Add nest1 chiplet model

[Cédric Le Goater]

On 10/28/23 13:30, Chalapathi V wrote:

The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.

This commit creates a nest1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet control registers are implemented.

Signed-off-by: Chalapathi V 
---
  hw/ppc/meson.build|   1 +
  hw/ppc/pnv_nest1_chiplet.c| 104 ++
  include/hw/ppc/pnv_nest_chiplet.h |  39 +++
  3 files changed, 144 insertions(+)
  create mode 100644 hw/ppc/pnv_nest1_chiplet.c
  create mode 100644 include/hw/ppc/pnv_nest_chiplet.h

diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index c80d2f6cfb..4e45e5c1a7 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_homer.c',
'pnv_pnor.c',
'pnv_pervasive.c',
+  'pnv_nest1_chiplet.c',
  ))
  # PowerPC 4xx boards
  ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
diff --git a/hw/ppc/pnv_nest1_chiplet.c b/hw/ppc/pnv_nest1_chiplet.c
new file mode 100644
index 00..160e2ba4cb
--- /dev/null
+++ b/hw/ppc/pnv_nest1_chiplet.c
@@ -0,0 +1,104 @@
+/*
+ * QEMU PowerPC nest1 chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_nest_chiplet.h"
+#include "hw/ppc/pnv_pervasive.h"
+#include "hw/ppc/fdt.h"
+#include 
+
+/*
+ * The nest1 chiplet contains chiplet control unit,
+ * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU)
+ * and more.
+ */
+
+static void pnv_nest1_chiplet_realize(DeviceState *dev, Error **errp)
+{
+PnvNest1Chiplet *nest1_chiplet = PNV_NEST1CHIPLET(dev);
+
+assert(nest1_chiplet->chip);
+
+object_initialize_child(OBJECT(nest1_chiplet), "perv_chiplet",
+_chiplet->perv_chiplet,
+TYPE_PNV_PERV_CHIPLET);
+
+if (!qdev_realize(DEVICE(_chiplet->perv_chiplet), NULL, errp)) {
+return;
+}
+}
+
+static int pnv_nest1_chiplet_dt_xscom(PnvXScomInterface *dev, void *fdt,
+ int offset)
+{
+char *name;
+int nest1_chiplet_offset;
+const char compat[] = "ibm,power10-nest1-chiplet";
+
+name = g_strdup_printf("nest1_chiplet@%x",
+   PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE);
+nest1_chiplet_offset = fdt_add_subnode(fdt, offset, name);
+_FDT(nest1_chiplet_offset);
+g_free(name);
+
+_FDT(fdt_setprop(fdt, nest1_chiplet_offset, "compatible",
+compat, sizeof(compat)));
+return 0;
+}
+
+static Property pnv_nest1_chiplet_properties[] = {
+DEFINE_PROP_LINK("chip", PnvNest1Chiplet, chip, TYPE_PNV_CHIP, PnvChip *),


Where is chip being used ?

Thanks,

C.


+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_nest1_chiplet_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass);
+
+xscomc->dt_xscom = pnv_nest1_chiplet_dt_xscom;
+
+dc->desc = "PowerNV nest1 chiplet";
+dc->realize = pnv_nest1_chiplet_realize;
+device_class_set_props(dc, pnv_nest1_chiplet_properties);
+}
+
+static const TypeInfo pnv_nest1_chiplet_info = {
+.name  = TYPE_PNV_NEST1_CHIPLET,
+.parent= TYPE_DEVICE,
+.instance_size = sizeof(PnvNest1Chiplet),
+.class_init= pnv_nest1_chiplet_class_init,
+.interfaces= (InterfaceInfo[]) {
+{ TYPE_PNV_XSCOM_INTERFACE },
+{ }
+}
+};
+
+static void pnv_nest1_chiplet_register_types(void)
+{
+type_register_static(_nest1_chiplet_info);
+}
+
+type_init(pnv_nest1_chiplet_register_types);
diff --git a/include/hw/ppc/pnv_nest_chiplet.h 
b/include/hw/ppc/pnv_nest_chiplet.h
new file mode 100644
index 00..b2ffe128bd
--- /dev/null
+++ b/include/hw/ppc/pnv_nest_chiplet.h
@@ -0,0 +1,39 @@
+/*
+ * QEMU PowerPC nest chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * This library is free software; you can 

Re: [PATCH v3 1/3] hw/ppc: Add pnv pervasive common chiplet units

[Cédric Le Goater]

On 10/28/23 13:30, Chalapathi V wrote:

This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.

The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.

Signed-off-by: Chalapathi V 
---
  hw/ppc/meson.build |   1 +
  hw/ppc/pnv_pervasive.c | 237 +
  include/hw/ppc/pnv_pervasive.h |  47 +++
  include/hw/ppc/pnv_xscom.h |   3 +
  4 files changed, 288 insertions(+)
  create mode 100644 hw/ppc/pnv_pervasive.c
  create mode 100644 include/hw/ppc/pnv_pervasive.h

diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 7c2c52434a..c80d2f6cfb 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -50,6 +50,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_bmc.c',
'pnv_homer.c',
'pnv_pnor.c',
+  'pnv_pervasive.c',
  ))
  # PowerPC 4xx boards
  ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
diff --git a/hw/ppc/pnv_pervasive.c b/hw/ppc/pnv_pervasive.c
new file mode 100644
index 00..794978756c
--- /dev/null
+++ b/hw/ppc/pnv_pervasive.c
@@ -0,0 +1,237 @@
+/*
+ * QEMU PowerPC pervasive common chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .



You could reduce the header. Look for a short version in QEMU code base.


+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_pervasive.h"
+#include "hw/ppc/fdt.h"
+#include 
+
+#define CPLT_CONF0   0x08
+#define CPLT_CONF0_OR0x18
+#define CPLT_CONF0_CLEAR 0x28
+#define CPLT_CONF1   0x09
+#define CPLT_CONF1_OR0x19
+#define CPLT_CONF1_CLEAR 0x29
+#define CPLT_STAT0   0x100
+#define CPLT_MASK0   0x101
+#define CPLT_PROTECT_MODE0x3FE
+#define CPLT_ATOMIC_CLOCK0x3FF
+
+static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+PnvPervChiplet *perv_chiplet = PNV_PERVCHIPLET(opaque);
+int reg = addr >> 3;
+uint64_t val = 0xull;


or ~0ull


+
+/* CPLT_CTRL0 to CPLT_CTRL5 */
+for (int i = 0; i <= 5; i++) {
+if (reg == i) {
+val = perv_chiplet->control_regs.cplt_ctrl[i];
+return val;
+} else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) {
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+   "xscom read at 0x%016lx\n",


This message should be formatted with PRIx64 instead


+  __func__, (unsigned long)reg);
+return val;
+}
+}
+
+switch (reg) {
+case CPLT_CONF0:
+val = perv_chiplet->control_regs.cplt_cfg0;
+break;
+case CPLT_CONF0_OR:
+case CPLT_CONF0_CLEAR:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+   "xscom read at 0x%016lx\n",
+   __func__, (unsigned long)reg);
+break;
+case CPLT_CONF1:
+val = perv_chiplet->control_regs.cplt_cfg1;
+break;
+case CPLT_CONF1_OR:
+case CPLT_CONF1_CLEAR:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+   "xscom read at 0x%016lx\n",
+   __func__, (unsigned long)reg);
+break;
+case CPLT_STAT0:
+val = perv_chiplet->control_regs.cplt_stat0;
+break;
+case CPLT_MASK0:
+val = perv_chiplet->control_regs.cplt_mask0;
+break;
+case CPLT_PROTECT_MODE:
+val = perv_chiplet->control_regs.ctrl_protect_mode;
+break;
+case CPLT_ATOMIC_CLOCK:
+val = perv_chiplet->control_regs.ctrl_atomic_lock;
+break;
+default:
+qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
+ "read at 0x%016lx\n", __func__, (unsigned long)reg);
+}
+return val;
+}
+
+static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr,
+ 

Re: [PATCH v2 05/19] gitlab: add build-loongarch to matrix

[Richard Henderson]

On 10/29/23 07:50, Alex Bennée wrote:

We have the compiler and with a few updates a container that can build
QEMU so we should at least run the check-tcg smoke tests.

Signed-off-by: Alex Bennée 
---
  .gitlab-ci.d/buildtest.yml|  9 
  .gitlab-ci.d/container-cross.yml  |  6 +
  tests/docker/Makefile.include |  1 -
  .../dockerfiles/debian-loongarch-cross.docker | 22 ++-
  4 files changed, 36 insertions(+), 2 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 04/19] gitlab: clean-up build-soft-softmmu job

[Richard Henderson]

On 10/29/23 07:50, Alex Bennée wrote:

Having dropped alpha we also now drop xtensa as we don't have the
compiler in this image. It's not all doom and gloom though as a number
of other targets have gained softmmu TCG tests so we can add them. We
will take care of the other targets with their own containers in
future commits.

Signed-off-by: Alex Bennée 
---
  .gitlab-ci.d/buildtest.yml | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 03/19] gitlab: split alpha testing into a legacy container

[Richard Henderson]

On 10/29/23 07:50, Alex Bennée wrote:

The current bookworm compiler doesn't build the static binaries due to
bug #1054412 and it might be awhile before it gets fixed. The problem
of keeping older architecture compilers running isn't going to go away
so lets prepare the ground. Create a legacy container and move some
tests around so the others can get upgraded.

Signed-off-by: Alex Bennée 
Message-Id: <20231028103311.347104-4-alex.ben...@linaro.org>

---
v2
   - split other softmmu patches into a new patch
---
  .gitlab-ci.d/buildtest.yml| 19 ++--
  .gitlab-ci.d/container-cross.yml  |  6 +++
  .../dockerfiles/debian-all-test-cross.docker  |  4 +-
  .../debian-legacy-test-cross.docker   | 46 +++
  4 files changed, 69 insertions(+), 6 deletions(-)
  create mode 100644 tests/docker/dockerfiles/debian-legacy-test-cross.docker


Reviewed-by: Richard Henderson 


r~

[PATCH v2 18/19] plugins: Remove an extra parameter

[Alex Bennée]

From: Akihiko Odaki 

copy_call() has an unused parameter so remove it.

Signed-off-by: Akihiko Odaki 
Message-Id: <20231019101030.128431-7-akihiko.od...@daynix.com>
Reviewed-by: Richard Henderson 
Message-Id: <20231028103311.347104-17-alex.ben...@linaro.org>
---
 accel/tcg/plugin-gen.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 39b3c9351f..78b331b251 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -327,8 +327,7 @@ static TCGOp *copy_st_ptr(TCGOp **begin_op, TCGOp *op)
 return op;
 }
 
-static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func,
-void *func, int *cb_idx)
+static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *func, int *cb_idx)
 {
 TCGOp *old_op;
 int func_idx;
@@ -372,8 +371,7 @@ static TCGOp *append_udata_cb(const struct 
qemu_plugin_dyn_cb *cb,
 }
 
 /* call */
-op = copy_call(_op, op, HELPER(plugin_vcpu_udata_cb),
-   cb->f.vcpu_udata, cb_idx);
+op = copy_call(_op, op, cb->f.vcpu_udata, cb_idx);
 
 return op;
 }
@@ -420,8 +418,7 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb 
*cb,
 
 if (type == PLUGIN_GEN_CB_MEM) {
 /* call */
-op = copy_call(_op, op, HELPER(plugin_vcpu_mem_cb),
-   cb->f.vcpu_udata, cb_idx);
+op = copy_call(_op, op, cb->f.vcpu_udata, cb_idx);
 }
 
 return op;
-- 
2.39.2

[PATCH v2 19/19] contrib/plugins: Close file descriptor on error return

[Alex Bennée]

From: Cong Liu 

This patch closes the file descriptor fd on error return to avoid
resource leak.

Fixes: ec7ee95db909 ("contrib/plugins: fix coverity warning in lockstep")
Signed-off-by: Cong Liu 
Message-Id: <20231018025225.1640122-1-liuco...@kylinos.cn>
Signed-off-by: Alex Bennée 
Message-Id: <20231028103311.347104-18-alex.ben...@linaro.org>
---
 contrib/plugins/lockstep.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/contrib/plugins/lockstep.c b/contrib/plugins/lockstep.c
index f0cb8792c6..237543b43a 100644
--- a/contrib/plugins/lockstep.c
+++ b/contrib/plugins/lockstep.c
@@ -257,6 +257,7 @@ static bool setup_socket(const char *path)
 sockaddr.sun_family = AF_UNIX;
 if (g_strlcpy(sockaddr.sun_path, path, pathlen) >= pathlen) {
 perror("bad path");
+close(fd);
 return false;
 }
 
@@ -303,6 +304,7 @@ static bool connect_socket(const char *path)
 sockaddr.sun_family = AF_UNIX;
 if (g_strlcpy(sockaddr.sun_path, path, pathlen) >= pathlen) {
 perror("bad path");
+close(fd);
 return false;
 }
 
-- 
2.39.2