to think of a case where this could actually cause a problem
but I can't. However from a clarity/correctness point of view it's
better.
Reviewed-by: Alex Bennée alex.ben...@linaro.org
---
target-arm/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm
Edgar E. Iglesias edgar.igles...@gmail.com writes:
On Thu, May 01, 2014 at 10:31:06AM +0100, Peter Maydell wrote:
On 1 May 2014 10:02, Alex Bennée alex.ben...@linaro.org wrote:
Edgar E. Iglesias edgar.igles...@gmail.com writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
for an academic
paper.
thanks
-- PMM
--
Alex Bennée
translator.
r~
--
Alex Bennée
-xregs[31];
-}
+aarch64_save_sp(env, cur_el);
env-exclusive_addr = -1;
Reviewed-by: Alex Bennée alex.ben...@linaro.org
--
Alex Bennée
(env, new_el);
env-pc = env-elr_el[cur_el];
}
It might be worth putting the Aarch64 ARM reference next to the aarch64_
functions to make it easier to find in future.
Reviewed-by: Alex Bennée alex.ben...@linaro.org
--
Alex Bennée
, PSTATE_DAIF | PSTATE_MODE_EL1h);
env-aarch64 = 1;
+aarch64_restore_sp(env, 1);
env-pc = addr;
cs-interrupt_request |= CPU_INTERRUPT_EXITTB;
Reviewed-by: Alex Bennée alex.ben...@linaro.org
--
Alex Bennée
This is a pre-cursor to removing the cpsr_write function.
diff --git a/linux-user/arm/nwfpe/fpa11.h b/linux-user/arm/nwfpe/fpa11.h
index bb9ac65..0dbdf75 100644
--- a/linux-user/arm/nwfpe/fpa11.h
+++ b/linux-user/arm/nwfpe/fpa11.h
@@ -108,7 +108,10 @@ static inline void writeRegister(unsigned int
As we only need to manipulate the single flag do it directly though env.
---
Q: should we add a new flags only access functions?
diff --git a/linux-user/main.c b/linux-user/main.c
index 22d0197..5d9d5f7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -469,7 +469,7 @@ void
This converts all users of pstate_write to use the common state
save/restore functionality.
diff --git a/linux-user/signal.c b/linux-user/signal.c
index c155bbc..48885e2 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1290,7 +1290,7 @@ static int target_restore_sigframe(CPUARMState
Use the unified save_state_to_spsr. I've also updated the interrupt
helpers to restore via the restore_state_from_spsr() functions. In the
aarch32 case this also needs to call switch_mode() to do the appropriate
fiddling.
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index
We have a number of program state saving functions (pstate, cpsr, xpsr)
which are dependant on the mode the CPU is in. This commit adds a little
documentation to each function and asserts to defend against incorrect
use.
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 8d04385..5e6df38
And use the new machinery to to save and restore program state. The old
cpsr_write function did some special handling for mode switches which
has been moved into the helper function.
diff --git a/linux-user/main.c b/linux-user/main.c
index 5d9d5f7..e594741 100644
--- a/linux-user/main.c
+++
This adds a universal program state save and restore function. This is
intended to simplify the migration serialisation functionality and avoid
special casing depending on the mode of the CPU at serialisation time.
---
WIP notes:
- From this I'll look at
- cpsr_read/cpsr_write
-
hidden behind
access functions so other flags can get split (i.e. env-el_mode?)
I've tested this with ARMv7 and ARMv8 with aarch32 user-space system
images. I've not given it a good linux-user test yet so I'm less sure
about the sigcontext manipulation code.
Comments?
Cheers,
--
Alex Bennée
This enables the saving and restoring of machine state by including the
current program state (*psr) and xregs. The save_state_to_spsr hides the
details of if the processor is in 32 or 64 bit mode at the time.
---
v2 (ajb)
- use common state save functions
- re-base to latest origin/master
Alex Bennée writes:
This converts all users of pstate_write to use the common state
save/restore functionality.
Oops, now I'll clean that up. I need to decide if it worth merge the
xpsr_ stuff anyway?
There is also some commented out code in the main save_state_to_spsr()
function which I
] = deposit64(env-cp15.far_el[1], 0, 32,
+env-exception.vaddress);
qemu_log_mask(CPU_LOG_INT, ...with DFSR 0x%x DFAR 0x%x\n,
(uint32_t)env-cp15.esr_el[1],
(uint32_t)env-exception.vaddress);
--
Alex
= offsetof(CPUARMState, cp15.far_el[3])
},
{ .name = SPSR_EL3, .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
--
Alex Bennée
},
{ .name = ELR_EL2, .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
--
Alex Bennée
~SCR_RES1_MASK)
Again I have similar cognitive dissonance with the naming of the mask
otherwise:
Reviewed-by: Alex Bennée alex.ben...@linaro.org
+
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
diff --git
;
+}
+}
+
static inline CPUARMState *cpu_init(const char *cpu_model)
{
ARMCPU *cpu = cpu_arm_init(cpu_model);
--
Alex Bennée
\n,
env-cp15.far_el[new_el]);
-break;
case EXCP_BKPT:
case EXCP_UDEF:
case EXCP_SWI:
+env-cp15.esr_el[new_el] = env-exception.syndrome;
break;
case EXCP_IRQ:
addr += 0x80;
Reviewed-by: Alex Bennée alex.ben
, syn_aa64_svc(imm16));
break;
case 1:
if (op2_ll != 0) {
--
Alex Bennée
= 2;
+}
+if (env-cp15.scr_el3 SCR_FIQ) {
+target_el = 3;
+}
+break;
I wonder if it's possible to make the common logic more common while
keeping the differences?
}
return target_el;
}
--
Alex Bennée
Greg Bellows writes:
On 3 June 2014 05:21, Alex Bennée alex.ben...@linaro.org wrote:
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.
Signed-off-by: Edgar E
Peter Maydell writes:
On 2 June 2014 17:21, Alex Bennée alex.ben...@linaro.org wrote:
This is a pre-cursor to removing the cpsr_write function.
diff --git a/linux-user/arm/nwfpe/fpa11.h b/linux-user/arm/nwfpe/fpa11.h
index bb9ac65..0dbdf75 100644
--- a/linux-user/arm/nwfpe/fpa11.h
+++ b
to be appropriate for this
task? I think the benchmarking should reflect real TCG use cases. So what the
most typical use cases for TCG are there? Seems that system and user modes
may be different from this point.
Appreciate any help.
Thanks,
Sergey.
--
Alex Bennée
in ${all_cpus}; do
+# Do not register the ELF format if it's the native one.
+host_cpu_compat ${cpu} continue
+
+# See if the user only wants to process a subset.
+if [ $# -gt 0 ]; then
+ has ${cpu} $@ || continue
+fi
+
+process_${cpu}
+ done
+}
+main $@
--
Alex
Alex Bennée alex.ben...@linaro.org writes:
Richard Henderson r...@twiddle.net writes:
Signed-off-by: Richard Henderson r...@twiddle.net
Subject looks a little space mangled. Otherwise:
That is apparently my fault, I shall kick my mailer.
Reviewed-by: Alex Bennée alex.ben...@linaro.org
Janne Grunau j...@jannau.net writes:
On 2014-02-25 15:54:37 +, Alex Bennée wrote:
snip
Have you got the log file unsupported line? I seem to recall you did
ping me but maybe it was just on IRC? I just want to make sure I
do the right ones. I'm working on this now.
We spoke on irc
/control.c
+#include ../trace/generated-events.c
#ifdef CONFIG_TRACE_SIMPLE
-#include ../trace/simple.c
+#include trace/simple.c
#endif
#include stdarg.h
--
Alex Bennée
things. But you did need to disable the x87 to do it.
But I get the impression that FP performance is currently good enough
for what QEMU gets used for.
--
Alex Bennée
for init in target-arm/cpu64.c.
Initial support is already in and the latest set of patches which get
you to boot a kernel to user-space is currently on this very list for review.
Cheers,
--
Alex Bennée
QEMU/KVM Hacker for Linaro
For SIGILL's it's useful to have the qemu log with -d unimp output.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1289527
Title:
qemu-aarch64-static: java dies with SIGILL
Status in QEMU:
New
Java under QEMU :-)
Having said that I'm sure there was another SIGILL related crash on
Launchpad and I think we would be interested in those. Is JAVA really
that buggy under QEMU just because of threading?
thanks
-- PMM
--
Alex Bennée
Michael Tokarev m...@tls.msk.ru writes:
12.03.2014 18:13, alex.ben...@linaro.org wrote:
From: Alex Bennée alex.ben...@linaro.org
are available in the git repository at:
g...@github.com:stsquad/qemu.git travis-updates
for you to fetch changes up
like a big ream of magic
numbers.
Cheers,
--
Alex Bennée
for
the now closed channel.
--
Alex Bennée
so
I'll clean-up the patches and re-submit to the list soon.
--
Alex Bennée
As we only need to manipulate the single flag do it directly though env.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- remove unused cpsr
- the direct flag setting seems a little hacky?
diff --git a/linux-user/main.c b/linux-user/main.c
index 8848e15..9101541 100644
This adds a universal program state save and restore function. This is
intended to simplify the migration serialisation functionality and avoid
special casing depending on the mode of the CPU at serialisation time.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- reword commentary
And use the new machinery to to save and restore program state. The old
cpsr_write function did some special handling for mode switches which
has been moved into the helper function.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- rebase
- add mask helper function
- checkpatch
This is a pre-cursor to removing the cpsr_write function completely from
the code base. set_condition_codes() only affects the integer condition
flags.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2
- fix nwfpe set_condition_codes
diff --git a/linux-user/arm/nwfpe/fpa11.h b/linux
Use the unified save_state_to_spsr. I've also updated the interrupt
helpers to restore via the restore_state_from_spsr() functions. In the
aarch32 case this also needs to call switch_mode() to do the appropriate
fiddling.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
--
v2
- include
This converts all users of pstate_write to use the common state
save/restore functionality.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/linux-user/signal.c b/linux-user/signal.c
index b6f9ef4..b1958a5 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1274,7
done that already...
Handily our patch tracker has remembered what I couldn't find ;-)
https://patches.linaro.org/27229/
As I mentioned previously I plan to clean these up over the next week.
--
Alex Bennée
From: Alex Bennée a...@bennee.com
When we have a problem syncing CP registers between kvm-qemu it's a
lot more useful to have the names of the registers in the log than just
a random abort() and core dump.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2
- less verbose log message
This enables the saving and restoring of machine state by including the
current program state (*psr) and xregs. The save_state_to_spsr hides the
details of if the processor is in 32 or 64 bit mode at the time.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2 (ajb)
- use common state
).
This list may well have more registers than are known by the TCG
emulation which is not necessarily a problem but it does stop us from
migrating between KVM and TCG hosted guests. I've added some additional
checking to report those registers under -d unimp.
Signed-off-by: Alex Bennée alex.ben
We have a number of program state saving functions (pstate, cpsr, xpsr)
which are dependant on the mode the CPU is in. This commit adds a little
documentation to each function and asserts to defend against incorrect
use.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- remove
- addition of final KVM patches
Alex Bennée (10):
target-arm/cpu.h: document various program state functions
target-arm/cpu.h: common pstate save/restore
target-arm: Support save/load for 64 bit CPUs
target-arm: replace cpsr/xpsr/pstate_read calls
arm/nwfps: replace cpsr_write
This allows the perf tool to map samples to each individual translation
block. This could be expanded for user space but currently it gives
enough information to find any hotblocks by other means.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- hoist up into translate-all.c
Richard Henderson writes:
On 07/11/2014 09:43 AM, Alex Bennée wrote:
+/* if I could put this in a header easily */
+void tb_enable_perfmap(void);
How about next to tb_flush in exec/exec-all.h?
Including exec/exec-all.h trips up some sort of include prevention
magic:
CCvl.o
This allows the perf tool to map samples to each individual translation
block. This could be expanded for user space but currently it gives
enough information to find any hotblocks by other means.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- hoist up into translate-all.c
This makes the UST backend pay attention to the format string arguments
that are defined when defining payload data. With this you can now
ensure integers are reported in hex mode if you want.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2
- remove silly debug statements
v3
- fix
This adds a couple of tcg specific trace-events which are useful for
tracing execution though tcg generated blocks. It's been tested with
lttng user space tracing but is generic enough for all systems. The tcg
events are:
* translate_block - when a subject block is translated
* exec_tb - when
of other tb_ related areas. I've also
added a trace_inc_counter() helper which gets inlined away when tracing
is disabled.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/cpu-exec.c b/cpu-exec.c
index 45ef77b..771272f 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -187,7 +187,10 @@ static
.
Alex Bennée (3):
trace: teach lttng backend to use format strings
trace: add some tcg tracing support
trace: instrument and trace tcg tb flush activity
cpu-exec.c | 9 +
cputlb.c | 2 +-
include/qom/cpu.h
Peter Maydell writes:
On 15 July 2014 12:42, Alex Bennée alex.ben...@linaro.org wrote:
+#ifndef CONFIG_TRACE_NOP
+static inline void trace_inc_counter(int *counter) {
+int cnt = *counter;
+cnt++;
+*counter = cnt;
+}
...why isn't this just *counter++; ?
You of course mean
Andreas Färber writes:
Hi,
Am 15.07.2014 13:42, schrieb Alex Bennée:
snip
index df977c8..8376678 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -243,6 +243,10 @@ struct CPUState {
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
struct
Paolo Bonzini writes:
Il 15/07/2014 13:42, Alex Bennée ha scritto:
+trace_inc_counter(cpu-tb_jmp_cache_stats.misses);
tb = tb_find_slow(env, pc, cs_base, flags);
+} else {
+trace_inc_counter(cpu-tb_jmp_cache_stats.hits);
}
I think this is premature
, \
__FILE__, __LINE__, insn, s-pc - 4); \
unallocated_encoding(s); \
} while (0);
So we signal it's unimplemented before falling through to the signal
generating code.
--
Alex Bennée
21));
snip
Could the #defines in the first patch be moved into a header and used
here rather than manually setting these bits?
--
Alex Bennée
be using an old enough ARM that has support for 1k page
tables (and may even use them?).
However review comments are welcome as well as any wider discussion on
reducing the time spent jumping between TBs.
Regards,
Alex Bennée (3):
target-arm: don't hardcode mask values
Otherwise we break quickly when we change TARGET_PAGE_SIZE.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a0e57cd..aa5d267 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4029,8 +4029,8 @@ int
According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/target
The aarch64 architecture only support 4k+ pages so using a smaller value
for QEMU's internal page table handling only makes us less efficient.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c83f249..33359b9 100644
--- a/target-arm/cpu.h
, 11 insertions(+), 9 deletions(-)
snip
I applaude this effort ;-)
Reviewed-by: Alex Bennée alex.ben...@linaro.org
--
Alex Bennée
Richard Henderson writes:
Around the cpu_exec_enter/exit hooks contain many empty
ifdef blocks. Delete all of these to highlight those
targets for which we actually need to do work.
Signed-off-by: Richard Henderson r...@twiddle.net
Reviewed-by: Alex Bennée alex.ben...@linaro.org
Richard Henderson writes:
Note that the code that was within the exit ifdef block
was identical to the cpu_compute_eflags inline, so make that
simplification at the same time.
Signed-off-by: Richard Henderson r...@twiddle.net
Reviewed-by: Alex Bennée alex.ben...@linaro.org
---
cpu
to replace the magic numbers with some define's
but seeing as the changes are mechanical so far best not get too fancy
in this series ;-)
Reviewed-by: Alex Bennée alex.ben...@linaro.org
--
Alex Bennée
them gets
confusing - is it really CPUState - ${ARCH}CPU - ${ARCH}CPUState?
Anyway...
Reviewed-by: Alex Bennée alex.ben...@linaro.org
+env-reserve_addr = -1;
+}
+
/* CPUClass::reset() */
static void ppc_cpu_reset(CPUState *s)
{
@@ -9638,6 +9646,7 @@ static void ppc_cpu_class_init
that hand pulls in
these dependancies then we can add a call to that for the mingw
builds. Any volenteers?
If there are no objections/negative reviews I'll push these at the
Trivial tree later this week. Or is it time we create a specific
testing tree for these particular type of patches?
Alex
A significant portion of the build time is spent initialising all the
sub-modules we use in the source tree. Often this is almost as long as
the build itself. By pre-seeding the .git/modules tree this will
hopefully improve things.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git
There are problems with unreliability in make check which still need
to be tracked down. As the tests are broadly the same for all targets if
added one explicit target to the matrix to run it. However this does
build all softmmu targets to ensure they at least run
Signed-off-by: Alex Bennée
At the same time I've grouped the $ARCH-linux-user and $ARCH-softmmu
builds together (hoping FS cache helps) and grouped all $ARCH-softmmu
only builds into one target. This reduces the build matrix slightly
which will hopefully help with build times.
Signed-off-by: Alex Bennée alex.ben
The Travis VMs have 1.5 cores so we might as well make some use of the
paralellism.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/.travis.yml b/.travis.yml
index 72cfc9f..f113339 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -41,7 +41,10 @@ before_install:
- git submodule
Richard Henderson writes:
Continuing the removal of ifdefs from cpu_exec.
Cc: Andreas Färber afaer...@suse.de
Signed-off-by: Richard Henderson r...@twiddle.net
Reviewed-by: Alex Bennée alex.ben...@linaro.org
---
cpu-exec.c| 14 +-
include/qom/cpu.h | 2 ++
qom
$ARCH_cpu_exec_interrupt?
--
Alex Bennée
Richard Henderson writes:
Cc: Alexander Graf ag...@suse.de
Signed-off-by: Richard Henderson r...@twiddle.net
Reviewed-by: Alex Bennée alex.ben...@linaro.org
---
cpu-exec.c | 6 --
target-s390x/cpu-qom.h | 1 +
target-s390x/cpu.c | 1 +
target-s390x/helper.c | 13
Richard Henderson writes:
Since do_interrupt_m68k_hardirq is no longer used outside
op_helper.c, make it static.
Signed-off-by: Richard Henderson r...@twiddle.net
Reviewed-by: Alex Bennée alex.ben...@linaro.org
---
cpu-exec.c | 13 -
target-m68k/cpu-qom.h | 1
Alex Bennée writes:
At the same time I've grouped the $ARCH-linux-user and $ARCH-softmmu
builds together (hoping FS cache helps) and grouped all $ARCH-softmmu
only builds into one target. This reduces the build matrix slightly
which will hopefully help with build times.
Pinging Alex who I
Alexander Graf writes:
On 15.09.14 18:48, Alex Bennée wrote:
A significant portion of the build time is spent initialising all the
sub-modules we use in the source tree. Often this is almost as long as
the build itself. By pre-seeding the .git/modules tree this will
hopefully improve things
addr) at %x
usb_ohci_mem_read_bad_offset(uint32_t addr) %x
--
Alex Bennée
This exceeded the trace argument limit for LTTNG UST and wasn't really
needed as the flags value is stored anyway. Dropping this fixes the
compile failure for UST. It can probably be merged with the previous
trace shortening patch.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
hw/usb/hcd
This only affects lttng user space tracing at the moment.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
scripts/tracetool/__init__.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py
index 36c789d..5aa2eed
-sta...@nongnu.org
snip
I've been testing it with my latest Travis patches (- the make check
once patch) and it seems a lot better now:
Reviewed-by: Alex Bennée alex.ben...@linaro.org
Tested-by: Alex Bennée alex.ben...@linaro.org
--
Alex Bennée
A significant portion of the build time is spent initialising all the
sub-modules we use in the source tree. Often this is almost as long as
the build itself. By pre-seeding the .git/modules tree this will
hopefully improve things.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed
There are problems with unreliability in make check which still need
to be tracked down. As the tests are broadly the same for all targets if
added one explicit target to the matrix to run it. However this does
build all softmmu targets to ensure they at least run
Signed-off-by: Alex Bennée
The Travis VMs have 1.5 cores so we might as well make some use of the
paralellism.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
Reviewed-by: Brian Jackson i...@theiggy.com
---
v3
- fix escaping of ${TEST_CMD}
diff --git a/.travis.yml b
At the same time I've grouped the $ARCH-linux-user and $ARCH-softmmu
builds together (hoping FS cache helps) and grouped all $ARCH-softmmu
only builds into one target. This reduces the build matrix slightly
which will hopefully help with build times.
Signed-off-by: Alex Bennée alex.ben
Hi,
Only one change in this set to ensure the second patch bisects
cleanly. I've also added the additional Reviewed-by tags.
Please apply to the trivial tree.
Alex Bennée (4):
.travis.yml: add more linux-user to the build matrix
.travis.yml: make the make slightly more parallel
?
Or is there some other issue?
Not currently - but patches are about. I can CC you when I send the next
set out if you want.
--
Alex Bennée
There is not much point storing the same value twice in a row.
Reported-by: Laurent Desnogues laurent.desnog...@gmail.com
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
target-arm/translate-a64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm
There is not much point storing the same value twice in a row.
Reported-by: Laurent Desnogues laurent.desnog...@gmail.com
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: Laurent Desnogues laurent.desnog...@gmail.com
---
target-arm/translate-a64.c | 1 -
1 file changed, 1 deletion
might never claw back that much.
I'll have a look through the patches and comment there when I've gotten
my head round the back-end issues.
Thanks for coding this up ;-)
--
Alex Bennée
before to
profile guest hot-blocks and work out which guest PID was responsible.
--
Alex Bennée
they are less likely to fall
in-between the cracks?
snip
Ideas? Takers?
My 0.2c ;-)
--
Alex Bennée
it doesn't apply them.
I think the main point is MAINTAINERS should really indicate a tree that
patches would get applied to. There is no one gathering up random
patches to the mailing list. The trivial patches don't really catch all
the stuff that gets to the list.
--
Alex Bennée
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