Both KVM and TCG populate the cpreg_list with 64 bit registers IDs, but in the
TCG side the cpreg_list is sorted using the 32 bit id version while in the kvm
side the 64 bit id version is used.
This patch makes the sorting of the cpreg_list consistent between KVM and TCG.
Signed-off-by: Alvise
The compare_u64 function was not sorting the KVM cpreg_list in the right way
due to the wrong returned value. Since we are comparing two 64bit values we
can't simply return their difference if the returned type is int.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm
, 2013 at 8:41 PM, Peter Maydell peter.mayd...@linaro.orgwrote:
On 12 October 2013 02:38, Alvise Rigo a.r...@virtualopensystems.com
wrote:
Both KVM and TCG populate the cpreg_list with 64 bit registers IDs, but
in the TCG side the cpreg_list is sorted using the 32 bit id version while
a user pointer, allowing to not call the IOMMU callbacks for
these regions, but rather to access the memory directly.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
exec.c| 2 +-
include/exec/memory.h | 16
memory.c | 14
will see in a
future version of VFIO for platform devices).
These patches are based on the QEMU branch mentioned in the original
thread ([Qemu-devel] [RFC v2 0/6] KVM platform device passthrough).
Alvise Rigo (4):
Allocate non-RAM MemoryRegion from user pointer
Add EXEC_FLAG to VFIO DMA mappings
-region=0;0x2c;4
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio/platform.c | 158 ++---
1 file changed, 150 insertions(+), 8 deletions(-)
diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
index c4a4286..9dae311 100644
--- a/hw
The flag is mandatory for the ARM SMMU, add it.
When VFIO will be able to tell about the IOMMU being used, we will add
it only if necessary.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio/common.c | 3 +++
linux-headers/linux/vfio.h | 1 +
2 files changed, 4
property will be added to the device tree node in order to allow the AMBA
bus code to probe the device.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/hw/arm
Now that VFIO can unmask the interrupt autonomously through an eventfd
file descriptor, get rid of the resampler_handler.
TODO: move this code and PCI one to common.c
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio/platform.c | 38 --
1
-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio/pci.c | 18 +-
hw/vfio/platform.c| 8
include/qemu/event_notifier.h | 1 +
util/event_notifier-posix.c | 24 +---
4 files changed, 35 insertions(+), 16 deletions
property will be added to the device tree node in order to allow the AMBA
bus code to probe the device.
[Eric Auger]
put str_ptr in the declaration part and rename pcompat into compat
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
Signed-off-by: Eric Auger eric.au...@linaro.org
---
hw
.
Alvise Rigo (3):
Add AMBA devices support to VFIO
Force eventfd as notifying mechanism for VFIO
Let VFIO handle the unmasking of interrupts at EOI
Eric Auger (1):
vfio: Add irqfd support in platform device
hw/arm/virt.c | 59 +++---
hw/intc/arm_gic_kvm.c
was tested with Calxeda Midway xgmac.
Signed-off-by: Eric Auger eric.au...@linaro.org
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 14 +
hw/intc/arm_gic_kvm.c | 1 +
hw/vfio/platform.c| 165 +-
3
further the correct behaviour of the device. This suite has been
tested with ARM FastModels.
Alvise Rigo (4):
Add EXEC_FLAG to VFIO DMA mappings
Add AMBA devices support to VFIO
MemoryRegion with EOI callbacks for VFIO Platform devices
Always use eventfd as notifying mechanism
hw/arm/virt.c
The flag is mandatory for the ARM SMMU so we always add it if the MMIO
handles it.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio/common.c | 9 +
hw/vfio/vfio-common.h | 1 +
linux-headers/linux/vfio.h | 2 ++
3 files changed, 12 insertions(+)
diff
property will be added to the device tree node in order to allow the AMBA
bus code to probe the device.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/hw/arm
-region=0;0x2c;4
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio/platform.c | 91 --
1 file changed, 89 insertions(+), 2 deletions(-)
diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
index c4a4286..ec6a29e 100644
--- a/hw
When eventfd is not configured the method event_notifier_init fallbacks
to the pipe/pipe2 system call, causing an error in VFIO_DEVICE_SET_IRQS
since we pass to the kernel a file descriptor which is not created by
eventfd.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/vfio
On 23/05/2014 10:40, Eric Auger wrote:
On 05/11/2014 07:13 PM, Alvise Rigo wrote:
The flag is mandatory for the ARM SMMU so we always add it if the MMIO
handles it.
Hi Alvise,
Refering to the root problem explanation found in
https://lkml.org/lkml/2014/2/8/176, I understand the problem
The method is not behaving in the way it's supposed to. It should return
the new value only if it's less than the actual one.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
vmstate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/vmstate.c b/vmstate.c
The value of this flag indicates the execution mode of the CPU prior the
migration. It is used to handle the KVM - TCG migration.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu-qom.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target
Since the irq bit seems to not be updated, exclude it from the check done
while copying data during migration.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/target-arm
was migrated to a x86 host running TCG.
The machine model used is vexpress-a15 with cortex-a15 as CPU.
Alvise Rigo (4):
Fix issue affecting get_int32_le() in vmstate.c
Added flag in ARMCPU to track last execution mode
Add l2ctlr cp register to CPUARMState
Relevant changes to enable KVM to TCG
with the
cpreg_list keeping a list of the registers that do not succeeded the
match.
* handle_cpreg_kvm2tcg_migration(): try to solve the mismatch of
cp registers coming from KVM; without this additional step the
migration would fail even if it's feasible.
Signed-off-by: Alvise Rigo a.r
of the process.
thanks,
alvise
On Tue, Feb 25, 2014 at 7:19 PM, Peter Maydell peter.mayd...@linaro.orgwrote:
On 25 February 2014 16:52, Alvise Rigo a.r...@virtualopensystems.com
wrote:
The value of this flag indicates the execution mode of the CPU prior the
migration. It is used to handle the KVM
:
On 25 February 2014 16:52, Alvise Rigo a.r...@virtualopensystems.com
wrote:
Since the irq bit seems to not be updated, exclude it from the check done
while copying data during migration.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu.c | 22
at 7:25 PM, Peter Maydell peter.mayd...@linaro.orgwrote:
On 25 February 2014 16:52, Alvise Rigo a.r...@virtualopensystems.com
wrote:
CPUARMState:
* added adfsr cp register.
* added aifsr cp register.
These registers have been added because they are migrated by KVM. This
prevents
register which is migrated in a
wildcarded case) could be considered to handle the migration.
alvise
On Wed, Feb 26, 2014 at 11:04 AM, Peter Maydell peter.mayd...@linaro.orgwrote:
On 26 February 2014 10:02, alvise rigo a.r...@virtualopensystems.com
wrote:
I agree that this is a sort
Hi Eric,
Thank you for reviewing it.
On 23/04/2014 17:00, Eric Auger wrote:
Hi Alvise,
Thank you for the patch. Indeed I am very interested in further
discussing the vfio-platform integration with you.
On 04/17/2014 07:29 PM, Alvise Rigo wrote:
The user can specify the location
On 24/04/2014 02:25, Peter Crosthwaite wrote:
On Fri, Apr 18, 2014 at 3:29 AM, Alvise Rigo
a.r...@virtualopensystems.com wrote:
The flag is mandatory for the ARM SMMU, add it.
When VFIO will be able to tell about the IOMMU being used, we will add
it only if necessary.
Signed-off-by: Alvise
Il 24/04/2014 02:16, Peter Crosthwaite ha scritto:
On Thu, Apr 24, 2014 at 1:21 AM, Eric Auger eric.au...@linaro.org wrote:
On 04/17/2014 07:29 PM, Alvise Rigo wrote:
These patches were born after trying the current work on device
passthrough (see thread [Qemu-devel] [RFC v2 0/6] KVM platform
On 23/04/2014 17:21, Eric Auger wrote:
On 04/17/2014 07:29 PM, Alvise Rigo wrote:
These patches were born after trying the current work on device
passthrough (see thread [Qemu-devel] [RFC v2 0/6] KVM platform device
passthrough) with a DMA330 and FastModels. This work want to be the
starting
VBAR for AArch32 and VBAR_EL1 for AArch64).
Regards,
alvise
On Mon, Mar 3, 2014 at 10:39 PM, Peter Maydell peter.mayd...@linaro.orgwrote:
On 26 February 2014 10:02, alvise rigo a.r...@virtualopensystems.com
wrote:
I agree that this is a sort of workaround, but it seems to me that a
proper
-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/helper.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f65cbac..2791dac 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2313,6
The real hardware seems to not set the Interrupt Controller bit of the
L2CTLR cp register; on the contrary it could set some other bits
regarding RAM features that are not modelled in TCG, so we can mask them out.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu.c | 8
, the guest was migrated to a x86 host
running TCG.
The machine model used is vexpress-a15 with cortex-a15 as CPU.
Alvise Rigo (7):
Decouple AArch64 cp registers from AArch32
Migrate CCSIDR registers values as cp17 registers
Add a way to mask some unimplemented bits of cp registers
Exclude IC
register
and then reading it from the CCSIDR register).
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu.c | 64
1 file changed, 64 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1ce8a9b
to the ARMCPRegInfo structure to exclude the bits not supported of
the incoming registers values.
In case of an outgoing migration, the unsupported data is retrieved from the
cpreg_vmstate array.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 49
These registers are required in TCG because they are migrated by KVM:
their absence from the cpreg table leads to a migration failure.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 9 +
2 files changed, 10 insertions
Revisit the definitions of the cp registers TTBR0/1 and TTBRC in such a way to
use the AArch32 ids format when the guest is using a 32bit model.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/helper.c | 38 +++---
1 file changed, 27
the Jazelle bits (in TCG
these bits are set in the reset value of the register, probably
we should consider to remove them).
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
target-arm/helper.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git
Il 07/07/2014 14:49, Will Deacon ha scritto:
On Mon, Jul 07, 2014 at 01:27:18PM +0100, Eric Auger wrote:
From: Alvise Rigo a.r...@virtualopensystems.com
The flag is mandatory for the ARM SMMU so we always add it if the MMIO
handles it.
I though the logic of this flag was changing (so
-devel] [RFC PATCH 2/2] hw/arm/virt: Add generic PCI host device
http://lists.gnu.org/archive/html/qemu-devel/2014-06/msg03483.html
Alvise Rigo (8):
mach-virt: move GIC inside mach-virt structure
mach-virt: improve PCI memory topology definition
QEMUMachine: finalize_dt function
generic_pci
Some of the unnecessary redundancy here will be decreased later in this
series.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 37 +
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7122e99..ed9fc7a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -83,6 +83,7 @@ typedef struct VirtBoardInfo
space of these regions (config, IO and memory) is specified by the
mach-virt platform.
TODO:
- Part of the ranges device node is still hardcoded.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 80 +++--
hw/pci-host
Create a generic_pci_host state to include the IRQ map to be used when
resolving the PCI interrupts. These structures can be useful to support
more complicated scenarios, like with multi functions PCI devices.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/pci-host/generic-pci.c
[PATCH 0/7] machvirt dynamic sysbus device instantiation, as soon as
those patches will be accepted, this work will be adapted making use of
them.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
include/hw/boards.h | 4
vl.c| 5 +
2 files changed, 9 insertions
Realize the device according to the offsets specified by the machine
memory map.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/pci-host/generic-pci.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/generic-pci.c b/hw/pci-host/generic
mapping; it will be added later by a patch of this series.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 10 ++
hw/pci-host/generic-pci.c | 15 ---
include/hw/pci-host/pci_generic.h | 4 +++-
3 files changed, 21
-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/pci-host/generic-pci.c | 31 +--
include/hw/pci-host/pci_generic.h | 33 +
2 files changed, 34 insertions(+), 30 deletions(-)
create mode 100644 include/hw/pci-host/pci_generic.h
The kernel version is a very recent one: v3.16.0-rc1.
Maybe you are right. I will test some older version to see if I'm able
to reproduce the issue.
Thank you,
alvise
Il 11/07/2014 11:09, Peter Maydell ha scritto:
On 11 July 2014 08:21, Alvise Rigo a.r...@virtualopensystems.com wrote
if=scsi,index=1,file=scsi.img \
-drive if=scsi,index=2,file=scsi_2.img ...
to attach the SCSI disks to the guest.
Thank you,
alvise
On Tue, Sep 9, 2014 at 6:35 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 11.07.2014 11:28, Alvise Rigo wrote:
The kernel version is a very
On Wed, Nov 5, 2014 at 11:23 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
Hi Alvise,
Hi Claudio,
On 11.07.2014 09:21, Alvise Rigo wrote:
This patch series is based on the previous work [1] and [2] by Rob
Herring and it tries to enhance this work on these points:
do your patches
On Wed, Nov 5, 2014 at 1:26 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 11.07.2014 09:21, Alvise Rigo wrote:
Keeping advantage of the finalize_dt QEMUMachine function, the mach-virt
machine now completes the device tree creation after that all the
generic devices have been
/msg01957.html
[4]
http://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg03816.html
Alvise Rigo (4):
hw/arm/virt: Allow multiple agents to modify dt
hw/arm/virt: find_machine_info: handle NULL value
hw/pci-host: Add a generic PCI host controller for virtual platforms
hw/arm/virt: Add
of the interrupt-map property generation. This property is fetched
by the guest operating system to map any PCI interrupt to the interrupt
controller. For the time being, the device expects a GIC v2 to be used
by the guest.
Only mach-virt has been used to test the controller.
Signed-off-by: Alvise Rigo a.r
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e8d527d..4e7b869 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -151,6 +151,10 @@ static VirtBoardInfo *find_machine_info(const
Keep a global list with all the functions that need to modify the device
tree. Using qemu_add_machine_init_done_notifier we register a notifier
that executes all the functions on the list and loads the kernel.
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 55
Yes, I forgot to remove this hard-coded (wrong) value. I will fix it in the
next release.
On Mon, Nov 24, 2014 at 11:38 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 21.11.2014 19:07, Alvise Rigo wrote:
Instantiate a generic-pci PCI controller to add a PCI bus to the
mach-virt
Hi Claudio,
Thank you for your review. Please see my in-line comments.
On Mon, Nov 24, 2014 at 11:34 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 21.11.2014 19:07, Alvise Rigo wrote:
Add a generic PCI host controller for virtual platforms, based on the
previous work by Rob Herring
registered.
alvise
Thanks,
Claudio
On 21.11.2014 19:07, Alvise Rigo wrote:
This patch series is based on the previous work [1] and [2] by Rob
Herring and on [3] by myself. For sake of readability and since this is
still a RFC, these patches come as a stand alone work, so there's no
need
Hello,
Related to TCG multithreaded, at Virtual Open Systems, we have also
been working on it. More specifically we are looking on how to enable
a basic multithreaded vCPU infrastructure with one cache per CPU. We
intend to focus on the vCPU private tcg structures
(instantiation/initialization),
Hi Claudio,
Sorry, I should have missed this one.
On Wed, Jan 14, 2015 at 2:12 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 14.01.2015 11:16, Alvise Rigo wrote:
Add a generic PCI host controller for virtual platforms, based on the
previous work by Rob Herring:
http
Auger eric.au...@linaro.org wrote:
On 01/05/2015 05:14 PM, alvise rigo wrote:
Hi,
On Mon, Jan 5, 2015 at 4:36 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 24 November 2014 at 11:47, Claudio Fontana
claudio.font...@huawei.com wrote:
On 21.11.2014 19:07, Alvise Rigo wrote:
Keep
Thank you. I will keep this in mind for the next spin of the patches.
Regards,
alvise
On Mon, Jan 5, 2015 at 7:07 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 January 2015 at 17:35, alvise rigo a.r...@virtualopensystems.com wrote:
So I suppose we need to define a fixed number of PCI
Hi,
On Mon, Jan 5, 2015 at 6:13 PM, Alexander Graf ag...@suse.de wrote:
On 21.11.14 19:07, Alvise Rigo wrote:
Add a generic PCI host controller for virtual platforms, based on the
previous work by Rob Herring:
http://lists.gnu.org/archive/html/qemu-devel/2014-06/msg03482.html
:
On 21 November 2014 at 18:07, Alvise Rigo a.r...@virtualopensystems.com
wrote:
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e8d527d..4e7b869 100644
--- a/hw/arm/virt.c
Hi,
On Mon, Jan 5, 2015 at 4:36 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 24 November 2014 at 11:47, Claudio Fontana
claudio.font...@huawei.com wrote:
On 21.11.2014 19:07, Alvise Rigo wrote:
Keep a global list with all the functions that need to modify the device
tree. Using
On Mon, Jan 5, 2015 at 5:41 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 January 2015 at 16:14, alvise rigo a.r...@virtualopensystems.com wrote:
On Mon, Jan 5, 2015 at 4:36 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
Sorry, I think I must have missed this series first time
the -device option (e.g., -device
virtio-blk-pci).
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
hw/arm/virt.c | 112 +-
1 file changed, 111 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2353440
). The device
needs the following qdev properties to configure the memory regions:
- cfg_win_size: size of the configuration memory
- pio_win_size: size of the port I/O space
- mmio_win_size: size of the MMIO space
- mmio_win_addr: offset of MMIO space in the system memory
Signed-off-by: Alvise
/2014-06/msg03483.html
[3]
[Qemu-devel] [PATCH 0/4] ARM: Add support for a generic PCI Express host
bridge
https://www.mail-archive.com/qemu-devel@nongnu.org/msg272648.html
Alvise Rigo (2):
pci/pci-host: Add generic-pci PCI host controller device
hw/arm/virt: add generic-pci PCI host controller
Hi Claudio,
On Wed, Jan 14, 2015 at 2:10 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 14.01.2015 11:16, Alvise Rigo wrote:
The platform memory map has now three more memory ranges to map the
device's memory regions (Configuration region, I/O region and Memory
region).
The dt
Hi Alexander,
Just a comment below.
On Tue, Jan 6, 2015 at 5:03 PM, Alexander Graf ag...@suse.de wrote:
With simple exposure of MMFG, ioport window, mmio window and an IRQ line we
can successfully create a workable PCIe host bridge that can be mapped
anywhere
and only needs to get described
Hi Alexander,
Just a comment below.
On Tue, Jan 6, 2015 at 5:03 PM, Alexander Graf ag...@suse.de wrote:
Now that we have a working generic PCIe host bridge driver, we can plug
it into ARMs virt machine to always have PCIe available to normal ARM VMs.
I've successfully managed to expose a
On Thu, Jan 8, 2015 at 1:55 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
(added cc: Alvise which I mistakenly assumed was in Cc: already)
On 07.01.2015 22:47, Alexander Graf wrote:
On 07.01.15 16:52, Claudio Fontana wrote:
On 06.01.2015 17:03, Alexander Graf wrote:
Now that we
, at 17:38, Alvise Rigo a.r...@virtualopensystems.com wrote:
This patch series provides an infrastructure for atomic
instruction implementation in QEMU, paving the way for TCG multi-threading.
The adopted design does not rely on host atomic
instructions and is intended to propose a 'legacy
you,
alvise
Or have you already taken a look at that - it’s pretty short.
Cheers
Mark.
On 6 May 2015, at 17:51, Paolo Bonzini pbonz...@redhat.com wrote:
On 06/05/2015 17:38, Alvise Rigo wrote:
This patch series provides an infrastructure for atomic
instruction implementation in QEMU
, but they have to
be so in a real multi-threading TCG.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
include/exec/cpu-defs.h | 2 ++
include/exec/memory.h | 3 ++-
include/exec
the 'legacy'
slow-path will set the accessed memory page to dirty.
In this series only the ARM ldrex/strex instructions are implemented.
The code was tested with bare-metal test cases and with Linux, using
upstream QEMU.
This work has been sponsored by Huawei Technologies Dusseldorf GmbH.
Alvise Rigo (5
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only the 32bit instructions are supported.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r
Create a new pair of instructions that implement a LoadLink/StoreConditional
mechanism.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
tcg/tcg-op.c | 20
On Thu, May 7, 2015 at 7:12 PM, Richard Henderson r...@twiddle.net wrote:
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
The purpose of this new bitmap is to flag the memory pages that are in
the middle of LL/SC operations (after a LL, before a SC).
For all these pages, the corresponding TLB
Hi Richard,
Thank you for looking at this.
Some comments below.
On Thu, May 7, 2015 at 7:25 PM, Richard Henderson r...@twiddle.net wrote:
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
Add a new flag for the TLB entries to force all the accesses made to a
page to follow the slow-path.
Mark
Hi,
On Fri, May 8, 2015 at 5:22 PM, Alex Bennée alex.ben...@linaro.org wrote:
Alvise Rigo a.r...@virtualopensystems.com writes:
This patch series provides an infrastructure for atomic
instruction implementation in QEMU, paving the way for TCG multi-threading.
The adopted design does
On Thu, May 7, 2015 at 7:56 PM, Richard Henderson r...@twiddle.net wrote:
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
+#define DATA_SIZE (1 SHIFT)
+
+#if DATA_SIZE == 8
+#define SUFFIX q
+#define LSUFFIX q
+#define SDATA_TYPE int64_t
+#define DATA_TYPE uint64_t
Duplicating all
On Thu, May 7, 2015 at 7:58 PM, Richard Henderson r...@twiddle.net wrote:
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
+/* An output operand to return the StoreConditional result */
+static void gen_stcond_i32(TCGOpcode opc, TCGv_i32 is_dirty, TCGv_i32 val,
+ TCGv addr
On Fri, May 8, 2015 at 8:29 PM, Emilio G. Cota c...@braap.org wrote:
On Wed, May 06, 2015 at 17:38:02 +0200, Alvise Rigo wrote:
This patch series provides an infrastructure for atomic
instruction implementation in QEMU, paving the way for TCG multi-threading.
The adopted design does not rely
-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
cputlb.c | 7 ++-
include/exec/cpu-all.h | 1 +
softmmu_template.h | 48 +++-
3 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 38f2151
claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
cputlb.c| 4 +
softmmu_llsc_template.h | 233
softmmu_template.h | 4 +
tcg/tcg-be-ldst.h | 2 +
tcg/tcg.h | 20 +
5
-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
tcg/tcg-be-ldst.h | 1 +
tcg/tcg-op.c | 23 +++
tcg/tcg-op.h | 3 +++
tcg/tcg-opc.h | 4
tcg/tcg.c
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only the 32bit instructions are supported.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only 32bit configurations are supported.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r
the execution of the other vCPUs in order to update accordingly (flush)
the TLB cache.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
cputlb.c| 3
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rigo (7):
bitmap: Add bitmap_one_extend operation
exec: Add new exclusive bitmap to ram_list
Add new TLB_EXCL flag
softmmu: Add helpers for a new slow-path
tcg-op: create new TCG qemu_ldlink and qemu_stcond
, but they have to
be so in a real multi-threading TCG.
Fix also one bracket alignment.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
exec.c | 7 +--
include/exec
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
include/qemu/bitmap.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/qemu/bitmap.h b/include/qemu
if a vCPU writes to the protected address.
Suggested-by: Jani Kokkonen jani.kokko...@huawei.com
Suggested-by: Claudio Fontana claudio.font...@huawei.com
Signed-off-by: Alvise Rigo a.r...@virtualopensystems.com
---
cputlb.c| 18 -
include/exec/cpu-all.h | 2 +
include/exec/cpu
Hi Alex,
Let me just add one comment.
On Fri, Jun 12, 2015 at 6:37 PM, Alex Bennée alex.ben...@linaro.org wrote:
Hi,
One thing that Peter has been asking for is a design document for the
way we are going to approach multi-threaded TCG emulation. I started
with the information that was
1 - 100 of 296 matches
Mail list logo
