Video RAM is typically mapped as uncached by guests. Flag it as
such.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
hw/display/vga.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/display/vga.c b/hw/display/vga.c
index c0f7b343bbab5..5c8c249a8d780 100644
--- a/hw/display/vga.c
+++ b
On Wed, Mar 18, 2015 at 03:08:20PM -0400, Andrew Jones wrote:
In reply to this message I'll send two series' one for KVM and
one for QEMU. The two series' are their respective component
complements, and attempt to implement cache coherency for arm
guests using emulated devices, where
Introduce a new memory region flag, KVM_MEM_UNCACHED, which
is needed by ARM. This flag informs KVM that the given memory
region is typically mapped by the guest as uncached. KVM for
ARM then maps that region as uncached for userspace as well,
in order to keep coherency.
Andrew Jones (3):
KVM
When userspace tells us a memory region is uncached, then we
need to pin all its pages and set them all to be uncached.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/asm/kvm_mmu.h| 9 +
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm/kvm/mmu.c
KVM_MEM_UNCACHED memory will no longer need caches to be flushed
for memory as it's faulted in. Just use READONLY directly, in that
case, now.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/kvm/mmu.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff
On Wed, Mar 11, 2015 at 05:02:00PM +, Peter Maydell wrote:
On 10 March 2015 at 21:06, Andrew Jones drjo...@redhat.com wrote:
This patch makes the following changes to the determination of
whether an address is executable, when translating addresses
using LPAE.
1. No longer assumes
-by: Andrew Jones drjo...@redhat.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 49 +++--
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3bc20af04f012
and cortex-a57
(just up to 'Unable to mount root fs'), and also with a kvm-unit-tests
test. The curious can check out the unit test here [1].
Thanks in advance for reviews!
drew
[1]
https://github.com/rhdrjones/kvm-unit-tests/commit/ee553e4bb795b0150e31c794bf8953dfb08d619a
Andrew Jones (3
translations.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
target-arm/helper.c | 130
1 file changed, 100 insertions(+), 30 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d996659652f8d..7fe3d14773068 100644
On Fri, Mar 06, 2015 at 01:53:38PM -0500, Andrew Jones wrote:
Add a function that flushes the cache to PoC. We need a new
function because __builtin___clear_cache only flushes to
PoU. Call this function each time an address in a memory
region that has been flagged as having an incoherent cache
On Wed, Mar 11, 2015 at 06:15:47PM +, Peter Maydell wrote:
On 11 March 2015 at 18:10, Andrew Jones drjo...@redhat.com wrote:
On Wed, Mar 11, 2015 at 05:49:39PM +, Peter Maydell wrote:
Still confused. If the page isn't readable or writable
then WXN isn't going to kick in anyway
used. I don't see CR_AFE
getting used by Linux, so possibly not. If it had been, then
the check would have been wrong for all but AP[2:1] = 0b11.
Anyway, this should fix it up, in case it ever does get used.
Signed-off-by: Andrew Jones drjo...@redhat.com
Reviewed-by: Peter Maydell peter.mayd
On Wed, Mar 11, 2015 at 05:49:39PM +, Peter Maydell wrote:
On 11 March 2015 at 17:42, Andrew Jones drjo...@redhat.com wrote:
On Wed, Mar 11, 2015 at 05:02:00PM +, Peter Maydell wrote:
+if (is_aa64) {
+switch (regime_el(env, mmu_idx)) {
+case 1
used. I don't see CR_AFE
getting used by Linux, so possibly not. If it had been, then
the check would have been wrong for all but AP[2:1] = 0b11.
Anyway, this should fix it up, in case it ever does get used.
Signed-off-by: Andrew Jones drjo...@redhat.com
Reviewed-by: Peter Maydell peter.mayd
test. The curious can check out the unit test here [1].
Thanks in advance for reviews!
drew
[1]
https://github.com/rhdrjones/kvm-unit-tests/commit/ee553e4bb795b0150e31c794bf8953dfb08d619a
Andrew Jones (3):
target-arm: convert check_ap to ap_to_rw_prot
target-arm: fix get_phys_addr_v6
-by: Andrew Jones drjo...@redhat.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 49 +++--
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3bc20af04f012
translations.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
target-arm/helper.c | 132
1 file changed, 102 insertions(+), 30 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d996659652f8d..193e6aa7c1f26 100644
Currently kvm_mem_flags just translates bools to bits, let's
make it also determine the bools first. This avoids its parameter
list growing each time we add a flag.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
This patch comes from an experimental series that added a kvm
memslot flag
Add the kvm_*_incoherent_memory_regions calls to arm's
kvm_arch_vcpu_ioctl_run and implement the corresponding
arch flush/invalidate functions.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm/kvm/arm.c| 4 +++
arch/arm/kvm
Currently kvm_mem_flags just translates bools to bits, let's
make it also determine the bools first. This avoids its parameter
list growing each time we add a flag.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Posted this, as it makes sense without this series.
http://lists.gnu.org/archive
kvm_arch_flush_incoherent makes things too slow, and we don't
need it. Userspace can flush for us, as the necessary cache
maintenance instruction is not (necessarily) privileged.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/kvm/mmu.c | 6 ++
1 file changed, 6 insertions
Signed-off-by: Andrew Jones drjo...@redhat.com
---
hw/display/vga.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/display/vga.c b/hw/display/vga.c
index c8c49abc6e8ba..2b74eb8e96462 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -2135,6 +2135,7 @@ void vga_common_init
Add support for the new KVM_MEM_INCOHERENT flag, and flag
appropriate memory. (Only flags vram for now.)
Patch 6/6 doesn't appear to be complete. While the VGA output is
99% corruption free, it's not perfect, so it's missing flushes
somewhere...
Andrew Jones (6):
memory: add incoherent cache
In reply to this message I'll send two series' one for KVM and
one for QEMU. The two series' are their respective component
complements, and attempt to implement cache coherency for arm
guests using emulated devices, where the emulator (qemu) uses
cached memory for the device memory, but the guest
Userspace flags memory regions as incoherent and kvm flushes/
invalidates those regions on entry/exit from userspace.
Result before patch 6/6: restores coherency, way t sloow
Result with patch 6/6: fast again - well, we removed the code...
Andrew Jones (6):
kvm: promote
Add an incoherent cache flag, which indicates the region
needs explicit cache maintenance.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
include/exec/memory.h | 23 +++
memory.c | 15 +++
2 files changed, 38 insertions(+)
diff --git a/include
Signed-off-by: Andrew Jones drjo...@redhat.com
---
kvm-all.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 507fa7204e062..924b4a0bec21c 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -305,6 +305,9 @@ static int kvm_mem_flags(MemoryRegion *mr)
if (readonly
Add two new memslot functions to the API
kvm_flush_incoherent_memory_regions
flush all KVM_MEM_INCOHERENT memslot addresses
kvm_invalidate_incoherent_memory_regions
invalidate all KVM_MEM_INCOHERENT memslot addresses
Signed-off-by: Andrew Jones drjo...@redhat.com
---
include/linux
Should do a proper update-linux-headers.sh update.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
linux-headers/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 12045a11c036b..d04e2d781c43b 100644
--- a/linux-headers
parameter.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/asm/kvm_mmu.h | 7 ++-
arch/arm/kvm/mmu.c | 3 ++-
arch/arm64/include/asm/kvm_mmu.h | 7 +++
3 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/kvm/mmu.c | 9 +++--
include/linux/kvm_host.h | 1 -
include/uapi/linux/kvm.h | 1 +
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index bcc1b3ad2adce..a806e8cecc01b
Also support only invalidating, rather than always invalidate+clear.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/asm/kvm_mmu.h | 7 +--
arch/arm/kvm/mmu.c | 2 +-
arch/arm64/include/asm/kvm_mmu.h | 7 +--
3 files changed, 11 insertions(+), 5
architectures don't need it anyway.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Currently only implemented for aarch64, doesn't completely work yet.
exec.c | 16 ++--
include/exec/exec-all.h | 41 +
2 files changed, 51
On Tue, Mar 10, 2015 at 04:41:45PM +, Peter Maydell wrote:
On 10 March 2015 at 16:32, Andrew Jones drjo...@redhat.com wrote:
On Tue, Mar 10, 2015 at 03:22:55PM +, Peter Maydell wrote:
I'm confused. Even if we're using the simple-permissions
model, the ap parameter is still AP[2:0
On Tue, Mar 10, 2015 at 04:55:53PM +, Peter Maydell wrote:
On 10 March 2015 at 16:48, Andrew Jones drjo...@redhat.com wrote:
On Tue, Mar 10, 2015 at 03:56:11PM +, Peter Maydell wrote:
For instance, you're missing a shift here on the ap bits, because
get_rw_prot needs AP[2:0
On Tue, Mar 10, 2015 at 05:14:21PM +, Peter Maydell wrote:
On 10 March 2015 at 17:02, Andrew Jones drjo...@redhat.com wrote:
On Tue, Mar 10, 2015 at 04:55:53PM +, Peter Maydell wrote:
On 10 March 2015 at 16:48, Andrew Jones drjo...@redhat.com wrote:
On Tue, Mar 10, 2015 at 03:56
On Tue, Mar 10, 2015 at 03:56:11PM +, Peter Maydell wrote:
On 12 February 2015 at 15:05, Andrew Jones drjo...@redhat.com wrote:
This patch makes the following changes to the determination of
whether an address is executable, when translating addresses
using LPAE.
1. No longer
On Tue, Mar 10, 2015 at 05:03:48PM +, Peter Maydell wrote:
On 10 March 2015 at 16:54, Andrew Jones drjo...@redhat.com wrote:
On Tue, Mar 10, 2015 at 03:57:27PM +, Peter Maydell wrote:
On 12 February 2015 at 17:08, Andrew Jones drjo...@redhat.com wrote:
Actually, I should point out
On Tue, Mar 10, 2015 at 03:57:27PM +, Peter Maydell wrote:
On 12 February 2015 at 17:08, Andrew Jones drjo...@redhat.com wrote:
On Thu, Feb 12, 2015 at 04:05:07PM +0100, Andrew Jones wrote:
Now that we have get_S1prot, we can apply it to get_phys_addr_v6
for a minor code cleanup.
I
On Tue, Mar 10, 2015 at 03:12:20PM +, Peter Maydell wrote:
On 12 February 2015 at 15:05, Andrew Jones drjo...@redhat.com wrote:
+*prot = get_rw_prot(env, mmu_idx, ap, domain_prot);
+*prot |= *prot !xn ? PAGE_EXEC : 0;
I'm not a great fan of complicated ?: expressions
On Tue, Mar 10, 2015 at 03:22:55PM +, Peter Maydell wrote:
On 12 February 2015 at 15:05, Andrew Jones drjo...@redhat.com wrote:
Teach get_rw_prot about the simple AP format AP[2:1]. An additional
switch was added, as opposed to converting ap := AP[2:1] to AP[2:0]
with a simple shift
On Thu, Feb 12, 2015 at 04:05:06PM +0100, Andrew Jones wrote:
This patch makes the following changes to the determination of
whether an address is executable, when translating addresses
using LPAE.
1. No longer assumes that PL0 can't execute when it can't read.
It can in AArch64
].
Thanks in advance for reviews!
drew
[1]
https://github.com/rhdrjones/kvm-unit-tests/commit/ee553e4bb795b0150e31c794bf8953dfb08d619a
Andrew Jones (3):
target-arm: convert check_ap to ap_to_rw_prot
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check
target-arm: get_phys_addr_lpae: more xn
-by: Andrew Jones drjo...@redhat.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 49 +++--
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3bc20af04f012
used. I don't see CR_AFE
getting used by Linux, so possibly not. If it had been, then
the check would have been wrong for all but AP[2:1] = 0b11.
Anyway, this should fix it up, in case it ever does get used.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
target-arm/helper.c | 49
translations.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
target-arm/helper.c | 129
1 file changed, 100 insertions(+), 29 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d996659652f8d..c457e9ab8c85a 100644
On Thu, Feb 12, 2015 at 04:05:02PM +0100, Andrew Jones wrote:
This series fixes and extends the determination of whether or
not an address is executable for LPAE translations. The main
patch is 4/5, and describes the details in its commit message.
Patches 1-3 prepare for the main patch
On Wed, Feb 25, 2015 at 12:08:16AM +0900, Peter Maydell wrote:
On 25 February 2015 at 00:06, Andrew Jones drjo...@redhat.com wrote:
Ping? This isn't a huge priority, but I wouldn't want it to get lost either.
I'm on holiday :-) Easy stuff is getting done but things that
take time (read
On Wed, Apr 29, 2015 at 10:19:55AM +0100, Peter Maydell wrote:
On 29 April 2015 at 10:03, Alexander Graf ag...@suse.de wrote:
On 18.03.15 20:10, Andrew Jones wrote:
Introduce a new memory region flag, KVM_MEM_UNCACHED, which
is needed by ARM. This flag informs KVM that the given memory
On Thu, May 07, 2015 at 01:31:42PM +0200, Alexander Spyridakis wrote:
Sample spinlock test case with the option to implement the spinlock
by means of GCC atomic instructions or unsafe memory operations.
Additionally, printf is wrapped around a spinlock to avoid concurrent
access to the serial
Provide a method to change normal, cacheable memory to non-cacheable.
KVM will make use of this to keep emulated device memory regions
coherent with the guest.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/asm/cacheflush.h | 1 +
arch/arm/mm/pageattr.c | 7
on the same page (pun intended)
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/asm/kvm_mmu.h| 5 -
arch/arm/include/asm/pgtable-3level.h | 1 +
arch/arm/include/asm/pgtable.h| 1 +
arch/arm/kvm/mmu.c| 37
not sure
what I'm missing...
This series applies to Linus' 110bc76729d4, but I tested with
a version backported to the current RHELSA kernel.
Thanks for reviews and testing!
drew
Andrew Jones (3):
arm/arm64: pageattr: add set_memory_nc
KVM: promote KVM_MEMSLOT_INCOHERENT to uapi
arm/arm64
regions. Also rename to KVM_MEM_UNCACHED.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Documentation/virtual/kvm/api.txt | 20 ++--
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm/kvm/arm.c| 1 +
arch/arm/kvm/mmu.c| 4 ++--
arch/arm64/include
On Thu, May 14, 2015 at 11:37:46AM +0100, Peter Maydell wrote:
On 14 May 2015 at 11:31, Andrew Jones drjo...@redhat.com wrote:
Forgot to (4): switch from setting userspace's mapping to
device memory to normal, non-cacheable. Using device memory
caused a problem that Alex Graf found
On Thu, May 14, 2015 at 12:55:49PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
When S1 and S2 memory attributes combine wrt to caching policy,
non-cacheable types take precedence. If a guest maps a region as
device memory, which KVM userspace
On Thu, May 14, 2015 at 01:38:11PM +0100, Peter Maydell wrote:
On 14 May 2015 at 13:28, Paolo Bonzini pbonz...@redhat.com wrote:
Well, PCI BARs are generally MMIO resources, and hence should not be cached.
As an optimization, OS drivers can mark them as cacheable or
write-combining or
On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
Provide a method to change normal, cacheable memory to non-cacheable.
KVM will make use of this to keep emulated device memory regions
coherent with the guest
On Thu, May 14, 2015 at 02:11:59PM +0100, Peter Maydell wrote:
On 14 May 2015 at 14:03, Andrew Jones drjo...@redhat.com wrote:
On Thu, May 14, 2015 at 11:37:46AM +0100, Peter Maydell wrote:
On 14 May 2015 at 11:31, Andrew Jones drjo...@redhat.com wrote:
Forgot to (4): switch from setting
On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
needed by ARM. This flag informs KVM that the given memory region
is typically mapped by the guest as non-cacheable. KVM for ARM
then ensures that that memory is indeed
Hi Catalin,
Thanks for the feedback. Some comments to your comments below.
On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote:
On Thu, May 14, 2015 at 02:46:44PM +0100, Andrew Jones wrote:
On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015
On Tue, May 19, 2015 at 12:18:54PM +0100, Catalin Marinas wrote:
On Tue, May 19, 2015 at 11:03:22AM +0100, Andrew Jones wrote:
On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote:
Another way would be to split the vma containing the non-cacheable
memory so that you get
On Fri, May 15, 2015 at 08:02:59AM -0700, Christoffer Dall wrote:
On Thu, May 14, 2015 at 03:32:13PM +0200, Andrew Jones wrote:
On Thu, May 14, 2015 at 12:55:49PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
When S1 and S2 memory attributes
Hi Shannon,
Thanks for the review.
On Tue, Jun 09, 2015 at 10:54:44AM +0800, Shannon Zhao wrote:
On 2015/6/8 22:00, Andrew Jones wrote:
Signed-off-by: Andrew Jones drjo...@redhat.com
---
hw/arm/virt-acpi-build.c | 44 +++-
1 file changed, 43
SPCR is the Serial Port Console Redirection table. See the document
linked from http://uefi.org/acpi. For serial port types, Interface
Type, see the documentation for the Debug Port Table 2 (DBG2).
Signed-off-by: Andrew Jones drjo...@redhat.com
Tested-by: Shannon Zhao shannon.z...@linaro.org
AML_SYSTEM_MEMORY [Shannon]
- tested-by Shannon
Andrew Jones (2):
ACPI: Add definitions for the SPCR table
hw/arm/virt-acpi-build: Add SPCR table
hw/arm/virt-acpi-build.c| 43 ++-
include/hw/acpi/acpi-defs.h | 72 +
2 files
Signed-off-by: Andrew Jones drjo...@redhat.com
---
hw/arm/virt-acpi-build.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index a9373ccaca6cb..192bbecf6e573 100644
--- a/hw/arm
SPCR is the Serial Port Console Redirection table. See the document
linked from http://uefi.org/acpi. For serial port types, Interface
Type, see the documentation for the Debug Port Table 2 (DBG2).
Signed-off-by: Andrew Jones drjo...@redhat.com
---
include/hw/acpi/acpi-defs.h | 72
Adding this table allows the guest to boot without the console=
parameter added to the kernel command line. And anyway, kernel doc
Documentation/arm64/acpi_object_usage.txt says it's a required
table for arm64.
Andrew Jones (2):
ACPI: Add definitions for the SPCR table
hw/arm/virt-acpi-build
On Tue, Jun 09, 2015 at 04:52:39PM +0200, Michael S. Tsirkin wrote:
On Mon, Jun 08, 2015 at 10:00:49AM -0400, Andrew Jones wrote:
SPCR is the Serial Port Console Redirection table. See the document
linked from http://uefi.org/acpi. For serial port types, Interface
Type, see
SPCR is the Serial Port Console Redirection Table. See the document
linked from http://uefi.org/acpi. For serial port types, Interface
Type, see the documentation for the Debug Port Table 2 (DBG2).
Signed-off-by: Andrew Jones drjo...@redhat.com
Tested-by: Shannon Zhao shannon.z...@linaro.org
Signed-off-by: Andrew Jones drjo...@redhat.com
Tested-by: Shannon Zhao shannon.z...@linaro.org
---
hw/arm/virt-acpi-build.c | 43 ++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index
version for table [mst]
- clarify _ADR comment [Igor]
v2:
- checkpatch style fixes [Shannon]
- table is revision 2, not 5 [Shannon]
- use AML_SYSTEM_MEMORY [Shannon]
- tested-by Shannon
Andrew Jones (2):
ACPI: Add definitions for the SPCR table
hw/arm/virt-acpi-build: Add SPCR table
hw/arm
Signed-off-by: Andrew Jones drjo...@redhat.com
Tested-by: Shannon Zhao shannon.z...@linaro.org
---
hw/arm/virt-acpi-build.c | 43 ++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index
-spinlock-test.flat -smp 4 # non-atomic locks
OR
arm/run arm/vos-spinlock-test.flat -smp 4 -append atomic # atomic locks
Thanks,
drew
[1] git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git
From dea26966a92cc65f23c0ac7bf2620982e0a9c57d Mon Sep 17 00:00:00 2001
From: Andrew Jones drjo
On Fri, Jun 26, 2015 at 08:06:55AM +0100, Alex Bennée wrote:
Andrew Jones drjo...@redhat.com writes:
On Wed, Jun 24, 2015 at 08:12:52PM +0100, Peter Maydell wrote:
On 24 June 2015 at 18:18, Alex Bennée alex.ben...@linaro.org wrote:
Paolo Bonzini pbonz...@redhat.com writes
On Tue, Jun 16, 2015 at 02:16:03PM +0100, Peter Maydell wrote:
On 16 June 2015 at 14:12, Andrew Jones drjo...@redhat.com wrote:
Can we now revert this revert, along with bumping the non-x86 arch
atleast-version to v2.2.1
Probably. I suggest you submit a patch and test it on the
relevant
On Fri, Jun 26, 2015 at 04:49:36PM +0200, Marc-André Lureau wrote:
From: David Marchand david.march...@6wind.com
When using ivshmem devices, notifications between guests can be sent as
interrupts using a ivshmem-server (typical use described in documentation).
The client is provided as a
Jones drjo...@redhat.com
Reviewed-by: Andrew Jones drjo...@redhat.com
---
Fix endianness [Peter]
---
hw/arm/virt-acpi-build.c| 11 +++
include/hw/acpi/acpi-defs.h | 12
2 files changed, 23 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi
- Original Message -
From: Shannon Zhao shannon.z...@linaro.org
The table revision is not the ACPI spec version. Fix the wrong revision
and also some comments.
Signed-off-by: Shannon Zhao shannon.z...@linaro.org
---
hw/arm/virt-acpi-build.c | 11 ++-
1 file changed, 6
On Fri, Jun 19, 2015 at 02:59:32PM -0400, Andrew Jones wrote:
- Original Message -
From: Shannon Zhao shannon.z...@linaro.org
The table revision is not the ACPI spec version. Fix the wrong revision
and also some comments.
Signed-off-by: Shannon Zhao shannon.z
On Fri, Apr 10, 2015 at 01:58:01PM +0100, Peter Maydell wrote:
Unfortunately it turns out that libseccomp 2.2 still does not work
correctly on non-x86 architectures; return to the previous configure
setup of insisting on libseccomp 2.1 or better and i386/x86_64 and
disabling seccomp support in
On Thu, Jun 18, 2015 at 06:28:36PM +0800, Shannon Zhao wrote:
On 2015/6/17 17:42, Andrew Jones wrote:
On Wed, Jun 17, 2015 at 09:06:47AM +0800, Shannon Zhao wrote:
On 2015/6/16 22:19, Michael S. Tsirkin wrote:
On Tue, Jun 16, 2015 at 09:33:19AM +0800, Shannon Zhao wrote
:
On 15 June 2015 at 17:32, Andrew Jones drjo...@redhat.com wrote:
On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
I'm still confused about when fields in these ACPI structs
need to be converted to little-endian
On Fri, Jun 12, 2015 at 06:21:35PM +0200, Igor Mammedov wrote:
On Fri, 12 Jun 2015 15:55:22 +0100
Peter Maydell peter.mayd...@linaro.org wrote:
On 1 June 2015 at 11:15, shannon.z...@linaro.org wrote:
From: Shannon Zhao shannon.z...@linaro.org
Add GICv2m description in ACPI MADT
On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
On 10 June 2015 at 10:52, Andrew Jones drjo...@redhat.com wrote:
Signed-off-by: Andrew Jones drjo...@redhat.com
Tested-by: Shannon Zhao shannon.z
cacheflush is an arm-specific syscall that qemu built for arm
uses. Add it to the whitelist.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
I'm not sure about the priority selection. Maybe cacheflush gets
used frequently enough that it deserves a higher one?
This patch isn't really
On Tue, Jun 30, 2015 at 01:18:49PM -0400, Paul Moore wrote:
On Tuesday, June 30, 2015 06:07:40 PM Peter Maydell wrote:
On 30 June 2015 at 18:01, Paul Moore pmo...@redhat.com wrote:
I'm starting to wonder if the 32-bit ARM build system didn't have
__NR_cacheflush defined in the system
On Mon, Jun 29, 2015 at 04:24:55PM -0400, Paul Moore wrote:
On Monday, June 29, 2015 07:47:29 PM Andrew Jones wrote:
On Mon, Jun 29, 2015 at 10:53:14AM -0400, Paul Moore wrote:
On Monday, June 29, 2015 09:50:17 AM Andrew Jones wrote:
On Fri, Jun 26, 2015 at 04:26:22PM -0400, Paul Moore
On Mon, Jun 29, 2015 at 10:53:14AM -0400, Paul Moore wrote:
On Monday, June 29, 2015 09:50:17 AM Andrew Jones wrote:
On Fri, Jun 26, 2015 at 04:26:22PM -0400, Paul Moore wrote:
Perhaps a stupid question, but you did verify that it is cacheflush that
is causing the problem? The seccomp
On Mon, Jun 29, 2015 at 07:51:15PM +0200, Claudio Fontana wrote:
Hello,
while heavily testing PSCI on QEMU+KVM during OSv enablement, I encountered,
among others, the following issue:
I am running a test in which I boot an OS at EL1 under KVM, then boot a
secondary VCPU,
then
On Fri, May 22, 2015 at 06:08:30PM -0700, Mario Smarduch wrote:
On 05/18/2015 08:53 AM, Catalin Marinas wrote:
On Thu, May 14, 2015 at 02:46:44PM +0100, Andrew Jones wrote:
On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew
On Wed, May 20, 2015 at 07:29:28PM -0700, Mario Smarduch wrote:
On 05/15/2015 10:04 AM, Andrew Jones wrote:
On Fri, May 15, 2015 at 08:02:59AM -0700, Christoffer Dall wrote:
On Thu, May 14, 2015 at 03:32:13PM +0200, Andrew Jones wrote:
On Thu, May 14, 2015 at 12:55:49PM +0200, Christoffer
On Thu, Aug 20, 2015 at 12:21:31PM +0100, Leif Lindholm wrote:
On Thu, Aug 20, 2015 at 07:09:57PM +0800, Shannon Zhao wrote:
Could somebody who understands ACPI and the ramifications
here let me know if I should apply this patch, please?
(since we're now post-2.4)
I presume my opinion
On Fri, Jun 26, 2015 at 04:26:22PM -0400, Paul Moore wrote:
On Friday, June 26, 2015 06:03:18 PM Andrew Jones wrote:
On Tue, Jun 16, 2015 at 02:16:03PM +0100, Peter Maydell wrote:
On 16 June 2015 at 14:12, Andrew Jones drjo...@redhat.com wrote:
Can we now revert this revert, along
On Tue, Jul 28, 2015 at 02:32:45AM +0200, Marc-André Lureau wrote:
From: Marc-André Lureau marcandre.lur...@gmail.com
As pointed out on the ML by Andrew Jones, glibc no longer permits
creating POSIX shm on hugetlbfs directly. When given a hugetlbfs path,
create a shareable file
On Tue, Jul 28, 2015 at 02:32:54AM +0200, Marc-André Lureau wrote:
From: Marc-André Lureau marcandre.lur...@gmail.com
Instead of handling allocation, teach ivshmem to use a memory backend.
This allows to use hugetlbfs backed memory now.
Signed-off-by: Marc-André Lureau
Bennée alex.ben...@linaro.org
Reviewed-by: Andrew Jones drjo...@redhat.com
To work with mkstandalone (which is in upstream's next branch), we need
some additions to this patch. See
https://github.com/rhdrjones/kvm-unit-tests/commit/be290c1d49c72dd100ab066a11c4ef6fa9017a1c
Thanks,
drew
On Fri, Jul 31, 2015 at 09:17:12PM +0200, Andrew Jones wrote:
On Fri, Jul 31, 2015 at 04:53:59PM +0100, Alex Bennée wrote:
From: Alex Bennée a...@bennee.com
The previous $(getconf _NPROCESSORS_CONF) isn't correct as the default
maximum VCPU configuration is 4 on arm64 machines which
On Fri, Jul 31, 2015 at 04:53:50PM +0100, Alex Bennée wrote:
Hi,
This is the current state of my MTTCG tests based on the KVM's unit
testing framework. The earlier patches in the series have already been
reviewed and will (with the exception of the emacs patch) be making
their way upstream.
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