When testing large LMB sizes (eg 4GB), I found a couple of places
that assume they are 32bit in size.
Signed-off-by: Anton Blanchard
---
hw/ppc/spapr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a1b06defe6..0ba2526215 100644
Hi,
> I've now had a bit of time to look through this and I believe it is
> correct, so:
>
> Reviewed-by: Mark Cave-Ayland
Thanks Mark. David: any chance we could get this merged? I can't run a
recent Ubuntu image successfully without it. sshd hangs when I try to
ssh into it.
Thanks,
Anton
We were using set_cpu_vsr*() when we should have used get_cpu_vsr*().
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 4 ++--
1 file changed, 2 insert
Hi Mark,
> Following on from this I've just gone through the load/store
> operations once again and spotted two things:
>
>
> 1) VSX_LOAD_SCALAR_DS has an extra get_cpu_vsrh() which can be removed
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c
for the suggestions.
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 68 -
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 4b7627f53b..cdb44b8b70 100644
xxspltib raises a VMX or a VSX exception depending on the register
set it is operating on. We had a check, but it was backwards.
Fixes: f113283525a4 ("target-ppc: add xxspltib instruction")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 8
1 file
Hi Alexey,
> Out of curiosity - how did you find this one and (especially) the next
> one - "Fix xxspltib"? Is there some testsuite, or by just looking at
> the code? Thanks,
I'm running test cases and comparing results between QEMU and real
hardware.
Thanks,
Anton
A recent cleanup changed the pre zeroing of the result from 64 bit
to 32 bit operations:
-result.u64[i] = 0;
+result.VsrW(i) = 0;
This corrupts the result.
Fixes: 60594fea298d ("target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in
int_helper.c")
Signed-off
The immediate field is 6 bits, not 5.
Fixes: 217f6b88058f ("target-ppc: add dtstsfi[q] instructions")
Signed-off-by: Anton Blanchard
---
target/ppc/internal.h | 2 ++
target/ppc/translate/dfp-impl.inc.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --gi
vslv and vsrv are broken on little endian, we append 00 to the
high byte not the low byte. Fix it by using the VsrB() accessor.
Signed-off-by: Anton Blanchard
---
target/ppc/int_helper.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/int_helper.c b
During the conversion these instructions were incorrectly treated as
stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/tra
We should only look at 5 bits of each byte, not 6.
Fixes: 3e00884f4e9f ("target-ppc: add vrldnmi and vrlwmi instructions")
Signed-off-by: Anton Blanchard
---
target/ppc/int_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/ppc/int_
We were using set_cpu_vsr* when we should have used set_cpu_vsrl*
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 4 ++--
1 file changed, 2 insert
xxspltib raises a VMX or a VSX exception depending on the register
set it is operating on. We had a check, but it was backwards.
Fixes: f113283525a4 ("target-ppc: add xxspltib instruction")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 9 +
1 file
Fix a typo in xvxsigdp where we put both results into the lower
doubleword.
Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Fix a typo in xxbrq and xxbrw where we put both results into the lower
doubleword.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 4 ++--
1 file
From: Anton Blanchard <an...@samba.org>
The mcrf emulation code was looking at the CR fields in the reverse
order. It also relied on reserved fields being zero which is somewhat
fragile, so fix that too.
Cc: sta...@vger.kernel.org
Signed-off-by: Anton Blanchard <an...@samba.org&g
From: Anton Blanchard <an...@samba.org>
gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus
is the wrong size. Fix it.
Signed-off-by: Anton Blanchard <an...@samba.org>
Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support")
---
target/ppc/arch
Hi Thomas,
> So if you like, I can try to come up with a small patch series that
> cleans up this mess - and I could also include an updated versions of
> Anton's patch there unless he wants to redo the changes on his own...?
Thanks for looking at this. I'm travelling (stuck in an airport at the
Hi David,
> I take it float_round_ties_away is the same thing the architecture
> refers to as "round to Nearest Away"?
Yeah. I noticed it when 0.5 got rounded to 0 on QEMU and 1.0 on real
hardware.
Anton
From: Anton Blanchard <an...@samba.org>
xsrdpi, xvrdpi and xvrspi use the round ties away method, not round
nearest even.
Signed-off-by: Anton Blanchard <an...@samba.org>
---
target-ppc/fpu_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Hi,
> From: Benjamin Herrenschmidt
>
> We were always advertising only 4K & 16M. Additionally the code wasn't
> properly matching the page size with the PTE content, which meant we
> could potentially hit an incorrect PTE if the guest used multiple
> sizes.
>
>
Hi rth,
> In 63ae0915f8ec, I arranged to use a 32-bit rotate, without
> considering the effect of a mask value that wraps around to
> the high bits of the word.
Thanks, that passes my tests.
Tested-by: Anton Blanchard <an...@samba.org>
Anton
> Signed-off-by: Ri
Hi,
> > > Bother. I've tentatively put a revert into ppc-for-2.7. Richard,
> > > do you have a better idea how to fix it?
> >
> > Please try the following.
>
> Thanks! This passes my tests. Feel free to add:
>
> Tested-by: Anton Blanchard <
Hi rth,
> > Bother. I've tentatively put a revert into ppc-for-2.7. Richard,
> > do you have a better idea how to fix it?
>
> Please try the following.
Thanks! This passes my tests. Feel free to add:
Tested-by: Anton Blanchard <an...@samba.org>
Anton
Hi,
> From: Richard Henderson
>
> A 32-bit rotate insn is more common on hosts than a deposit insn,
> and if the host has neither the result is truely horrific.
>
> At the same time, tidy up the temporaries within these functions,
> drop the over-use of "likely", drop some
From: Anton Blanchard <an...@samba.org>
There are a few issues with our handling of the ibm,pa-features
TM bit:
- We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
- In full emulation we have a minimal implementation of TM that always
fai
From: Anton Blanchard <an...@samba.org>
We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so
add the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Anton Blanchard <an...@samba.org>
---
diff --git a/include/elf.h b/include/elf.h
index 28d448b..8533b2a 100644
--- a/include
We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
Signed-off-by: Anton Blanchard <an...@samba.org>
---
v2: Fix build with CONFIG_KVM disabled, noticed by Alex.
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b69995e..dc3e3c9 100644
--- a/hw/ppc/spapr.c
instructions and it dies trying.
This (together with a QEMU patch) fixes PR KVM, which doesn't currently
support TM.
Signed-off-by: Anton Blanchard <an...@samba.org>
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/prom.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
scan_features() updates cpu_user_features but not cpu_user_features2.
Amongst other things, cpu_user_features2 contains the user TM feature
bits which we must keep in sync with the kernel TM feature bit.
Signed-off-by: Anton Blanchard <an...@samba.org>
Cc: sta...@vger.kernel.org
---
MMU-related features")
Signed-off-by: Anton Blanchard <an...@samba.org>
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/prom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 7030b03..9a3a7c6 100644
--- a/arc
the user CPU feature bits.
Without this patch userspace processes will think they can execute
TM instructions and get killed when they try.
Signed-off-by: Anton Blanchard <an...@samba.org>
Cc: sta...@vger.kernel.org
---
Michael I've added stable here because I'm seeing this on a number
of d
We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
Signed-off-by: Anton Blanchard <an...@samba.org>
---
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e7be21e..538bd87 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -696,6 +696,12 @@ stati
Hi Alexey,
> > I can't get an Ubuntu Wily guest to boot on an Ubuntu Wily host in
> > PR KVM mode. The kernel in both cases is 4.2. To reproduce:
> >
> > wget -N
> > https://cloud-images.ubuntu.com/wily/current/wily-server-cloudimg-ppc64el-disk1.img
> >
> > qemu-system-ppc64 -cpu POWER8
-by: Anton Blanchard an...@samba.org
---
linux-user/main.c| 2 +-
target-ppc/excp_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index c855bcc..9100130 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1650,7
Hi Alex,
On 24.03.15 09:59, Anton Blanchard wrote:
Add the XML and functions to get and set VSX registers.
Awesome, thanks. Have you verified that this works for LE as well as
BE guests?
Unfortunately all our XML gdbstub routines have endian issues (FPU,
Altivec and now VMX). I only
Add the XML and functions to get and set VSX registers.
Signed-off-by: Anton Blanchard an...@samba.org
---
configure | 6 +++---
gdb-xml/power-vsx.xml | 44
target-ppc/translate_init.c | 22 ++
3 files
Initialise our maximum page size capability to 64kB and increase
the page_size variable from 16 to 32 bits.
Signed-off-by: Anton Blanchard an...@samba.org
--
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 1327658..aa1ed98 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -811,6 +811,7
-by: Anton Blanchard an...@samba.org
---
Index: b/hw/ppc/spapr.c
===
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -362,10 +362,6 @@ static void *spapr_create_fdt_skel(hwadd
_FDT((fdt_property_string(fdt, model, IBM pSeries (emulated
Scubbing our ppc64 bugs. Thanks for the update Ken, I'll close this.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/965327
Title:
virtio-pci: can't reserve io 0x-0x001f
Status in QEMU:
New
The last 8 bytes of the buffer list is defined to contain the number
of dropped frames. At the moment we use it to store rx entries,
which trips up ethtool -S:
rx_no_buffer: 9223380832981355136
Fix this by skipping the last buffer list entry.
Signed-off-by: Anton Blanchard an...@samba.org
Hi Tom,
This patch series addresses bugs in the recently added VSX
instructions. Two general defects are fixed:
Thanks! This series fixes the issue I had with wget.
Tested-by: Anton Blanchard an...@samba.org
Anton
POWER8 supports isel, so enable it in QEMU.
Signed-off-by: Anton Blanchard an...@samba.org
Signed-off-by: Cédric Le Goater c...@fr.ibm.com
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
Remove MSR_POW from the msr_mask for POWER7/7+/8.
Signed-off-by: Anton Blanchard an...@samba.org
Signed-off-by: Cédric Le Goater c...@fr.ibm.com
---
target-ppc/translate_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc
Add MSR_LE to the msr_mask for POWER8.
Signed-off-by: Anton Blanchard an...@samba.org
Signed-off-by: Cédric Le Goater c...@fr.ibm.com
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
Most of the PMU SPRs were wrong on Book3S.
Signed-off-by: Anton Blanchard an...@samba.org
---
target-ppc/cpu.h| 29 -
target-ppc/translate_init.c | 139 +++-
2 files changed, 153 insertions(+), 15 deletions(-)
diff --git a/target-ppc
Without MSR_VSX we die early during a Linux boot.
Signed-off-by: Anton Blanchard an...@samba.org
Signed-off-by: Cédric Le Goater c...@fr.ibm.com
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc
970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
it 3 times, and simplify the existing code.
Signed-off-by: Anton Blanchard an...@samba.org
---
target-ppc/translate_init.c | 89 -
1 file changed, 39 insertions(+), 50 deletions(-)
diff
Since an OS can set LPCR_ILE we must clear it during reset. Otherwise
if we reset into an OS with a different endian we die when we take
the first exception.
This fixes an issue seen on both full emulation and KVM.
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/hw/ppc/spapr.c
Add MSR_LE to the msr_mask for POWER8.
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3eafbb0..7661543 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7173,7 +7173,7 @@ POWERPC_FAMILY
POWER8 supports isel, so enable it in QEMU.
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3eafbb0..7661543 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7156,7 +7156,7
Without MSR_VSX we die early during a Linux boot.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate_init.c
===
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7117,7 +7117,7
Remove MSR_POW from the msr_mask for POWER7/7+/8.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate_init.c
===
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7074,7 +7074,7
The DAR and DSISR can be very useful when debugging issues, so add
them to ppc_cpu_dump_state. We had another bug in this area: all
of the v2.06 MMU types were missing.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate.c
-by: Tom Musta tommu...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/cpu.h
===
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -549,6 +549,8 @@ enum {
POWERPC_FLAG_BUS_CLK = 0x0002,
/* Has
...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/cpu.h
===
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -236,6 +236,8 @@ enum {
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint
From: Tom Musta tommu...@gmail.com
This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.
Signed-off-by: Tom Musta tommu...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
[]. And the second 32 VSRs
are already defined via the cpu_avrh[] and cpu_avrl[] arrays.
Signed-off-by: Tom Musta tommu...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
From: Tom Musta tommu...@gmail.com
This patch adds the lxvd2x instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc
tommu...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7039,10 +7039,28 @@ static void gen_stxvd2x(DisasContext *ct
From: Tom Musta tommu...@gmail.com
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Try loading the kernel as little endian if it fails big endian.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Reviewed-by: Anton Blanchard an...@samba.org
---
Index: b/hw/ppc/spapr.c
(qemu) print $dar
(qemu) print $dsisr
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Anton Blanchard an...@samba.org
---
Index: b/monitor.c
===
--- a/monitor.c
+++ b/monitor.c
@@ -3186,6 +3186,9 @@ static const
ordering then
VRT[8*eb:8*eb+15] -- MEM(EA,2)
else
VRT[112-(8*eb):127-(8*eb)] -- MEM(EA,2)
This patch adds the element inversion, as described in the last line
of the RTL.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Anton Blanchard an...@samba.org
---
Index: b
is the endianness a guest takes its exceptions in.
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 16bfab9..de639f6 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -262,7 +262,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
uint32_t
to signal back to the qemu-char layer that we are
ready for more input. Without this we block until something
else kicks us (eg network activity).
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/hw/char/spapr_vty.c
Hi,
The distinction is important in QEMU. ppc64 is still
TARGET_WORDS_BIGENDIAN. We still want most stl_phys to treat
integers as big endian. There's just this extra concept that CPU
loads/stores are sometimes byte swapped. That affects virtio but
not a lot else.
You've
This patchset adds support for 64bit PowerPC little endian on POWER7.
Linux kernel patches to support this were sent out earlier today:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-August/109849.html
Anton
--
Anton Blanchard (4):
target-ppc: POWER7 supports the MSR_LE bit
target
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Try loading the kernel as little endian if it fails big endian.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Anton Blanchard an...@samba.org
---
hw/ppc/spapr.c | 13 -
1 file changed, 12
Add MSR_LE to the msr_mask for POWER7.
Signed-off-by: Anton Blanchard an...@samba.org
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b14aec8..33914bc 100644
--- a/target-ppc
H_SET_MODE is used for controlling various partition settings. One
of these settings is the endianness a guest takes its exceptions in.
Signed-off-by: Anton Blanchard an...@samba.org
---
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_hcall.c | 44
On POWER7, LPCR_ILE is used to control what endian guests take
their exceptions in so use it instead of MSR_ILE.
Signed-off-by: Anton Blanchard an...@samba.org
---
target-ppc/cpu.h | 2 ++
target-ppc/excp_helper.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target
Use info-endian to select the endian of the instruction to
be disassembled.
Signed-off-by: Anton Blanchard an...@samba.org
---
disas/ppc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/ppc.c b/disas/ppc.c
index c149506..99c4cbc 100644
--- a/disas/ppc.c
+++ b/disas
.
Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/tcg/ppc64/tcg-target.c
===
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg
Hi,
qemu is currently broken on ppc64. After applying the following patches
I am able to boot a ppc64 and x86-64 image successfully.
Anton
add2_i64 was adding the lower double word to the upper double word
of each input. Fix this so we add the lower double words, then the
upper double words with carry propagation.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard an...@samba.org
---
sub2 has similar issues, I haven't fixed
rotr_i32 calculates the amount to left shift and puts it into a
temporary, but then doesn't use it when doing the shift.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/tcg/ppc64/tcg-target.c
If our input and output is in the same register, bswap64 tries to
undo a rotate of the input. This just ends up rotating the output.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 0fcf2b5..64fb0af
The rldcl instruction doesn't have an sh field, so the minor opcode
of 8 is actually 4 when using the XO30 macro.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/tcg/ppc64/tcg-target.c
) at 0710
Signed-off-by: Anton Blanchard an...@au1.ibm.com
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4005,19 +4005,19 @@ static inline void gen_op_mfspr(DisasCon
Recent Linux kernels save and restore the PPR across exceptions
so we need to handle it.
Signed-off-by: Anton Blanchard an...@au1.ibm.com
---
Index: b/target-ppc/translate_init.c
===
--- a/target-ppc/translate_init.c
+++ b/target
82 matches
Mail list logo