duardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 145 +-
target/i386/cpu.h | 14 +++--
2 files changed, 75 insertions(+), 84 deletions(-)
diff --git a/target/i386/cpu.c b/targe
ious cache structures to legacy_*. If there is any change in
the cache information, then it needs to be initialized in builtin_x86_defs.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
include/hw/i386/pc.h | 5 +++
tar
Add pc-q35-2.13 and pc-i440fx-2.13 machine types
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
hw/i386/pc_piix.c| 15 ---
hw/i386/pc_q35.c | 13 +++--
include/hw/i386/pc.h | 3 +++
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc_
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McR
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable TOPOEXT feature for legacy (2.12 or older) machine types.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfi
Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (6):
pc: add 2.13 machine types
i386: Add new property to control cache info
i386: Populate AMD Processor Cache Information for cpuid 0x801D
i386: Add support for CPUID_8000_001E for AMD
i386: Enabl
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com&
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
The property legacy-cache will be used to control the cache information.
If user passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information. Otherwise
use the statically loaded cache definitions if available.
Signed-off-by:
8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (7):
i386: Add cache information in X86CPUDefinition
i386: Add new property to control cache info
i386: Initialize cache infor
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
Reviewed-by: Eduardo Habkost <ehabk...@redhat.com>
---
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McR
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
Reviewed-by: Eduardo Habkost <ehabk...@redhat.com>
---
target/i386/cpu.c | 1 +
target/i386/cpu.h | 7 +++
2 files cha
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a
encode
CPUID leaves for a cache.
This will help us ensure consistency between cache information
CPUID leaves, and make the existing inconsistencies in CPUID info
more visible.
Signed-off-by: Eduardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by:
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com&
eric non-intel check and made a separate patch
with some changes(Patch 5).
3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (4):
i386: Populate A
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
ciativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (4):
i386: Populate AMD Processor Cache Information for cpuid 0x801D
i386: Add support for CPUID_8000_001E for AMD
i386: Enable TOPOEXT feature on AMD EPYC CPU
i386: Remove generic SMT thread check
Eduardo Habkos
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com&
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
match the underlying hardware. Please refer to the Processor Programming
Reference (PPR) for AMD Family 17h Model for more details.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable TOPOEXT feature for legacy machines and also disable
TOPOEXT feature if the config cannot be supported.
Signed-off-by: Babu Moger <babu.mo...@amd.
-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 117 ++
target/i386/kvm.c | 29 --
2 files changed, 143 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5c9bdc9..0d423e5 100644
--- a/
duardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 117 +++---
target/i386/cpu.h | 14 ---
2 files changed, 67 insertions(+), 64 deletions(-)
diff --git a/target/i386/cpu.c b
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable TOPOEXT feature for legacy machines and also disable
TOPOEXT feature if the config cannot be supported.
Signed-off-by: Babu Moger <babu.mo...@amd.
duardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 117 +++---
target/i386/cpu.h | 14 ---
2 files changed, 67 insertions(+), 64 deletions(-)
diff --git a/target/i386/cpu.c b
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
match the underlying hardware. Please refer Processor Programming Reference
(PPR) for AMD Family 17h Model for more details.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com&
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 17
Introduce the auto_topoext bit to to control topoext feature.
Also add new field auto_topoext(in X86CPUDefinition). This will
be used to enable topoext on newer CPU models where topoext can
be supported.
Signed-off-by: Babu Moger
---
include/hw/i386/pc.h | 4
target/i386/cpu.c| 12
D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (5):
i386: Add support for CPUID_8000_001E for AMD
i386: Introduce auto_topoext bit to manage topoext
i386: Enable TOPOEXT feature on AMD EPYC CPU
i386: Verify and en
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
TOPOEXT feature is disabled for legacy machines.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386
If the CPU model supports topoext feature, enabled the
feature automatically if it can be supported.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 40
1 file changed, 40 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4dd9a82
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
match the underlying hardware. Please refer to the Processor Programming
Reference (PPR) for AMD Family 17h Model for more details.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 86
On 06/12/2018 02:05 PM, Eduardo Habkost wrote:
On Tue, Jun 12, 2018 at 06:38:08PM +, Moger, Babu wrote:
[...]
I'm starting to think that enabling TOPOEXT automatically is
adding too much complexity and compatibility problems, and it's
better to leave this task to management software.
atch 2 and 3).
2.Removed the generic non-intel check and made a separate patch
with some changes(Patch 5).
3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Ba
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable topoext on PC_COMPAT_2_12 and keep xlevel 0x800a.
Signed-off-by: Babu Moger
---
include/hw/i386/pc.h | 8
target/i386/cpu.c| 10 ++
2
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 17
here. We can achieve this by shifting the bits.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7a4484b..5246be4 100644
--- a/target/i386/cpu.c
+++ b/target/i386
1D and 0x801E (Patch 2 and 3).
2.Removed the generic non-intel check and made a separate patch
with some changes(Patch 5).
3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on A
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 17
the node id to make this work. We can achieve this by shifting the
socket_id bits left to address more nodes.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable topoext on PC_COMPAT_2_12 and keep xlevel 0x800a.
Signed-off-by: Babu Moger
---
include/hw/i386/pc.h | 8
target/i386/cpu.c| 10 ++
2
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
Disable TOPOEXT feature for older machines.
Signed-off-by: Babu Moger
---
include/hw/i386/pc.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 04d1f8c..ecccf6b 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -303,6
Disable the TOPOEXT feature if it cannot be supported.
We cannot support this feature with more than 2 nr_threads
or more than 32 cores in a socket.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/i386
Enabling TOPOEXT feature might cause compatibility issues if
older kernels does not set this feature. Lets set this feature
unconditionally.
Signed-off-by: Babu Moger
---
target/i386/kvm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index
Add new function topology_supports_topoext to verify
if we can support topoext feature. Will be used to enable/disable
topoext feature.
Signed-off-by: Babu Moger
---
accel/tcg/user-exec-stub.c | 5 +
cpus.c | 13 +
include/qom/cpu.h | 9
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 17
D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (6):
i386: Set TOPOEXT unconditionally for comapatibility
i386: Enable TOPOEXT feature on AMD EPYC CPU
i386: Disable TOPOEXT feature on pc-2.12
cpus: Add new function t
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable TOPOEXT feature for legacy machines.
Signed-off-by: Babu Moger
---
include/hw/i386/pc.h | 4
target/i386/cpu.c| 11 +--
2 files changed, 13
ges(Patch 5).
3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (4):
i386: Add support for CPUID_8000_001E for AMD
i386: Verify if topoext feature can be
topoext feature cannot be supported in certain cases
with large number of cores or threads. Add the check.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 86fb1a4
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
match the underlying hardware. Please refer to the Processor Programming
Reference (PPR) for AMD Family 17h Model for more details.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 86
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 17
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
for compatibility.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
include/hw/i386/pc.h | 4
target/i386/cpu.c| 1 +
target/i386/cpu.h| 5 +
3 files changed, 10 insertions(+)
diff --git a/include/hw/i386/pc.h b/i
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McR
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 4
target/i386/cpu.h | 8
2 files changed, 12 insertions(+)
diff --git a/target/i386/cp
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 11 +--
1 file changed,
encode
CPUID leaves for a cache.
This will help us ensure consistency between cache information
CPUID leaves, and make the existing inconsistencies in CPUID info
more visible.
Signed-off-by: Eduardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by:
).
2.Removed the generic non-intel check and made a separate patch
with some changes(Patch 5).
3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (8):
i386: A
Use the statically loaded cache definitions if available
and legacy-cache parameter is not set.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 22 +-
1 file changed, 17 insertions(+),
Hi Stanislav,
I am working on to support hyperthreading feature on kvm/qemu guests for
AMD EPYC family of processors. I saw your patch series
https://patchwork.ozlabs.org/patch/834022/.
I am planning to refresh these patches with few changes. Let me know
if it is fine with you.
Thanks
Babu
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 13 -
1 file chan
feature on AMD EPYC CPU.
Babu Moger (3):
target/i386: Fix instruction cache associativity for AMD
target/i386: Enable TOPOEXT feature on AMD EPYC CPU
target/i386: Remove generic SMT thread check
Stanislav Lanci (2):
target/i386: Populate AMD Processor Cache Information
target/i386: Add
Per Processor Programming Reference, CPUID_Fn8005_EDX should
report L1 instruction cache associativity as 4(way) instead of 2(way).
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/c
nci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 31ee746dac..52591a1486 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3219,
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. These are supported via
CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff
From: Stanislav Lanci <p...@polepetko.eu>
Adds information about cache size and topology from cpuid 0x801D leaf
for different cache types on AMD processors.
Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
targ
Posted few patches to support this feature on AMD EPYC processors. Feel free to
test and review.
1. Kernel kvm patch
https://patchwork.kernel.org/patch/10190107/
2. qemu patches
https://patchwork.kernel.org/project/qemu-devel/list/?submitter=178527
Thanks
--
You received this bug
just to be clear.. The kernel kvm patch is rebased on linux-next. If you
are on older kernel then try this kernel patch.
https://patchwork.kernel.org/patch/10031775/ plus qemu patch.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
Changed KVM_CPUID_FLAG_SIGNIFCANT_INDEX to KVM_CPUID_FLAG_SIGNIFICANT_INDEX
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
linux-headers/asm-x86/kvm.h | 2 +-
target/i386/kvm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-headers/asm-x86/k
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 15 +--
1 file chan
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
These are supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 5 +++--
1 file changed, 3 inse
nci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a5a480e..191e850 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3666,6 +3666,14 @@
4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (3):
target/i386: Fix a minor typo found while reviwing
target/i386: Enable TOPOEXT feature on AMD EPYC CPU
target/i386: Remove
From: Stanislav Lanci <p...@polepetko.eu>
Adds information about cache size and topology from cpuid 0x801D leaf
for different cache types on AMD processors.
Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
targ
Model for more details.
Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 65 +++
target/i386/kvm.c | 29 ++---
2 files changed, 91 insertio
nci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5fdbedd..ba63d0c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3655,6 +3655,13 @@
Generalize some of the macro definitions which are generic cache
properties that are common between CPUID 4 and CPUID 0x801D
in preparation for adding support for 0x801D.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.
XT feature on AMD EPYC CPU.
Babu Moger (3):
target/i386: Generalize some of the macro definitions
target/i386: Enable TOPOEXT feature on AMD EPYC CPU
target/i386: Remove generic SMT thread check
Stanislav Lanci (2):
target/i386: Populate AMD Processor Cache Information
target/i386: A
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/c
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 15 +--
1 file chan
Use the statically loaded cache definitions if available
and legacy-cache parameter is not set.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 22 +-
1 file changed, 17 insertions(+),
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McR
for compatibility.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
include/hw/i386/pc.h | 4
target/i386/cpu.c| 1 +
target/i386/cpu.h| 5 +
3 files changed, 10 insertions(+)
diff --git a/include/hw/i386/pc.h b/i
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 4
target/i386/cpu.h | 8
2 files changed, 12 insertions(+)
diff --git a/target/i386/cp
ty.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (8):
i386: Add cache information in X86CPUDefinition
i386: Initialize cache information for EPYC family processors
i386: Add new property to control cache info
i386: Use the statically loaded cache definitions
i386: Populate A
encode
CPUID leaves for a cache.
This will help us ensure consistency between cache information
CPUID leaves, and make the existing inconsistencies in CPUID info
more visible.
Signed-off-by: Eduardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by:
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
---
target/i386/cpu.c | 11 +--
1 file changed,
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
encode
CPUID leaves for a cache.
This will help us ensure consistency between cache information
CPUID leaves, and make the existing inconsistencies in CPUID info
more visible.
Signed-off-by: Eduardo Habkost <ehabk...@redhat.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
targe
4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (8):
i386: Add cache information in X86CPUDefinition
i386: Initialize cache information for EPYC family processors
i386: Add new
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 4
target/i386/cpu.h | 8
2 files changed, 12 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index da59dc4..eec4a97
1 - 100 of 385 matches
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