Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 15 +--
1 file chan
Use the statically loaded cache definitions if available
and legacy-cache parameter is not set.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/c
This will be used to control the cache information.
By default new information will be displayed. If user
passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
include/
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/
nci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1485175..555ab83 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3666,6 +3666,15 @@
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 15 +--
1 file chan
Generalize some of the macro definitions which are generic cache
properties that are common between CPUID 4 and CPUID 0x801D
in preparation for adding support for 0x801D.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.
ntel check and made a separate patch
with some changes(Patch 5).
3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03.
Added 2 more patches.
Patch 1. Fixes cache associativity.
Patch 4. Adds TOPOEXT feature on AMD EPYC CPU.
Babu Moger (3):
target/i386: Generalize some of
Model for more details.
Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 76 +++
target/i386/kvm.c | 29 ++---
2 files changed, 102 insertio
Add function pointer apic_id_from_topo_ids in PCMachineState.
Initialize with correct handler based on the mode selected.
Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids
for consistency. x86_apicid_from_topo_ids will be the default handler.
Signed-off-by: Babu Moger
Add function pointers in PCMachineState to handle apic id specific
functionalities. This will be used to initialize with correct handlers based on
the cpu model selected.
x86_apicid_from_cpu_idx will be default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 -
include
Introduce last level cache id(llc_id) in x86CPU topology. This information is
required to build the topology in EPIC mode.
Signed-off-by: Babu Moger
---
hw/core/machine-hmp-cmds.c |3 +++
hw/core/machine.c | 13 +
hw/i386/pc.c | 10 ++
include
Now that we have all the parameters in X86CPUTopoInfo, we can just pass the
structure to calculate the offsets and width.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 64 ++--
target/i386/cpu.c | 23
2 files
This is an effort to re-arrange few data structure for better readability.
Add X86CPUTopoInfo which will have all the topology informations required
to build the cpu topology. There is no functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 40
are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors.
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 93
1 file changed, 93
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e87487bae3..0eaedeb848 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4456,7 +4456,7 @@ void cpu_x86_cpuid
Introduce following handlers for new epyc mode.
x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index.
x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id.
x86_apicid_from_topo_ids_epyc: Generate apicid from topo ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c
binations to make things are working as
expected.
5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
supported only on AMD EPYC models. I may need some guidance on that.
v1:
https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.mo...@amd.com/
---
B
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162
Add function pointer topo_ids_from_apicid in PCMachineState.
Initialize with correct handler based on mode selected.
x86_apicid_from_cpu_idx will be the default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 13 +++--
include/hw/i386/pc.h |2 ++
2 files changed, 9
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger
---
tests/test-x86-cpuid.c | 115
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test
Add a new function init_apicid_fn in MachineClass to initialize the mode
specific handlers to decode the apic ids.
Signed-off-by: Babu Moger
---
include/hw/boards.h |1 +
vl.c|3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
Initialize all the parameters in one function initialize_topo_info.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 8c23b1e8c9
Add CPUX86Family type in CPUX86State. This will be used to differentiate
generic x86 and x86 EPYC based cpu models.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |4
target/i386/cpu.c |1 +
target/i386/cpu.h |7 +++
3 files changed, 12 insertions(+)
diff --git a/hw/i386
nodes are
configured. So, save the cpu indexes and move the cpu initialization inside the
numa_complete_configuration. Cpu initialization is done in new function
numa_node_complete_configuration.
Signed-off-by: Babu Moger
---
hw/core/numa.c| 62
Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg. This
is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |4
include/hw/i386/topology.h |1 +
target/i386/cpu.c |1 +
target/i386/cpu.h
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/core/machine.c
uild the cpu topology. There is no
>> functional changes.
>>
>> Signed-off-by: Babu Moger
>> ---
>> hw/i386/pc.c | 40 +++-
>> include/hw/i386/topology.h | 40 ++--
>>
uild the cpu topology. There is no
>> functional changes.
>>
>> Signed-off-by: Babu Moger
>> ---
> [...]
>> +typedef struct X86CPUTopoInfo {
>> +unsigned numa_nodes;
>> +unsigned nr_sockets;
>> +unsigned nr_dies;
>> +unsign
fied apic id decoding in v3 version. We don't need these changes
anymore.
>
>>
>> The function machine_set_cpu_numa_node will fail to find a match to assign
>> the node. Added new function machine_set_cpu_numa_node_epyc to set the
>> node_id
>> directly in epyc mode.
&g
; }
>
> void numa_node_complete_configuration(MachineState *ms, NodeInfo *node)
> {
> for (cpu_index = node->cpu_indexes; cpu_index; cpu_index =
> cpu_index->next) {
> CpuInstanceProperties props;
> props = mc->cpu_index_to_instance_props(ms, cpu_in
On 10/10/19 9:32 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:12:11PM +, Moger, Babu wrote:
>> Some parameters are unnecessarily passed for offset/width
>> calculation. Remove those parameters from function prototypes.
>> No functional change.
>>
&
l use these functions to build the topology.
>>
>> The topology details are available in Processor Programming Reference (PPR)
>> for AMD Family 17h Model 01h, Revision B1 Processors.
>> It is available at https://www.amd.com/en/support/tech-docs
>>
>> Signed-off-by:
Damir,
We normally test Linux guests here. Can you please give me exact qemu command
line. Even the SMP parameters(sockets,cores,threads,dies) will also work. I
will try to recreate it locally first.
Give me example what works and what does not work.
I have recently sent few more patches to
. At this time smp parameter is already
completed and numa node information is available.
Signed-off-by: Babu Moger
---
hw/i386/x86.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index b825861b85..472dc3eb77 100644
--- a/hw/i386
different combinations to make things are working as
expected.
5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
supported only on AMD EPYC models. I may need some guidance on that.
v1:
https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.mo...@amd.com/
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/core/machine.c
Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg.
This is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |2 ++
include/hw/i386/topology.h |2 ++
include/hw/i386/x86.h
Initialize all the parameters in one function init_topo_info.
Move the data structure X86CPUTopoIDs and X86CPUTopoInfo into
x86.h.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c |4 +---
hw/i386/x86.c | 14 +++---
include/hw
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |4
target/i386/cpu.c |4 ++--
target/i386/cpu.h |1 +
4 files
This is an effort to re-arrange few data structure for better readability.
Add X86CPUTopoInfo which will have all the topology informations required
to build the cpu topology. There is no functional changes.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
hw/i386/pc.c
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |2 +-
include/hw/i386/topology.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c
Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
include/hw/i386/topology.h | 64 ++--
target/i386/cpu.c | 23
ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
Signed-off-by: Babu Moger
---
target/i386/cpu.c |4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 389b68d765..082865d72b 100644
--- a/target/i386/cpu.c
+++ b/ta
Load the model specific handlers if available or else default handlers
will be loaded. Add the model specific handlers if apicid decoding
differs from the standard sequential numbering.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 38 ++
target/i386
Check and Load the apicid handlers from X86CPUDefinition if available.
Update the calling convention for the apicid handlers.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 27 +++
2 files changed, 26 insertions(+), 7 deletions(-)
diff
On 2/24/20 11:19 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:46 -0600
> Babu Moger wrote:
>
>> Check and Load the apicid handlers from X86CPUDefinition if available.
>> Update the calling convention for the apicid handlers.
>
> Previous and this
On 2/24/20 2:50 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:18 -0600
> Babu Moger wrote:
>
>> These functions add support for building EPYC mode topology given the smp
>> details like numa nodes, cores, threads and sockets.
>>
>> The new apic id deco
On 2/24/20 2:34 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:04 -0600
> Babu Moger wrote:
>
>> Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg.
>> This is required to build EPYC mode topology.
>>
>> Signed-off-by: Ba
On 2/24/20 11:01 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:32 -0600
> Babu Moger wrote:
>
>> Introduce model specific apicid functions inside X86MachineState.
>> These functions will be loaded from X86CPUDefinition.
>>
>> Signed-off-by: Babu Moger
On 2/24/20 2:52 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:25 -0600
> Babu Moger wrote:
>
>> Use the new functions from topology.h and delete the unused code. Given the
>> sockets, nodes, cores and threads, the new functions generate apic id for
>>
On 2/25/20 9:32 AM, Eduardo Habkost wrote:
> On Mon, Feb 24, 2020 at 05:13:18PM -0600, Babu Moger wrote:
>>
>>
>> On 2/24/20 4:31 PM, Eduardo Habkost wrote:
>>> On Mon, Feb 24, 2020 at 11:58:09AM -0600, Babu Moger wrote:
>>>>
>>>>
>>&
On 2/24/20 4:31 PM, Eduardo Habkost wrote:
> On Mon, Feb 24, 2020 at 11:58:09AM -0600, Babu Moger wrote:
>>
>>
>> On 2/24/20 11:19 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:17:46 -0600
>>> Babu Moger wrote:
>>>
>>>&
On 2/25/20 1:49 AM, Igor Mammedov wrote:
> On Mon, 24 Feb 2020 11:29:37 -0600
> Babu Moger wrote:
>
>> On 2/24/20 2:52 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:17:25 -0600
>>> Babu Moger wrote:
>>>
>>>> Use the new funct
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162
Update structures X86CPUTopoIDs and CPUX86State to hold the number of
nodes per package. This is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |1 +
include/hw/i386/topology.h |1 +
target/i386/cpu.c
emu-devel/20190731232032.51786-1-babu.mo...@amd.com/
---
Babu Moger (16):
hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
hw/i386: Introduce X86CPUTopoInfo to contain topology info
hw/i386: Consolidate topology functions
machine: Add SMP Sockets in CpuTopology
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c
Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
include/hw/i386/topology.h | 68 ++--
target/i386/cpu.c | 23
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger
---
tests/test-x86-cpuid.c | 115
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
hw/i386/pc.c |2 +-
include/hw/i386/topology.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
X86MachineState.
There is no functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 12 ++--
hw/i386/x86.c | 32
include/hw/i386/topology.h | 38 --
include/hw/i386/x86.h |3
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
Reviewed-by: Igor
The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
So, remove the initialization here.
Suggested-by: Igor Mammedov
Signed-off-by: Babu Moger
---
hw/i386/x86.c |4
1 file changed, 4 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 03b8962c98
Check and Load the apicid handlers from X86CPUDefinition if available.
Update the calling convention for the apicid handlers.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 11 +++
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
target/i386/cpu.c |4 ++--
target/i386/cpu.h |1 +
3 files changed, 4 insertions(+), 2 deletions
are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors. The revision guides are
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
Acked-by: Igor Mammedov
---
include/hw
ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
Signed-off-by: Babu Moger
---
target/i386/cpu.c |4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f33d8b77f5..f870f7c55b 100644
--- a/target/i386/cpu.c
+++ b/ta
Introduce model specific apicid functions inside X86MachineState.
These functions will be loaded from X86CPUDefinition.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |5 +
include/hw/i386/x86.h |9 +
2 files changed, 14 insertions(+)
diff --git a/hw/i386/x86.c b/hw
. At this time smp parameter is already
completed and numa node information is available.
Signed-off-by: Babu Moger
---
hw/i386/x86.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index d46dd4ad9e..66998b065c 100644
--- a/hw/i386
Load the model specific handlers if available or else default handlers
will be loaded. Add the model specific handlers if apicid decoding
differs from the standard sequential numbering.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 34 ++
target/i386/cpu.h
On 2/25/20 1:49 AM, Igor Mammedov wrote:
> On Mon, 24 Feb 2020 11:29:37 -0600
> Babu Moger wrote:
>
>> On 2/24/20 2:52 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:17:25 -0600
>>> Babu Moger wrote:
>>>
>>>> Use the new funct
On 2/24/20 2:18 AM, Igor Mammedov wrote:
> On Fri, 21 Feb 2020 11:51:15 -0600
> Babu Moger wrote:
>
>> On 2/21/20 11:05 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:16:51 -0600
>>> Babu Moger wrote:
>>>
>>>> Initia
On 1/29/20 10:51 AM, Eduardo Habkost wrote:
> On Wed, Jan 29, 2020 at 10:32:01AM -0600, Babu Moger wrote:
>>
>>
>> On 1/29/20 3:14 AM, Igor Mammedov wrote:
>>> On Tue, 28 Jan 2020 13:45:31 -0600
>>> Babu Moger wrote:
>>>
>>>> On 1/28
On 1/29/20 3:14 AM, Igor Mammedov wrote:
> On Tue, 28 Jan 2020 13:45:31 -0600
> Babu Moger wrote:
>
>> On 1/28/20 10:29 AM, Igor Mammedov wrote:
>>> On Tue, 03 Dec 2019 18:37:42 -0600
>>> Babu Moger wrote:
>>>
>>>> Add a new function
On 1/29/20 3:14 AM, Igor Mammedov wrote:
> On Tue, 28 Jan 2020 13:45:31 -0600
> Babu Moger wrote:
>
>> On 1/28/20 10:29 AM, Igor Mammedov wrote:
>>> On Tue, 03 Dec 2019 18:37:42 -0600
>>> Babu Moger wrote:
>>>
>>>> Add a new function
On 1/28/20 2:04 PM, Eduardo Habkost wrote:
> Hi,
>
> Sorry for taking so long. I was away from the office for a
> month, and now I'm finally back.
no worries.
>
> On Tue, Dec 03, 2019 at 06:38:46PM -0600, Babu Moger wrote:
>> Introduce following ha
On 2/4/20 2:02 AM, Igor Mammedov wrote:
> On Mon, 3 Feb 2020 13:31:29 -0600
> Babu Moger wrote:
>
>> On 2/3/20 8:59 AM, Igor Mammedov wrote:
>>> On Tue, 03 Dec 2019 18:36:54 -0600
>>> Babu Moger wrote:
>>>
>>>> This series fixes
On 2/5/20 10:56 AM, Igor Mammedov wrote:
> On Wed, 5 Feb 2020 10:10:06 -0600
> Babu Moger wrote:
>
>> On 2/5/20 3:38 AM, Igor Mammedov wrote:
>>> On Tue, 4 Feb 2020 13:08:58 -0600
>>> Babu Moger wrote:
>>>
>>>> On 2/4/20 2:02 AM, Ig
On 2/6/20 7:08 AM, Igor Mammedov wrote:
> On Wed, 5 Feb 2020 13:07:31 -0600
> Babu Moger wrote:
>
>> On 2/5/20 10:56 AM, Igor Mammedov wrote:
>>> On Wed, 5 Feb 2020 10:10:06 -0600
>>> Babu Moger wrote:
>>>
>>>> On 2/5/20 3:38 AM, Ig
On 2/6/20 9:52 AM, Eduardo Habkost wrote:
> On Thu, Feb 06, 2020 at 12:00:04AM +, Moger, Babu wrote:
>> [AMD Official Use Only - Internal Distribution Only]
>
> Considering that this was posted to qemu-devel, I'm assuming this
> notice was added by accident.
Yes. I noticed that after
On 2/5/20 11:53 PM, Ani Sinha wrote:
>
>
>> On Feb 6, 2020, at 11:16 AM, Ani Sinha wrote:
>>
>>
>>
>>> On Feb 6, 2020, at 5:30 AM, Moger, Babu wrote:
>>>
>>> Ani, I am already working on it.
>>
>> Wow, I see a whole new AMD-Rome CPU model with it’s own cache info data :
>>
>>
On 2/3/20 8:59 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:36:54 -0600
> Babu Moger wrote:
>
>> This series fixes APIC ID encoding problems on AMD EPYC CPUs.
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%
On 2/3/20 9:08 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:01 -0600
> Babu Moger wrote:
>
>> Rename few data structures related to X86 topology. X86CPUTopoIDs will
>> have individual arch ids. Next patch introduces X86CPUTopoInfo which will
>> have al
On 2/3/20 9:17 AM, Igor Mammedov wrote:
> On Wed, 29 Jan 2020 10:17:11 -0600
> Babu Moger wrote:
>
>> On 1/29/20 3:14 AM, Igor Mammedov wrote:
>>> On Tue, 28 Jan 2020 13:45:31 -0600
>>> Babu Moger wrote:
>>>
>>>> On 1/28/20 10:29 AM,
ype-based CPU
> compatibility (commented by Eduardo).
>
> Babu Moger (2):
> i386: Add missing cpu feature bits in EPYC model
> i386: Add 2nd Generation AMD EPYC processors
>
>
> target/i386/cpu.c | 119
> +++
On 1/28/20 10:31 AM, Eric Blake wrote:
> On 12/3/19 6:37 PM, Babu Moger wrote:
>> Introduce last level cache id(llc_id) in x86CPU topology. This
>> information is
>> required to build the topology in EPIC mode.
>>
>> Signed-off-by: Babu Moger
>> ---
>
On 1/28/20 10:27 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:35 -0600
> Babu Moger wrote:
>
>> Introduce last level cache id(llc_id) in x86CPU topology. This information
>> is
>> required to build the topology in EPIC mode.
> can you add a reference
Igor,
On 1/28/20 9:49 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:21 -0600
> Babu Moger wrote:
>
>> Initialize all the parameters in one function initialize_topo_info.
>>
>> Signed-off-by: Babu Moger
>> Reviewed-by: Eduardo Habkos
On 1/28/20 10:29 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:42 -0600
> Babu Moger wrote:
>
>> Add a new function init_apicid_fn in MachineClass to initialize the mode
>> specific handlers to decode the apic ids.
>>
>> Signed-off-by: Babu Moger
>
On 2/5/20 3:38 AM, Igor Mammedov wrote:
> On Tue, 4 Feb 2020 13:08:58 -0600
> Babu Moger wrote:
>
>> On 2/4/20 2:02 AM, Igor Mammedov wrote:
>>> On Mon, 3 Feb 2020 13:31:29 -0600
>>> Babu Moger wrote:
>>>
>>>> On 2/3/20 8:59 AM, Igo
On 2/21/20 11:05 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:16:51 -0600
> Babu Moger wrote:
>
>> Initialize all the parameters in one function init_topo_info.
>
> is it possible to squash it in 2/16
>
Sure. We can do that.
>
>>
>>
are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors.
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 93
include/hw/i386/x86.h
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162
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