Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v2 - v3:
- Replace ADD instructions with gen_add_i32 for PSW bit calculation.
- Add gen_sub/mul_i32 for PSW bit calculation
- Replace SUB
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v2 - v3:
- Add cache for PSW_USB bits and psw_write/_read functions.
- Add tricore_feature, set_feature functions and enum of cpu features.
- Remove translate_init.c.
- Move
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v2 - v3:
- Fix CDC.COUNT calculation in cdc_zero.
- helper_ret now uses psw_write.
- Add
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v2 - v3:
- Fix CDC.COUNT calculation in cdc_increment/_decrement
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 66 +-
1 file changed
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 54
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tricore/tricore.h | 54 +
3
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59
.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes for decoding
target-tricore
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v2 - v3:
- Add initialization for PSW_USB bits as TCG regs.
- Remove cpu_tricore_init from
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v2 - v3:
- Remove helper_shac, gen_shac
- Remove len parameter of gen_shaci
- Change gen_shaci
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v3 - v4:
- Replace gen_calc_psw_sv, gen_calc_psw_sav, gen_calc_psw_av calls.
- Rename gen_sub_i32 to gen_sub_d.
- Fix V bit calculation in gen_sub_d
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 66 +-
1 file changed
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v3 - v4:
- tricore_cpu_type_info changed to abstract.
- Change documentation of PSW_USB_AV and PSW_USB_SAV bit to only use bit 31.
- Change psw_read/_write to only use bit 31
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 54
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files changed, 1407 insertions(+)
create
.
- Remove unnecessary temp register in gen_adds/_subs.
- Add missing break in gen_compute_branch at CALL insn.
- Replace movcond with setcond at RSUB insn.
- Add AV, SAV calculation to RSUB insn.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tricore/tricore.h | 54 +
3
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v3 - v4:
- Remove gen_calc_psw_sv, gen_calc_psw_av, gen_calc_psw_sav functions.
- Replace gen_calc_psw_sv
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
configure | 5 ++
default-configs/tricore-softmmu.mak | 3 +
target
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v3 - v4:
- Add missing break in gen_compute_branch at CALL insn.
target
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v3 - v4:
- Replace first movcond with tcg_gen_setcond and second with tcg_gen_or at
RSUB insn
On 08/08/2014 03:28 AM, Richard Henderson wrote:
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
+/* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+*/
+target_ulong PSW_USB_C;
+target_ulong PSW_USB_V;
+target_ulong
On 08/08/2014 11:40 AM, Bastian Koppelmann wrote:
On 08/08/2014 03:28 AM, Richard Henderson wrote:
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
+/* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+*/
+target_ulong PSW_USB_C
On 08/08/2014 03:28 AM, Richard Henderson wrote:
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
+/* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+*/
+target_ulong PSW_USB_C;
+target_ulong PSW_USB_V;
+target_ulong
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- gen_sub_d now saves result of substraction into tcg temp to handle ret =
r1 cases.
- gen_mul_i32s now calculates V, SV bits in bit 31
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- gen_intermediate_code_internal: Move calculation of next_pc after the ifs
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files changed, 1407 insertions(+)
create
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- Change int cond to TCGCond in functions gen_branch_cond
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- gen_shaci: Change case of shift_count == 32 to shift_count == -32 and add
the clear of V bit
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- Change documentation of S, SV bits to use bit 31.
- psw_read/_write now uses only bit 31 of S, SV bits.
arch_init.c | 2 +
cpu-exec.c
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 66 +-
1 file changed
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- decode_16Bit_opc: Add if to handle ADDSC.A opcode being 6 bit instead of
7 bit long
target-tricore/translate.c
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tricore/tricore.h | 54 +
3
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v4 - v5:
- Switched sat_neg and arg in first movcond in function gen_saturate.
- SR_NOT: Remove
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions
gen_goto_tb so qemu finds new tb on
singlestep and after long tbs without branch.
- Switched sat_neg and arg in first movcond in function gen_saturate.
- SR_NOT: Remove if checking OP2.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 130 +
include/hw/tricore/tricore.h | 54 +
3
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 69 ++
1 file changed, 69 insertions(+)
diff --git a/target-tricore
Add TriCore target stubs, QOM cpu and basic machine.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
arch_init.c | 2 +
configure | 13 ++
cpu-exec.c | 11 +-
cpus.c
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 149 +
1 file changed, 149 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.h| 5 ++
target-tricore/op_helper.c | 192
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for indirect loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 52 ++
1 file changed, 52 insertions(+)
diff --git
Add instructions of SRC opcode format.
Add helper for sh arithmetic carry.
Add micro-op generator functions for conditional add/sub/mov and sh.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.h| 19 +
target-tricore/op_helper.c | 36
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 160 +++-
target-tricore/translate_init.c | 30
2 files changed, 189
Add instructions of SC opcode format.
Add makro to generate helper with 1 arg.
Add micro-op generator functions for indirect loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.h| 2 +-
target-tricore/op_helper.c | 40
of patches. Another one will follow, which adds a lot of the
32 bit long instructions.
Peter Maydall: Sorry if i spammed you with mails. The --cc option of git
confused me a little bit, which resulted in a SMTP 550 error.
All the best
Bastian
Bastian Koppelmann (15):
target-tricore: Add target stubs
Add instructions of SRR opcode format.
Add micro-op generator function for ssov.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 140 -
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/translate.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target
Add instructions of SR opcode format.
Add micro-op generator functions for saturate and rsubi.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 58
Hi Peter,
On 07/07/2014 08:24 PM, Peter Maydell wrote:
I think you probably want the configure and default-configs changes to
be at the end of the patch series (or at least part way through it),
not at the start. The general approach is: * some patches which
implement the basic absolute
Add instructions of SRC opcode format.
Add helper for sh arithmetic carry.
Add micro-op generator functions for conditional add/sub and shi.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- helper_shac uses sextract32 for the constant and add len parameter
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Add save_context_lower. (see patch v2 10/15)
- Remove printfs in helper_bisr.
- Add one decode function for all SC
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Move activation of target patch1-patch4.
- Remove host related in configure.
- Remove host related code in user-exec.
- Remove active_tc struct.
- Change
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Add next_pc to DisasContext and change pc calculation.
- Remove insn_bytes
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 130 +
include/hw/tricore/tricore.h | 54 +
3
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Replace OP_MEM_INDIRECT with gen_offset_ld/st functions using TCGMemOp.
- Change load/store instructions
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Change compare to 0 at instructions JZ_T and JNZ_T.
- Group SBC instructions to one case.
- Group SBRN instructions to one case.
target-tricore/translate.c
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Add one decode function for all SLR instructions.
- Add one decode function for all SRO instructions.
- Remove duplicate SSRO instructions, which were
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Replace gen_ssov with helper for add_ssov and sub_ssov.
- Move SRR instructions to one decode function.
target-tricore/helper.h| 2
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Remove AND in ST_B and ST_H instructions.
- Load/Store instructions now use new TCGMemOp.
- Move SSR instructions to one decode function.
target-tricore/translate.c
instructions.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes for decoding
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Fill in cdc_increment/cdc_decrement
- Replace save
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Change gen_loop() to subtract first and then compare to -1.
- Change gen_loop() using next_pc insted of insn_bytes.
- Change
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v1 - v2:
- Change cdc_zero using clo32 instead of a loop.
- Change gen_saturate/_h using
+tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
Are you planning to come back to implement V and AV bits later?
Yes. I will do that in the next version of this patchset.
+case OPC1_16_SRC_MOV_A:
+/* load const4 again unsigned */
+const4 =
+tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
Are you planning to come back to implement V and AV bits later?
Would you recommend implementing this as a helper? It seems rather
complex. Especially with half-word and byte arithmetic. On the other
hand the instructions using
/
12: https://patchwork.ozlabs.org/patch/379595/
13: https://patchwork.ozlabs.org/patch/379586/
14: https://patchwork.ozlabs.org/patch/379590/
15: https://patchwork.ozlabs.org/patch/379599/
Thanks,
Bastian
On 08/13/2014 01:07 PM, Bastian Koppelmann wrote:
Hi,
my aim is to add
Hi Andreas,
On 08/20/2014 02:17 PM, Andreas Färber wrote:
Hi,
Am 13.08.2014 14:07, schrieb Bastian Koppelmann:
arch_init.c |2 +
configure |5 +
cpu-exec.c | 11 +-
cpus.c
On 08/21/2014 09:48 PM, Richard Henderson wrote:
On 08/13/2014 05:07 AM, Bastian Koppelmann wrote:
+/* SR-format */
+case OPCM_16_SR_SYSTEM:
+decode_sr_system(env, ctx);
+ break;
+case OPCM_16_SR_ACCU:
+decode_sr_accu(env, ctx);
+ break;
Formatting
.
- get_physical_address: Add PAGE_EXEC permission.
- gen_shaci: Add calculation of PSW.C to shift_count = -32 case.
- gen_intermediate_code_internal: Replace gen_goto_tb with setting of
next_pc and exit_tb(0).
- SBC/SBR_JEQ: Negate condition.
- Formating fixes.
Bastian Koppelmann (15
Add TriCore target stubs, and QOM cpu, and Maintainer
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- Add myself to MAINTAINERS
MAINTAINERS | 6 +
arch_init.c | 2 +
cpu-exec.c| 11 +-
cpus.c
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
configure | 5
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- get_physical_address: Add PAGE_EXEC permission.
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- tricore_testboard: Fix machine name containing blanks.
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- gen_shaci: Add calculation of PSW.C to shift_count = -32 case.
- Remove useless parenthesis
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- SBC_JEQ: Negate condition.
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-tricore
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- gen_intermediate_code_internal: Replace gen_goto_tb with setting
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 59
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/helper.h| 4 ++
target-tricore/op_helper.c | 43
target-tricore/translate.c
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
---
v5 - v6:
- Fix formating.
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 52
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann kbast...@mail.uni-paderborn.de
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git
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