-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
Sent: Wednesday, May 01, 2013 7:09 AM
To: Chen, Tiejun
Cc: ag...@suse.de; qemu-...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [Qemu-ppc] [v1][PATCH 1/1] PPC: e500: correct
params-ram_size with ram_size
-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
Sent: Wednesday, May 01, 2013 7:36 AM
To: Chen, Tiejun
Cc: ag...@suse.de; qemu-...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [Qemu-ppc] [v1][PATCH 1/1] PPC: e500: correct
params-ram_size with ram_size
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Tuesday, April 30, 2013 5:53 PM
To: Scott Wood
Cc: Chen, Tiejun; qemu-...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [Qemu-ppc] [v1][PATCH 1/1] PPC: e500: correct
params-ram_size with ram_size
-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
Sent: Tuesday, April 30, 2013 3:19 AM
To: Chen, Tiejun
Cc: ag...@suse.de; qemu-...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [Qemu-ppc] [v1][PATCH 1/1] PPC: e500: correct
params-ram_size with ram_size
Michael, Paolo and Stefano,
Any comments?
Thanks
Tiejun
On 2014/7/24 19:30, Tiejun Chen wrote:
As we discussed currently we have to introduce a separate machine
to work out igd passthrough.
Tiejun Chen (4):
On 2014/7/26 1:01, Konrad Rzeszutek Wilk wrote:
On Thu, Jul 24, 2014 at 09:44:41AM +0800, Chen, Tiejun wrote:
On 2014/7/24 4:54, Konrad Rzeszutek Wilk wrote:
On Sat, Jul 19, 2014 at 12:27:21AM +, Kay, Allen M wrote:
For the MCH PCI registers that do need to be read - can you tell us which
On 2014/7/29 16:32, Paolo Bonzini wrote:
Il 29/07/2014 08:59, Chen, Tiejun ha scritto:
(see https://lkml.org/lkml/2014/6/19/121)
gpu:drm:i915:intel_detect_pch: back to check devfn instead of check
class
type. Because Windows always use this way, so I think this point
should be
same between
On 2014/7/29 19:26, Michael S. Tsirkin wrote:
On Thu, Jul 24, 2014 at 07:30:26PM +0800, Tiejun Chen wrote:
We'd like to split pc_init1 and then we can share something
with other stuff.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
Did you test this patch? It does not look like it can
On 2014/7/29 19:17, Michael S. Tsirkin wrote:
On Thu, Jul 24, 2014 at 07:30:27PM +0800, Tiejun Chen wrote:
Implement that pci
s/that/a/
Fixed.
host bridge to specific
s/to specific/specific/
Fixed.
to passthrough. Actually
this just inherit
s/inherit/inherits/
Fixed.
the
On 2014/7/29 19:19, Michael S. Tsirkin wrote:
On Thu, Jul 24, 2014 at 07:30:28PM +0800, Tiejun Chen wrote:
This is almost same as an original i440fx_init but just
work with that xen igd host bridge to passthrough.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
---
hw/pci-host/piix.c | 79
On 2014/7/29 19:29, Michael S. Tsirkin wrote:
On Thu, Jul 24, 2014 at 07:30:29PM +0800, Tiejun Chen wrote:
Now we can introduce a new machine, xenigd, specific to IGD
passthrough. This can avoid involving other common codes.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
---
On 2014/7/31 17:10, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 02:31:36PM +0800, Tiejun Chen wrote:
We'd like to split i440fx_init and then we can share something
with other stuff.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
I think this is too much work for very little benefit.
On 2014/7/31 17:53, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 05:26:41PM +0800, Chen, Tiejun wrote:
On 2014/7/31 17:10, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 02:31:36PM +0800, Tiejun Chen wrote:
We'd like to split i440fx_init and then we can share something
with other
On 2014/7/31 18:12, Chen, Tiejun wrote:
On 2014/7/31 17:53, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 05:26:41PM +0800, Chen, Tiejun wrote:
On 2014/7/31 17:10, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 02:31:36PM +0800, Tiejun Chen wrote:
We'd like to split i440fx_init
On 2014/7/31 23:44, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 06:12:32PM +0800, Chen, Tiejun wrote:
On 2014/7/31 17:53, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 05:26:41PM +0800, Chen, Tiejun wrote:
On 2014/7/31 17:10, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 02:31
On 2014/7/31 23:47, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 08:10:53PM +0800, Chen, Tiejun wrote:
On 2014/7/31 18:12, Chen, Tiejun wrote:
On 2014/7/31 17:53, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 05:26:41PM +0800, Chen, Tiejun wrote:
On 2014/7/31 17:10, Michael S
On 2014/7/31 20:09, Tiejun Chen wrote:
v3:
* Drop patch #4
* Add one patch #1 from Michael
* Rebase
v2:
* Fix some coding style
* New patch to separate i440fx_init
* Just add prefix with XEN_IGD_PASSTHROUGH/xen_igd_passthrough
* Based on patch #2 to regenerate
* Unify prefix with
On 2014/7/31 17:53, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 05:26:41PM +0800, Chen, Tiejun wrote:
On 2014/7/31 17:10, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 02:31:36PM +0800, Tiejun Chen wrote:
We'd like to split i440fx_init and then we can share something
with other
On 2014/8/4 21:48, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 08:09:32PM +0800, Tiejun Chen wrote:
We'd like to split pc_init1 and then we can share something
with other stuff.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
With patch 1 in place, this should not be
necessary - just
On 2014/8/4 21:48, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 08:09:31PM +0800, Tiejun Chen wrote:
Xen wants to supply a different pci and host devices,
inheriting i440fx devices. Make types configurable.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Tiejun Chen
On 2014/8/4 21:50, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 08:09:33PM +0800, Tiejun Chen wrote:
Implement a pci host bridge specific to passthrough. Actually
this just inherits the standard one.
This is based on http://patchwork.ozlabs.org/patch/363810/.
Signed-off-by: Tiejun Chen
On 2014/8/4 21:51, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 08:09:30PM +0800, Tiejun Chen wrote:
v3:
* Drop patch #4
* Add one patch #1 from Michael
* Rebase
You added my patch but don't use it, so most of
my comment weren't addressed.
I guess I should cover those comments and
On 2014/8/6 17:42, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 02:50:34PM +0800, Tiejun Chen wrote:
Implement a pci host bridge specific to passthrough. Actually
this just inherits the standard one.
This is based on http://patchwork.ozlabs.org/patch/363810/.
Signed-off-by: Tiejun Chen
On 2014/8/6 17:45, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 02:50:33PM +0800, Tiejun Chen wrote:
We need to use this index to reuse this macro later
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
Which index?
Most users don't need to change.
Just open-code OBJECT_CHECK where
On 2014/8/7 5:07, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 06:17:02PM +0800, Chen, Tiejun wrote:
On 2014/8/6 17:45, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 02:50:33PM +0800, Tiejun Chen wrote:
We need to use this index to reuse this macro later
Signed-off-by: Tiejun Chen
On 2014/8/7 5:04, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 05:47:12PM +0800, Chen, Tiejun wrote:
On 2014/8/6 17:42, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 02:50:34PM +0800, Tiejun Chen wrote:
Implement a pci host bridge specific to passthrough. Actually
this just
On 2014/8/11 4:27, Michael S. Tsirkin wrote:
On Thu, Aug 07, 2014 at 09:40:49AM +0800, Chen, Tiejun wrote:
On 2014/8/7 5:07, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 06:17:02PM +0800, Chen, Tiejun wrote:
On 2014/8/6 17:45, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 02:50
On 2014/8/12 16:54, Michael S. Tsirkin wrote:
On Mon, Aug 11, 2014 at 10:50:48AM +0800, Chen, Tiejun wrote:
On 2014/8/11 4:27, Michael S. Tsirkin wrote:
On Thu, Aug 07, 2014 at 09:40:49AM +0800, Chen, Tiejun wrote:
On 2014/8/7 5:07, Michael S. Tsirkin wrote:
On Wed, Aug 06, 2014 at 06:17
On 2014/8/12 17:25, Chen, Tiejun wrote:
On 2014/8/12 16:54, Michael S. Tsirkin wrote:
On Mon, Aug 11, 2014 at 10:50:48AM +0800, Chen, Tiejun wrote:
On 2014/8/11 4:27, Michael S. Tsirkin wrote:
On Thu, Aug 07, 2014 at 09:40:49AM +0800, Chen, Tiejun wrote:
On 2014/8/7 5:07, Michael S
Michael,
Any further comments to this revision?
Thanks
Tiejun
On 2014/8/12 17:49, Tiejun Chen wrote:
v5:
* Simplify to make sure its really inherited from the standard one in patch #3
* Then drop the original patch #3
v4:
* Rebase on latest tree
* Drop patch #2
* Regenerate patches after
On 2014/8/14 15:09, Michael S. Tsirkin wrote:
On Tue, Aug 12, 2014 at 05:49:13PM +0800, Tiejun Chen wrote:
v5:
* Simplify to make sure its really inherited from the standard one in patch #3
* Then drop the original patch #3
v4:
* Rebase on latest tree
* Drop patch #2
* Regenerate patches
On 2014/8/15 0:03, Michael S. Tsirkin wrote:
On Tue, Aug 12, 2014 at 05:49:17PM +0800, Tiejun Chen wrote:
Now we can introduce a new machine, xenigd, specific to IGD
passthrough. This can avoid involving other common codes.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
This broke make
Just ping, any comments?
Thanks
Tiejun
On 2014/6/19 17:53, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to expose ISA bridge to let driver know the real
hardware underneath. This is a
. And especially, we wouldn't
provide that ISA bridge with an explicit class type in qemu-upstream, so
we need to the i915 driver to probe pch by checking devfn.
This should work both on the native case and the virtualized case.
Thanks
Tiejun
-Daniel
On Fri, Jun 20, 2014 at 11:40 AM, Chen
On 2014/6/20 20:48, Paolo Bonzini wrote:
Il 19/06/2014 11:53, Tiejun Chen ha scritto:
so this mean that isa bridge is still represented with Dev31:Func0
like the native OS. Furthermore, currently we're pushing VGA
passthrough support into qemu upstream, and with some discussion,
we wouldn't set
On 2014/6/24 10:59, Zhenyu Wang wrote:
On 2014.06.19 17:53:51 +0800, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to expose ISA bridge to let driver know the real
hardware underneath.
On 2014/5/19 19:22, Gerd Hoffmann wrote:
Hi,
I think '-vga none' just guarantees the qemu vga cards doesn't occupy
00:02.0, but this doesn't mean others use this specific slot since in
qemu internal, we always pass -1 to assign a slot automatically to
register a PCI device. So in some cases,
On 2014/6/25 14:48, Paolo Bonzini wrote:
Il 22/06/2014 10:25, Chen, Tiejun ha scritto:
In qemu-upstream, as you commented we can't create this as a ISA class
type explicitly.
Note I didn't say that QEMU doesn't like having two ISA bridges.
I commented that the firmware will see two ISA
On 2014/6/25 14:19, Paolo Bonzini wrote:
Il 25/06/2014 04:17, Tiejun Chen ha scritto:
* Don't set that ISA class property, instead, just fake this ISA bridge
with 00:1f.0.
How are you going to make this work for Q35 or another PCIe machine that
already has an ISA bridge at 00:1f.0?
Could
On 2014/6/25 14:21, Paolo Bonzini wrote:
Il 25/06/2014 04:17, Tiejun Chen ha scritto:
+static int get_vgabios(unsigned char *buf, XenHostPCIDevice *dev)
+{
+char rom_file[64];
+FILE *fp;
+uint8_t val;
+struct stat st;
+uint16_t magic = 0;
+int ret = 0;
+
+
On 2014/6/25 14:22, Paolo Bonzini wrote:
Il 25/06/2014 04:17, Tiejun Chen ha scritto:
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice
*hdev)
+{
+struct PCIDevice *dev;
+
+char rid;
+
+/* We havt to use a simple PCI device to fake this ISA bridge
+ * to
On 2014/6/25 14:25, Paolo Bonzini wrote:
Il 25/06/2014 04:17, Tiejun Chen ha scritto:
+int pci_create_pch(PCIBus *bus)
+{
+XenHostPCIDevice hdev;
+int r = 0;
+
+if (!xen_has_gfx_passthru) {
+return r;
+}
+
You could make this an assertion, since the function is never
On 2014/6/25 14:45, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:18AM +0800, Tiejun Chen wrote:
ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0
to make graphics device passthrough work well for VMM, that only need
to expose this pseudo ISA bridge to let driver
On 2014/6/25 16:28, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:10:44PM +0800, Chen, Tiejun wrote:
On 2014/6/25 14:45, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:18AM +0800, Tiejun Chen wrote:
ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0
to make
On 2014/6/25 16:43, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:39:07PM +0800, Chen, Tiejun wrote:
In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c
can be reused. How do you poke at the host device? sysfs?
Yes, sysfs.
Thanks
Tiejun
On 2014/6/25 16:48, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:39:43AM +0200, Paolo Bonzini wrote:
Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:
It might be possible to move the Q35 bridge elsewhere.
seabios doesn't care where the host bridge is.
ACPI tables in QEMU can be
On 2014/6/25 14:35, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:17AM +0800, Tiejun Chen wrote:
basic gfx passthrough support:
- add a vga type for gfx passthrough
- retrieve VGA bios from sysfs, then load it to guest at 0xC
- register/unregister legacy VGA I/O ports and MMIOs
On 2014/6/25 17:04, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:48:02PM +0800, Chen, Tiejun wrote:
On 2014/6/25 16:43, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:39:07PM +0800, Chen, Tiejun wrote:
In fact it's exactly what passthrough does.
I wonder if more bits from ./hw
On 2014/6/25 17:09, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:55:25PM +0800, Chen, Tiejun wrote:
On 2014/6/25 16:48, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:39:43AM +0200, Paolo Bonzini wrote:
Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:
It might be possible
On 2014/6/25 17:21, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 05:14:30PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:04, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:48:02PM +0800, Chen, Tiejun wrote:
On 2014/6/25 16:43, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:39
On 2014/6/25 17:31, Paolo Bonzini wrote:
Il 25/06/2014 11:21, Chen, Tiejun ha scritto:
Adding a vendor-specific capability or BAR
in an existing device is painful - hard to find
free space for it.
Yes, this is a potential risk as well since we can't guarantee current
free space is always
On 2014/6/25 17:44, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 05:28:48PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:21, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 05:14:30PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:04, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 04:48
On 2014/6/25 17:59, Paolo Bonzini wrote:
Il 25/06/2014 11:55, Michael S. Tsirkin ha scritto:
You're saying we will reserve a free BAR to address those
information to
expose to guest, but which device does this free BAR belong to? The
video
device? Or PCH/MCH?
If you just want to pass a
On 2014/6/25 18:09, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 11:59:21AM +0200, Paolo Bonzini wrote:
Il 25/06/2014 11:55, Michael S. Tsirkin ha scritto:
You're saying we will reserve a free BAR to address those information to
expose to guest, but which device does this free BAR belong
On 2014/6/25 18:21, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 06:06:50PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:59, Paolo Bonzini wrote:
Il 25/06/2014 11:55, Michael S. Tsirkin ha scritto:
You're saying we will reserve a free BAR to address those
information to
expose to guest
On 2014/6/25 18:32, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 06:28:34PM +0800, Chen, Tiejun wrote:
On 2014/6/25 18:21, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 06:06:50PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:59, Paolo Bonzini wrote:
Il 25/06/2014 11:55, Michael S
On 2014/6/26 7:04, Slutz, Donald Christopher wrote:
On 06/24/14 22:49, Chen, Tiejun wrote:
On 2014/5/19 19:22, Gerd Hoffmann wrote:
Hi,
I think '-vga none' just guarantees the qemu vga cards doesn't occupy
00:02.0, but this doesn't mean others use this specific slot since in
qemu internal
On 2014/6/25 22:05, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:19AM +0800, Tiejun Chen wrote:
Some registers of Intel IGD are mapped in host bridge, so it needs to
passthrough these registers of physical host bridge to guest because
emulated host bridge in guest doesn't have these
On 2014/6/26 10:00, Chen, Tiejun wrote:
On 2014/6/26 7:04, Slutz, Donald Christopher wrote:
On 06/24/14 22:49, Chen, Tiejun wrote:
On 2014/5/19 19:22, Gerd Hoffmann wrote:
Hi,
I think '-vga none' just guarantees the qemu vga cards doesn't occupy
00:02.0, but this doesn't mean others use
On 2014/6/26 14:04, Michael S. Tsirkin wrote:
On Thu, Jun 26, 2014 at 01:34:14PM +0800, Chen, Tiejun wrote:
On 2014/6/25 22:05, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:19AM +0800, Tiejun Chen wrote:
Some registers of Intel IGD are mapped in host bridge, so it needs
On 2014/6/25 17:54, Paolo Bonzini wrote:
Il 25/06/2014 11:50, Chen, Tiejun ha scritto:
For past devices, we know which BARs they use. For future devices, it
would be nice if the PCH/MCH backdoor was specified so that we know they
will leave a free BAR for virtualization.
Now I'm a bit
On 2014/6/25 17:58, Chen, Tiejun wrote:
On 2014/6/25 17:44, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 05:28:48PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:21, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 05:14:30PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:04, Michael S
On 2014/6/25 14:24, Paolo Bonzini wrote:
Il 25/06/2014 04:17, Tiejun Chen ha scritto:
+if (xen_enabled() xen_has_gfx_passthru) {
+d = pci_create_simple(b, 0, TYPE_I440FX_XEN_PCI_DEVICE);
+*pi440fx_state = I440FX_XEN_PCI_DEVICE(d);
+pci_create_pch(b);
+} else {
+
On 2014/6/25 15:04, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:19AM +0800, Tiejun Chen wrote:
Some registers of Intel IGD are mapped in host bridge, so it needs to
[snip]
static int is_vga_passthrough(XenHostPCIDevice *dev)
{
@@ -291,3 +292,158 @@ static int
On 2014/6/25 15:13, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:21AM +0800, Tiejun Chen wrote:
[snip]
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
index 507165c..25147cf 100644
--- a/hw/xen/xen_pt.h
+++ b/hw/xen/xen_pt.h
@@ -63,7 +63,7 @@ typedef int (*xen_pt_conf_byte_read)
On 2014/6/27 19:26, Paolo Bonzini wrote:
Il 27/06/2014 10:34, Chen, Tiejun ha scritto:
So how to separate this to specific to xen? Or you mean we need to
create an new machine to address this scenario? But actually this is
same as xenfv_machine except for these little codes.
Yes, please
On 2014/6/29 19:43, Michael S. Tsirkin wrote:
On Fri, Jun 27, 2014 at 05:22:18PM +0800, Chen, Tiejun wrote:
On 2014/6/25 15:13, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 10:17:21AM +0800, Tiejun Chen wrote:
[snip]
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
index 507165c
On 2014/6/26 18:03, Paolo Bonzini wrote:
Il 26/06/2014 11:18, Chen, Tiejun ha scritto:
- offsets 0x..0x0fff map to configuration space of the host MCH
Are you saying the config space in the video device?
No, I am saying in a new BAR, or at some magic offset of an existing
MMIO BAR
On 2014/6/29 20:14, Michael S. Tsirkin wrote:
On Sun, Jun 29, 2014 at 03:56:10PM +0800, Chen, Tiejun wrote:
On 2014/6/27 19:26, Paolo Bonzini wrote:
Il 27/06/2014 10:34, Chen, Tiejun ha scritto:
So how to separate this to specific to xen? Or you mean we need to
create an new machine
On 2014/6/25 15:55, Paolo Bonzini wrote:
Il 25/06/2014 09:34, Chen, Tiejun ha scritto:
On 2014/6/25 14:48, Paolo Bonzini wrote:
Second problem. Your IGD passthrough code currently works with QEMU's
PIIX4-based machine. But what happens if you try to extend it, so that
Yes, current xen
On 2014/6/30 14:48, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 10:51:49AM +0800, Chen, Tiejun wrote:
On 2014/6/26 18:03, Paolo Bonzini wrote:
Il 26/06/2014 11:18, Chen, Tiejun ha scritto:
- offsets 0x..0x0fff map to configuration space of the host MCH
Are you saying
On 2014/6/30 17:05, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 03:24:58PM +0800, Chen, Tiejun wrote:
On 2014/6/30 14:48, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 10:51:49AM +0800, Chen, Tiejun wrote:
On 2014/6/26 18:03, Paolo Bonzini wrote:
Il 26/06/2014 11:18, Chen, Tiejun
On 2014/6/30 17:55, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 05:38:21PM +0800, Chen, Tiejun wrote:
On 2014/6/30 17:05, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 03:24:58PM +0800, Chen, Tiejun wrote:
On 2014/6/30 14:48, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 10:51
On 2014/6/30 17:29, Gerd Hoffmann wrote:
Hi,
/* Make cirrues VGA S3 suspend/resume work in Windows
XP/2003 */
Device (VGA)
{
- Name (_ADR, 0x0002)
+ // Address of the VGA (device F function 0)
+ Name
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Monday, May 19, 2014 2:45 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com
-Original Message-
From: Fabio Fantoni [mailto:fabio.fant...@m2r.biz]
Sent: Monday, May 19, 2014 3:48 PM
To: Gerd Hoffmann; Chen, Tiejun
Cc: peter.mayd...@linaro.org; xen-de...@lists.xensource.com;
m...@redhat.com; Kay, Allen M; stefano.stabell...@eu.citrix.com;
weidong
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Friday, May 16, 2014 10:06 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Friday, May 16, 2014 10:07 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Friday, May 16, 2014 10:09 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Friday, May 16, 2014 10:12 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Friday, May 16, 2014 10:37 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Friday, May 16, 2014 10:35 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Monday, May 19, 2014 7:23 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; Kay
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Monday, May 19, 2014 8:10 PM
To: Konrad Rzeszutek Wilk
Cc: Chen, Tiejun; anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd
-Original Message-
From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
Sent: Monday, May 19, 2014 9:34 PM
To: Zhang, Yang Z
Cc: Chen, Tiejun; anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Monday, May 19, 2014 7:54 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; qemu-devel@nongnu.org;
xen-de
Just resend since looks this delivery is delayed to these recipients or groups.
Sorry for any inconveniences.
Thanks
Tiejun
-Original Message-
From: Chen, Tiejun
Sent: Tuesday, May 20, 2014 9:30 AM
To: 'Konrad Rzeszutek Wilk'
Cc: anthony.per...@citrix.com; stefano.stabell
-Original Message-
From: Michael S. Tsirkin [mailto:m...@redhat.com]
Sent: Monday, May 19, 2014 6:13 PM
To: Chen, Tiejun
Cc: Gerd Hoffmann; anthony.per...@citrix.com;
stefano.stabell...@eu.citrix.com; kelly.zyta...@amd.com;
peter.mayd...@linaro.org; xen-de...@lists.xensource.com
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Tuesday, May 20, 2014 6:51 PM
To: Chen, Tiejun
Cc: Stefano Stabellini; anthony.per...@citrix.com; m...@redhat.com;
kelly.zyta...@amd.com; qemu-devel@nongnu.org;
xen-de...@lists.xensource.com
-Original Message-
From: Anthony PERARD [mailto:anthony.per...@citrix.com]
Sent: Tuesday, May 20, 2014 10:45 PM
To: Chen, Tiejun
Cc: Gerd Hoffmann; stefano.stabell...@eu.citrix.com; m...@redhat.com;
kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; Kay
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Monday, May 19, 2014 9:51 PM
To: Chen, Tiejun
Cc: anthony.per...@citrix.com; stefano.stabell...@eu.citrix.com;
m...@redhat.com; kelly.zyta...@amd.com; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; Kay
Just ping, any concern about this?
Thanks
Tiejun
-Original Message-
From: qemu-devel-bounces+tiejun.chen=intel@nongnu.org
[mailto:qemu-devel-bounces+tiejun.chen=intel@nongnu.org] On Behalf Of
Chen, Tiejun
Sent: Wednesday, May 21, 2014 3:08 PM
To: Gerd Hoffmann; Anthony
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Thursday, May 22, 2014 1:40 PM
To: Chen, Tiejun
Cc: Anthony PERARD; Daniel P. Berrange; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; m...@redhat.com;
stefano.stabell...@eu.citrix.com; Kay, Allen M
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Thursday, May 22, 2014 2:45 PM
To: Chen, Tiejun
Cc: Anthony PERARD; Daniel P. Berrange; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; m...@redhat.com;
stefano.stabell...@eu.citrix.com; Kay, Allen M
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Thursday, May 22, 2014 2:45 PM
To: Chen, Tiejun
Cc: Anthony PERARD; Daniel P. Berrange; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; m...@redhat.com;
stefano.stabell...@eu.citrix.com; Kay, Allen M
-Original Message-
From: qemu-devel-bounces+tiejun.chen=intel@nongnu.org
[mailto:qemu-devel-bounces+tiejun.chen=intel@nongnu.org] On Behalf Of
Michael S. Tsirkin
Sent: Thursday, May 22, 2014 3:22 PM
To: Gerd Hoffmann
Cc: qemu-devel@nongnu.org; Anthony Liguori
Subject: Re:
-Original Message-
From: Gerd Hoffmann [mailto:kra...@redhat.com]
Sent: Thursday, May 22, 2014 7:22 PM
To: Chen, Tiejun
Cc: Anthony PERARD; Daniel P. Berrange; peter.mayd...@linaro.org;
xen-de...@lists.xensource.com; m...@redhat.com;
stefano.stabell...@eu.citrix.com; Kay, Allen M
-Original Message-
From: Igor Mammedov [mailto:imamm...@redhat.com]
Sent: Thursday, May 22, 2014 10:20 PM
To: Michael S. Tsirkin
Cc: Chen, Tiejun; peter.mayd...@linaro.org; xen-de...@lists.xensource.com;
Daniel P. Berrange; stefano.stabell...@eu.citrix.com; Kay, Allen M;
kelly.zyta
Please ignore this series since I have some typos to some email address :(
Sorry for any inconveniences.
Thanks
Tiejun
-Original Message-
From: qemu-devel-bounces+tiejun.chen=intel@nongnu.org
[mailto:qemu-devel-bounces+tiejun.chen=intel@nongnu.org] On Behalf Of
Tiejun Chen
Any further comments?
Thanks
Tiejun
-Original Message-
From: qemu-devel-bounces+tiejun.chen=intel@nongnu.org
[mailto:qemu-devel-bounces+tiejun.chen=intel@nongnu.org] On Behalf Of
Tiejun Chen
Sent: Monday, May 26, 2014 5:43 PM
To: anthony.per...@citrix.com;
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