specification, for
which all the four variations([o][.]) have been handled with a single pattern.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32
Hi Richard,
On 2/13/24 03:51, Richard Henderson wrote:
On 2/9/24 01:35, Chinmay Rath wrote:
+_tab_cy rt ra rb cy
+@Z23_tab_cy .. rt:5 ra:5 rb:5 cy:2 . _tab_cy
...
+ADDEX 01 . . . .. 10101010 - @Z23_tab_cy
...
+static bool trans_ADDEX
specification, for
which all the four variations([o][.]) have been handled with a single pattern.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
Changes v1 ->
been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Nicholas Piggin
---
target/ppc/helper.h| 44
On 3/12/24 15:31, Nicholas Piggin wrote:
On Thu Mar 7, 2024 at 9:03 PM AEST, Chinmay Rath wrote:
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index 189cd8c979..03b84ba79b 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp
On 3/12/24 19:59, Peter Maydell wrote:
On Tue, 12 Mar 2024 at 14:25, Nicholas Piggin wrote:
On Wed Mar 13, 2024 at 12:01 AM AEST, Richard Henderson wrote:
On 3/11/24 23:36, Nicholas Piggin wrote:
[snip]
#define FPU_HELPER(name, op, flags_handler) \
float64
to decodetree.
Change log :
v2 : Addressed review comments on v1
v1 :
https://lore.kernel.org/qemu-devel/20240307110318.170319-1-ra...@linux.ibm.com/
Chinmay Rath (2):
target/ppc: Merge various fpu helpers
target/ppc: Move floating-point arithmetic instructions to decodetree.
target/ppc/helper.h
This patch merges the definitions of the following set of fpu helper methods,
which are similar, using macros :
1. f{add, sub, mul, div}(s)
2. fre(s)
3. frsqrte(s)
Signed-off-by: Chinmay Rath
---
target/ppc/fpu_helper.c | 221 +++-
1 file changed, 62
in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 44 ++---
target/ppc/insn32.decode | 42 +
target/ppc/fpu_helper.c| 265 +-
target/ppc/translate/fp-impl.c.inc | 288 +++--
target/ppc
Hi Richard,
On 4/16/24 23:26, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.] : XO-form
The changes were verified by validating that the tcg
Hi Richard,
On 4/17/24 00:50, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form
The changes were verified by validating
On 4/16/24 23:55, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by
those
On 4/16/24 23:49, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by
those
instructions remain the same
On 4/17/24 01:05, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d
On 4/17/24 00:08, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.] : XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved
Hi Richard,
On 4/16/24 23:27, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
The handler methods for divw[u] instructions internally use
Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if
we move
the above said instructions to decodet
Hi Richard,
On 4/17/24 00:06, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+ tcg_gen_movi_i64(t1, 0);
Drop the movi.
+ tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc], t1);
Hi Richard,
On 4/20/24 21:21, Richard Henderson wrote:
On 4/19/24 02:25, Chinmay Rath wrote:
Hi Richard,
On 4/17/24 00:06, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+ tcg_gen_movi_i64(t1, 0);
Drop
,op'
flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode | 9 ++
target/ppc/translate.c | 101 -
target/ppc/translate/fixedpoint-impl.c.inc | 85 +
3 files changed, 94 insertions
le, so that the
mentioned insns can be safely move to decodetree specs.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c455
with the '-d in_asm,op' flag.
Also cleaned up code for mullw[o][.] as per review comments while
keeping the logic of the tcg ops generated semantically same.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode | 9 +++
target/ppc/translate.c
-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/helper.h| 6 +-
target/ppc/insn32.decode | 16 +++
target/ppc/excp_helper.c | 4 +-
target/ppc/int_helper.c| 2 +-
target/ppc/translate.c
/20240416063927.99428-1-ra...@linux.ibm.com/
Chinmay Rath (8):
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible.
target/ppc: Move divw[u, e, eu] instructions to decodetree.
target/ppc: Move neg, darn, mod{sw, uw
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/helper.h| 4 +-
target/ppc/insn32.decode | 8
target/ppc/int_helper.c| 4 +-
target/ppc/translate.c | 56
generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is
now used to divide doubleword operands as well, and not just words.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard
Moving all fixed-point instructions of the following type to decodetree
specification : arithmetic, compare, trap, select and logical.
Chinmay Rath (8):
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h
' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 4 +-
target/ppc/insn32.decode | 8
target/ppc/int_helper.c| 4 +-
target/ppc/translate.c | 56 --
target/ppc/translate/fixedpoint
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is
now used to divide doubleword operands as well, and not just words.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h
le, so that the
mentioned insns can be safely move to decodetree specs.
Signed-off-by: Chinmay Rath
---
target/ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c45547a770..be7d807e3c 100644
--- a/targ
with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32.decode | 9 +++
target/ppc/translate.c | 89 --
target/ppc/translate/fixedpoint-impl.c.inc | 71 +
3 files changed, 80 insertions(+), 89 deletions
, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 6 +-
target/ppc/insn32.decode | 16 +++
target/ppc/excp_helper.c | 4 +-
target/ppc/int_helper.c| 2
,op'
flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32.decode | 9 ++
target/ppc/translate.c | 101 -
target/ppc/translate/fixedpoint-impl.c.inc | 85 +
3 files changed, 94 insertions(+), 101 deletions(-)
diff
Moving VMX instructions of the following types to decodetree
specification : storage access, integer logical & integer max/min.
Chinmay Rath (3):
target/ppc: Move VMX storage access instructions to decodetree
target/ppc: Move VMX integer logical instructions to decodetree
target/ppc:
Moving the following instructions to decodetree specification :
v{max, min}{u, s}{b, h, w, d} : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay
in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h | 12 +-
target/ppc/insn32.decode| 17 +++
target/ppc/mem_helper.c | 12 +-
target/ppc/translate.c | 2 -
target/ppc/translate/vmx-impl.c.inc | 221
-by: Chinmay Rath
---
target/ppc/insn32.decode| 11 +++
target/ppc/translate/vmx-impl.c.inc | 22 ++
target/ppc/translate/vmx-ops.c.inc | 15 ---
3 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/target/ppc/insn32.decode b/target
,
Chinmay
Chinmay Rath (1):
target/ppc: Move VMX integer add/sub saturate insns to decodetree.
target/ppc/helper.h | 24 +--
target/ppc/insn32.decode| 16 ++
target/ppc/int_helper.c | 22 +--
target/ppc/translate/vmx-impl.c.inc | 242
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay
On 5/1/24 18:34, Nicholas Piggin wrote:
POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.
Implement the store-store syncs and plwsync/phwsync.
Signed-off-by: Nicholas Piggin
Reviewed-by: Chinmay Rath
On 5/1/24 18:34, Nicholas Piggin wrote:
Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Signed-off-by: Nicholas Piggin
Reviewed-by: Chinmay
fields. The existing behaviour causes illegal instruction exceptions
when using new POWER10 sync variants that add new fields, after this
the instructions are accepted and are implemented as supersets of
the new behaviour, as intended.
Signed-off-by: Nicholas Piggin
Reviewed-by: Chinmay Rath
Hi Richard,
On 5/12/24 17:08, Richard Henderson wrote:
On 5/12/24 11:38, Chinmay Rath wrote:
@@ -2934,6 +2870,184 @@ static bool do_vx_vaddsubcuw(DisasContext
*ctx, arg_VX *a, int add)
return true;
}
+static inline void do_vadd_vsub_sat
+(
+ unsigned vece, TCGv_vec t, TCGv_vec
Hi Richard,
On 5/12/24 15:59, Richard Henderson wrote:
On 5/12/24 11:38, Chinmay Rath wrote:
1. vsubsbs and bcdtrunc :
In this pair, bcdtrunc has the insn flag check PPC2_ISA300 in the
vmx-impl file, within the GEN_VXFORM_DUAL macro, which does this flag
check.
However it also has this flag
-off-by: Chinmay Rath
---
target/ppc/insn32.decode| 11
target/ppc/translate/vsx-impl.c.inc | 39 +
target/ppc/translate/vsx-ops.c.inc | 11
3 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/target/ppc/insn32.decode b/target
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay
patch to improve the moved insns as per suggestion by
Richard in v1.
v1:
https://lore.kernel.org/qemu-devel/20240512093847.18099-1-ra...@linux.ibm.com/
Chinmay Rath (2):
target/ppc: Move VMX integer add/sub
No need for a full comparison; xor produces non-zero bits for QC just fine.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vmx-impl.c.inc | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h | 44 ++--
target/ppc/insn32.decode| 30 ++
target/ppc/fpu_helper.c | 44 ++--
target/ppc/translate/vsx-impl.c.inc | 63
Moving PPC2_ISA300 flag check out of do_helper_XX3 method in vmx-impl.c.inc
so that the helper can be used with other instructions as well.
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vsx-impl.c.inc | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git
Moving a number of VSX arithmetic, max/min and logical instructions to
decodetree specification.
Also moving ISA300 flag check in the do_helper_XX3 methods in
vsx-impl.c.inc file; out of it, to make it usable for a larger num of
instructions.
Chinmay Rath (3):
target/ppc: Move ISA300 flag
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