This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
all microblaze machines that uses microblaze_load_dtb().
Cc: Edgar E. Iglesias
Signed-off-by: Daniel Henrique Barboza
---
hw/microblaze/boot.c | 13 -
hw/microblaze/meson.build | 2 +-
We'll introduce QMP/HMP commands that requires machine->fdt to be set
properly.
Cc: BALATON Zoltan
Cc: qemu-...@nongnu.org
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pegasos2.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
the sam460ex machine.
Cc: BALATON Zoltan
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/sam460ex.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/sam460ex.c b/hw/
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
the sifive_u machine.
Cc: Alistair Francis
Cc: Bin Meng
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/sifive_u.c | 8
1 file changed, 8 insertions(+)
diff --git a/h
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
all nios2 machines that uses nios2_load_dtb().
Cc: Chris Wulff
Cc: Marek Vasut
Signed-off-by: Daniel Henrique Barboza
---
hw/nios2/boot.c | 13 -
hw/nios2/meson.build | 2 +-
ma-window' from the v-scsi device inside the pSeries
FDT:
(qemu) info fdt /vdevice/v-scsi@7103 ibm,my-dma-window
/vdevice/v-scsi@7103/ibm,my-dma-window = <0x7103 0x0 0x0 0x0 0x1000>
Cc: Dr. David Alan Gilbert
Signed-off-by: Daniel Henrique Barboza
---
hmp-commands-info.hx
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
all powernv machines.
Cc: Cédric Le Goater
Cc: Frederic Barrat
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
all xtensa machines that uses a FDT.
Signed-off-by: Daniel Henrique Barboza
---
hw/xtensa/meson.build | 2 +-
hw/xtensa/xtfpga.c| 11 ++-
2 files changed, 11 insertions(+), 2 deletions(-)
di
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
the virtex_ml507 machine.
Cc: Edgar E. Iglesias
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/virtex_ml507.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/ppc
umpdtb' that can be fired on demand via QMP/HMP.
A valid FDT consists of a FDT that was created using libfdt being
retrieved via 'current_machine->fdt' in device_tree.c. This condition is
met by most FDT users in QEMU.
Cc: Dr. David Alan Gilbert
Signed-off-by: Daniel Henri
er0 {
core0 {
cpu = <0x8001>
}
}
}
}
Signed-off-by: Daniel Henrique Barboza
---
softmmu/device_tree.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/softmmu/device_tree.c b/softmmu/device_tree.
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
the spike machine.
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Bin Meng
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/spike.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/h
nly = <0x0>
stdout-path = '/vdevice/vty@7100'
linux,stdout-path = '/vdevice/vty@7100'
qemu,graphic-depth = <0x20>
qemu,graphic-height = <0x258>
qemu,graphic-width = <0x320>
}
Signed-off-by: Daniel Henrique Barboza
---
e same node for the aarch64 'virt' machine:
(qemu) info fdt /chosen
chosen {
stdout-path;
rng-seed;
kaslr-seed;
}
Cc: Dr. David Alan Gilbert
Signed-off-by: Daniel Henrique Barboza
---
hmp-commands-info.hx | 13 ++
include/monitor/hmp.h| 1 +
includ
We want to be able to also print properties with 'info fdt'.
Create a helper to format properties based on the already existing code
from fdt_format_node().
Signed-off-by: Daniel Henrique Barboza
---
softmmu/device_tree.c | 35 ---
1 file changed, 20
'
rng-seed;
kaslr-seed;
}
Signed-off-by: Daniel Henrique Barboza
---
softmmu/device_tree.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index 3fb07b537f..8691c3ccc0 100644
--- a/softmmu/d
On 8/5/22 08:03, Frederic Barrat wrote:
On 05/08/2022 11:39, Daniel Henrique Barboza wrote:
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
all powernv machines.
Cc: Cédric Le Goater
Cc: Frederic Barrat
Signed-off-by: Daniel Henrique Barboza
On 8/5/22 14:17, Richard Henderson wrote:
On 8/5/22 07:15, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
When an overflow exception occurs and OE is set the intermediate result
should be adjusted (by subtracting from the exponent) to avoid rounding
to inf. The sa
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 8/5/22 11:15, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Changes in v2:
- Completely reworked the solution:
* Created re_bias in FloatFmt, it is 3/4 of the total exponent
g the first operand to uint64_t to force the product to
be 64 bit.
Fixes: Coverity CID 1490852
Fixes: 3c409c1927ef ("ppc440_uc: Basic emulation of PPC440 DMA controller")
Cc: BALATON Zoltan
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440_uc.c | 2 +-
1 file changed, 1 insertion
On 8/5/22 21:30, BALATON Zoltan wrote:
On Fri, 5 Aug 2022, Daniel Henrique Barboza wrote:
Coverity reports a OVERFLOW_BEFORE_WIDEN issue in dcr_write_dma(). When
handling the DMA0_CR switch we're doing a multiplication between two
integers (count and width), and the product is assigned
cularly
better after the changes I was about to send, so let's forget about it.
Daniel
On 8/6/22 07:39, Daniel Henrique Barboza wrote:
On 8/5/22 21:30, BALATON Zoltan wrote:
On Fri, 5 Aug 2022, Daniel Henrique Barboza wrote:
Coverity reports a OVERFLOW_BEFORE_WIDEN issue in dcr_write
On 8/5/22 07:41, Frederic Barrat wrote:
On 03/08/2022 15:44, Daniel Henrique Barboza wrote:
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to
On 8/5/22 07:50, Frederic Barrat wrote:
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 077f391d59..953c384bf6 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -17,6 +17,7 @@
#include "hw/ppc/pnv.h"
#include "hw/qdev-properties.h"
#include "qom/object
On 8/8/22 00:23, David Gibson wrote:
On Fri, Aug 05, 2022 at 06:39:29AM -0300, Daniel Henrique Barboza wrote:
At this moment, arm_load_dtb() can free machine->fdt when
binfo->dtb_filename is NULL. If there's no 'dtb_filename', 'fdt' will be
retrieved by binfo-&
On 8/8/22 13:50, Daniel Henrique Barboza wrote:
On 8/5/22 07:50, Frederic Barrat wrote:
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 077f391d59..953c384bf6 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -17,6 +17,7 @@
#include "hw/ppc/
om v2:
- patch 5: avoid parenting the PHB to NULL
- patch 11 (new):
- fix QOM parenting of user created root ports
- v2 link: https://lists.gnu.org/archive/html/qemu-devel/2022-08/msg00505.html
Daniel Henrique Barboza (11):
ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties
ppc/pnv: add phb-id
t ports, without doing anything too
shady with QOM.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 50 ++
include/hw/pci-host/pnv_phb3.h | 9 +-
2 files changed, 58 insertions(+), 1 deletion(-)
diff --g
nted by the chip
because pnv_xscom_dt() relies on it, and then assigned to the array.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 7 +++
hw/ppc/pnv.c | 20 +++-
include/hw/ppc/pnv.h | 6 +-
3 files changed, 27 insertions(+), 6 deletions(-)
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_
deal with phb3 code.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 51 ++
include/hw/pci-host/pnv_phb4.h | 10 +++
2 files changed, 61 insertions(+)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci
e phb3/phb4 backends untouched.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 826c0c144e..18a050a6d3 100644
--- a/hw/pci-host/pnv_phb
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 9 +++--
hw/ppc/pnv.c | 6 ++
2 files changed, 13 insertions
ing default devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index c47ed92462..826c0c144e 100644
---
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb4_pec.c | 6 --
hw/ppc/pnv.c | 2 ++
3 files changed, 7 insertions(+), 3 deletions(-)
diff
e root port as a child of the bus as well.
While we're at it, change pnv_phb_attach_root_port() to receive a PCIBus
instead of a PCIHostState to make it clear that the function does not
make use of the PHB.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 36 ++
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv.c b/h
user-created PHB{3,4,5}
devices". We'll use it to determine the appropriate PEC for a given user
created pnv-phb that uses a PHB4 backend.
This is done during realize() time, in pnv_phb_user_device_init().
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host
On 8/9/22 14:37, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_boards.c | 55 +-
1 file changed, 38 insertions(+), 17 deletions(-)
diff --git a
On 8/8/22 04:13, Cédric Le Goater wrote:
On 8/8/22 08:47, Cédric Le Goater wrote:
On 8/5/22 11:39, Daniel Henrique Barboza wrote:
This will enable support for 'dumpdtb' and 'info fdt' HMP commands for
all powernv machines.
I might have missed some emails but dumpdtb i
On 8/8/22 01:36, David Gibson wrote:
On Fri, Aug 05, 2022 at 06:39:44AM -0300, Daniel Henrique Barboza wrote:
To support printing string properties in 'info fdt' we need to determine
whether a void data might contain a string.
Oh... sorry, obviously I hadn't read these later
Cedric,
I pushed patches 1-7 to gitlab.com/danielhb/qemu/tree/ppc-7.2. This
way you have 7 less patches to worry about for the next versions.
Thanks,
Daniel
On 8/9/22 12:38, Cédric Le Goater wrote:
Hello,
Here is large series QOM'ifying the PPC405 board. It introduces a new
generic machine
pnv.c
- patch 9:
- use g_assert_not_reached() in pnv_phb4_get_pec()
- v3 link: https://lists.gnu.org/archive/html/qemu-devel/2022-08/msg01548.html
Daniel Henrique Barboza (11):
ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties
ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties
ppc/pnv: set r
t ports, without doing anything too
shady with QOM.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 50 ++
include/hw/pci-host/pnv_phb3.h | 9 +-
2 files changed, 58 insertions(+), 1 deletion(-)
diff --g
deal with phb3 code.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 51 ++
include/hw/pci-host/pnv_phb4.h | 10 +++
2 files changed, 61 insertions(+)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci
ing default devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index c47ed92462..826c0c144e 100644
---
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 9 +++--
hw/ppc/pnv.c | 32
nted by the chip
because pnv_xscom_dt() relies on it, and then assigned to the array.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 27 ++-
include/hw/ppc/pnv.h | 6 +-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/h
e phb3/phb4 backends untouched.
Another helper called pnv_chip_add_phb() was added to handle the
particularities of each chip version when adding a new PHB.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 75 +++
hw/ppc/pnv.c | 20
user-created PHB{3,4,5}
devices". We'll use it to determine the appropriate PEC for a given user
created pnv-phb that uses a PHB4 backend.
This is done during realize() time, in pnv_phb_user_device_init().
Signed-off-by: Daniel Henrique Barboza
---
hw
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb4_pec.c | 6 --
hw/ppc/pnv.c | 2 ++
3 files changed, 7
aydell
CC: Cédric Le Goater
CC: Daniel Henrique Barboza
CC: David Gibson
CC: Greg Kurz
CC: Palmer Dabbelt
CC: Alistair Francis
CC: Bin Meng
CC: Cornelia Huck
CC: Thomas Huth
CC: Richard Henderson
CC: David Hildenbrand
---
For target/ppc changes:
Acked-by: Daniel Henrique Barboza
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 2 ++
1 file changed, 2 inser
e root port as a child of the bus as well.
While we're at it, change pnv_phb_attach_root_port() to receive a PCIBus
instead of a PCIHostState to make it clear that the function does not
make use of the PHB.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 35 +
Alistair,
I'm doing some overly complicated stuff here w.r.t to KVM specific code
that are biting me back in further cleanups I'm working on.
I'll do some changes in this series and re-send. Thanks,
Daniel
On 7/14/23 14:43, Daniel Henrique Barboza wrote:
Hi,
This vers
follow-up. As for this patch:
Reviewed-by: Daniel Henrique Barboza
/* register system main memory (actual RAM) */
memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 00c22492a7..1d7ddf5df0 100644
On 7/12/23 13:39, Sunil V L wrote:
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt-acpi-build.c | 66 +++---
1 file changed, 62 insertions(+), 4 deletions
On 7/12/23 13:39, Sunil V L wrote:
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt
On 7/12/23 13:39, Sunil V L wrote:
Add APLIC structures for each socket in the MADT when
system is configured with APLIC as the external wired
interrupt controller.
Signed-off-by: Sunil V L
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt-acpi-build.c | 36
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt-acpi-build.c | 64 +-
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 9f2d0c92b0..2d2bd3b970 100644
--- a/hw/riscv/virt-acpi-build.c
On 7/12/23 13:39, Sunil V L wrote:
MMU type information is available via MMU node in RHCT.
Add this node in RHCT.
Signed-off-by: Sunil V L
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt-acpi-build.c | 36
1 file changed, 36 insertions
On 7/12/23 13:39, Sunil V L wrote:
Add basic IO controllers and devices like PCI, VirtIO and UART
in the ACPI namespace.
Signed-off-by: Sunil V L
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 87
e macro to ADD_CPU_QDEV_PROPERTIES_ARRAY()
- patch 8 (new):
- add ADD_UNAVAIL_KVM_PROP_ARRAY macro
- v3 link:
https://lore.kernel.org/qemu-riscv/20230714174311.672359-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (11):
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
target/riscv/c
all these properties in
riscv_cpu_add_user_properties() as it is already being done today.
No functional changes made.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
di
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new ratified extensions to be enabled.
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/riscv_opensbi.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/ris
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair
new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu-qom.h | 1 +
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b6d546522..918acb9e6c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1836,8 +1836,6 @@
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a macro to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 26 +++---
1 file changed, 11 insertions(+), 15
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions
st remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
Signed-off-by: Danie
users.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b59b06cddd..4d78276058 100644
--- a/target/
having
to deal with KVM constraints.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 65 ++
1 file changed, 42 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 29f2543f6d..1b6d546522 100644
---
Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition, similar to what we're already doing with
ADD_CPU_QDEV_PROPERTIES_ARRAY().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 22 ++
1 file changed, 10 insertions(+
Hi,
Found these 2 instances while working in more 8.2 material.
I believe both are safe for freeze but I won't lose my sleep if we
decide to postpone it.
Daniel Henrique Barboza (2):
target/riscv/cpu.c: add zmmul isa string
target/riscv/cpu.c: add smepmp isa string
target/riscv/cpu.
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
properties")
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertio
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d64ac0755
tension.
No functional changes made.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 33 +++--
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453..9a3afc0482 100644
--- a/target/riscv
having
to deal with KVM constraints.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 65 ++
1 file changed, 42 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f10d40733a..7f0852a14e 100644
---
users.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3a20a41dfc..7c6060ffa3 100644
--- a/target/
st remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
Signed-off-by: Danie
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions
cpu 'for' loop to use ARRAY_SIZE()
- v4 link:
https://lore.kernel.org/qemu-riscv/20230718210329.200404-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (11):
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
target/riscv/cpu.c: skip 'bool' check when fil
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7f0852a14e..4dadb7f0a0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1835,8 +1835,6 @@
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a macro to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 26 +++---
1 file changed, 11 insertions(+), 15
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new ratified extensions to be enabled.
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/riscv_opensbi.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/ris
new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu-qom.h | 1 +
Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition, similar to what we're already doing with
ADD_CPU_QDEV_PROPERTIES_ARRAY().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 22 ++
1 file changed, 10 insertions(+
dian hosts where the least significant bits
are stored on the lowest address. To do this in a portable way, we have
to store the value in an uint8_t variable instead.
Fixes: 5033606780 ("RISC-V HTIF Console")
Signed-off-by: Thomas Huth
---
Reviewed-by: Daniel Henrique Barboza
hw/c
by: Thomas Huth
---
Reviewed-by: Daniel Henrique Barboza
hw/char/riscv_htif.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index f96df40124..40de6b8b77 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
27; CPU is not compatible with TCG acceleration
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453..08db3d613f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
On 7/21/23 11:37, Philippe Mathieu-Daudé wrote:
On 21/7/23 15:34, Daniel Henrique Barboza wrote:
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do t
On 7/20/23 23:38, Nicholas Piggin wrote:
On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote:
On 7/12/23 11:56 AM, Cédric Le Goater wrote:
Hello Shawn,
On 7/12/23 18:13, Shawn Anastasio wrote:
Change radix model to always generate a storage interrupt when the R/C
bits are not set ap
AmigaOS with VOF and
only touches parts that are used with VOF only so I'd like these to be
merged for 8.1.
Reviewed-by: Daniel Henrique Barboza
And pushed to ppc-next. Thanks,
Daniel
Regards,
BALATON Zoltan (3):
ppc/pegasos2: Fix reset state of USB functions
ppc/pegasos2: Fi
On 7/21/23 19:17, BALATON Zoltan wrote:
On Fri, 21 Jul 2023, Daniel Henrique Barboza wrote:
On 7/18/23 21:32, BALATON Zoltan wrote:
These are some small fixes when using pegasos2 with the QEMU built in
VOF instead of the non-free board firmware that fix bugs in the
generated device tree and
On 7/21/23 19:13, BALATON Zoltan wrote:
The board firmware handles this correctly following the Open Firmware
standard which we missed. This fixes 64 bit BARs when using VOF.
Signed-off-by: BALATON Zoltan
---
Reviewed-by: Daniel Henrique Barboza
And queued. Thanks,
Daniel
hw/ppc
On 7/23/23 23:51, Alistair Francis wrote:
On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza
wrote:
Hi,
Found these 2 instances while working in more 8.2 material.
I believe both are safe for freeze but I won't lose my sleep if we
decide to postpone it.
I wasn't going
Hi,
As some of you are already aware the current RVV emulation could be faster.
We have at least one commit (bc0ec52eb2, "target/riscv/vector_helper.c:
skip set tail when vta is zero") that tried to address at least part of the
problem.
Running a simple program like this:
---
#define SZ 10
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