troducing a
KVM parameter that each architecture which supports KVM_CREATE_IRQCHIP
sets. Adding parameters isn't awesome, but given how the
KVM_CAP_IRQCHIP isn't very helpful on its own, we don't have a lot of
options.
Signed-off-by: Andrew Jones
---
Reviewed-by: Daniel Henrique Barboz
QEMU dependencies
using meson and a cross-file could be shared. Additionally, other
approaches to creating sysroots, such as with debootstrap, may be
documented in this file in the future.
Signed-off-by: Andrew Jones
---
Reviewed-by: Daniel Henrique Barboza
I've also tested the steps and it
On 7/27/23 11:16, Conor Dooley wrote:
On Thu, Jul 27, 2023 at 11:12:34AM -0300, Daniel Henrique Barboza wrote:
On 7/27/23 10:59, Conor Dooley wrote:
Hey Daniel,
On Thu, Jul 20, 2023 at 02:19:31PM -0300, Daniel Henrique Barboza wrote:
The 'max' CPU type is used by tooling to
us_reg): /soc/pmu: missing or empty reg/ranges property
Moving the riscv,pmu node out of the soc bus solves the problem.
Signed-off-by: Conor Dooley
---
Reviewed-by: Daniel Henrique Barboza
CC: Palmer Dabbelt
CC: Alistair Francis
CC: Bin Meng
CC: Weiwei Li
CC: Daniel Henrique Barboza
C
On 7/27/23 10:59, Conor Dooley wrote:
Hey Daniel,
On Thu, Jul 20, 2023 at 02:19:31PM -0300, Daniel Henrique Barboza wrote:
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements t
tension.
No functional changes made.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 33 +++--
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f1a292d967..33a2e9328c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
users.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c8e1de68d3..d829517f40 100644
--- a/target/
c' to get rid of this
message.
Change riscv_cpu_validate_v() to not throw this log message if
env->vext_ver is already set.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/tar
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new ratified extensions to be enabled.
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/riscv_opensbi.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/ris
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a macro to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 26 +++---
1 file changed, 11 insertions(+), 15
having
to deal with KVM constraints.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 65 ++
1 file changed, 42 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2fa2581
st remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
Signed-off-by: Danie
CPU sets a
specific env->vext_ver
- patch 10 (former 9)
- set env->vext_ver in riscv_init_max_cpu_extensions()
- v5 link:
https://lore.kernel.org/qemu-riscv/20230720171933.404398-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (12):
target/riscv/cpu.c: split CPU options fr
Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition, similar to what we're already doing with
ADD_CPU_QDEV_PROPERTIES_ARRAY().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 22 ++
1 file change
new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
---
target/riscv/cpu-qom.h | 1 +
On 7/27/23 21:39, LIU Zhiwei wrote:
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa
extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the
fltq.s
helper function.
Signed-off-by: LIU Zhiwei
---
Reviewed-by: Danie
ther extension enablement
during realize is now done via cpu_cfg_ext_auto_update().
The end goal is that only cpu init() functions will handle extension
flags directly via "cpu->cfg.ext_N = true|false".
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 50
ned-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 ++
target/riscv/kvm.c | 8 +++-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 644ce7a018..3e62881d85 100644
--- a/target/riscv/cpu.c
++
not.
For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 44 +---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv
while enabling RVG will
result in error:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false
--nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
Signed-off-by: Daniel Hen
ts'
hash.
This means that, as is today, all extensions we're setting for the 'max'
CPU will be seen as user set in the future. Let's change set_bool() to
isa_ext_update_enabled() that will just enable/disable the flag on a
certain offset.
Signed-off-by: Daniel Henriq
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza
---
targe
that's the idea. Users will have more power, and the adequate dose
of responsibility that comes with it.
Daniel Henrique Barboza (8):
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
target/riscv: make CPUCFG() macro public
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_
ystem-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension
This didn't happen before because we were enabling 'zca' if 'zce' was enabled
regardless if the user explictly set 'zca' to f
p() is a new helper that will replace the
qdev_property_add_static() calls that our macros are doing to populate
user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
for clarity. Note that the non-extension properties in
riscv_cpu_options[] still need to be d
dilligent to to not introduce new ones.
Michael, feel free to take it via qemu-trivial.
[1]
https://www.qemu.org/docs/master/devel/style.html#low-level-memory-management
Daniel Henrique Barboza (2):
hw/ppc: use g_free() in spapr_tce_table_post_load()
target/ppc: use g_free() in test_opc
Use g_free(table[i]) instead of free(table[i]) to comply with QEMU low
level memory management guidelines.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index
On 7/26/23 15:22, Nicholas Piggin wrote:
Sorry for the delay following up on the fixes, I got sucked down
the decrementer rabbit hole that took longer than expected.
Question about what is suitable for merge at this time and what
should be stable. The first 3 have caused crashes or hangs runn
tcet->mig_table is memcpy'ed from tcet->table, which in turn is created
via spapr_tce_alloc_table().
Use g_free() instead of free() to deallocate it.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
On 7/29/23 12:32, Peter Maydell wrote:
On Fri, 28 Jul 2023 at 21:47, Daniel Henrique Barboza
wrote:
Use g_free(table[i]) instead of free(table[i]) to comply with QEMU low
level memory management guidelines.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/translate.c | 2 +-
1
On 7/29/23 12:35, Peter Maydell wrote:
On Fri, 28 Jul 2023 at 21:57, Daniel Henrique Barboza
wrote:
Here's some trivial changes following Peter's call to arms against
free() and friends in gitlab issue #1798 in an attempt to enforce
our memory management guidelines [1].
To cla
On 7/27/23 05:05, Nikita Shubin wrote:
From: Nikita Shubin
Allow using instances derivative from RISCVCPU
Signed-off-by: Nikita Shubin
---
Currently it is not possible to overload instance of RISCVCPU,
i.e. something like this:
static const TypeInfo riscv_cpu_type_infos[] = {
{
Patch looks correct IMHO. I have a few cosmetic suggestions:
On 7/27/23 05:17, Nikita Shubin wrote:
From: Nikita Shubin
In case of write-only CSR don't return illegal inst error when CSR is
written and lacks read op.
It's worth citing the ISA bits you put down below in the commit msg.
It w
On 7/30/23 22:53, Fei Wu wrote:
riscv virt platform's memory started at 0x8000 and
straddled the 4GiB boundary. Curiously enough, this choice
of a memory layout will prevent from launching a VM with
a bit more than 2000MiB and PCIe pass-thru on an x86 host, due
to identity mapping requirem
: 0xcd
marchid : 0xab
mimpid : 0xef
This bug affects only the generic (rv64) CPUs when running with KVM in a
64 bit env since the 'host' CPU does not allow the machine IDs to be
changed via command line.
Fixes: 1fb5a622f7 ("target/riscv: handle mvendorid/marchid/mimp
On 8/3/23 06:29, Andrew Jones wrote:
On Wed, Aug 02, 2023 at 03:00:58PM -0300, Daniel Henrique Barboza wrote:
cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write
a target_ulong val, i.e. a 64 bit field in a 64 bit host.
Given that we're passing a pointer to the m
On 8/3/23 09:05, Andrew Jones wrote:
On Thu, Aug 03, 2023 at 08:36:57AM -0300, Daniel Henrique Barboza wrote:
On 8/3/23 06:29, Andrew Jones wrote:
On Wed, Aug 02, 2023 at 03:00:58PM -0300, Daniel Henrique Barboza wrote:
cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() alw
-B 0x10 ./a.out
RVV detected
$ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,vlen=128 -B 0x10 ./a.out
RVV not found
Reviewed-by: Daniel Henrique Barboza
Tested-by: Daniel Henrique Barboza
Looks like 8.1 material to me. Thanks,
Daniel
linux-user/elfload.c | 3 ++-
1 file changed, 2 i
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/30/23 08:18, Nicholas Piggin wrote:
Until v2.07s, the VRMA page size (L||LP) was encoded in LPCR[VRMASD].
In v3.0 that moved to the partition table PS field.
The powernv machine can now run KVM HPT guests on POWER9/10 CPUs
From: BALATON Zoltan
The board firmware handles this correctly following the Open Firmware
standard which we missed. This fixes 64 bit BARs when using VOF.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230721221320.1311e745...@zero.eik.bme.hu>
Signed-
From: BALATON Zoltan
The register offset of the ROM BAR is 0x30 not 0x28. This fixes the
reg property entry of the ROM region in the device tree.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-ID:
<6abd73b1211f9d0776dfa5d71d6294f17eecb426.1689725688.git.b
ned-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Message-ID: <20230726182230.433945-2-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/mmu-hash64.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/target/pp
The following changes since commit c26d005e62f4fd177dae0cd70c24cb96761edebc:
Merge tag 'hppa-linux-user-speedup-pull-request' of
https://github.com/hdeller/qemu-hppa into staging (2023-08-03 18:49:45 -0700)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pu
Power Save
mode.
Fixes: 4b236b621bf ("ppc: Initial HDEC support")
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Message-ID: <20230726182230.433945-4-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 6 ++
1 file chang
found.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-ID:
<808ade37aa141563d1ee349254151672bf7a5d59.1689725688.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pegasos2.c | 8
1 file changed, 8 insertions(+)
diff --git a/
From: BALATON Zoltan
The original non-free board firmware sets the command register of the
USB functions to 7 and some guests rely on this for working USB. Match
what the board firmware does when using VOF instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-ID
pport for POWER9 native hash")
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Message-ID: <20230730111842.39292-1-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/mmu-hash64.c | 45 +++--
target/ppc/mmu-hash64
On 2/29/24 15:06, Christoph Müllner wrote:
Running test-fcvtmod triggers the following deprecation warning:
warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
Let's fix that.
Signed-off-by: Christoph Müllner
---
Reviewed-by: Daniel Henriq
[1] https://jira.riscv.org/browse/RVS-438
[2] https://jira.riscv.org/browse/RVS-871
[3] https://jira.riscv.org/browse/RVS-704
[4] https://jira.riscv.org/browse/RVS-1995
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 22 +-
1 file changed, 9 insertions(+), 13 deletion
Hi,
Let's update QEMU KVM extension support up to 6.8-rc6 before the 9.0
freeze.
Patches based on alistair/riscv-to-apply.next.
Daniel Henrique Barboza (2):
linux-headers: Update to Linux v6.8-rc6
target/riscv/kvm: update KVM exts to Linux 6.8
include/standard-headers/drm/drm_fou
The last KVM extensions added were back in 6.6. Sync them to Linux 6.8.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index
The idea with this update is to get the latest KVM caps for RISC-V.
Signed-off-by: Daniel Henrique Barboza
---
include/standard-headers/drm/drm_fourcc.h | 10 +-
include/standard-headers/linux/ethtool.h | 41 +++--
.../standard-headers/linux/virtio_config.h| 8 +-
include
On 2/28/24 15:51, Atish Patra wrote:
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 2 ++
target
v
---
For hw/riscv/virt.c changes:
Acked-by: Daniel Henrique Barboza
PS: I've moved/kept legacy smbios_entries to smbios_get_tables()
but it at least is not visible to API users. To get rid of it
as well, it would be necessary to change how '-smbios' CLI
option is process
On 2/27/24 12:47, Igor Mammedov wrote:
Signed-off-by: Igor Mammedov
---
For hw/riscv/virt.c changes:
Acked-by: Daniel Henrique Barboza
hw/i386/fw_cfg.h | 3 ++-
include/hw/firmware/smbios.h | 5 +++--
hw/arm/virt.c| 4 ++--
hw/i386/fw_cfg.c
On 3/4/24 07:25, Fei Wu wrote:
The RISC-V Server Platform specification[1] defines a standardized set
of hardware and software capabilities, that portable system software,
such as OS and hypervisors can rely on being present in a RISC-V server
platform.
A corresponding Qemu RISC-V server plat
On 3/4/24 07:25, Fei Wu wrote:
The harts requirements of RISC-V server platform [1] require RVA23 ISA
profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
a virt CPU type (rvsp-ref) as compliant as possible.
[1]
https://github.com/riscv-non-isa/riscv-server-platform/blob/m
On 3/5/24 02:56, Wu, Fei wrote:
On 3/5/2024 3:35 AM, Daniel Henrique Barboza wrote:
On 3/4/24 07:25, Fei Wu wrote:
The RISC-V Server Platform specification[1] defines a standardized set
of hardware and software capabilities, that portable system software,
such as OS and hypervisors can
Hi Alistair,
Please don't forget to queue this up. Thanks,
Daniel
On 2/26/24 06:31, Daniel Henrique Barboza wrote:
On 2/25/24 14:41, demin.han wrote:
The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.
Signed-off-by: demin.han
---
Reviewed-by
s: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
Reviewed-by: Daniel Henrique Barboza
hw/intc/riscv_aplic.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/
cification as:
"rectified input value = (incoming wire value) XOR (source is inverted)"
Update the riscv_aplic_read_input_word() implementation to match the above.
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
Review
vide the context.
Tweak it so it provides it. The command above now fails with
{"error": {"class": "GenericError", "desc": "Invalid parameter type for
'modelb.props', expected: dict"}}
Signed-off-by: Markus Armbrust
ment.
Both changes are visible in tests/qtest/arm-cpu-features.c.
Signed-off-by: Markus Armbruster
---
For RISC-V changes:
Acked-by: Daniel Henrique Barboza
target/arm/arm-qmp-cmds.c| 15 ---
target/riscv/riscv-qmp-cmds.c| 19 +--
On 3/6/24 13:10, Max Chou wrote:
When vlmul is larger than 5, the original fractional LMUL checking may
gets unexpected result.
Signed-off-by: Max Chou
---
There's already a fix for it in the ML:
"[PATCH v3] target/riscv: Fix shift count overflow"
https://lore.kernel.org/qemu-riscv/20240
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
t = 0
every time.
While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.in
The global is unused after recent changes.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv
Hi,
This version is rebased on top of alistair/riscv-to-apply.next, fixing
onflicts with the Ztso changes in ldst_us_trans().
No other changes made. All patches acked.
v6 link:
https://lore.kernel.org/qemu-riscv/20240221213140.365232-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (8
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in some load/store functions that were changed. Remove it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-
to save vector
state on task switch."
Do a mark_vs_dirty() before both loads and stores.
[1]
https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aa...@linaro.org/
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Revi
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1 +
1 file
At this moment the global is used only in do_vsetvl(). Do a direct env
load in do_vsetvl() to read 'vl' and remove the global.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-b
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
tar
Hi,
This patch break check-qtest, most specifically 'bios-table'test', for aarch64.
I found this while running riscv-to-apply.next in the Gitlab pipeline.
Here's the output:
$ make -j && QTEST_QEMU_BINARY=./qemu-system-aarch64 V=1
./tests/qtest/bios-tables-test
TAP version 13
# random seed: R
On 3/6/24 15:57, Daniel Henrique Barboza wrote:
As a side note, it seems like 'bios-table-test' isn't being run for RISC-V. Not
sure if this
is intentional or a foresight.
s/foresight/hindsight
There's no 'make check' for what we want to say in the ML but hop
On 3/7/24 00:45, Sunil V L wrote:
On Thu, Mar 07, 2024 at 11:33:25AM +1000, Alistair Francis wrote:
On Thu, Mar 7, 2024 at 4:59 AM Daniel Henrique Barboza
wrote:
Hi,
This patch break check-qtest, most specifically 'bios-table'test', for aarch64.
I found this while r
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/riscv-iommu-bits.h | 20
From: Tomasz Jeznach
This device models the RISC-V IOMMU as a sysbus device.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/meson.build | 2 +-
hw/riscv/riscv-iommu-sys.c | 93 ++
include/hw/riscv/iommu.h | 4
ecome a linux-header we
would import instead of keeping our own. The Linux implementation isn't
upstream yet so for now we'll have to manage riscv-iommu-bits.h.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/riscv-iom
From: Andrew Jones
And add mrif notification trace.
Signed-off-by: Andrew Jones
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/riscv-iommu-pci.c | 2 +-
hw/riscv/riscv-iommu.c | 1 +
hw/riscv/trace-events | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 33 -
1
lizing the IOMMU.
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/libqos/riscv-iommu.h | 29 +++
tests/qtest/riscv-iommu-test.c | 141 +++
2 files changed, 170 insertions(+)
diff --git a/tests/qtest/libqos/riscv-iommu.h b/tests/qtest/libqos/riscv-iom
aniel Henrique Barboza
---
hw/riscv/Kconfig |4 +
hw/riscv/meson.build |1 +
hw/riscv/riscv-iommu.c | 1492 ++
hw/riscv/riscv-iommu.h | 141
hw/riscv/trace-events| 11 +
hw/riscv/trace.h |2 +
include/hw/riscv/iommu.h |
basic tests: a PCI sanity check and a reset state register
test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2,
"Reset behavior".
More tests will be added later.
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/libqos/meson.build | 4 ++
tests/qtest/
iommu: Add another irq for mrif notifications
Daniel Henrique Barboza (2):
test/qtest: add riscv-iommu-pci tests
qtest/riscv-iommu-test: add init queues test
Tomasz Jeznach (12):
exec/memtxattr: add process identifier to the transaction attributes
hw/riscv: add riscv-iommu-bits.h
hw/risc
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
---
include/exec/memattrs.h |
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/meson.build |
From: Tomasz Jeznach
Extension to support DMA with PASID identifier and reporting PASID
extended PCIe capabilities.
Signed-off-by: Tomasz Jeznach
---
hw/misc/edu.c | 57 +++
1 file changed, 44 insertions(+), 13 deletions(-)
diff --git a/hw/misc/
: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/riscv-iommu-bits.h | 11 ++
hw/riscv/riscv-iommu.c | 282 ++--
hw/riscv/riscv-iommu.h | 2 +
3 files changed, 286 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/riscv-iommu-bits.h b
From: Tomasz Jeznach
Mimic ATS interface with IOMMU translate request with IOMMU_NONE. If
mapping exists, translation service will return current permission
flags, otherwise will report no permissions.
Implement and register the IOMMU memory region listener to be notified
whenever an ATS invali
nd
g-stage elements, although we don't support it yet. We'll introduce them
next.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/riscv-iommu.c | 190 -
hw/riscv/riscv-iommu.h | 2 +
2 files changed, 188 insert
On 3/7/24 04:36, Wu, Fei wrote:
On 3/6/2024 9:26 PM, Wu, Fei wrote:
On 3/5/2024 1:58 PM, Wu, Fei wrote:
On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
On 3/4/24 07:25, Fei Wu wrote:
The harts requirements of RISC-V server platform [1] require RVA23 ISA
profile support, plus Sv48
On 3/7/24 09:17, Heinrich Schuchardt wrote:
On 07.03.24 08:36, Wu, Fei2 wrote:
On 3/6/2024 9:26 PM, Wu, Fei wrote:
On 3/5/2024 1:58 PM, Wu, Fei wrote:
On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
On 3/4/24 07:25, Fei Wu wrote:
The harts requirements of RISC-V server platform [1
(--- adding Richard ---)
On 3/6/24 06:33, Huang Tao wrote:
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heteroge
On 3/7/24 17:11, Richard Henderson wrote:
On 3/7/24 09:55, Daniel Henrique Barboza wrote:
(--- adding Richard ---)
On 3/6/24 06:33, Huang Tao wrote:
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
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