Public bug reported:
@@ -165,7 +165,7 @@ static void ide_identify(IDEState *s)
put_le16(p + 76, (1 << 8));
}
put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
- put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
+ put_le16(p + 80, ((1 << 6) | (1 << 5) (1 << 4) (1 << 3));
for what it's worth, i have yet to see a driver actually check this
field.
I have seen a ton of code (OVMF and others) detect other information and
just straight up say "I'm in QEMU" and YOLO a bunch of things like
assuming DMA is available and such, so I somewhat doubt anyone
*actually* checks
I would just fix the comment for now, likewise I don't have the time to audit
whether the emulation provides full coverage of the standard.
Really there's two cases here
1) We report ATA4-7 (current status), someone discovers missing bits feature
Response: They file a ticket on the missing
On Mon, Sep 04, 2023 at 06:02:14PM +0100, Jonathan Cameron wrote:
> On Thu, 31 Aug 2023 21:29:13 -0400
> Gregory Price wrote:
>
> > When memory accesses are made, some MHSLD's would validate the address
> > is within the scope of allocated sections. To do this, the base
On Tue, Sep 05, 2023 at 11:04:56AM +0200, Philippe Mathieu-Daudé wrote:
> On 1/9/23 03:29, Gregory Price wrote:
> > v2:
> > - 5 patch series, first 4 are pull-aheads that can be merged separately
> >
> > This patch set includes an emulation of the SK hynix Niagara MHS
On Tue, Sep 05, 2023 at 10:59:15AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Gregory,
>
> On 1/9/23 03:29, Gregory Price wrote:
> > For devices built on top of ct3, we need the init, realize, and
> > exit functions exposed to correctly start up and tear down.
>
> Yo
For multi-headed type 3 devices, this command reports logical device
mappings for each head. Implement a callback which can be
initialized by MHD devices to field these commands.
Reports "unsupported" if the command is called but the callback is
not implemented.
Signed-off-by: Gre
Preparation for allowing devices to define their own CCI commands
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 30 +-
include/hw/cxl/cxl_mailbox.h | 18 ++
2 files changed, 31 insertions(+), 17 deletions(-)
create mode 100644
For devices built on top of ct3, we need the init, realize, and
exit functions exposed to correctly start up and tear down.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 6 +++---
include/hw/cxl/cxl_device.h | 4
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git
of sections
section_size : size of a section in 128mb increments
shmid : shmid produced by ipcmk
Example:
$shmid1=ipcmk -M 131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig | 4 +
hw/cxl/meson.build
When memory accesses are made, some MHSLD's would validate the address
is within the scope of allocated sections. To do this, the base device
must call an optional function set by inherited devices.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 15 +++
include/hw
CXL commands to be passed through
the mailbox driver, so users should enable
`CONFIG_CXL_MEM_RAW_COMMANDS=y` on the kernel of their QEMU instance
if they wish to test it.
Signed-off-by: Gregory Price
Gregory Price (6):
cxl/mailbox: move mailbox effect definitions to a header
cxl/type3
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index fd9d134d46..80d596ee10 100644
--- a/hw/mem
On Mon, Aug 07, 2023 at 03:56:09PM +0100, Jonathan Cameron wrote:
> On Fri, 21 Jul 2023 12:35:08 -0400
> Gregory Price wrote:
>
> > Implement the MHD GET_INFO cci command and add a shared memory
> > region to the type3 device to host the information.
> >
> > A
of sections
section_size : size of a section in 128mb increments
shmid : shmid produced by ipcmk
Example:
$shmid1=ipcmk -M 131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
Signed-off-by: Junhee Ryu
Signed-off-by: Kwangjin Ko
---
hw/cxl/Kconfig
Preparation for allowing devices to define their own CCI commands
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 35 +++
include/hw/cxl/cxl_mailbox.h | 18 ++
2 files changed, 37 insertions(+), 16 deletions(-)
create mode 100644
allowing raw CXL commands to be passed through the mailbox
driver, so users should enable `CONFIG_CXL_MEM_RAW_COMMANDS=y` on the
kernel of their QEMU instance if they wish to test it
Signed-off-by: Gregory Price
Gregory Price (5):
cxl/mailbox: move mailbox effect definitions to a header
cxl/type3
For devices built on top of ct3, we need the init, realize, and
exit functions exposed to correctly start up and tear down.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 8
include/hw/cxl/cxl_device.h | 5 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff
When memory accesses are made, some MHSLD's would validate the address
is within the scope of allocated sections. To do this, the base device
must call an optional function set by inherited devices.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 15 +++
include/hw
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index fd9d134d46..80d596ee10 100644
--- a/hw/mem
On Wed, Sep 06, 2023 at 02:04:45PM +0100, Jonathan Cameron wrote:
> On Thu, 31 Aug 2023 21:29:14 -0400
> Gregory Price wrote:
>
> Hi Gregory,
>
> Some comments inline, but I'm happy to add this to my staging tree in the
> meantime
> as it stands (might be a few days u
Niagara uses which presently limits its compatibility to
linux hosts. Change build to only build it on linux.
Add Kconfig file for skhynix directory, and make niagara depend on
CXL_MEM_DEVICE and LINUX. Add an explicit flag for niagara.
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig
On Wed, Sep 20, 2023 at 01:46:18PM +0100, Jonathan Cameron wrote:
> On Mon, 18 Sep 2023 13:36:56 -0400
> Gregory Price wrote:
>
> > Create a new device to emulate the SK hynix Niagara MHSLD platform.
> >
>
> Hi Gregory,
>
> Seems this doesn't drop in
of sections
section_size : size of a section in 128mb increments
shmid : shmid produced by ipcmk
Example:
$shmid1=ipcmk -M 131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
Signed-off-by: Junhee Ryu
Signed-off-by: Kwangjin Ko
---
hw/cxl/Kconfig
v4 update: Kconfig and meson fixes
Since Niagara uses , it presently can only be built
for linux. Also addings missing Kconfig files and options
to turn it off, and turns it off by default if VENDOR or
CXL_MEM_DEVICE are turned off.
Gregory Price (1):
cxl/vendor: SK hynix Niagara Multi-Headed
Niagara uses which presently limits its compatibility to
linux hosts. Change build to only build it on linux.
Add Kconfig file for skhynix directory, and make niagara depend on
CXL_MEM_DEVICE. Add an explicit flag for niagara.
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig
er.
To save some list spam, I can't say i've reviewed and tested the entire
set, but this patch series to help model the Niagara work so please add
my tags as appropriate to the above.
Reviewed-by: Gregory Price
Tested-by: Gregory Price
~Gregory
AM Gregory Price
> wrote:
> >
> > Early-boot e820 records will be inserted by the bios/efi/early boot
> > software and be reported to the kernel via insert_resource. Later, when
> > CXL drivers iterate through the regions again, they will insert another
> > resour
> > -e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
> > memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
> > memory_region_add_subregion(system_memory, cxl_base, mr);
> > cxl_resv_end = cxl_base + cxl_size;
> > @@ -1077,7 +1076,6 @@ void
On Fri, Oct 14, 2022 at 04:10:44PM +0100, Jonathan Cameron wrote:
> From: Huai-Cheng Kuo
>
> The CDAT can be specified in two ways. One is to add ",cdat="
> in "-device cxl-type3"'s command option. The file is required to provide
> the whole CDAT table in binary mode. The other is to use the
at DPA(0x0), while Persistent memory is mapped
at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
Signed-off-by: Gregory Price
---
docs/system/devices/cxl.rst | 53 +--
hw/cxl/cxl-mailbox-utils.c | 21 ++-
hw/mem/cxl_type3.c |
s
`cxl create-region` to always fail.
Signed-off-by: Gregory Price
---
hw/i386/pc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 768982ae9a..203c90fedb 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1062,7 +1062,6 @@ void pc_memory_init(PCMachineState *p
ory regions may be supported on
following patch sets.
Gregory Price (4):
hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios
hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition
hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
hw/acpi/cxl.c: Fill in SRAT for v
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
---
hw/cxl/cxl-mailbox-utils.c | 14 --
1 file changed, 8 insertions(+), 6 deletions
-off-by: Gregory Price
---
docs/system/devices/cxl.rst | 21
hw/acpi/cxl.c | 67 +
hw/i386/acpi-build.c| 4 +++
include/hw/acpi/cxl.h | 1 +
4 files changed, 93 insertions(+)
diff --git a/docs/system/devices/cxl.rst b
On Wed, Oct 26, 2022 at 08:13:24PM +, Adam Manzanares wrote:
> On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > Submitted as an extention to the multi-feature branch maintained
> > by Jonathan Cameron at:
> > https://urldefense.com/v3/__https://gitlab.
s
`cxl create-region` to always fail.
Signed-off-by: Gregory Price
---
hw/i386/pc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 768982ae9a..203c90fedb 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1062,7 +1062,6 @@ void pc_memory_init(PCMachineState *p
On Wed, Oct 26, 2022 at 04:20:40PM -0400, Michael S. Tsirkin wrote:
> On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > Submitted as an extention to the multi-feature branch maintained
> > by Jonathan Cameron at:
> > https://gitlab.com/jic23/qemu/-/tree/cxl-20
:06 PM
To: Gregory Price
Cc: qemu-devel@nongnu.org; jonathan.came...@huawei.com;
linux-...@vger.kernel.org; alison.schofi...@intel.com; d...@stgolabs.net;
a.manzana...@samsung.com; bwida...@kernel.org; Gregory Price
Subject: Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type
On Wed, Oct 26, 2022 at 04:11:29PM -0400, Michael S. Tsirkin wrote:
> He does but in the end he sends patches not pull requests.
> I don't care really as long as someone will send it up.
>
Jonathan will submit this, it's not a critical issue so it can wait for
the larger feature set.
0100, Jonathan Cameron wrote:
> On Wed, 26 Oct 2022 16:47:18 -0400
> Gregory Price wrote:
>
> > On Wed, Oct 26, 2022 at 08:13:24PM +, Adam Manzanares wrote:
> > > On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > > > Submitted as an extentio
_intersects()`. Due to this reserved area, the
intersect check will only ever return REGION_INTERSECTS, which causes
`cxl create-region` to always fail.
Signed-off-by: Gregory Price
---
hw/i386/pc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 566accf7e6..5bf5465a21
Makes the size of the allocated cdat table static (6 entries),
flattens the code, and reduces the number of exit conditions
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 52 --
1 file changed, 22 insertions(+), 30 deletions(-)
diff --git a/hw
This code contains heap corruption on free, and I think should be
refactored to pre-allocate all the entries we're interested in putting
into the table. This would flatten the code and simplify the error
handling steps.
Also, should we consider making a union with all the possible entries to
The existing code allocates a subtable for SLBIS entries, uses a
local variable to avoid a g_autofree footgun, and the cleanup code
causes heap corruption.
Rather than allocate a table, explicitly allocate each individual entry
and make the sub-table size static.
Signed-off-by: Gregory Price
For style - pulling these validations ahead flattens the code.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 193 ++---
1 file changed, 96 insertions(+), 97 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 94bc439d89
resolves a heap
corruption bug
5) Refactor of CDAT initialization code into a function that initializes
sub-tables per memory-region.
Gregory Price (5):
hw/mem/cxl_type3: fix checkpatch errors
hw/mem/cxl_type3: Pull validation checks ahead of functional code
hw/mem/cxl_type3: CDAT pre
This fixes checkpatch errors in the prior commit.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 3fa5d70662..94bc439d89 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw
The CDAT can contain multiple entries for multiple memory regions, this
will allow us to re-use the initialization code when volatile memory
region support is added.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 137 -
1 file changed, 72
turn ret;
}
On Thu, Oct 13, 2022 at 12:53:13PM +0100, Jonathan Cameron wrote:
> On Thu, 13 Oct 2022 07:36:28 -0400
> Gregory Price wrote:
>
> > Reading through your notes, everything seems reasonable, though I'm not
> > sure I agree with the two pass notion, though I'll
) and
allocate the table as I have once we know how many MRs are present?
6 eggs/half dozen though, I'm ultimately fine with either.
On Thu, Oct 13, 2022, 4:58 AM Jonathan Cameron
wrote:
> On Wed, 12 Oct 2022 14:21:15 -0400
> Gregory Price wrote:
>
> > Included in this response is a recomm
Cameron wrote:
> On Thu, 13 Oct 2022 13:09:26 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Thu, Oct 13, 2022 at 12:26:58PM -0400, Gregory Price wrote:
> > > Other than the nitpicks below, lgtm. Not sure if you need a sign off
> > > from me given the contrib
> > /* For now, no memory side cache, plausiblish numbers */
> > -*dslbis_nonvolatile1 = (CDATDslbis) {
> > +*dslbis1 = (CDATDslbis) {
> > .header = {
> > .type = CDAT_TYPE_DSLBIS,
> > -.length = sizeof(*dslbis_nonvolatile1),
> > +.length
Other than the nitpicks below, lgtm. Not sure if you need a sign off
from me given the contributions:
Signed-off-by: Gregory Price
> +/* If no cdat_table == NULL returns number of entries */
> +static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat
Context included below from prior discussion
- `cxl create-region` would fail on inability to allocate memory
- traced this down to the memory region being marked RESERVED
- E820 map marks the CXL fixed memory window as RESERVED
Re: x86 errors, I found that region worked with this
On Thu, Oct 06, 2022 at 09:50:07AM +0100, Jonathan Cameron wrote:
> On Thu, 6 Oct 2022 09:45:57 +0100
> Jonathan Cameron wrote:
>
> > Great to see this.
> >
> > Missing Signed-off by so we can't apply this (no developer certificate of
> > origin) Probably want your from address to match that
CDAT". Do the devices presently emulate this? I'm
finding it hard to pick
apart the code to identify it.
On Thu, Oct 6, 2022 at 1:30 PM Gregory Price
wrote:
> On Thu, Oct 06, 2022 at 05:42:14PM +0100, Jonathan Cameron wrote:
> > >
> > > 1) The PCI device typ
On Thu, Oct 06, 2022 at 05:42:14PM +0100, Jonathan Cameron wrote:
> >
> > 1) The PCI device type is set prior to realize/attributes, and is
> > currently still set to PCI_CLASS_STORAGE_EXPRESS. Should this instead
> > be PCI_CLASS_MEMORY_CXL when presenting as a simple memory expander?
>
> We
On Fri, Oct 07, 2022 at 11:16:19AM -0700, Davidlohr Bueso wrote:
>
> Yeah, putting this back together was on my todo list, but happy to see
> patches are out. Recollecting my thoughts on this, my original approach
> was also to support only volatile or persistent capacities, but through
> two
ces to represent DIMMs on a Single-Logical-Device
MemoryExpander fairly straightforward.
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 22 ++
hw/mem/cxl_type3.c | 46 +
include/hw/cxl/cxl_device.h | 7 +-
3 files chan
Current code sets to STORAGE_EXPRESS and then overrides it.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index ada2108fac..1837c1c83a 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem
>
> https://gitlab.com/jic23/qemu/-/commits/cxl-2022-10-09
> There are a few messy corners in that tree but it should work. I'll be
> pushing out a new version in a few days.
>
> I updated that in latest version to build the tables based on the
> memdev provided. We'll want to add the volatile
Hang tight, I'm whipping up a multi-region patch that will support a
vmem and pmem region and such. Finally got oriented enough to figure
out the DPA decoding a bit. I will probably need some help validating
the decoder logic and the CDAT table logic.
I will integrate the suggestions below
> >
> > Maybe we should consider 2 new options:
> > --persistent-memdevs=pm1 pm2 pm3
> > --volatile-memdevs=vm1 vm2 vm3
> >
> > etc, and deprecate --memdev, and go with your array of memdevs idea.
> >
> > I think I could probably whip that up in a day or two. Thoughts?
>
> I wonder if we care
and Read/Write Change Validation*
5/5: Test and documentation update
On Mon, Oct 10, 2022 at 11:25:31AM -0400, Gregory Price wrote:
> >
> > https://gitlab.com/jic23/qemu/-/commits/cxl-2022-10-09
> > There are a few messy corners in that tree but it should work. I'll be
> > p
to mailing list contributions, where would these
go exactly?
On Tue, Oct 11, 2022 at 10:14:38AM -0700, Davidlohr Bueso wrote:
> On Mon, 10 Oct 2022, Gregory Price wrote:
>
> > I've pushed 5 new commits to this branch here (@Jonathan I've also made
> > a merge request to pull the
This is a preparatory commit for enabling multiple memory regions within
a single CXL Type-3 device. We will need to initialize multiple CDAT
DSMAS regions (and subsequent DSLBIS, and DSEMTS entries), so generalize
the intialization into a function.
Signed-off-by: Gregory Price
---
hw/mem
MAS
entry concerns memory mapping and is required to successfully map memory
regions correctly in bios/efi.
Gregory Price (5):
hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition
hw/mem/cxl_type: Generalize CDATDsmas initialization for Mem
Current code sets to STORAGE_EXPRESS and then overrides it.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Reviewed-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index
at DPA(0x0), while Persistent memory is mapped
at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 21 ++--
hw/mem/cxl_type3.c | 197 ++--
include/hw/cxl/cxl_device.h | 11 +-
Adds explicit examples for --persistent-memdev and --volatile-memdev
Signed-off-by: Gregory Price
---
docs/system/devices/cxl.rst | 53 ++--
tests/qtest/cxl-test.c | 81 +++--
2 files changed, 110 insertions(+), 24 deletions(-)
diff
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
---
hw/cxl/cxl-mailbox-utils.c | 14 --
1 file changed, 8 insertions(+), 6 deletions
On Wed, Jan 11, 2023 at 02:24:32PM +, Jonathan Cameron via wrote:
> Gregory's patches were posted as part of his work on adding volatile support.
> https://lore.kernel.org/linux-cxl/20221006233702.18532-1-gregory.pr...@memverge.com/
>
On Thu, Jan 12, 2023 at 05:21:30PM +, Jonathan Cameron wrote:
> On Thu, 12 Jan 2023 10:39:17 -0500
> Gregory Price wrote:
>
> > On Wed, Jan 11, 2023 at 02:24:32PM +, Jonathan Cameron via wrote:
> > > Gregory's patches were posted as part of his work on adding
Ah I see, i forgot about that one. Give me a bit and I'll see if it is the
same issue.
On Fri, Jan 13, 2023 at 9:41 AM Jonathan Cameron <
jonathan.came...@huawei.com> wrote:
> On Fri, 13 Jan 2023 09:19:59 -0500
> Gregory Price wrote:
>
> > On Fri, Jan 13, 2023 at 09:12
On Fri, Jan 13, 2023 at 04:12:06PM +0100, Lukas Wunner wrote:
> On Fri, Jan 13, 2023 at 02:45:11PM +, Jonathan Cameron wrote:
> > On Fri, 13 Jan 2023 14:40:26 + Jonathan Cameron
> > wrote:
> > > On Fri, 13 Jan 2023 09:19:59 -0500 Gregory Price
> > > wr
On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote:
>
> Just to check, are these different from the on stack problem you reported
> previously? Doesn't look like the fix for that has made it upstream yet.
>
> What kernel are you running?
>
>
The prior issue I saw was related to
instances.
On Tue, Jan 3, 2023, 10:56 AM Jonathan Cameron
wrote:
> On Tue, 20 Dec 2022 14:27:31 -0500
> Gregory Price wrote:
>
> > On Tue, Dec 20, 2022 at 03:34:53PM +, Jonathan Cameron wrote:
> > > > However I don't think this is successful in creating the dax dev
On Mon, Dec 19, 2022 at 12:42:11PM +, Jonathan Cameron wrote:
> As a process thing, when reworking a patch I picked up for the
> CXL qemu gitlab tree, drop the SOB that I added as it's not relevant
> to the new patch.
>
ack
> Still no need to post a new version unless you particularly
>
> I think an address space needs a memory region, not a memdev.
> Initialize a container region with memory_region_init()
> We could then add the two memdev associated regions (with different
> attributes) as subregions using memory_region_add_subregion()
>
> Similar is done for the system
On Tue, Dec 20, 2022 at 03:34:53PM +, Jonathan Cameron wrote:
> > However I don't think this is successful in creating the dax devices,
> > and therefore the reconfiguring into ram.
>
> Sure. I only bothered testing the it in some dax modes rather than via kmem.
> It 'should' work but more
On Thu, Dec 08, 2022 at 10:55:58PM +, Fan Ni wrote:
> On Mon, Nov 28, 2022 at 10:01:57AM -0500, Gregory Price wrote:
> >
> > -if (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) {
> > +if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) ||
&g
> > - -object
> > memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M
> > \
> > - -object
> > memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \
> > + -object
> >
From: Gregory Price
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/cxl
DPA immediately following the volatile capacity
Partitioning of Persistent Memory regions may be supported on following
patch sets, but is not supported in this version.
Gregory Price (3):
hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition
tests/qtest/cxl-test: whitespace, line ending cleanup
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
---
tests/qtest/cxl-test.c | 99 +++---
1 file changed, 54 insertions(+), 45 deletions(-)
diff --git a/tests/qtest/cxl
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been
On Thu, Jan 19, 2023 at 05:31:12PM +, Jonathan Cameron wrote:
> On Thu, 19 Jan 2023 12:15:45 -0500
> Gregory Price wrote:
>
> > Found a bug, not sure how we missed this, probably happed with rebasing
> > and some fixups. We're presently reporting the volatile region a
On Thu, Jan 19, 2023 at 10:19:46AM +, Jonathan Cameron wrote:
> Even if everything else worked, it will currently fail because of the
> issue with pass through decoders.
> (Kernel assumes always pass through for single rp, qemu assumes never
> pass through - both are valid under spec).
> Add
On Thu, Jan 19, 2023 at 06:48:11AM -0500, Michael S. Tsirkin wrote:
> >
> > I clearly need to run some more rests as not seen this issue (and I've
> > had a couple of reports of it now). I guess I never tend to be running
> > a completely clean tree on either side + testing is mostly on arm64
>
Found a bug, not sure how we missed this, probably happed with rebasing
and some fixups. We're presently reporting the volatile region as
non-volatile, 1 line patch.
Jonathan do you want a separate patch shipped or would you rather just
apply a fixup to the commit in your current branch?
diff
On Thu, Jan 19, 2023 at 03:04:49PM +, Jonathan Cameron wrote:
> Gregory, would you mind checking if
> cxl_nvb is NULL here...
> https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/pmem.c#L67
> (printk before it is used should work).
>
> Might also be worth checking cxl_nvd and cxl_ds
On Thu, Jan 19, 2023 at 04:17:11PM +, Jonathan Cameron wrote:
>
> Whilst I still have no idea if this is the same problem, I have identified
> what goes wrong if there is a module probe ordering issue.
> https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/core/pmem.c#L306
>
>
On Fri, Jan 20, 2023 at 09:38:13AM -0800, Dan Williams wrote:
> As it stands currently that dax device and the cxl device are not
> related since a default dax-device is loaded just based on the presence
> of an EFI_MEMORY_SP address range in the address map. With the new ram
> enabling that
On Mon, Jan 30, 2023 at 01:11:50PM +, Jonathan Cameron wrote:
> On Thu, 5 Jan 2023 14:38:07 +
> Jonathan Cameron wrote:
>
> > On Mon, 28 Nov 2022 10:01:56 -0500
> > Gregory Price wrote:
> >
> > > Defines are starting to exceed line length limits, ali
On Mon, Jan 30, 2023 at 01:24:51PM +, Jonathan Cameron wrote:
>
> > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> > index e59ba22387..6893f54e28 100644
> > --- a/tests/qtest/cxl-test.c
> > +++ b/tests/qtest/cxl-test.c
> > @@ -40,32 +40,46 @@
> >"-device
Tested and reviewed this series (except my own patches, obviously).
Reviewed-by: Gregory Price
Tested-by: Gregory Price
On Mon, Jan 30, 2023 at 02:36:55PM +, Jonathan Cameron wrote:
> V3: Thanks to Michael Tsirkin
> - Update tests/data/acpi/q35/DSDT.cxl to reflect dr
I apparently forgot an intro lol
I tested the DOE linux branch with the 2023-1-11 QEMU branch with both
volatile, non-volatile, and "legacy" (pre-my-patch) non-volatile mode.
1) *In volatile mode, there are no stack traces present (during boot*)
On Wed, Jan 18, 2023 at 02:22:08PM -050
1) No stack traces present
2) Device usage appears to work, but cxl-cli fails to create a region, i
haven't checked why yet (also tried ndctl-75, same results)
3) There seems to be some other regression with the cxl_pmem_init
routine, because I get a stack trace in this setup regardless of
On Fri, Jan 20, 2023 at 02:41:05PM -0800, Dan Williams wrote:
>
> Which mode are you referring?
>
> The next steps for the kernel enabling relevant to this thread are:
>
> * ram region discovery (platform firmware or kexec established)
> * ram region creation
> * pmem region discovery (from
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