Resending to expand CC list. Looking in particular for review of the QAPI
part of patch 8.
v6: Thanks to Philippe Mathieu-Daudé
- Added 'Since' entries to qapi docs.
- Added error prints to stubs rather than doing nothing at all.
(these two comments will be applied to the Poison injeciton series
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pcie_aer.c | 4
On Thu, 2 Mar 2023 05:59:16 -0500
"Michael S. Tsirkin" wrote:
> On Fri, Feb 24, 2023 at 04:37:39PM +0100, Igor Mammedov wrote:
> > Series extends acpi-index support to host-bridge(s) and bridges
> > with disabled hotplug (either explicitly or implicitly).
> > Whats new (it is still limited to
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
v2:
- Endian fix
---
hw/cxl/cxl-mailbox-utils.c | 79 +
hw/mem/cxl_type3.c | 36
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Signed-off-by: Jonathan
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size specifier is limiting. So "24" was
used for
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v8:
Picked up tag from Fan Ni
---
hw/cxl/cxl-device-utils.c | 15
Given the increasing usage of this mailbox return code type, now
is a good time to switch to QEMU style naming.
Reviewed-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v8: Picked up tag from Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 64
v3:
- Gather tags. Thanks Fan Ni
- CC qapi maintainers. Thanks Michael Tsirkin
Note Alison has stated the kernel series will be post 6.3 material
so this one isn't quite as urgent as the patches it is based on.
However I think this series in a good state (plus I have lots more queued
behind it)
Jonathan Cameron via wrote:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
> capability.
>
> For uncorrectable errors: support multiple injection in one operation
> as this is
On Wed, 1 Mar 2023 17:15:56 -0800
Alison Schofield wrote:
> On Mon, Feb 27, 2023 at 05:03:05PM +, Jonathan Cameron wrote:
>
> Hi Jonathan,
> Can you share your repo with this support? How about your qemu cmdline?
> I'm more of a 'try it out' type of a reviewer for qemu changes.
Fan Ni has offered to help out with QEMU CXL emulation reviewing.
Add him as a designated reviewer.
Signed-off-by: Jonathan Cameron
--
Thanks to Fan for stepping up after I requested help following Ben
stepping down as co-maintainer. Fan base been active in testing
and review recently so great
On Mon, 27 Feb 2023 11:06:47 +
Jørgen Hansen wrote:
> On 2/18/23 11:22, Gregory Price wrote:
> > Breaking this off into a separate thread for archival sake.
> >
> > There's a bug with handling execution of instructions held in CXL
> > memory - specifically when an instruction crosses a page
These events include a copy of the device health information at the
time of the event. Actually using the emulated device health would
require a lot of controls to manipulate that state. Given the aim
of this injection code is to just test the flows when events occur,
inject the contents of the
Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
provides information related to DRAM devices.
Example injection command in QMP:
{ "execute": "cxl-inject-dram-event",
"arguments": {
"path": "/machine/peripheral/cxl-mem0",
"log": "informational",
"flags":
From: Ira Weiny
To facilitate testing provide a QMP command to inject a general media
event. The event can be added to the log specified.
Signed-off-by: Ira Weiny
Link:
https://lore.kernel.org/r/20221221-ira-cxl-events-2022-11-17-v2-8-2ce2ecc06...@intel.com
Signed-off-by: Jonathan Cameron
From: Ira Weiny
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
commands. Enable those commands to control interrupts for each of the
event log types.
Skip the standard input mailbox length on the Set command due to DCD
being optional. Perform the checks separately.
From: Ira Weiny
CXL testing is benefited from an artificial event log injection
mechanism.
Add an event log infrastructure to insert, get, and clear events from
the various logs available on a device.
Replace the stubbed out CXL Get/Clear Event mailbox commands with
commands that operate on
Following patches will need access to the mailbox return code
type so move it to the header.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 28
include/hw/cxl/cxl_device.h | 28
2 files changed,
From: Ira Weiny
The device status register block was defined. However, there were no
individual registers nor any data wired up.
Define the event status register [CXL 3.0; 8.2.8.3.1] as part of the
device status register block. Wire up the register and initialize the
event status for each
Whilst I'm an optimist, I suspect this is now 8.1 material because we have
5 CXL patch sets outstanding before it. One of the earlier series has non
trivial
PCI changes, so I'm hoping to route all these through Michael Tsirkin as for
previous releases.
v3: A lot of changes due to rebasing on
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
v2:
- Endian fix
---
hw/cxl/cxl-mailbox-utils.c | 79 +
hw/mem/cxl_type3.c | 36
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Signed-off-by: Jonathan
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size specifier is limiting. So "24" was
used for
Given the increasing usage of this mailbox return code type, now
is a good time to switch to QEMU style naming.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
--
v7: (thanks to Ira Weiny for review)
- Rename in place as the move to the header isn't needed for this series
That move
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-device-utils.c | 15 +++
hw/cxl/cxl-mailbox-utils.c | 11
v2: Thanks to Ira for review and also to Philippe as some of the
changes follow through from comments on precusor series.
- Fixed a bunch of endian issues. Note that QEMU CXL suppport only currently
supports platforms that happen to be little endian so these are more
theoretical than bugs
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84 +++---
1 file changed, 46
v4: Thanks to Philippe for review.
- Fixed up little endian issues in code that was changing anyway.
- Added deprected docs entry.
Based on following series (in order)
1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream
2. [PATCH v6 0/8] hw/cxl: RAS error emulation and
The CXL r3.0 specification allows for there to be no HDM decoders on CXL
Host Bridges if they have only a single root port. Instead, all accesses
directed to the host bridge (as specified in CXL Fixed Memory Windows)
are assumed to be routed to the single root port.
Linux currently assumes this
These two helpers enable host bridges to operate differently depending on
the number of downstream ports, in particular if there is only a single
port.
Useful for CXL where HDM address decoders are allowed to be implicit in
the host bridge if there is only a single root port.
Signed-off-by:
v2:
- Rebase and pick up tags.
- State prereq patche sets more clearly.
Mostly sending out again because some of the precursors have been updated
and to fix a typo in a tag given on v1.
Until now, testing using CXL has relied up always using two root ports
below a host bridge, to work around a
On Tue, 21 Feb 2023 17:18:01 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > Very simple implementation to allow testing of corresponding
> > kernel code. Note that for now we track each 64 byte section
> > independently. Whilst a valid implementation choice, it may
> > make sense to fuse
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Reviewed-by: Dave Jiang
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pcie_aer.c | 4
v6: Thanks to Philippe Mathieu-Daudé
- Added 'Since' entries to qapi docs.
- Added error prints to stubs rather than doing nothing at all.
(these two comments will be applied to the Poison injeciton series as well)
- Picked up tags
Long discussion on whether there was a good way to make the qapi
On Thu, 23 Feb 2023 14:27:48 +
Jonathan Cameron wrote:
> On Thu, 23 Feb 2023 08:37:46 +0100
> Markus Armbruster wrote:
>
> > Thomas Huth writes:
> >
> > > On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> > >> +Thomas (meson) & Marc-André (conditional QAPI)
> > >
> > > +
On Tue, 21 Feb 2023 17:47:23 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > Needs tidy up and rename to something more generic now it is
> > in a header.
>
> I'm not opposed to this change and patch 2 but I don't see where
> CXLRetCode is being used outside of cxl-mailbox-utils.c in
On Fri, 24 Feb 2023 00:29:47 +
Fan Ni wrote:
> On Mon, Feb 20, 2023 at 11:46:46AM +, Jonathan Cameron wrote:
>
> > On Fri, 17 Feb 2023 06:08:57 -0500
> > Gregory Price wrote:
> >
> > > On Fri, Feb 17, 2023 at 04:16:17PM +, Jonathan Cameron vi
On Thu, 23 Feb 2023 08:37:46 +0100
Markus Armbruster wrote:
> Thomas Huth writes:
>
> > On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> >> +Thomas (meson) & Marc-André (conditional QAPI)
> >
> > + Markus
> >
> >> On 22/2/23 17:49, Jonathan Cameron wrote:
>
> [...]
>
> >>
On Tue, 21 Feb 2023 17:14:05 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > Inject poison using qmp command cxl-inject-poison to add an entry to the
> > poison list.
> >
> > For now, the poison is not returned CXL.mem reads, but only via the
> > mailbox command Get Poison List.
> >
> >
...
> >>> +# Type of uncorrectable CXL error to inject. These errors are reported
> >>> via
> >>> +# an AER uncorrectable internal error with additional information logged
> >>> at
> >>> +# the CXL device.
> >>> +#
> >>> +# @cache-data-parity: Data error such as data parity or data ECC error
On Tue, 21 Feb 2023 23:15:49 +0100
Philippe Mathieu-Daudé wrote:
> Hi Jonathan,
>
> On 21/2/23 16:21, Jonathan Cameron wrote:
> > CXL uses PCI AER Internal errors to signal to the host that an error has
> > occurred. The host can then read more detailed status from the CXL RAS
> > capability.
>
On Tue, 21 Feb 2023 14:00:21 +
Jonathan Cameron wrote:
> v3: Noticed whilst chasing an unrelated kernel bug.
> - Drop setting of DVSEC range base addresses. Whilst harmless,
>expectation is that this will be 0 until the OS sets it (or uses
>HDM decoders instead)
>
> Based on
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Reviewed-by: Dave Jiang
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Reviewed-by: Dave Jiang
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Reviewed-by: Dave Jiang
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Reviewed-by: Dave Jiang
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 4
v5: thanks to Dave Jiang for review.
- Spell out Implementation Defined.
- Pick up Dave's tags - thanks!
v4:
In response to similar feedback on poison injection series (Markus Armbruster).
- More detailed documentation in cxl.json
- Based on tag in format suggested by Markus.
Based on series
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84 +++---
1 file changed, 46
v3: Noticed whilst chasing an unrelated kernel bug.
- Drop setting of DVSEC range base addresses. Whilst harmless,
expectation is that this will be 0 until the OS sets it (or uses
HDM decoders instead)
Based on following series (in order)
1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups
On Mon, 20 Feb 2023 22:24:37 +0100
Markus Armbruster wrote:
> Ben is no longer with intel. He told me he expected to get back to
> CXL, but it's not happening as quickly as he'd like, and that it's
> best to remove him as maintainer. So let's do that.
>
> Thank you for serving as maintainer,
On Fri, 17 Feb 2023 06:08:57 -0500
Gregory Price wrote:
> On Fri, Feb 17, 2023 at 04:16:17PM +0000, Jonathan Cameron via wrote:
> > On Tue, 31 Jan 2023 16:38:47 +
> > Jonathan Cameron via wrote:
> >
> > > From: Gregory Price
> > >
> >
> > static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
> > unsigned size)
> > {
> > @@ -341,6 +402,83 @@ static void ct3d_reg_write(void *opaque, hwaddr
> > offset, uint64_t value,
> > should_commit = FIELD_EX32(value,
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 77 +
hw/mem/cxl_type3.c | 36 +
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Signed-off-by: Jonathan
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here:
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-device-utils.c | 15 +++
hw/cxl/cxl-mailbox-utils.c | 11
This enum typedef used to be local to one file, so having a generic
name wasn't a big problem even if it wasn't compliant with QEMU naming
conventions. Now it is in cxl_device.h to support use outside of
cxl-mailbox-utils.c rename it.
Signed-off-by: Jonathan Cameron
---
Needs tidy up and rename to something more generic now it is
in a header.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 28
include/hw/cxl/cxl_device.h | 28
2 files changed, 28 insertions(+), 28 deletions(-)
diff
Note Alison has stated the kernel series will be post 6.3 material
so this one isn't quite as urgent as the patches it is based on.
However I think this series in a good state (plus I have lots more queued
behind it) hence promoting it from RFC.
Changes since RFC v2: Thanks to Markus for review.
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84 +++---
1 file changed, 46
v2:
- Fix an off by one in address space matching when both volatile and
persistent memory is in present (meant 1st byte of persistent memory
not readale)
- Picked up tags (thanks to all who tested!)
Based on following series (in order)
1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups and
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 4
include/hw/pci/pcie_regs.h |
v4: (no functional changes)
In response to similar feedback on poison injection series (Markus Armbruster).
- More detailed documentation in cxl.json
- Based on tag in format suggested by Markus.
Based on series "[PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor
fixes for upstream"
On Tue, 31 Jan 2023 16:38:47 +
Jonathan Cameron via wrote:
> From: Gregory Price
>
> This commit enables each CXL Type-3 device to contain one volatile
> memory region and one persistent region.
>
> Two new properties have been added to cxl-type3 device initializatio
On Thu, 16 Feb 2023 15:52:31 -0500
Gregory Price wrote:
> On Thu, Feb 16, 2023 at 06:00:57PM +, Jonathan Cameron wrote:
> > On Wed, 15 Feb 2023 04:10:20 -0500
> > Gregory Price wrote:
> >
> > > On Wed, Feb 15, 2023 at 03:18:54PM +, Jonathan Cameron via
On Wed, 15 Feb 2023 04:10:20 -0500
Gregory Price wrote:
> On Wed, Feb 15, 2023 at 03:18:54PM +0000, Jonathan Cameron via wrote:
> > On Wed, 8 Feb 2023 16:28:44 -0600
> > zhiting zhu wrote:
> >
> > > Hi,
> > >
> > > I saw a PoC:
> > >
On Wed, 8 Feb 2023 16:28:44 -0600
zhiting zhu wrote:
> Hi,
>
> I saw a PoC:
> https://lore.kernel.org/qemu-devel/20220525121422.3...@huawei.com/T/ to
> implement memory pooling and fabric manager on qemu. Is there any further
> development on this? Can qemu emulate a memory pooling on a
On Tue, 14 Feb 2023 16:54:02 -0500
Gregory Price wrote:
> On Tue, Feb 14, 2023 at 04:51:53PM -0500, Gregory Price wrote:
> > On Tue, Feb 14, 2023 at 09:18:24PM +, Jonathan Cameron wrote:
> > > On Tue, 14 Feb 2023 14:01:23 -0500
> > > Gregory Price wrote:
> > >
> > > Could you test it
From: Ira Weiny
The cel_uuid was programatically generated previously because there was
no static initializer for network order UUIDs.
Use the new network order initializer for cel_uuid. Adjust
cxl_initialize_mailbox() because it can't fail now.
Update specification reference.
Reviewed-by:
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Reviewed-by: Gregory Price
Tested-by: Gregory Price
Signed-off-by: Ira Weiny
Signed-off-by:
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Gregory Price
Tested-by: Gregory Price
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v2: Update comment
Dropping the ID effects this table in trivial fashion.
Reviewed-by: Gregory Price
Tested-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/DSDT.cxl| Bin 9578 -> 9564 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1
Next patch will drop duplicate _UID entry so allow update.
Reviewed-by: Gregory Price
Tested-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
Noticed as this prevents iASL disasembling the DSDT table.
Reviewed-by: Ira Weiny
Reviewed-by: Gregory Price
Tested-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index
From: Gregory Price
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
---
v2:
Change to 256 * MiB and include
From: Gregory Price
Current code sets to STORAGE_EXPRESS and then overrides it.
Reviewed-by: Davidlohr Bueso
Reviewed-by: Ira Weiny
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
801 - 900 of 1605 matches
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